Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include <string.h>
<> 144:ef7eb2e8f9f7 35 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 38 #include "gpio_api.h"
<> 144:ef7eb2e8f9f7 39 #include "uart_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 41 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #define UART_NUM 2
<> 144:ef7eb2e8f9f7 44 #define DEFAULT_BAUD 9600
<> 144:ef7eb2e8f9f7 45 #define DEFAULT_STOP 1
<> 144:ef7eb2e8f9f7 46 #define DEFAULT_PARITY ParityNone
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \
<> 144:ef7eb2e8f9f7 49 MXC_F_UART_INTFL_RX_PARITY_ERROR | \
<> 144:ef7eb2e8f9f7 50 MXC_F_UART_INTFL_RX_OVERRUN)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 // Variables for managing the stdio UART
<> 144:ef7eb2e8f9f7 53 int stdio_uart_inited;
<> 144:ef7eb2e8f9f7 54 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 // Variables for interrupt driven
<> 144:ef7eb2e8f9f7 57 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 58 static uint32_t serial_irq_ids[UART_NUM];
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 //******************************************************************************
<> 144:ef7eb2e8f9f7 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 // Determine which uart is associated with each pin
<> 144:ef7eb2e8f9f7 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 // Make sure that both pins are pointing to the same uart
<> 144:ef7eb2e8f9f7 69 MBED_ASSERT(uart != (UARTName)NC);
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 // Set the obj pointer to the proper uart
<> 144:ef7eb2e8f9f7 72 obj->uart = (mxc_uart_regs_t*)uart;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 // Set the uart index
<> 144:ef7eb2e8f9f7 75 obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart);
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 // Configure the pins
<> 144:ef7eb2e8f9f7 78 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 79 pinmap_pinout(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 // Flush the RX and TX FIFOs, clear the settings
<> 144:ef7eb2e8f9f7 82 obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH);
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // Disable interrupts
<> 144:ef7eb2e8f9f7 85 obj->uart->inten = 0;
<> 144:ef7eb2e8f9f7 86 obj->uart->intfl = 0;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 // Configure to default settings
<> 144:ef7eb2e8f9f7 89 serial_baud(obj, DEFAULT_BAUD);
<> 144:ef7eb2e8f9f7 90 serial_format(obj, 8, ParityNone, 1);
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 // Manage stdio UART
<> 144:ef7eb2e8f9f7 93 if(uart == STDIO_UART) {
<> 144:ef7eb2e8f9f7 94 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 95 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 //******************************************************************************
<> 144:ef7eb2e8f9f7 100 void serial_baud(serial_t *obj, int baudrate)
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 uint32_t idiv = 0, ddiv = 0, div = 0;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 // Calculate the integer and decimal portions
<> 144:ef7eb2e8f9f7 105 div = SystemCoreClock / ((baudrate / 100) * 128);
<> 144:ef7eb2e8f9f7 106 idiv = (div / 100);
<> 144:ef7eb2e8f9f7 107 ddiv = (div - idiv * 100) * 128 / 100;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 obj->uart->baud_int = idiv;
<> 144:ef7eb2e8f9f7 110 obj->uart->baud_div_128 = ddiv;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 // Enable the baud clock
<> 144:ef7eb2e8f9f7 113 obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN;
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 //******************************************************************************
<> 144:ef7eb2e8f9f7 117 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 // Check the validity of the inputs
<> 144:ef7eb2e8f9f7 121 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
<> 144:ef7eb2e8f9f7 122 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
<> 144:ef7eb2e8f9f7 123 (parity == ParityEven) || (parity == ParityForced1) ||
<> 144:ef7eb2e8f9f7 124 (parity == ParityForced0));
<> 144:ef7eb2e8f9f7 125 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 // Adjust the stop and data bits
<> 144:ef7eb2e8f9f7 128 stop_bits -= 1;
<> 144:ef7eb2e8f9f7 129 data_bits -= 5;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 // Adjust the parity setting
<> 144:ef7eb2e8f9f7 132 int paren = 0, mode = 0;
<> 144:ef7eb2e8f9f7 133 switch (parity) {
<> 144:ef7eb2e8f9f7 134 case ParityNone:
<> 144:ef7eb2e8f9f7 135 paren = 0;
<> 144:ef7eb2e8f9f7 136 mode = 0;
<> 144:ef7eb2e8f9f7 137 break;
<> 144:ef7eb2e8f9f7 138 case ParityOdd :
<> 144:ef7eb2e8f9f7 139 paren = 1;
<> 144:ef7eb2e8f9f7 140 mode = 0;
<> 144:ef7eb2e8f9f7 141 break;
<> 144:ef7eb2e8f9f7 142 case ParityEven:
<> 144:ef7eb2e8f9f7 143 paren = 1;
<> 144:ef7eb2e8f9f7 144 mode = 1;
<> 144:ef7eb2e8f9f7 145 break;
<> 144:ef7eb2e8f9f7 146 case ParityForced1:
<> 144:ef7eb2e8f9f7 147 // Hardware does not support forced parity
<> 144:ef7eb2e8f9f7 148 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 149 break;
<> 144:ef7eb2e8f9f7 150 case ParityForced0:
<> 144:ef7eb2e8f9f7 151 // Hardware does not support forced parity
<> 144:ef7eb2e8f9f7 152 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 153 break;
<> 144:ef7eb2e8f9f7 154 default:
<> 144:ef7eb2e8f9f7 155 paren = 1;
<> 144:ef7eb2e8f9f7 156 mode = 0;
<> 144:ef7eb2e8f9f7 157 break;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) |
<> 144:ef7eb2e8f9f7 161 (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) |
<> 144:ef7eb2e8f9f7 162 (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) |
<> 144:ef7eb2e8f9f7 163 (mode << MXC_F_UART_CTRL_PARITY_MODE_POS));
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 //******************************************************************************
<> 144:ef7eb2e8f9f7 167 void uart_handler(mxc_uart_regs_t* uart, int id)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 // Check for errors or RX Threshold
<> 144:ef7eb2e8f9f7 170 if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) {
<> 144:ef7eb2e8f9f7 171 irq_handler(serial_irq_ids[id], RxIrq);
<> 144:ef7eb2e8f9f7 172 uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 // Check for TX Threshold
<> 144:ef7eb2e8f9f7 176 if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) {
<> 144:ef7eb2e8f9f7 177 irq_handler(serial_irq_ids[id], TxIrq);
<> 144:ef7eb2e8f9f7 178 uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY);
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 void uart0_handler(void)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 uart_handler(MXC_UART0, 0);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 void uart1_handler(void)
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 uart_handler(MXC_UART1, 1);
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 //******************************************************************************
<> 144:ef7eb2e8f9f7 192 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 irq_handler = handler;
<> 144:ef7eb2e8f9f7 195 serial_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 //******************************************************************************
<> 144:ef7eb2e8f9f7 199 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 if(obj->index == 0) {
<> 144:ef7eb2e8f9f7 202 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
<> 144:ef7eb2e8f9f7 203 NVIC_EnableIRQ(UART0_IRQn);
<> 144:ef7eb2e8f9f7 204 } else {
<> 144:ef7eb2e8f9f7 205 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
<> 144:ef7eb2e8f9f7 206 NVIC_EnableIRQ(UART1_IRQn);
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 if(irq == RxIrq) {
<> 144:ef7eb2e8f9f7 210 // Set the RX FIFO Threshold to 1
<> 144:ef7eb2e8f9f7 211 obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD;
<> 144:ef7eb2e8f9f7 212 obj->uart->ctrl |= 0x1;
<> 144:ef7eb2e8f9f7 213 // Enable RX FIFO Threshold Interrupt
<> 144:ef7eb2e8f9f7 214 if(enable) {
<> 144:ef7eb2e8f9f7 215 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 216 obj->uart->intfl = 0;
<> 144:ef7eb2e8f9f7 217 obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
<> 144:ef7eb2e8f9f7 218 UART_ERRORS);
<> 144:ef7eb2e8f9f7 219 } else {
<> 144:ef7eb2e8f9f7 220 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 221 obj->uart->intfl = 0;
<> 144:ef7eb2e8f9f7 222 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
<> 144:ef7eb2e8f9f7 223 UART_ERRORS);
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 } else if (irq == TxIrq) {
<> 144:ef7eb2e8f9f7 227 // Enable TX Almost empty Interrupt
<> 144:ef7eb2e8f9f7 228 if(enable) {
<> 144:ef7eb2e8f9f7 229 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 230 obj->uart->intfl = 0;
<> 144:ef7eb2e8f9f7 231 obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
<> 144:ef7eb2e8f9f7 232 } else {
<> 144:ef7eb2e8f9f7 233 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 234 obj->uart->intfl = 0;
<> 144:ef7eb2e8f9f7 235 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 } else {
<> 144:ef7eb2e8f9f7 239 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 //******************************************************************************
<> 144:ef7eb2e8f9f7 245 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 int c;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 // Wait for data to be available
<> 144:ef7eb2e8f9f7 250 while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
<> 144:ef7eb2e8f9f7 251 c = obj->uart->tx_rx_fifo & 0xFF;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 // Echo characters for stdio
<> 144:ef7eb2e8f9f7 254 if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) {
<> 144:ef7eb2e8f9f7 255 obj->uart->tx_rx_fifo = c;
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 return c;
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 //******************************************************************************
<> 144:ef7eb2e8f9f7 262 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 // Append a carriage return for stdio
<> 144:ef7eb2e8f9f7 265 if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) {
<> 144:ef7eb2e8f9f7 266 while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
<> 144:ef7eb2e8f9f7 267 obj->uart->tx_rx_fifo = '\r';
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 // Wait for TXFIFO to not be full
<> 144:ef7eb2e8f9f7 271 while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
<> 144:ef7eb2e8f9f7 272 obj->uart->tx_rx_fifo = c;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 //******************************************************************************
<> 144:ef7eb2e8f9f7 277 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY));
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 //******************************************************************************
<> 144:ef7eb2e8f9f7 283 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL));
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 //******************************************************************************
<> 144:ef7eb2e8f9f7 289 void serial_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 // Clear the rx and tx fifos
<> 144:ef7eb2e8f9f7 292 obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH );
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 //******************************************************************************
<> 144:ef7eb2e8f9f7 296 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 // Make sure that nothing is being sent
<> 144:ef7eb2e8f9f7 299 while (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_EMPTY));
<> 144:ef7eb2e8f9f7 300 while (obj->uart->status & MXC_F_UART_STATUS_TX_BUSY);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 // Configure the GPIO to outpu 0
<> 144:ef7eb2e8f9f7 303 gpio_t tx_gpio;
<> 144:ef7eb2e8f9f7 304 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 305 case UART_0:
<> 144:ef7eb2e8f9f7 306 gpio_init_out(&tx_gpio, UART0_TX);
<> 144:ef7eb2e8f9f7 307 break;
<> 144:ef7eb2e8f9f7 308 case UART_1:
<> 144:ef7eb2e8f9f7 309 gpio_init_out(&tx_gpio, UART1_TX);
<> 144:ef7eb2e8f9f7 310 break;
<> 144:ef7eb2e8f9f7 311 default:
<> 144:ef7eb2e8f9f7 312 gpio_init_out(&tx_gpio, (PinName)NC);
<> 144:ef7eb2e8f9f7 313 break;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 gpio_write(&tx_gpio, 0);
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 // GPIO is setup now, but we need to maps gpio to the pin
<> 144:ef7eb2e8f9f7 319 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 320 case UART_0:
<> 144:ef7eb2e8f9f7 321 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_CORE_IO;
<> 144:ef7eb2e8f9f7 322 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
<> 144:ef7eb2e8f9f7 323 break;
<> 144:ef7eb2e8f9f7 324 case UART_1:
<> 144:ef7eb2e8f9f7 325 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_CORE_IO;
<> 144:ef7eb2e8f9f7 326 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
<> 144:ef7eb2e8f9f7 327 break;
<> 144:ef7eb2e8f9f7 328 default:
<> 144:ef7eb2e8f9f7 329 break;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 //******************************************************************************
<> 144:ef7eb2e8f9f7 334 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 // Configure the GPIO to output 1
<> 144:ef7eb2e8f9f7 337 gpio_t tx_gpio;
<> 144:ef7eb2e8f9f7 338 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 339 case UART_0:
<> 144:ef7eb2e8f9f7 340 gpio_init_out(&tx_gpio, UART0_TX);
<> 144:ef7eb2e8f9f7 341 break;
<> 144:ef7eb2e8f9f7 342 case UART_1:
<> 144:ef7eb2e8f9f7 343 gpio_init_out(&tx_gpio, UART1_TX);
<> 144:ef7eb2e8f9f7 344 break;
<> 144:ef7eb2e8f9f7 345 default:
<> 144:ef7eb2e8f9f7 346 gpio_init_out(&tx_gpio, (PinName)NC);
<> 144:ef7eb2e8f9f7 347 break;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 gpio_write(&tx_gpio, 1);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 // Renable UART
<> 144:ef7eb2e8f9f7 353 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 354 case UART_0:
<> 144:ef7eb2e8f9f7 355 serial_pinout_tx(UART0_TX);
<> 144:ef7eb2e8f9f7 356 break;
<> 144:ef7eb2e8f9f7 357 case UART_1:
<> 144:ef7eb2e8f9f7 358 serial_pinout_tx(UART1_TX);
<> 144:ef7eb2e8f9f7 359 break;
<> 144:ef7eb2e8f9f7 360 default:
<> 144:ef7eb2e8f9f7 361 serial_pinout_tx((PinName)NC);
<> 144:ef7eb2e8f9f7 362 break;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 //******************************************************************************
<> 144:ef7eb2e8f9f7 367 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 //******************************************************************************
<> 144:ef7eb2e8f9f7 374 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 if(FlowControlNone == type) {
<> 144:ef7eb2e8f9f7 377 // Disable hardware flow control
<> 144:ef7eb2e8f9f7 378 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN);
<> 144:ef7eb2e8f9f7 379 return;
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 // Check to see if we can use HW flow control
<> 144:ef7eb2e8f9f7 383 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 384 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 385 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) {
<> 144:ef7eb2e8f9f7 388 // Make sure pin is in the PinMap
<> 144:ef7eb2e8f9f7 389 MBED_ASSERT(uart_cts != (UARTName)NC);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 // Enable the pin for CTS function
<> 144:ef7eb2e8f9f7 392 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) {
<> 144:ef7eb2e8f9f7 396 // Make sure pin is in the PinMap
<> 144:ef7eb2e8f9f7 397 MBED_ASSERT(uart_rts != (UARTName)NC);
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 // Enable the pin for RTS function
<> 144:ef7eb2e8f9f7 400 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 if(FlowControlRTSCTS == type){
<> 144:ef7eb2e8f9f7 404 // Make sure that the pins are pointing to the same UART
<> 144:ef7eb2e8f9f7 405 MBED_ASSERT(uart != (UARTName)NC);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 // Enable hardware flow control
<> 144:ef7eb2e8f9f7 409 obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN;
<> 144:ef7eb2e8f9f7 410 }