added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/spi_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <math.h> |
<> | 144:ef7eb2e8f9f7 | 17 | #include "mbed_assert.h" |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | #include "spi_api.h" |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | #if DEVICE_SPI |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 24 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 25 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 26 | #include "fsl_dspi.h" |
<> | 144:ef7eb2e8f9f7 | 27 | #include "peripheral_clock_defines.h" |
<> | 144:ef7eb2e8f9f7 | 28 | #include "PeripheralPins.h" |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | /* Array of SPI peripheral base address. */ |
<> | 144:ef7eb2e8f9f7 | 31 | static SPI_Type *const spi_address[] = SPI_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 32 | /* Array of SPI bus clock frequencies */ |
<> | 144:ef7eb2e8f9f7 | 33 | static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS; |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { |
<> | 144:ef7eb2e8f9f7 | 36 | // determine the SPI to use |
<> | 144:ef7eb2e8f9f7 | 37 | uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 38 | uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 39 | uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
<> | 144:ef7eb2e8f9f7 | 40 | uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
<> | 144:ef7eb2e8f9f7 | 41 | uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); |
<> | 144:ef7eb2e8f9f7 | 42 | uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | obj->instance = pinmap_merge(spi_data, spi_cntl); |
<> | 144:ef7eb2e8f9f7 | 45 | MBED_ASSERT((int)obj->instance != NC); |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | // pin out the spi pins |
<> | 144:ef7eb2e8f9f7 | 48 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 49 | pinmap_pinout(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 50 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
<> | 144:ef7eb2e8f9f7 | 51 | if (ssel != NC) { |
<> | 144:ef7eb2e8f9f7 | 52 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
<> | 144:ef7eb2e8f9f7 | 53 | } |
<> | 144:ef7eb2e8f9f7 | 54 | } |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | void spi_free(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 57 | DSPI_Deinit(spi_address[obj->instance]); |
<> | 144:ef7eb2e8f9f7 | 58 | } |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | dspi_master_config_t master_config; |
<> | 144:ef7eb2e8f9f7 | 63 | dspi_slave_config_t slave_config; |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | if (slave) { |
<> | 144:ef7eb2e8f9f7 | 66 | /* Slave config */ |
<> | 144:ef7eb2e8f9f7 | 67 | DSPI_SlaveGetDefaultConfig(&slave_config); |
<> | 144:ef7eb2e8f9f7 | 68 | slave_config.whichCtar = kDSPI_Ctar0; |
<> | 144:ef7eb2e8f9f7 | 69 | slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; |
<> | 144:ef7eb2e8f9f7 | 70 | slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; |
<> | 144:ef7eb2e8f9f7 | 71 | slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | DSPI_SlaveInit(spi_address[obj->instance], &slave_config); |
<> | 144:ef7eb2e8f9f7 | 74 | } else { |
<> | 144:ef7eb2e8f9f7 | 75 | /* Master config */ |
<> | 144:ef7eb2e8f9f7 | 76 | DSPI_MasterGetDefaultConfig(&master_config); |
<> | 144:ef7eb2e8f9f7 | 77 | master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; |
<> | 144:ef7eb2e8f9f7 | 78 | master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; |
<> | 144:ef7eb2e8f9f7 | 79 | master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; |
<> | 144:ef7eb2e8f9f7 | 80 | master_config.ctarConfig.direction = kDSPI_MsbFirst; |
<> | 144:ef7eb2e8f9f7 | 81 | master_config.ctarConfig.pcsToSckDelayInNanoSec = 0; |
<> | 144:ef7eb2e8f9f7 | 82 | |
<> | 144:ef7eb2e8f9f7 | 83 | DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance])); |
<> | 144:ef7eb2e8f9f7 | 84 | } |
<> | 144:ef7eb2e8f9f7 | 85 | } |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | void spi_frequency(spi_t *obj, int hz) { |
<> | 144:ef7eb2e8f9f7 | 88 | uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]); |
<> | 144:ef7eb2e8f9f7 | 89 | DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock); |
<> | 144:ef7eb2e8f9f7 | 90 | //Half clock period delay after SPI transfer |
<> | 144:ef7eb2e8f9f7 | 91 | DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz); |
<> | 144:ef7eb2e8f9f7 | 92 | } |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | static inline int spi_readable(spi_t * obj) { |
<> | 144:ef7eb2e8f9f7 | 95 | return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag); |
<> | 144:ef7eb2e8f9f7 | 96 | } |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | int spi_master_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 99 | dspi_command_data_config_t command; |
<> | 144:ef7eb2e8f9f7 | 100 | uint32_t rx_data; |
<> | 144:ef7eb2e8f9f7 | 101 | DSPI_GetDefaultDataCommandConfig(&command); |
<> | 144:ef7eb2e8f9f7 | 102 | command.isEndOfQueue = true; |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value); |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag); |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | // wait rx buffer full |
<> | 144:ef7eb2e8f9f7 | 109 | while (!spi_readable(obj)); |
<> | 144:ef7eb2e8f9f7 | 110 | rx_data = DSPI_ReadData(spi_address[obj->instance]); |
<> | 144:ef7eb2e8f9f7 | 111 | DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag); |
<> | 144:ef7eb2e8f9f7 | 112 | return rx_data & 0xffff; |
<> | 144:ef7eb2e8f9f7 | 113 | } |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | int spi_slave_receive(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 116 | return spi_readable(obj); |
<> | 144:ef7eb2e8f9f7 | 117 | } |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | int spi_slave_read(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 120 | uint32_t rx_data; |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | while (!spi_readable(obj)); |
<> | 144:ef7eb2e8f9f7 | 123 | rx_data = DSPI_ReadData(spi_address[obj->instance]); |
<> | 144:ef7eb2e8f9f7 | 124 | DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag); |
<> | 144:ef7eb2e8f9f7 | 125 | return rx_data & 0xffff; |
<> | 144:ef7eb2e8f9f7 | 126 | } |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | void spi_slave_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 129 | DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value); |
<> | 144:ef7eb2e8f9f7 | 130 | } |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | #endif |