Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_slcd.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef _FSL_SLCD_H_
<> 144:ef7eb2e8f9f7 32 #define _FSL_SLCD_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @addtogroup slcd
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*! @file */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*******************************************************************************
<> 144:ef7eb2e8f9f7 44 * Definitions
<> 144:ef7eb2e8f9f7 45 ******************************************************************************/
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 48 /*@{*/
<> 144:ef7eb2e8f9f7 49 /*! @brief SLCD driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 50 #define FSL_SLCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 51 /*@}*/
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*! @brief SLCD power supply option. */
<> 144:ef7eb2e8f9f7 54 typedef enum _slcd_power_supply_option
<> 144:ef7eb2e8f9f7 55 {
<> 144:ef7eb2e8f9f7 56 kSLCD_InternalVll3UseChargePump =
<> 144:ef7eb2e8f9f7 57 2U, /*!< VLL3 connected to VDD internally, charge pump is used to generate VLL1 and VLL2. */
<> 144:ef7eb2e8f9f7 58 kSLCD_ExternalVll3UseResistorBiasNetwork =
<> 144:ef7eb2e8f9f7 59 4U, /*!< VLL3 is driven externally and resistor bias network is used to generate VLL1 and VLL2. */
<> 144:ef7eb2e8f9f7 60 kSLCD_ExteranlVll3UseChargePump =
<> 144:ef7eb2e8f9f7 61 6U, /*!< VLL3 is driven externally and charge pump is used to generate VLL1 and VLL2. */
<> 144:ef7eb2e8f9f7 62 kSLCD_InternalVll1UseChargePump =
<> 144:ef7eb2e8f9f7 63 7U /*!< VIREG is connected to VLL1 internally and charge pump is used to generate VLL2 and VLL3. */
<> 144:ef7eb2e8f9f7 64 } slcd_power_supply_option_t;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /*! @brief SLCD regulated voltage trim parameter, be used to meet the desired contrast. */
<> 144:ef7eb2e8f9f7 67 typedef enum _slcd_regulated_voltage_trim
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 kSLCD_RegulatedVolatgeTrim00 = 0U, /*!< Increase the voltage to 0.91 V. */
<> 144:ef7eb2e8f9f7 70 kSLCD_RegulatedVolatgeTrim01, /*!< Increase the voltage to 1.01 V. */
<> 144:ef7eb2e8f9f7 71 kSLCD_RegulatedVolatgeTrim02, /*!< Increase the voltage to 0.96 V. */
<> 144:ef7eb2e8f9f7 72 kSLCD_RegulatedVolatgeTrim03, /*!< Increase the voltage to 1.06 V. */
<> 144:ef7eb2e8f9f7 73 kSLCD_RegulatedVolatgeTrim04, /*!< Increase the voltage to 0.93 V. */
<> 144:ef7eb2e8f9f7 74 kSLCD_RegulatedVolatgeTrim05, /*!< Increase the voltage to 1.02 V. */
<> 144:ef7eb2e8f9f7 75 kSLCD_RegulatedVolatgeTrim06, /*!< Increase the voltage to 0.98 V. */
<> 144:ef7eb2e8f9f7 76 kSLCD_RegulatedVolatgeTrim07, /*!< Increase the voltage to 1.08 V. */
<> 144:ef7eb2e8f9f7 77 kSLCD_RegulatedVolatgeTrim08, /*!< Increase the voltage to 0.92 V. */
<> 144:ef7eb2e8f9f7 78 kSLCD_RegulatedVolatgeTrim09, /*!< Increase the voltage to 1.02 V. */
<> 144:ef7eb2e8f9f7 79 kSLCD_RegulatedVolatgeTrim10, /*!< Increase the voltage to 0.97 V. */
<> 144:ef7eb2e8f9f7 80 kSLCD_RegulatedVolatgeTrim11, /*!< Increase the voltage to 1.07 V. */
<> 144:ef7eb2e8f9f7 81 kSLCD_RegulatedVolatgeTrim12, /*!< Increase the voltage to 0.94 V. */
<> 144:ef7eb2e8f9f7 82 kSLCD_RegulatedVolatgeTrim13, /*!< Increase the voltage to 1.05 V. */
<> 144:ef7eb2e8f9f7 83 kSLCD_RegulatedVolatgeTrim14, /*!< Increase the voltage to 0.99 V. */
<> 144:ef7eb2e8f9f7 84 kSLCD_RegulatedVolatgeTrim15 /*!< Increase the voltage to 1.09 V. */
<> 144:ef7eb2e8f9f7 85 } slcd_regulated_voltage_trim_t;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*! @brief SLCD load adjust to handle different LCD glass capacitance or
<> 144:ef7eb2e8f9f7 88 * configure the LCD charge pump clock source.
<> 144:ef7eb2e8f9f7 89 * Adjust the LCD glass capacitance if resistor bias network is enabled:
<> 144:ef7eb2e8f9f7 90 * kSLCD_LowLoadOrFastestClkSrc - Low load (LCD glass capacitance 2000pF or lower.
<> 144:ef7eb2e8f9f7 91 * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
<> 144:ef7eb2e8f9f7 92 * kSLCD_LowLoadOrIntermediateClkSrc - low load (LCD glass capacitance 2000pF or lower.
<> 144:ef7eb2e8f9f7 93 * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
<> 144:ef7eb2e8f9f7 94 * kSLCD_HighLoadOrIntermediateClkSrc - high load (LCD glass capacitance 8000pF or lower.
<> 144:ef7eb2e8f9f7 95 * LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
<> 144:ef7eb2e8f9f7 96 * kSLCD_HighLoadOrSlowestClkSrc - high load (LCD glass capacitance 8000pF or lower
<> 144:ef7eb2e8f9f7 97 * LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
<> 144:ef7eb2e8f9f7 98 * Adjust clock for charge pump if charge pump is enabled:
<> 144:ef7eb2e8f9f7 99 * kSLCD_LowLoadOrFastestClkSrc - Fasten clock source (LCD glass capacitance
<> 144:ef7eb2e8f9f7 100 * 8000pF or 4000pF or lower if Fast Frame Rate is set)
<> 144:ef7eb2e8f9f7 101 * kSLCD_LowLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
<> 144:ef7eb2e8f9f7 102 * capacitance 4000pF or 2000pF or lower if Fast Frame Rate is set)
<> 144:ef7eb2e8f9f7 103 * kSLCD_HighLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
<> 144:ef7eb2e8f9f7 104 * capacitance 2000pF or 1000pF or lower if Fast Frame Rate is set)
<> 144:ef7eb2e8f9f7 105 * kSLCD_HighLoadOrSlowestClkSrc - slowest clock source (LCD glass capacitance
<> 144:ef7eb2e8f9f7 106 * 1000pF or 500pF or lower if Fast Frame Rate is set)
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 typedef enum _slcd_load_adjust
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110 kSLCD_LowLoadOrFastestClkSrc = 0U, /*!< Adjust in low load or selects fastest clock. */
<> 144:ef7eb2e8f9f7 111 kSLCD_LowLoadOrIntermediateClkSrc, /*!< Adjust in low load or selects intermediate clock. */
<> 144:ef7eb2e8f9f7 112 kSLCD_HighLoadOrIntermediateClkSrc, /*!< Adjust in high load or selects intermediate clock. */
<> 144:ef7eb2e8f9f7 113 kSLCD_HighLoadOrSlowestClkSrc /*!< Adjust in high load or selects slowest clock. */
<> 144:ef7eb2e8f9f7 114 } slcd_load_adjust_t;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /*! @brief SLCD clock source. */
<> 144:ef7eb2e8f9f7 117 typedef enum _slcd_clock_src
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 kSLCD_DefaultClk = 0U, /*!< Select default clock ERCLK32K. */
<> 144:ef7eb2e8f9f7 120 kSLCD_AlternateClk1 = 1U, /*!< Select alternate clock source 1 : MCGIRCLK. */
<> 144:ef7eb2e8f9f7 121 #if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE
<> 144:ef7eb2e8f9f7 122 kSLCD_AlternateClk2 = 3U /*!< Select alternate clock source 2 : OSCERCLK. */
<> 144:ef7eb2e8f9f7 123 #endif /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */
<> 144:ef7eb2e8f9f7 124 } slcd_clock_src_t;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /*! @brief SLCD alternate clock divider. */
<> 144:ef7eb2e8f9f7 127 typedef enum _slcd_alt_clock_div
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 kSLCD_AltClkDivFactor1 = 0U, /*!< No divide for alternate clock. */
<> 144:ef7eb2e8f9f7 130 kSLCD_AltClkDivFactor64, /*!< Divide alternate clock with factor 64. */
<> 144:ef7eb2e8f9f7 131 kSLCD_AltClkDivFactor256, /*!< Divide alternate clock with factor 256. */
<> 144:ef7eb2e8f9f7 132 kSLCD_AltClkDivFactor512 /*!< Divide alternate clock with factor 512. */
<> 144:ef7eb2e8f9f7 133 } slcd_alt_clock_div_t;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /*! @brief SLCD clock prescaler to generate frame frequency. */
<> 144:ef7eb2e8f9f7 136 typedef enum _slcd_clock_prescaler
<> 144:ef7eb2e8f9f7 137 {
<> 144:ef7eb2e8f9f7 138 kSLCD_ClkPrescaler00 = 0U, /*!< Prescaler 0. */
<> 144:ef7eb2e8f9f7 139 kSLCD_ClkPrescaler01, /*!< Prescaler 1. */
<> 144:ef7eb2e8f9f7 140 kSLCD_ClkPrescaler02, /*!< Prescaler 2. */
<> 144:ef7eb2e8f9f7 141 kSLCD_ClkPrescaler03, /*!< Prescaler 3. */
<> 144:ef7eb2e8f9f7 142 kSLCD_ClkPrescaler04, /*!< Prescaler 4. */
<> 144:ef7eb2e8f9f7 143 kSLCD_ClkPrescaler05, /*!< Prescaler 5. */
<> 144:ef7eb2e8f9f7 144 kSLCD_ClkPrescaler06, /*!< Prescaler 6. */
<> 144:ef7eb2e8f9f7 145 kSLCD_ClkPrescaler07 /*!< Prescaler 7. */
<> 144:ef7eb2e8f9f7 146 } slcd_clock_prescaler_t;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /*! @brief SLCD duty cycle. */
<> 144:ef7eb2e8f9f7 149 typedef enum _slcd_duty_cycle
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 kSLCD_1Div1DutyCycle = 0U, /*!< LCD use 1 BP 1/1 duty cycle. */
<> 144:ef7eb2e8f9f7 152 kSLCD_1Div2DutyCycle, /*!< LCD use 2 BP 1/2 duty cycle. */
<> 144:ef7eb2e8f9f7 153 kSLCD_1Div3DutyCycle, /*!< LCD use 3 BP 1/3 duty cycle. */
<> 144:ef7eb2e8f9f7 154 kSLCD_1Div4DutyCycle, /*!< LCD use 4 BP 1/4 duty cycle. */
<> 144:ef7eb2e8f9f7 155 kSLCD_1Div5DutyCycle, /*!< LCD use 5 BP 1/5 duty cycle. */
<> 144:ef7eb2e8f9f7 156 kSLCD_1Div6DutyCycle, /*!< LCD use 6 BP 1/6 duty cycle. */
<> 144:ef7eb2e8f9f7 157 kSLCD_1Div7DutyCycle, /*!< LCD use 7 BP 1/7 duty cycle. */
<> 144:ef7eb2e8f9f7 158 kSLCD_1Div8DutyCycle /*!< LCD use 8 BP 1/8 duty cycle. */
<> 144:ef7eb2e8f9f7 159 } slcd_duty_cycle_t;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /*! @brief SLCD segment phase type. */
<> 144:ef7eb2e8f9f7 162 typedef enum _slcd_phase_type
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 kSLCD_NoPhaseActivate = 0x00U, /*!< LCD wareform no phase activates. */
<> 144:ef7eb2e8f9f7 165 kSLCD_PhaseAActivate = 0x01U, /*!< LCD waveform phase A activates. */
<> 144:ef7eb2e8f9f7 166 kSLCD_PhaseBActivate = 0x02U, /*!< LCD waveform phase B activates. */
<> 144:ef7eb2e8f9f7 167 kSLCD_PhaseCActivate = 0x04U, /*!< LCD waveform phase C activates. */
<> 144:ef7eb2e8f9f7 168 kSLCD_PhaseDActivate = 0x08U, /*!< LCD waveform phase D activates. */
<> 144:ef7eb2e8f9f7 169 kSLCD_PhaseEActivate = 0x10U, /*!< LCD waveform phase E activates. */
<> 144:ef7eb2e8f9f7 170 kSLCD_PhaseFActivate = 0x20U, /*!< LCD waveform phase F activates. */
<> 144:ef7eb2e8f9f7 171 kSLCD_PhaseGActivate = 0x40U, /*!< LCD waveform phase G activates. */
<> 144:ef7eb2e8f9f7 172 kSLCD_PhaseHActivate = 0x80U /*!< LCD waveform phase H activates. */
<> 144:ef7eb2e8f9f7 173 } slcd_phase_type_t;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /*! @brief SLCD segment phase bit index. */
<> 144:ef7eb2e8f9f7 176 typedef enum _slcd_phase_index
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 kSLCD_PhaseAIndex = 0x0U, /*!< LCD phase A bit index. */
<> 144:ef7eb2e8f9f7 179 kSLCD_PhaseBIndex = 0x1U, /*!< LCD phase B bit index. */
<> 144:ef7eb2e8f9f7 180 kSLCD_PhaseCIndex = 0x2U, /*!< LCD phase C bit index. */
<> 144:ef7eb2e8f9f7 181 kSLCD_PhaseDIndex = 0x3U, /*!< LCD phase D bit index. */
<> 144:ef7eb2e8f9f7 182 kSLCD_PhaseEIndex = 0x4U, /*!< LCD phase E bit index. */
<> 144:ef7eb2e8f9f7 183 kSLCD_PhaseFIndex = 0x5U, /*!< LCD phase F bit index. */
<> 144:ef7eb2e8f9f7 184 kSLCD_PhaseGIndex = 0x6U, /*!< LCD phase G bit index. */
<> 144:ef7eb2e8f9f7 185 kSLCD_PhaseHIndex = 0x7U /*!< LCD phase H bit index. */
<> 144:ef7eb2e8f9f7 186 } slcd_phase_index_t;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /*! @brief SLCD display mode. */
<> 144:ef7eb2e8f9f7 189 typedef enum _slcd_display_mode
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 kSLCD_NormalMode = 0U, /*!< LCD Normal display mode. */
<> 144:ef7eb2e8f9f7 192 kSLCD_AlternateMode, /*!< LCD Alternate display mode. For four back planes or less. */
<> 144:ef7eb2e8f9f7 193 kSLCD_BlankMode /*!< LCD Blank display mode. */
<> 144:ef7eb2e8f9f7 194 } slcd_display_mode_t;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /*! @brief SLCD blink mode. */
<> 144:ef7eb2e8f9f7 197 typedef enum _slcd_blink_mode
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 kSLCD_BlankDisplayBlink = 0U, /*!< Display blank during the blink period. */
<> 144:ef7eb2e8f9f7 200 kSLCD_AltDisplayBlink /*!< Display alternate display during the blink period if duty cycle is lower than 5. */
<> 144:ef7eb2e8f9f7 201 } slcd_blink_mode_t;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /*! @brief SLCD blink rate. */
<> 144:ef7eb2e8f9f7 204 typedef enum _slcd_blink_rate
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 kSLCD_BlinkRate00 = 0U, /*!< SLCD blink rate is LCD clock/((2^12)). */
<> 144:ef7eb2e8f9f7 207 kSLCD_BlinkRate01, /*!< SLCD blink rate is LCD clock/((2^13)). */
<> 144:ef7eb2e8f9f7 208 kSLCD_BlinkRate02, /*!< SLCD blink rate is LCD clock/((2^14)). */
<> 144:ef7eb2e8f9f7 209 kSLCD_BlinkRate03, /*!< SLCD blink rate is LCD clock/((2^15)). */
<> 144:ef7eb2e8f9f7 210 kSLCD_BlinkRate04, /*!< SLCD blink rate is LCD clock/((2^16)). */
<> 144:ef7eb2e8f9f7 211 kSLCD_BlinkRate05, /*!< SLCD blink rate is LCD clock/((2^17)). */
<> 144:ef7eb2e8f9f7 212 kSLCD_BlinkRate06, /*!< SLCD blink rate is LCD clock/((2^18)). */
<> 144:ef7eb2e8f9f7 213 kSLCD_BlinkRate07 /*!< SLCD blink rate is LCD clock/((2^19)). */
<> 144:ef7eb2e8f9f7 214 } slcd_blink_rate_t;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /*! @brief SLCD fault detect clock prescaler. */
<> 144:ef7eb2e8f9f7 217 typedef enum _slcd_fault_detect_clock_prescaler
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 kSLCD_FaultSampleFreqDivider1 = 0U, /*!< Fault detect sample clock frequency is 1/1 bus clock. */
<> 144:ef7eb2e8f9f7 220 kSLCD_FaultSampleFreqDivider2, /*!< Fault detect sample clock frequency is 1/2 bus clock. */
<> 144:ef7eb2e8f9f7 221 kSLCD_FaultSampleFreqDivider4, /*!< Fault detect sample clock frequency is 1/4 bus clock. */
<> 144:ef7eb2e8f9f7 222 kSLCD_FaultSampleFreqDivider8, /*!< Fault detect sample clock frequency is 1/8 bus clock. */
<> 144:ef7eb2e8f9f7 223 kSLCD_FaultSampleFreqDivider16, /*!< Fault detect sample clock frequency is 1/16 bus clock. */
<> 144:ef7eb2e8f9f7 224 kSLCD_FaultSampleFreqDivider32, /*!< Fault detect sample clock frequency is 1/32 bus clock. */
<> 144:ef7eb2e8f9f7 225 kSLCD_FaultSampleFreqDivider64, /*!< Fault detect sample clock frequency is 1/64 bus clock. */
<> 144:ef7eb2e8f9f7 226 kSLCD_FaultSampleFreqDivider128 /*!< Fault detect sample clock frequency is 1/128 bus clock. */
<> 144:ef7eb2e8f9f7 227 } slcd_fault_detect_clock_prescaler_t;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /*! @brief SLCD fault detect sample window width. */
<> 144:ef7eb2e8f9f7 230 typedef enum _slcd_fault_detect_sample_window_width
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 kSLCD_FaultDetectWindowWidth4SampleClk = 0U, /*!< Sample window width is 4 sample clock cycles. */
<> 144:ef7eb2e8f9f7 233 kSLCD_FaultDetectWindowWidth8SampleClk, /*!< Sample window width is 8 sample clock cycles. */
<> 144:ef7eb2e8f9f7 234 kSLCD_FaultDetectWindowWidth16SampleClk, /*!< Sample window width is 16 sample clock cycles. */
<> 144:ef7eb2e8f9f7 235 kSLCD_FaultDetectWindowWidth32SampleClk, /*!< Sample window width is 32 sample clock cycles. */
<> 144:ef7eb2e8f9f7 236 kSLCD_FaultDetectWindowWidth64SampleClk, /*!< Sample window width is 64 sample clock cycles. */
<> 144:ef7eb2e8f9f7 237 kSLCD_FaultDetectWindowWidth128SampleClk, /*!< Sample window width is 128 sample clock cycles. */
<> 144:ef7eb2e8f9f7 238 kSLCD_FaultDetectWindowWidth256SampleClk, /*!< Sample window width is 256 sample clock cycles. */
<> 144:ef7eb2e8f9f7 239 kSLCD_FaultDetectWindowWidth512SampleClk /*!< Sample window width is 512 sample clock cycles. */
<> 144:ef7eb2e8f9f7 240 } slcd_fault_detect_sample_window_width_t;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /*! @brief SLCD interrupt source. */
<> 144:ef7eb2e8f9f7 243 typedef enum _slcd_interrupt_enable
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 kSLCD_FaultDetectCompleteInterrupt = 1U, /*!< SLCD fault detection complete interrupt source. */
<> 144:ef7eb2e8f9f7 246 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 247 kSLCD_FrameFreqInterrupt = 2U /*!< SLCD frame frequency interrupt source. Not available in all low-power modes. */
<> 144:ef7eb2e8f9f7 248 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 249 } slcd_interrupt_enable_t;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /*! @brief SLCD behavior in low power mode. */
<> 144:ef7eb2e8f9f7 252 typedef enum _slcd_lowpower_behavior
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 kSLCD_EnabledInWaitStop = 0, /*!< SLCD works in wait and stop mode. */
<> 144:ef7eb2e8f9f7 255 kSLCD_EnabledInWaitOnly, /*!< SLCD works in wait mode and is disabled in stop mode. */
<> 144:ef7eb2e8f9f7 256 kSLCD_EnabledInStopOnly, /*!< SLCD works in stop mode and is disabled in wait mode. */
<> 144:ef7eb2e8f9f7 257 kSLCD_DisabledInWaitStop /*!< SLCD is disabled in stop mode and wait mode. */
<> 144:ef7eb2e8f9f7 258 } slcd_lowpower_behavior;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /*! @brief SLCD fault frame detection configure structure. */
<> 144:ef7eb2e8f9f7 261 typedef struct _slcd_fault_detect_config
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 bool faultDetectIntEnable; /*!< Fault frame detection interrupt enable flag.*/
<> 144:ef7eb2e8f9f7 264 bool faultDetectBackPlaneEnable; /*!< True means the pin id fault detected is back plane otherwise front plane. */
<> 144:ef7eb2e8f9f7 265 uint8_t faultDetectPinIndex; /*!< Fault detected pin id from 0 to 63. */
<> 144:ef7eb2e8f9f7 266 slcd_fault_detect_clock_prescaler_t faultPrescaler; /*!< Fault detect clock prescaler. */
<> 144:ef7eb2e8f9f7 267 slcd_fault_detect_sample_window_width_t width; /*!< Fault detect sample window width. */
<> 144:ef7eb2e8f9f7 268 } slcd_fault_detect_config_t;
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /*! @brief SLCD clock configure structure. */
<> 144:ef7eb2e8f9f7 271 typedef struct _slcd_clock_config
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 slcd_clock_src_t clkSource; /*!< Clock source. "slcd_clock_src_t" is recommended to be used.
<> 144:ef7eb2e8f9f7 274 The SLCD is optimized to operate using a 32.768kHz clock input. */
<> 144:ef7eb2e8f9f7 275 slcd_alt_clock_div_t
<> 144:ef7eb2e8f9f7 276 altClkDivider; /*!< The divider to divide the alternate clock used for alternate clock source. */
<> 144:ef7eb2e8f9f7 277 slcd_clock_prescaler_t clkPrescaler; /*!< Clock prescaler. */
<> 144:ef7eb2e8f9f7 278 #if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE
<> 144:ef7eb2e8f9f7 279 bool fastFrameRateEnable; /*!< Fast frame rate enable flag. */
<> 144:ef7eb2e8f9f7 280 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
<> 144:ef7eb2e8f9f7 281 } slcd_clock_config_t;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /*! @brief SLCD configure structure. */
<> 144:ef7eb2e8f9f7 284 typedef struct _slcd_config
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 slcd_power_supply_option_t powerSupply; /*!< Power supply option. */
<> 144:ef7eb2e8f9f7 287 slcd_regulated_voltage_trim_t voltageTrim; /*!< Regulated voltage trim used for the internal regulator VIREG to
<> 144:ef7eb2e8f9f7 288 adjust to facilitate contrast control. */
<> 144:ef7eb2e8f9f7 289 slcd_clock_config_t *clkConfig; /*!< Clock configure. */
<> 144:ef7eb2e8f9f7 290 slcd_display_mode_t displayMode; /*!< SLCD display mode. */
<> 144:ef7eb2e8f9f7 291 slcd_load_adjust_t loadAdjust; /*!< Load adjust to handle glass capacitance. */
<> 144:ef7eb2e8f9f7 292 slcd_duty_cycle_t dutyCycle; /*!< Duty cycle. */
<> 144:ef7eb2e8f9f7 293 slcd_lowpower_behavior lowPowerBehavior; /*!< SLCD behavior in low power mode. */
<> 144:ef7eb2e8f9f7 294 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 295 bool frameFreqIntEnable; /*!< Frame frequency interrupt enable flag.*/
<> 144:ef7eb2e8f9f7 296 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
<> 144:ef7eb2e8f9f7 297 uint32_t slcdLowPinEnabled; /*!< Setting enabled SLCD pin 0 ~ pin 31. Setting bit n to 1 means enable pin n. */
<> 144:ef7eb2e8f9f7 298 uint32_t
<> 144:ef7eb2e8f9f7 299 slcdHighPinEnabled; /*!< Setting enabled SLCD pin 32 ~ pin 63. Setting bit n to 1 means enable pin (n + 32). */
<> 144:ef7eb2e8f9f7 300 uint32_t backPlaneLowPin; /*!< Setting back plane pin 0 ~ pin 31. Setting bit n to 1 means setting pin n as back
<> 144:ef7eb2e8f9f7 301 plane. It should never have the same bit setting as the frontPlane Pin. */
<> 144:ef7eb2e8f9f7 302 uint32_t backPlaneHighPin; /*!< Setting back plane pin 32 ~ pin 63. Setting bit n to 1 means setting pin (n + 32) as
<> 144:ef7eb2e8f9f7 303 back plane. It should never have the same bit setting as the frontPlane Pin. */
<> 144:ef7eb2e8f9f7 304 slcd_fault_detect_config_t *faultConfig; /*!< Fault frame detection configure. If not requirement, set to NULL. */
<> 144:ef7eb2e8f9f7 305 } slcd_config_t;
<> 144:ef7eb2e8f9f7 306 /*******************************************************************************
<> 144:ef7eb2e8f9f7 307 * API
<> 144:ef7eb2e8f9f7 308 ******************************************************************************/
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 311 extern "C" {
<> 144:ef7eb2e8f9f7 312 #endif /* __cplusplus*/
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /*!
<> 144:ef7eb2e8f9f7 315 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /*!
<> 144:ef7eb2e8f9f7 320 * @brief Initializes the SLCD, ungates the module clock, initializes the power
<> 144:ef7eb2e8f9f7 321 * setting, enables all used plane pins, and sets with interrupt and work mode
<> 144:ef7eb2e8f9f7 322 * with configuration.
<> 144:ef7eb2e8f9f7 323 *
<> 144:ef7eb2e8f9f7 324 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 325 * @param configure SLCD configuration pointer.
<> 144:ef7eb2e8f9f7 326 * For the configuration structure, many parameters have the default setting
<> 144:ef7eb2e8f9f7 327 * and the SLCD_Getdefaultconfig() is provided to get them. Use it
<> 144:ef7eb2e8f9f7 328 * verified for their applications.
<> 144:ef7eb2e8f9f7 329 * The others have no default settings such as "clkConfig" and must be provided
<> 144:ef7eb2e8f9f7 330 * by the application before calling the SLCD_Init() API.
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 void SLCD_Init(LCD_Type *base, slcd_config_t *configure);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /*!
<> 144:ef7eb2e8f9f7 335 * @brief Deinitializes the SLCD module, gates the module clock, disables an interrupt,
<> 144:ef7eb2e8f9f7 336 * and displays the SLCD.
<> 144:ef7eb2e8f9f7 337 *
<> 144:ef7eb2e8f9f7 338 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 void SLCD_Deinit(LCD_Type *base);
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /*!
<> 144:ef7eb2e8f9f7 343 * @brief Gets the SLCD default configuration structure. The
<> 144:ef7eb2e8f9f7 344 * purpose of this API is to get default parameters of the configuration structure
<> 144:ef7eb2e8f9f7 345 * for the SLCD_Init(). Use these initialized parameters unchanged in SLCD_Init(),
<> 144:ef7eb2e8f9f7 346 * or modify some fields of the structure before the calling SLCD_Init().
<> 144:ef7eb2e8f9f7 347 * All default parameters of the configure structure are listed:
<> 144:ef7eb2e8f9f7 348 * @code
<> 144:ef7eb2e8f9f7 349 config.displayMode = kSLCD_NormalMode; // SLCD normal mode
<> 144:ef7eb2e8f9f7 350 config.powerSupply = kSLCD_InternalVll3UseChargePump; // Use charge pump internal VLL3
<> 144:ef7eb2e8f9f7 351 config.voltageTrim = kSLCD_RegulatedVolatgeTrim00;
<> 144:ef7eb2e8f9f7 352 config.lowPowerBehavior = kSLCD_EnabledInWaitStop; // Work on low power mode
<> 144:ef7eb2e8f9f7 353 config.interruptSrc = 0; // No interrupt source is enabled
<> 144:ef7eb2e8f9f7 354 config.faultConfig = NULL; // Fault detection is disabled
<> 144:ef7eb2e8f9f7 355 config.frameFreqIntEnable = false;
<> 144:ef7eb2e8f9f7 356 @endcode
<> 144:ef7eb2e8f9f7 357 * @param configure The SLCD configuration structure pointer.
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 void SLCD_GetDefaultConfig(slcd_config_t *configure);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* @}*/
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /*!
<> 144:ef7eb2e8f9f7 364 * @name Plane Setting and Display Control
<> 144:ef7eb2e8f9f7 365 * @{
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /*!
<> 144:ef7eb2e8f9f7 369 * @brief Enables the SLCD controller, starts generate, and displays the front plane and back plane waveform.
<> 144:ef7eb2e8f9f7 370 *
<> 144:ef7eb2e8f9f7 371 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 static inline void SLCD_StartDisplay(LCD_Type *base)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 base->GCR |= LCD_GCR_LCDEN_MASK;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /*!
<> 144:ef7eb2e8f9f7 379 * @brief Stops the SLCD controller. There is no waveform generator and all enabled pins
<> 144:ef7eb2e8f9f7 380 * only output a low value.
<> 144:ef7eb2e8f9f7 381 *
<> 144:ef7eb2e8f9f7 382 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 static inline void SLCD_StopDisplay(LCD_Type *base)
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 base->GCR &= ~LCD_GCR_LCDEN_MASK;
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /*!
<> 144:ef7eb2e8f9f7 390 * @brief Starts the SLCD blink mode.
<> 144:ef7eb2e8f9f7 391 *
<> 144:ef7eb2e8f9f7 392 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 393 * @param mode SLCD blink mode.
<> 144:ef7eb2e8f9f7 394 * @param rate SLCD blink rate.
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate);
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /*!
<> 144:ef7eb2e8f9f7 399 * @brief Stops the SLCD blink mode.
<> 144:ef7eb2e8f9f7 400 *
<> 144:ef7eb2e8f9f7 401 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 static inline void SLCD_StopBlinkMode(LCD_Type *base)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 base->AR &= ~LCD_AR_BLINK_MASK;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /*!
<> 144:ef7eb2e8f9f7 409 * @brief Sets the SLCD back plane pin phase.
<> 144:ef7eb2e8f9f7 410 *
<> 144:ef7eb2e8f9f7 411 * This function sets the SLCD back plane pin phase. "kSLCD_PhaseXActivate" setting
<> 144:ef7eb2e8f9f7 412 * means the phase X is active for the back plane pin. "kSLCD_NoPhaseActivate" setting
<> 144:ef7eb2e8f9f7 413 * means there is no phase active for the back plane pin.
<> 144:ef7eb2e8f9f7 414 * register value.
<> 144:ef7eb2e8f9f7 415 * For example, set the back plane pin 20 for phase A:
<> 144:ef7eb2e8f9f7 416 * @code
<> 144:ef7eb2e8f9f7 417 * SLCD_SetBackPlanePhase(LCD, 20, kSLCD_PhaseAActivate);
<> 144:ef7eb2e8f9f7 418 * @endcode
<> 144:ef7eb2e8f9f7 419 *
<> 144:ef7eb2e8f9f7 420 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 421 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
<> 144:ef7eb2e8f9f7 422 * @param phase The phase activates for the back plane pin.
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 static inline void SLCD_SetBackPlanePhase(LCD_Type *base, uint32_t pinIndx, slcd_phase_type_t phase)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 base->WF8B[pinIndx] = phase;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /*!
<> 144:ef7eb2e8f9f7 430 * @brief Sets the SLCD front plane segment operation for a front plane pin.
<> 144:ef7eb2e8f9f7 431 *
<> 144:ef7eb2e8f9f7 432 * This function sets the SLCD front plane segment on or off operation.
<> 144:ef7eb2e8f9f7 433 * Each bit turns on or off the segments associated with the front plane pin in
<> 144:ef7eb2e8f9f7 434 * the following pattern: HGFEDCBA (most significant bit controls segment H and
<> 144:ef7eb2e8f9f7 435 * least significant bit controls segment A).
<> 144:ef7eb2e8f9f7 436 * For example, turn on the front plane pin 20 for phase B and phase C:
<> 144:ef7eb2e8f9f7 437 * @code
<> 144:ef7eb2e8f9f7 438 * SLCD_SetFrontPlaneSegments(LCD, 20, (kSLCD_PhaseBActivate | kSLCD_PhaseCActivate));
<> 144:ef7eb2e8f9f7 439 * @endcode
<> 144:ef7eb2e8f9f7 440 *
<> 144:ef7eb2e8f9f7 441 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 442 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
<> 144:ef7eb2e8f9f7 443 * @param operation The operation for the segment on the front plane pin.
<> 144:ef7eb2e8f9f7 444 * This is a logical OR of the enumeration :: slcd_phase_type_t.
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 static inline void SLCD_SetFrontPlaneSegments(LCD_Type *base, uint32_t pinIndx, uint8_t operation)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 base->WF8B[pinIndx] = operation;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /*!
<> 144:ef7eb2e8f9f7 452 * @brief Sets one SLCD front plane pin for one phase.
<> 144:ef7eb2e8f9f7 453 *
<> 144:ef7eb2e8f9f7 454 * This function can be used to set one phase on or off for the front plane pin.
<> 144:ef7eb2e8f9f7 455 * It can be call many times to set the plane pin for different phase indexes.
<> 144:ef7eb2e8f9f7 456 * For example, turn on the front plane pin 20 for phase B and phase C:
<> 144:ef7eb2e8f9f7 457 * @code
<> 144:ef7eb2e8f9f7 458 * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseBIndex, true);
<> 144:ef7eb2e8f9f7 459 * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseCIndex, true);
<> 144:ef7eb2e8f9f7 460 * @endcode
<> 144:ef7eb2e8f9f7 461 *
<> 144:ef7eb2e8f9f7 462 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 463 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
<> 144:ef7eb2e8f9f7 464 * @param phaseIndx The phase bit index @ref slcd_phase_index_t.
<> 144:ef7eb2e8f9f7 465 * @param enable True to turn on the segment for phaseIndx phase
<> 144:ef7eb2e8f9f7 466 * false to turn off the segment for phaseIndx phase.
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 static inline void SLCD_SetFrontPlaneOnePhase(LCD_Type *base,
<> 144:ef7eb2e8f9f7 469 uint32_t pinIndx,
<> 144:ef7eb2e8f9f7 470 slcd_phase_index_t phaseIndx,
<> 144:ef7eb2e8f9f7 471 bool enable)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 uint8_t reg = base->WF8B[pinIndx];
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 if (enable)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 base->WF8B[pinIndx] = (reg | (1U << phaseIndx));
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479 else
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 base->WF8B[pinIndx] = (reg & ~(1U << phaseIndx));
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #if FSL_FEATURE_SLCD_HAS_PAD_SAFE
<> 144:ef7eb2e8f9f7 486 /*!
<> 144:ef7eb2e8f9f7 487 * @brief Enables/disables the SLCD pad safe state.
<> 144:ef7eb2e8f9f7 488 *
<> 144:ef7eb2e8f9f7 489 * Forces the safe state on the LCD pad controls. All LCD front plane
<> 144:ef7eb2e8f9f7 490 * and backplane functions are disabled.
<> 144:ef7eb2e8f9f7 491 *
<> 144:ef7eb2e8f9f7 492 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 493 * @param enable True enable, false disable.
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 static inline void SLCD_EnablePadSafeState(LCD_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 if (enable)
<> 144:ef7eb2e8f9f7 498 { /* Enable. */
<> 144:ef7eb2e8f9f7 499 base->GCR |= LCD_GCR_PADSAFE_MASK;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 else
<> 144:ef7eb2e8f9f7 502 { /* Disable. */
<> 144:ef7eb2e8f9f7 503 base->GCR &= ~LCD_GCR_PADSAFE_MASK;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506 #endif /* FSL_FEATURE_SLCD_HAS_PAD_SAFE */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /*!
<> 144:ef7eb2e8f9f7 509 * @brief Gets the SLCD fault detect counter.
<> 144:ef7eb2e8f9f7 510 *
<> 144:ef7eb2e8f9f7 511 * This function gets the number of samples inside the
<> 144:ef7eb2e8f9f7 512 * fault detection sample window.
<> 144:ef7eb2e8f9f7 513 *
<> 144:ef7eb2e8f9f7 514 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 515 * @return The fault detect counter. The maximum return value is 255.
<> 144:ef7eb2e8f9f7 516 * If the maximum 255 returns, the overflow may happen.
<> 144:ef7eb2e8f9f7 517 * Reconfigure the fault detect sample window and fault detect clock prescaler
<> 144:ef7eb2e8f9f7 518 * for proper sampling.
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 static inline uint32_t SLCD_GetFaultDetectCounter(LCD_Type *base)
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 return base->FDSR & LCD_FDSR_FDCNT_MASK;
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* @} */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /*!
<> 144:ef7eb2e8f9f7 528 * @name Interrupts.
<> 144:ef7eb2e8f9f7 529 * @{
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /*!
<> 144:ef7eb2e8f9f7 533 * @brief Enables the SLCD interrupt.
<> 144:ef7eb2e8f9f7 534 * For example, to enable fault detect complete interrupt and frame frequency interrupt,
<> 144:ef7eb2e8f9f7 535 * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
<> 144:ef7eb2e8f9f7 536 * @code
<> 144:ef7eb2e8f9f7 537 * SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
<> 144:ef7eb2e8f9f7 538 * @endcode
<> 144:ef7eb2e8f9f7 539 *
<> 144:ef7eb2e8f9f7 540 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 541 * @param mask SLCD interrupts to enable. This is a logical OR of the
<> 144:ef7eb2e8f9f7 542 * enumeration :: slcd_interrupt_enable_t.
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544 void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /*!
<> 144:ef7eb2e8f9f7 547 * @brief Disables the SLCD interrupt.
<> 144:ef7eb2e8f9f7 548 * For example, to disable fault detect complete interrupt and frame frequency interrupt,
<> 144:ef7eb2e8f9f7 549 * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
<> 144:ef7eb2e8f9f7 550 * @code
<> 144:ef7eb2e8f9f7 551 * SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
<> 144:ef7eb2e8f9f7 552 * @endcode
<> 144:ef7eb2e8f9f7 553 *
<> 144:ef7eb2e8f9f7 554 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 555 * @param mask SLCD interrupts to disable. This is a logical OR of the
<> 144:ef7eb2e8f9f7 556 * enumeration :: slcd_interrupt_enable_t.
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /*!
<> 144:ef7eb2e8f9f7 561 * @brief Gets the SLCD interrupt status flag.
<> 144:ef7eb2e8f9f7 562 *
<> 144:ef7eb2e8f9f7 563 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 564 * @return The event status of the interrupt source. This is the logical OR of members
<> 144:ef7eb2e8f9f7 565 * of the enumeration :: slcd_interrupt_enable_t.
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 uint32_t SLCD_GetInterruptStatus(LCD_Type *base);
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /*!
<> 144:ef7eb2e8f9f7 570 * @brief Clears the SLCD interrupt events status flag.
<> 144:ef7eb2e8f9f7 571 *
<> 144:ef7eb2e8f9f7 572 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 573 * @param mask SLCD interrupt source to be cleared.
<> 144:ef7eb2e8f9f7 574 * This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* @} */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 #endif /* __cplusplus*/
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /*! @}*/
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 #endif /* _FSL_SLCD_H_*/