Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_flexio_uart_dma.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_flexio_uart_dma.h"
<> 144:ef7eb2e8f9f7 32 #include "fsl_dmamux.h"
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /*******************************************************************************
<> 144:ef7eb2e8f9f7 35 * Definitions
<> 144:ef7eb2e8f9f7 36 ******************************************************************************/
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /*<! @brief Structure definition for DMA callback param pass in. */
<> 144:ef7eb2e8f9f7 39 typedef struct _flexio_uart_dma_private_handle
<> 144:ef7eb2e8f9f7 40 {
<> 144:ef7eb2e8f9f7 41 FLEXIO_UART_Type *base;
<> 144:ef7eb2e8f9f7 42 flexio_uart_dma_handle_t *handle;
<> 144:ef7eb2e8f9f7 43 } flexio_uart_dma_private_handle_t;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /*<! @brief uart transfer state. */
<> 144:ef7eb2e8f9f7 46 enum _flexio_uart_dma_transfer_states
<> 144:ef7eb2e8f9f7 47 {
<> 144:ef7eb2e8f9f7 48 kFLEXIO_UART_TxIdle, /* TX idle. */
<> 144:ef7eb2e8f9f7 49 kFLEXIO_UART_TxBusy, /* TX busy. */
<> 144:ef7eb2e8f9f7 50 kFLEXIO_UART_RxIdle, /* RX idle. */
<> 144:ef7eb2e8f9f7 51 kFLEXIO_UART_RxBusy /* RX busy. */
<> 144:ef7eb2e8f9f7 52 };
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /*******************************************************************************
<> 144:ef7eb2e8f9f7 55 * Variables
<> 144:ef7eb2e8f9f7 56 ******************************************************************************/
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /*< @brief user configurable flexio uart handle count. */
<> 144:ef7eb2e8f9f7 59 #define FLEXIO_UART_HANDLE_COUNT 2
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*<! Private handle only used for internally. */
<> 144:ef7eb2e8f9f7 62 static flexio_uart_dma_private_handle_t s_dmaPrivateHandle[FLEXIO_UART_HANDLE_COUNT];
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*******************************************************************************
<> 144:ef7eb2e8f9f7 65 * Prototypes
<> 144:ef7eb2e8f9f7 66 ******************************************************************************/
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /*!
<> 144:ef7eb2e8f9f7 69 * @brief FLEXIO UART DMA send finished callback function.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * This function is called when FLEXIO UART DMA send finished. It disables the UART
<> 144:ef7eb2e8f9f7 72 * TX DMA request and sends @ref kStatus_FLEXIO_UART_TxIdle to FLEXIO UART callback.
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * @param handle The DMA handle.
<> 144:ef7eb2e8f9f7 75 * @param param Callback function parameter.
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 static void FLEXIO_UART_TransferSendDMACallback(dma_handle_t *handle, void *param);
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /*!
<> 144:ef7eb2e8f9f7 80 * @brief FLEXIO UART DMA receive finished callback function.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 * This function is called when FLEXIO UART DMA receive finished. It disables the FLEXIO
<> 144:ef7eb2e8f9f7 83 * UART RX DMA request and sends @ref kStatus_FLEXIO_UART_RxIdle to UART callback.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 * @param handle The DMA handle.
<> 144:ef7eb2e8f9f7 86 * @param param Callback function parameter.
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 static void FLEXIO_UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /*******************************************************************************
<> 144:ef7eb2e8f9f7 91 * Code
<> 144:ef7eb2e8f9f7 92 ******************************************************************************/
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 static void FLEXIO_UART_TransferSendDMACallback(dma_handle_t *handle, void *param)
<> 144:ef7eb2e8f9f7 95 {
<> 144:ef7eb2e8f9f7 96 flexio_uart_dma_private_handle_t *uartPrivateHandle = (flexio_uart_dma_private_handle_t *)param;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Disable UART TX DMA. */
<> 144:ef7eb2e8f9f7 99 FLEXIO_UART_EnableTxDMA(uartPrivateHandle->base, false);
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Disable interrupt. */
<> 144:ef7eb2e8f9f7 102 DMA_DisableInterrupts(handle->base, handle->channel);
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uartPrivateHandle->handle->txState = kFLEXIO_UART_TxIdle;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 if (uartPrivateHandle->handle->callback)
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle,
<> 144:ef7eb2e8f9f7 109 kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData);
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 static void FLEXIO_UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 flexio_uart_dma_private_handle_t *uartPrivateHandle = (flexio_uart_dma_private_handle_t *)param;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Disable UART RX DMA. */
<> 144:ef7eb2e8f9f7 118 FLEXIO_UART_EnableRxDMA(uartPrivateHandle->base, false);
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Disable interrupt. */
<> 144:ef7eb2e8f9f7 121 DMA_DisableInterrupts(handle->base, handle->channel);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 uartPrivateHandle->handle->rxState = kFLEXIO_UART_RxIdle;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 if (uartPrivateHandle->handle->callback)
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle,
<> 144:ef7eb2e8f9f7 128 kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData);
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130 }
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 status_t FLEXIO_UART_TransferCreateHandleDMA(FLEXIO_UART_Type *base,
<> 144:ef7eb2e8f9f7 133 flexio_uart_dma_handle_t *handle,
<> 144:ef7eb2e8f9f7 134 flexio_uart_dma_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 135 void *userData,
<> 144:ef7eb2e8f9f7 136 dma_handle_t *txDmaHandle,
<> 144:ef7eb2e8f9f7 137 dma_handle_t *rxDmaHandle)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 assert(handle);
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 dma_transfer_config_t dmaXferConfig;
<> 144:ef7eb2e8f9f7 142 uint8_t index = 0;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Find the an empty handle pointer to store the handle. */
<> 144:ef7eb2e8f9f7 145 for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 if (s_dmaPrivateHandle[index].base == NULL)
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 s_dmaPrivateHandle[index].base = base;
<> 144:ef7eb2e8f9f7 150 s_dmaPrivateHandle[index].handle = handle;
<> 144:ef7eb2e8f9f7 151 break;
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 if (index == FLEXIO_UART_HANDLE_COUNT)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 return kStatus_OutOfRange;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 memset(handle, 0, sizeof(*handle));
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 handle->rxState = kFLEXIO_UART_RxIdle;
<> 144:ef7eb2e8f9f7 163 handle->txState = kFLEXIO_UART_TxIdle;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 handle->callback = callback;
<> 144:ef7eb2e8f9f7 166 handle->userData = userData;
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 handle->rxDmaHandle = rxDmaHandle;
<> 144:ef7eb2e8f9f7 169 handle->txDmaHandle = txDmaHandle;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Set DMA channel configuration. */
<> 144:ef7eb2e8f9f7 172 memset(&dmaXferConfig, 0, sizeof(dmaXferConfig));
<> 144:ef7eb2e8f9f7 173 dmaXferConfig.srcSize = kDMA_Transfersize8bits;
<> 144:ef7eb2e8f9f7 174 dmaXferConfig.destSize = kDMA_Transfersize8bits;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Configure TX. */
<> 144:ef7eb2e8f9f7 177 if (txDmaHandle)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 DMA_SetCallback(txDmaHandle, FLEXIO_UART_TransferSendDMACallback, &s_dmaPrivateHandle[index]);
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 DMA_ResetChannel(txDmaHandle->base, txDmaHandle->channel);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 dmaXferConfig.destAddr = FLEXIO_UART_GetTxDataRegisterAddress(base);
<> 144:ef7eb2e8f9f7 184 dmaXferConfig.enableSrcIncrement = true;
<> 144:ef7eb2e8f9f7 185 dmaXferConfig.enableDestIncrement = false;
<> 144:ef7eb2e8f9f7 186 DMA_SetTransferConfig(txDmaHandle->base, txDmaHandle->channel, &dmaXferConfig);
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Configure RX. */
<> 144:ef7eb2e8f9f7 190 if (rxDmaHandle)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 DMA_SetCallback(rxDmaHandle, FLEXIO_UART_TransferReceiveDMACallback, &s_dmaPrivateHandle[index]);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 DMA_ResetChannel(rxDmaHandle->base, rxDmaHandle->channel);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 dmaXferConfig.destAddr = 0U;
<> 144:ef7eb2e8f9f7 197 dmaXferConfig.srcAddr = FLEXIO_UART_GetRxDataRegisterAddress(base);
<> 144:ef7eb2e8f9f7 198 dmaXferConfig.enableSrcIncrement = false;
<> 144:ef7eb2e8f9f7 199 dmaXferConfig.enableDestIncrement = true;
<> 144:ef7eb2e8f9f7 200 DMA_SetTransferConfig(rxDmaHandle->base, rxDmaHandle->channel, &dmaXferConfig);
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 return kStatus_Success;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 status_t FLEXIO_UART_TransferSendDMA(FLEXIO_UART_Type *base,
<> 144:ef7eb2e8f9f7 207 flexio_uart_dma_handle_t *handle,
<> 144:ef7eb2e8f9f7 208 flexio_uart_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 status_t status;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Return error if xfer invalid. */
<> 144:ef7eb2e8f9f7 215 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* If previous TX not finished. */
<> 144:ef7eb2e8f9f7 221 if (kFLEXIO_UART_TxBusy == handle->txState)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 status = kStatus_FLEXIO_UART_TxBusy;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225 else
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 handle->txState = kFLEXIO_UART_TxBusy;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Set transfer data address and data size. */
<> 144:ef7eb2e8f9f7 230 DMA_SetSourceAddress(handle->txDmaHandle->base, handle->txDmaHandle->channel, (uint32_t)xfer->data);
<> 144:ef7eb2e8f9f7 231 DMA_SetTransferSize(handle->txDmaHandle->base, handle->txDmaHandle->channel, xfer->dataSize);
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Enable FLEXIO UART TX DMA. */
<> 144:ef7eb2e8f9f7 234 FLEXIO_UART_EnableTxDMA(base, true);
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Enable DMA transfer complete interrupt and start transfer. */
<> 144:ef7eb2e8f9f7 237 DMA_EnableInterrupts(handle->txDmaHandle->base, handle->txDmaHandle->channel);
<> 144:ef7eb2e8f9f7 238 DMA_EnableChannelRequest(handle->txDmaHandle->base, handle->txDmaHandle->channel);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 status = kStatus_Success;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 return status;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 status_t FLEXIO_UART_TransferReceiveDMA(FLEXIO_UART_Type *base,
<> 144:ef7eb2e8f9f7 247 flexio_uart_dma_handle_t *handle,
<> 144:ef7eb2e8f9f7 248 flexio_uart_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 status_t status;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Return error if xfer invalid. */
<> 144:ef7eb2e8f9f7 255 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* If previous RX not finished. */
<> 144:ef7eb2e8f9f7 261 if (kFLEXIO_UART_RxBusy == handle->rxState)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 status = kStatus_FLEXIO_UART_RxBusy;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265 else
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 handle->rxState = kFLEXIO_UART_RxBusy;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Set transfer data address and data size. */
<> 144:ef7eb2e8f9f7 270 DMA_SetDestinationAddress(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, (uint32_t)xfer->data);
<> 144:ef7eb2e8f9f7 271 DMA_SetTransferSize(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, xfer->dataSize);
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Enable FLEXIO UART RX DMA. */
<> 144:ef7eb2e8f9f7 274 FLEXIO_UART_EnableRxDMA(base, true);
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Enable DMA transfer complete interrupt and start transfer. */
<> 144:ef7eb2e8f9f7 277 DMA_EnableInterrupts(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
<> 144:ef7eb2e8f9f7 278 DMA_EnableChannelRequest(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 status = kStatus_Success;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 return status;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 void FLEXIO_UART_TransferAbortSendDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Disable FLEXIO UART TX DMA. */
<> 144:ef7eb2e8f9f7 291 FLEXIO_UART_EnableTxDMA(base, false);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Stop transfer. */
<> 144:ef7eb2e8f9f7 294 DMA_StopTransfer(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 144:ef7eb2e8f9f7 297 DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 handle->txState = kFLEXIO_UART_TxIdle;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 void FLEXIO_UART_TransferAbortReceiveDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Disable FLEXIO UART RX DMA. */
<> 144:ef7eb2e8f9f7 307 FLEXIO_UART_EnableRxDMA(base, false);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Stop transfer. */
<> 144:ef7eb2e8f9f7 310 DMA_StopTransfer(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 144:ef7eb2e8f9f7 313 DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 handle->rxState = kFLEXIO_UART_RxIdle;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 status_t FLEXIO_UART_TransferGetSendCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 if (!count)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 if (kFLEXIO_UART_TxBusy == handle->txState)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 *count = (handle->txSize - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel));
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331 else
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 *count = handle->txSize;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 return kStatus_Success;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 status_t FLEXIO_UART_TransferGetReceiveCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 if (!count)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 if (kFLEXIO_UART_RxBusy == handle->rxState)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 *count = (handle->rxSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel));
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352 else
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 *count = handle->rxSize;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 return kStatus_Success;
<> 144:ef7eb2e8f9f7 358 }