Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_flexio_i2c_master.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_flexio_i2c_master.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitions
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /*! @brief FLEXIO I2C transfer state */
<> 144:ef7eb2e8f9f7 38 enum _flexio_i2c_master_transfer_states
<> 144:ef7eb2e8f9f7 39 {
<> 144:ef7eb2e8f9f7 40 kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */
<> 144:ef7eb2e8f9f7 41 kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */
<> 144:ef7eb2e8f9f7 42 kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */
<> 144:ef7eb2e8f9f7 43 kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/
<> 144:ef7eb2e8f9f7 44 kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
<> 144:ef7eb2e8f9f7 45 kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/
<> 144:ef7eb2e8f9f7 46 };
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /*******************************************************************************
<> 144:ef7eb2e8f9f7 49 * Prototypes
<> 144:ef7eb2e8f9f7 50 ******************************************************************************/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*!
<> 144:ef7eb2e8f9f7 53 * @brief Set up master transfer, send slave address and decide the initial
<> 144:ef7eb2e8f9f7 54 * transfer state.
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * @param base pointer to FLEXIO_I2C_Type structure
<> 144:ef7eb2e8f9f7 57 * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 58 * @param transfer pointer to flexio_i2c_master_transfer_t structure
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 61 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 62 flexio_i2c_master_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*!
<> 144:ef7eb2e8f9f7 65 * @brief Master run transfer state machine to perform a byte of transfer.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * @param base pointer to FLEXIO_I2C_Type structure
<> 144:ef7eb2e8f9f7 68 * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 69 * @param statusFlags flexio i2c hardware status
<> 144:ef7eb2e8f9f7 70 * @retval kStatus_Success Successfully run state machine
<> 144:ef7eb2e8f9f7 71 * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 74 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 75 uint32_t statusFlags);
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /*!
<> 144:ef7eb2e8f9f7 78 * @brief Complete transfer, disable interrupt and call callback.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * @param base pointer to FLEXIO_I2C_Type structure
<> 144:ef7eb2e8f9f7 81 * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 82 * @param status flexio transfer status
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 85 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 86 status_t status);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /*******************************************************************************
<> 144:ef7eb2e8f9f7 89 * Codes
<> 144:ef7eb2e8f9f7 90 ******************************************************************************/
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 93 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 94 flexio_i2c_master_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 95 {
<> 144:ef7eb2e8f9f7 96 bool needRestart;
<> 144:ef7eb2e8f9f7 97 uint32_t byteCount;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Init the handle member. */
<> 144:ef7eb2e8f9f7 100 handle->transfer.slaveAddress = xfer->slaveAddress;
<> 144:ef7eb2e8f9f7 101 handle->transfer.direction = xfer->direction;
<> 144:ef7eb2e8f9f7 102 handle->transfer.subaddress = xfer->subaddress;
<> 144:ef7eb2e8f9f7 103 handle->transfer.subaddressSize = xfer->subaddressSize;
<> 144:ef7eb2e8f9f7 104 handle->transfer.data = xfer->data;
<> 144:ef7eb2e8f9f7 105 handle->transfer.dataSize = xfer->dataSize;
<> 144:ef7eb2e8f9f7 106 handle->transfer.flags = xfer->flags;
<> 144:ef7eb2e8f9f7 107 handle->transferSize = xfer->dataSize;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Initial state, i2c check address state. */
<> 144:ef7eb2e8f9f7 110 handle->state = kFLEXIO_I2C_CheckAddress;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Clear all status before transfer. */
<> 144:ef7eb2e8f9f7 113 FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag);
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Calculate whether need to send re-start. */
<> 144:ef7eb2e8f9f7 116 needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Calculate total byte count in a frame. */
<> 144:ef7eb2e8f9f7 119 byteCount = 1;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 if (!needRestart)
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 byteCount += handle->transfer.dataSize;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 if (handle->transfer.subaddressSize != 0)
<> 144:ef7eb2e8f9f7 127 {
<> 144:ef7eb2e8f9f7 128 byteCount += handle->transfer.subaddressSize;
<> 144:ef7eb2e8f9f7 129 /* Next state, send command byte. */
<> 144:ef7eb2e8f9f7 130 handle->state = kFLEXIO_I2C_SendCommand;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Configure data count. */
<> 144:ef7eb2e8f9f7 134 if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success)
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Send address byte first. */
<> 144:ef7eb2e8f9f7 144 if (needRestart)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write);
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148 else
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction);
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 return kStatus_Success;
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 157 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 158 uint32_t statusFlags)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 /* Clear receive nak flag. */
<> 144:ef7eb2e8f9f7 163 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) &&
<> 144:ef7eb2e8f9f7 166 (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) &&
<> 144:ef7eb2e8f9f7 167 (handle->transfer.dataSize == 1U))))
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 FLEXIO_I2C_MasterReadByte(base);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 FLEXIO_I2C_MasterAbortStop(base);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 handle->state = kFLEXIO_I2C_Idle;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 return kStatus_FLEXIO_I2C_Nak;
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 if (handle->state == kFLEXIO_I2C_CheckAddress)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 if (handle->transfer.direction == kFLEXIO_I2C_Write)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 /* Next state, send data. */
<> 144:ef7eb2e8f9f7 184 handle->state = kFLEXIO_I2C_SendData;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 else
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 /* Next state, receive data begin. */
<> 144:ef7eb2e8f9f7 189 handle->state = kFLEXIO_I2C_ReceiveDataBegin;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData))
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 FLEXIO_I2C_MasterReadByte(base);
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 switch (handle->state)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 case kFLEXIO_I2C_SendCommand:
<> 144:ef7eb2e8f9f7 201 if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 if (handle->transfer.subaddressSize > 0)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 handle->transfer.subaddressSize--;
<> 144:ef7eb2e8f9f7 206 FLEXIO_I2C_MasterWriteByte(
<> 144:ef7eb2e8f9f7 207 base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)));
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 if (handle->transfer.subaddressSize == 0)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 /* Load re-start in advance. */
<> 144:ef7eb2e8f9f7 212 if (handle->transfer.direction == kFLEXIO_I2C_Read)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217 FLEXIO_I2C_MasterRepeatedStart(base);
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221 else
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 if (handle->transfer.direction == kFLEXIO_I2C_Write)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 /* Next state, send data. */
<> 144:ef7eb2e8f9f7 226 handle->state = kFLEXIO_I2C_SendData;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Send first byte of data. */
<> 144:ef7eb2e8f9f7 229 if (handle->transfer.dataSize > 0)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 handle->transfer.data++;
<> 144:ef7eb2e8f9f7 234 handle->transfer.dataSize--;
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 else
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1));
<> 144:ef7eb2e8f9f7 240 FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Next state, receive data begin. */
<> 144:ef7eb2e8f9f7 243 handle->state = kFLEXIO_I2C_ReceiveDataBegin;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 break;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Send command byte. */
<> 144:ef7eb2e8f9f7 250 case kFLEXIO_I2C_SendData:
<> 144:ef7eb2e8f9f7 251 if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 /* Send one byte of data. */
<> 144:ef7eb2e8f9f7 254 if (handle->transfer.dataSize > 0)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 handle->transfer.data++;
<> 144:ef7eb2e8f9f7 259 handle->transfer.dataSize--;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 else
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 FLEXIO_I2C_MasterStop(base);
<> 144:ef7eb2e8f9f7 264 handle->state = kFLEXIO_I2C_Idle;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267 break;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 case kFLEXIO_I2C_ReceiveDataBegin:
<> 144:ef7eb2e8f9f7 270 if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 /* Read one byte of data. */
<> 144:ef7eb2e8f9f7 273 FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Send nak at the last receive byte. */
<> 144:ef7eb2e8f9f7 276 if (handle->transfer.dataSize == 1)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 FLEXIO_I2C_MasterEnableAck(base, false);
<> 144:ef7eb2e8f9f7 279 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282 FLEXIO_I2C_MasterStop(base);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 else
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 FLEXIO_I2C_MasterEnableAck(base, true);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289 else
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 handle->state = kFLEXIO_I2C_ReceiveData;
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 break;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 case kFLEXIO_I2C_ReceiveData:
<> 144:ef7eb2e8f9f7 296 if (statusFlags & kFLEXIO_I2C_RxFullFlag)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base);
<> 144:ef7eb2e8f9f7 299 handle->transfer.data++;
<> 144:ef7eb2e8f9f7 300 /* Receive one byte of data. */
<> 144:ef7eb2e8f9f7 301 if (handle->transfer.dataSize--)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 if (handle->transfer.dataSize != 0)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 else
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable);
<> 144:ef7eb2e8f9f7 310 handle->state = kFLEXIO_I2C_Idle;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Send nak at the last receive byte. */
<> 144:ef7eb2e8f9f7 314 if (handle->transfer.dataSize == 1)
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 FLEXIO_I2C_MasterEnableAck(base, false);
<> 144:ef7eb2e8f9f7 317 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320 FLEXIO_I2C_MasterStop(base);
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 break;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 default:
<> 144:ef7eb2e8f9f7 327 break;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 return kStatus_Success;
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 334 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 335 status_t status)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 if (handle->completionCallback)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 handle->completionCallback(base, handle, status, handle->userData);
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 void FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 assert(base && masterConfig);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 flexio_shifter_config_t shifterConfig;
<> 144:ef7eb2e8f9f7 350 flexio_timer_config_t timerConfig;
<> 144:ef7eb2e8f9f7 351 uint32_t controlVal = 0;
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 memset(&shifterConfig, 0, sizeof(shifterConfig));
<> 144:ef7eb2e8f9f7 354 memset(&timerConfig, 0, sizeof(timerConfig));
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Ungate flexio clock. */
<> 144:ef7eb2e8f9f7 357 CLOCK_EnableClock(kCLOCK_Flexio0);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 FLEXIO_Reset(base->flexioBase);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Do hardware configuration. */
<> 144:ef7eb2e8f9f7 362 /* 1. Configure the shifter 0 for tx. */
<> 144:ef7eb2e8f9f7 363 shifterConfig.timerSelect = base->timerIndex[1];
<> 144:ef7eb2e8f9f7 364 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
<> 144:ef7eb2e8f9f7 365 shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
<> 144:ef7eb2e8f9f7 366 shifterConfig.pinSelect = base->SDAPinIndex;
<> 144:ef7eb2e8f9f7 367 shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
<> 144:ef7eb2e8f9f7 368 shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
<> 144:ef7eb2e8f9f7 369 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
<> 144:ef7eb2e8f9f7 370 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
<> 144:ef7eb2e8f9f7 371 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* 2. Configure the shifter 1 for rx. */
<> 144:ef7eb2e8f9f7 376 shifterConfig.timerSelect = base->timerIndex[1];
<> 144:ef7eb2e8f9f7 377 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
<> 144:ef7eb2e8f9f7 378 shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
<> 144:ef7eb2e8f9f7 379 shifterConfig.pinSelect = base->SDAPinIndex;
<> 144:ef7eb2e8f9f7 380 shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 144:ef7eb2e8f9f7 381 shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
<> 144:ef7eb2e8f9f7 382 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
<> 144:ef7eb2e8f9f7 383 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
<> 144:ef7eb2e8f9f7 384 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /*3. Configure the timer 0 for generating bit clock. */
<> 144:ef7eb2e8f9f7 389 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
<> 144:ef7eb2e8f9f7 390 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
<> 144:ef7eb2e8f9f7 391 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
<> 144:ef7eb2e8f9f7 392 timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
<> 144:ef7eb2e8f9f7 393 timerConfig.pinSelect = base->SCLPinIndex;
<> 144:ef7eb2e8f9f7 394 timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 144:ef7eb2e8f9f7 395 timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
<> 144:ef7eb2e8f9f7 396 timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
<> 144:ef7eb2e8f9f7 397 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
<> 144:ef7eb2e8f9f7 398 timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
<> 144:ef7eb2e8f9f7 399 timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
<> 144:ef7eb2e8f9f7 400 timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
<> 144:ef7eb2e8f9f7 401 timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
<> 144:ef7eb2e8f9f7 402 timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */
<> 144:ef7eb2e8f9f7 405 timerConfig.timerCompare = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* 4. Configure the timer 1 for controlling shifters. */
<> 144:ef7eb2e8f9f7 410 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
<> 144:ef7eb2e8f9f7 411 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
<> 144:ef7eb2e8f9f7 412 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
<> 144:ef7eb2e8f9f7 413 timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
<> 144:ef7eb2e8f9f7 414 timerConfig.pinSelect = base->SCLPinIndex;
<> 144:ef7eb2e8f9f7 415 timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
<> 144:ef7eb2e8f9f7 416 timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
<> 144:ef7eb2e8f9f7 417 timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
<> 144:ef7eb2e8f9f7 418 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
<> 144:ef7eb2e8f9f7 419 timerConfig.timerReset = kFLEXIO_TimerResetNever;
<> 144:ef7eb2e8f9f7 420 timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
<> 144:ef7eb2e8f9f7 421 timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
<> 144:ef7eb2e8f9f7 422 timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
<> 144:ef7eb2e8f9f7 423 timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
<> 144:ef7eb2e8f9f7 426 timerConfig.timerCompare = 8 * 2 - 1;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Configure FLEXIO I2C Master. */
<> 144:ef7eb2e8f9f7 431 controlVal = base->flexioBase->CTRL;
<> 144:ef7eb2e8f9f7 432 controlVal &=
<> 144:ef7eb2e8f9f7 433 ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
<> 144:ef7eb2e8f9f7 434 controlVal |=
<> 144:ef7eb2e8f9f7 435 (FLEXIO_CTRL_DOZEN(masterConfig->enableInDoze) | FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) |
<> 144:ef7eb2e8f9f7 436 FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 base->flexioBase->CTRL = controlVal;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 FLEXIO_Deinit(base->flexioBase);
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 assert(masterConfig);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 masterConfig->enableMaster = true;
<> 144:ef7eb2e8f9f7 451 masterConfig->enableInDoze = false;
<> 144:ef7eb2e8f9f7 452 masterConfig->enableInDebug = true;
<> 144:ef7eb2e8f9f7 453 masterConfig->enableFastAccess = false;
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Default baud rate at 100kbps. */
<> 144:ef7eb2e8f9f7 456 masterConfig->baudRate_Bps = 100000U;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 uint32_t status = 0;
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 status =
<> 144:ef7eb2e8f9f7 464 ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
<> 144:ef7eb2e8f9f7 465 status |=
<> 144:ef7eb2e8f9f7 466 (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
<> 144:ef7eb2e8f9f7 467 << 1U);
<> 144:ef7eb2e8f9f7 468 status |=
<> 144:ef7eb2e8f9f7 469 (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
<> 144:ef7eb2e8f9f7 470 << 2U);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 return status;
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 if (mask & kFLEXIO_I2C_TxEmptyFlag)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 if (mask & kFLEXIO_I2C_RxFullFlag)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 if (mask & kFLEXIO_I2C_ReceiveNakFlag)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499 if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 uint16_t timerDiv = 0;
<> 144:ef7eb2e8f9f7 520 uint16_t timerCmp = 0;
<> 144:ef7eb2e8f9f7 521 FLEXIO_Type *flexioBase = base->flexioBase;
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
<> 144:ef7eb2e8f9f7 524 timerDiv = srcClock_Hz / baudRate_Bps;
<> 144:ef7eb2e8f9f7 525 timerDiv = timerDiv / 2 - 1U;
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
<> 144:ef7eb2e8f9f7 528 timerCmp &= 0xFF00;
<> 144:ef7eb2e8f9f7 529 timerCmp |= timerDiv;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 if (count > 14U)
<> 144:ef7eb2e8f9f7 537 {
<> 144:ef7eb2e8f9f7 538 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 uint16_t timerCmp = 0;
<> 144:ef7eb2e8f9f7 542 uint32_t timerConfig = 0;
<> 144:ef7eb2e8f9f7 543 FLEXIO_Type *flexioBase = base->flexioBase;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
<> 144:ef7eb2e8f9f7 546 timerCmp &= 0x00FFU;
<> 144:ef7eb2e8f9f7 547 timerCmp |= (count * 18 + 1U) << 8U;
<> 144:ef7eb2e8f9f7 548 flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
<> 144:ef7eb2e8f9f7 549 timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
<> 144:ef7eb2e8f9f7 550 timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
<> 144:ef7eb2e8f9f7 551 timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
<> 144:ef7eb2e8f9f7 552 flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 return kStatus_Success;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 uint32_t data;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 FLEXIO_I2C_MasterWriteByte(base, data);
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 /* Prepare for RESTART condition, no stop.*/
<> 144:ef7eb2e8f9f7 569 FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 /* Prepare normal stop. */
<> 144:ef7eb2e8f9f7 575 FLEXIO_I2C_MasterSetTransferCount(base, 0x0U);
<> 144:ef7eb2e8f9f7 576 FLEXIO_I2C_MasterWriteByte(base, 0x0U);
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 uint32_t tmpConfig;
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Prepare abort stop. */
<> 144:ef7eb2e8f9f7 584 tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]];
<> 144:ef7eb2e8f9f7 585 tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
<> 144:ef7eb2e8f9f7 586 tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge);
<> 144:ef7eb2e8f9f7 587 base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 uint32_t tmpConfig = 0;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]];
<> 144:ef7eb2e8f9f7 595 tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK;
<> 144:ef7eb2e8f9f7 596 if (enable)
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow);
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600 else
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh);
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604 base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 assert(txBuff);
<> 144:ef7eb2e8f9f7 610 assert(txSize);
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 uint32_t status;
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 while (txSize--)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 FLEXIO_I2C_MasterWriteByte(base, *txBuff++);
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Wait until data transfer complete. */
<> 144:ef7eb2e8f9f7 619 while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag))
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 if (status & kFLEXIO_I2C_ReceiveNakFlag)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
<> 144:ef7eb2e8f9f7 626 return kStatus_FLEXIO_I2C_Nak;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629 return kStatus_Success;
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 assert(rxBuff);
<> 144:ef7eb2e8f9f7 635 assert(rxSize);
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 while (rxSize--)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* Wait until data transfer complete. */
<> 144:ef7eb2e8f9f7 640 while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 *rxBuff++ = FLEXIO_I2C_MasterReadByte(base);
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 649 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 650 flexio_i2c_master_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 651 void *userData)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 assert(handle);
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Zero the handle. */
<> 144:ef7eb2e8f9f7 658 memset(handle, 0, sizeof(*handle));
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Register callback and userData. */
<> 144:ef7eb2e8f9f7 661 handle->completionCallback = callback;
<> 144:ef7eb2e8f9f7 662 handle->userData = userData;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Enable interrupt in NVIC. */
<> 144:ef7eb2e8f9f7 665 EnableIRQ(flexio_irqs[0]);
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Save the context in global variables to support the double weak mechanism. */
<> 144:ef7eb2e8f9f7 668 return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
<> 144:ef7eb2e8f9f7 672 flexio_i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 673 flexio_i2c_master_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 assert(handle);
<> 144:ef7eb2e8f9f7 676 assert(xfer);
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 if (handle->state != kFLEXIO_I2C_Idle)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 return kStatus_FLEXIO_I2C_Busy;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 else
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 /* Set up transfer machine. */
<> 144:ef7eb2e8f9f7 685 FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Enable both tx empty and rxfull interrupt. */
<> 144:ef7eb2e8f9f7 688 FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 return kStatus_Success;
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 assert(handle);
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Disable interrupts. */
<> 144:ef7eb2e8f9f7 699 FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Reset to idle state. */
<> 144:ef7eb2e8f9f7 702 handle->state = kFLEXIO_I2C_Idle;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
<> 144:ef7eb2e8f9f7 706 {
<> 144:ef7eb2e8f9f7 707 if (!count)
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 *count = handle->transferSize - handle->transfer.dataSize;
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 return kStatus_Success;
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
<> 144:ef7eb2e8f9f7 720 flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
<> 144:ef7eb2e8f9f7 721 uint32_t statusFlags;
<> 144:ef7eb2e8f9f7 722 status_t result;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base);
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags);
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 if (handle->state == kFLEXIO_I2C_Idle)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 FLEXIO_I2C_MasterTransferComplete(base, handle, result);
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732 }