Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sdhc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_SDHC_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_SDHC_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup sdhc
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions.
<> 144:ef7eb2e8f9f7 44 *****************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief Driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief Maximum block count can be set one time */
<> 144:ef7eb2e8f9f7 53 #define SDHC_MAX_BLOCK_COUNT (SDHC_BLKATTR_BLKCNT_MASK >> SDHC_BLKATTR_BLKCNT_SHIFT)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*! @brief SDHC status */
<> 144:ef7eb2e8f9f7 56 enum _sdhc_status
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 kStatus_SDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_SDHC, 0U), /*!< Transfer is on-going */
<> 144:ef7eb2e8f9f7 59 kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */
<> 144:ef7eb2e8f9f7 60 kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U), /*!< Send command failed */
<> 144:ef7eb2e8f9f7 61 kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U), /*!< Transfer data failed */
<> 144:ef7eb2e8f9f7 62 };
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*! @brief Host controller capabilities flag mask */
<> 144:ef7eb2e8f9f7 65 enum _sdhc_capability_flag
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 kSDHC_SupportAdmaFlag = SDHC_HTCAPBLT_ADMAS_MASK, /*!< Support ADMA */
<> 144:ef7eb2e8f9f7 68 kSDHC_SupportHighSpeedFlag = SDHC_HTCAPBLT_HSS_MASK, /*!< Support high-speed */
<> 144:ef7eb2e8f9f7 69 kSDHC_SupportDmaFlag = SDHC_HTCAPBLT_DMAS_MASK, /*!< Support DMA */
<> 144:ef7eb2e8f9f7 70 kSDHC_SupportSuspendResumeFlag = SDHC_HTCAPBLT_SRS_MASK, /*!< Support suspend/resume */
<> 144:ef7eb2e8f9f7 71 kSDHC_SupportV330Flag = SDHC_HTCAPBLT_VS33_MASK, /*!< Support voltage 3.3V */
<> 144:ef7eb2e8f9f7 72 #if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT
<> 144:ef7eb2e8f9f7 73 kSDHC_SupportV300Flag = SDHC_HTCAPBLT_VS30_MASK, /*!< Support voltage 3.0V */
<> 144:ef7eb2e8f9f7 74 #endif
<> 144:ef7eb2e8f9f7 75 #if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT
<> 144:ef7eb2e8f9f7 76 kSDHC_SupportV180Flag = SDHC_HTCAPBLT_VS18_MASK, /*!< Support voltage 1.8V */
<> 144:ef7eb2e8f9f7 77 #endif
<> 144:ef7eb2e8f9f7 78 /* Put additional two flags in HTCAPBLT_MBL's position. */
<> 144:ef7eb2e8f9f7 79 kSDHC_Support4BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 0U), /*!< Support 4 bit mode */
<> 144:ef7eb2e8f9f7 80 kSDHC_Support8BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 1U), /*!< Support 8 bit mode */
<> 144:ef7eb2e8f9f7 81 };
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /*! @brief Wakeup event mask */
<> 144:ef7eb2e8f9f7 84 enum _sdhc_wakeup_event
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 kSDHC_WakeupEventOnCardInt = SDHC_PROCTL_WECINT_MASK, /*!< Wakeup on card interrupt */
<> 144:ef7eb2e8f9f7 87 kSDHC_WakeupEventOnCardInsert = SDHC_PROCTL_WECINS_MASK, /*!< Wakeup on card insertion */
<> 144:ef7eb2e8f9f7 88 kSDHC_WakeupEventOnCardRemove = SDHC_PROCTL_WECRM_MASK, /*!< Wakeup on card removal */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 kSDHC_WakeupEventsAll = (kSDHC_WakeupEventOnCardInt | kSDHC_WakeupEventOnCardInsert |
<> 144:ef7eb2e8f9f7 91 kSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */
<> 144:ef7eb2e8f9f7 92 };
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /*! @brief Reset type mask */
<> 144:ef7eb2e8f9f7 95 enum _sdhc_reset
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97 kSDHC_ResetAll = SDHC_SYSCTL_RSTA_MASK, /*!< Reset all except card detection */
<> 144:ef7eb2e8f9f7 98 kSDHC_ResetCommand = SDHC_SYSCTL_RSTC_MASK, /*!< Reset command line */
<> 144:ef7eb2e8f9f7 99 kSDHC_ResetData = SDHC_SYSCTL_RSTD_MASK, /*!< Reset data line */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 kSDHC_ResetsAll = (kSDHC_ResetAll | kSDHC_ResetCommand | kSDHC_ResetData), /*!< All reset types */
<> 144:ef7eb2e8f9f7 102 };
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /*! @brief Transfer flag mask */
<> 144:ef7eb2e8f9f7 105 enum _sdhc_transfer_flag
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 kSDHC_EnableDmaFlag = SDHC_XFERTYP_DMAEN_MASK, /*!< Enable DMA */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 kSDHC_CommandTypeSuspendFlag = (SDHC_XFERTYP_CMDTYP(1U)), /*!< Suspend command */
<> 144:ef7eb2e8f9f7 110 kSDHC_CommandTypeResumeFlag = (SDHC_XFERTYP_CMDTYP(2U)), /*!< Resume command */
<> 144:ef7eb2e8f9f7 111 kSDHC_CommandTypeAbortFlag = (SDHC_XFERTYP_CMDTYP(3U)), /*!< Abort command */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 kSDHC_EnableBlockCountFlag = SDHC_XFERTYP_BCEN_MASK, /*!< Enable block count */
<> 144:ef7eb2e8f9f7 114 kSDHC_EnableAutoCommand12Flag = SDHC_XFERTYP_AC12EN_MASK, /*!< Enable auto CMD12 */
<> 144:ef7eb2e8f9f7 115 kSDHC_DataReadFlag = SDHC_XFERTYP_DTDSEL_MASK, /*!< Enable data read */
<> 144:ef7eb2e8f9f7 116 kSDHC_MultipleBlockFlag = SDHC_XFERTYP_MSBSEL_MASK, /*!< Multiple block data read/write */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 kSDHC_ResponseLength136Flag = SDHC_XFERTYP_RSPTYP(1U), /*!< 136 bit response length */
<> 144:ef7eb2e8f9f7 119 kSDHC_ResponseLength48Flag = SDHC_XFERTYP_RSPTYP(2U), /*!< 48 bit response length */
<> 144:ef7eb2e8f9f7 120 kSDHC_ResponseLength48BusyFlag = SDHC_XFERTYP_RSPTYP(3U), /*!< 48 bit response length with busy status */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 kSDHC_EnableCrcCheckFlag = SDHC_XFERTYP_CCCEN_MASK, /*!< Enable CRC check */
<> 144:ef7eb2e8f9f7 123 kSDHC_EnableIndexCheckFlag = SDHC_XFERTYP_CICEN_MASK, /*!< Enable index check */
<> 144:ef7eb2e8f9f7 124 kSDHC_DataPresentFlag = SDHC_XFERTYP_DPSEL_MASK, /*!< Data present flag */
<> 144:ef7eb2e8f9f7 125 };
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*! @brief Present status flag mask */
<> 144:ef7eb2e8f9f7 128 enum _sdhc_present_status_flag
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 kSDHC_CommandInhibitFlag = SDHC_PRSSTAT_CIHB_MASK, /*!< Command inhibit */
<> 144:ef7eb2e8f9f7 131 kSDHC_DataInhibitFlag = SDHC_PRSSTAT_CDIHB_MASK, /*!< Data inhibit */
<> 144:ef7eb2e8f9f7 132 kSDHC_DataLineActiveFlag = SDHC_PRSSTAT_DLA_MASK, /*!< Data line active */
<> 144:ef7eb2e8f9f7 133 kSDHC_SdClockStableFlag = SDHC_PRSSTAT_SDSTB_MASK, /*!< SD bus clock stable */
<> 144:ef7eb2e8f9f7 134 kSDHC_WriteTransferActiveFlag = SDHC_PRSSTAT_WTA_MASK, /*!< Write transfer active */
<> 144:ef7eb2e8f9f7 135 kSDHC_ReadTransferActiveFlag = SDHC_PRSSTAT_RTA_MASK, /*!< Read transfer active */
<> 144:ef7eb2e8f9f7 136 kSDHC_BufferWriteEnableFlag = SDHC_PRSSTAT_BWEN_MASK, /*!< Buffer write enable */
<> 144:ef7eb2e8f9f7 137 kSDHC_BufferReadEnableFlag = SDHC_PRSSTAT_BREN_MASK, /*!< Buffer read enable */
<> 144:ef7eb2e8f9f7 138 kSDHC_CardInsertedFlag = SDHC_PRSSTAT_CINS_MASK, /*!< Card inserted */
<> 144:ef7eb2e8f9f7 139 kSDHC_CommandLineLevelFlag = SDHC_PRSSTAT_CLSL_MASK, /*!< Command line signal level */
<> 144:ef7eb2e8f9f7 140 kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */
<> 144:ef7eb2e8f9f7 141 kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */
<> 144:ef7eb2e8f9f7 142 kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */
<> 144:ef7eb2e8f9f7 143 kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */
<> 144:ef7eb2e8f9f7 144 kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */
<> 144:ef7eb2e8f9f7 145 kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */
<> 144:ef7eb2e8f9f7 146 kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */
<> 144:ef7eb2e8f9f7 147 kSDHC_Data7LineLevelFlag = (1U << 31U), /*!< Data7 line signal level */
<> 144:ef7eb2e8f9f7 148 };
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /*! @brief Interrupt status flag mask */
<> 144:ef7eb2e8f9f7 151 enum _sdhc_interrupt_status_flag
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 kSDHC_CommandCompleteFlag = SDHC_IRQSTAT_CC_MASK, /*!< Command complete */
<> 144:ef7eb2e8f9f7 154 kSDHC_DataCompleteFlag = SDHC_IRQSTAT_TC_MASK, /*!< Data complete */
<> 144:ef7eb2e8f9f7 155 kSDHC_BlockGapEventFlag = SDHC_IRQSTAT_BGE_MASK, /*!< Block gap event */
<> 144:ef7eb2e8f9f7 156 kSDHC_DmaCompleteFlag = SDHC_IRQSTAT_DINT_MASK, /*!< DMA interrupt */
<> 144:ef7eb2e8f9f7 157 kSDHC_BufferWriteReadyFlag = SDHC_IRQSTAT_BWR_MASK, /*!< Buffer write ready */
<> 144:ef7eb2e8f9f7 158 kSDHC_BufferReadReadyFlag = SDHC_IRQSTAT_BRR_MASK, /*!< Buffer read ready */
<> 144:ef7eb2e8f9f7 159 kSDHC_CardInsertionFlag = SDHC_IRQSTAT_CINS_MASK, /*!< Card inserted */
<> 144:ef7eb2e8f9f7 160 kSDHC_CardRemovalFlag = SDHC_IRQSTAT_CRM_MASK, /*!< Card removed */
<> 144:ef7eb2e8f9f7 161 kSDHC_CardInterruptFlag = SDHC_IRQSTAT_CINT_MASK, /*!< Card interrupt */
<> 144:ef7eb2e8f9f7 162 kSDHC_CommandTimeoutFlag = SDHC_IRQSTAT_CTOE_MASK, /*!< Command timeout error */
<> 144:ef7eb2e8f9f7 163 kSDHC_CommandCrcErrorFlag = SDHC_IRQSTAT_CCE_MASK, /*!< Command CRC error */
<> 144:ef7eb2e8f9f7 164 kSDHC_CommandEndBitErrorFlag = SDHC_IRQSTAT_CEBE_MASK, /*!< Command end bit error */
<> 144:ef7eb2e8f9f7 165 kSDHC_CommandIndexErrorFlag = SDHC_IRQSTAT_CIE_MASK, /*!< Command index error */
<> 144:ef7eb2e8f9f7 166 kSDHC_DataTimeoutFlag = SDHC_IRQSTAT_DTOE_MASK, /*!< Data timeout error */
<> 144:ef7eb2e8f9f7 167 kSDHC_DataCrcErrorFlag = SDHC_IRQSTAT_DCE_MASK, /*!< Data CRC error */
<> 144:ef7eb2e8f9f7 168 kSDHC_DataEndBitErrorFlag = SDHC_IRQSTAT_DEBE_MASK, /*!< Data end bit error */
<> 144:ef7eb2e8f9f7 169 kSDHC_AutoCommand12ErrorFlag = SDHC_IRQSTAT_AC12E_MASK, /*!< Auto CMD12 error */
<> 144:ef7eb2e8f9f7 170 kSDHC_DmaErrorFlag = SDHC_IRQSTAT_DMAE_MASK, /*!< DMA error */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 kSDHC_CommandErrorFlag = (kSDHC_CommandTimeoutFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag |
<> 144:ef7eb2e8f9f7 173 kSDHC_CommandIndexErrorFlag), /*!< Command error */
<> 144:ef7eb2e8f9f7 174 kSDHC_DataErrorFlag = (kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | kSDHC_DataEndBitErrorFlag |
<> 144:ef7eb2e8f9f7 175 kSDHC_AutoCommand12ErrorFlag), /*!< Data error */
<> 144:ef7eb2e8f9f7 176 kSDHC_ErrorFlag = (kSDHC_CommandErrorFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< All error */
<> 144:ef7eb2e8f9f7 177 kSDHC_DataFlag = (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_BufferWriteReadyFlag |
<> 144:ef7eb2e8f9f7 178 kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< Data interrupts */
<> 144:ef7eb2e8f9f7 179 kSDHC_CommandFlag = (kSDHC_CommandErrorFlag | kSDHC_CommandCompleteFlag), /*!< Command interrupts */
<> 144:ef7eb2e8f9f7 180 kSDHC_CardDetectFlag = (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag), /*!< Card detection interrupts */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 kSDHC_AllInterruptFlags = (kSDHC_BlockGapEventFlag | kSDHC_CardInterruptFlag | kSDHC_CommandFlag | kSDHC_DataFlag |
<> 144:ef7eb2e8f9f7 183 kSDHC_ErrorFlag), /*!< All flags mask */
<> 144:ef7eb2e8f9f7 184 };
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /*! @brief Auto CMD12 error status flag mask */
<> 144:ef7eb2e8f9f7 187 enum _sdhc_auto_command12_error_status_flag
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 kSDHC_AutoCommand12NotExecutedFlag = SDHC_AC12ERR_AC12NE_MASK, /*!< Not executed error */
<> 144:ef7eb2e8f9f7 190 kSDHC_AutoCommand12TimeoutFlag = SDHC_AC12ERR_AC12TOE_MASK, /*!< Timeout error */
<> 144:ef7eb2e8f9f7 191 kSDHC_AutoCommand12EndBitErrorFlag = SDHC_AC12ERR_AC12EBE_MASK, /*!< End bit error */
<> 144:ef7eb2e8f9f7 192 kSDHC_AutoCommand12CrcErrorFlag = SDHC_AC12ERR_AC12CE_MASK, /*!< CRC error */
<> 144:ef7eb2e8f9f7 193 kSDHC_AutoCommand12IndexErrorFlag = SDHC_AC12ERR_AC12IE_MASK, /*!< Index error */
<> 144:ef7eb2e8f9f7 194 kSDHC_AutoCommand12NotIssuedFlag = SDHC_AC12ERR_CNIBAC12E_MASK, /*!< Not issued error */
<> 144:ef7eb2e8f9f7 195 };
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /*! @brief ADMA error status flag mask */
<> 144:ef7eb2e8f9f7 198 enum _sdhc_adma_error_status_flag
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 kSDHC_AdmaLenghMismatchFlag = SDHC_ADMAES_ADMALME_MASK, /*!< Length mismatch error */
<> 144:ef7eb2e8f9f7 201 kSDHC_AdmaDescriptorErrorFlag = SDHC_ADMAES_ADMADCE_MASK, /*!< Descriptor error */
<> 144:ef7eb2e8f9f7 202 };
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /*!
<> 144:ef7eb2e8f9f7 205 * @brief ADMA error state
<> 144:ef7eb2e8f9f7 206 *
<> 144:ef7eb2e8f9f7 207 * This state is the detail state when ADMA error has occurred.
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 typedef enum _sdhc_adma_error_state
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 kSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */
<> 144:ef7eb2e8f9f7 212 kSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */
<> 144:ef7eb2e8f9f7 213 kSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */
<> 144:ef7eb2e8f9f7 214 kSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */
<> 144:ef7eb2e8f9f7 215 } sdhc_adma_error_state_t;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /*! @brief Force event mask */
<> 144:ef7eb2e8f9f7 218 enum _sdhc_force_event
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 kSDHC_ForceEventAutoCommand12NotExecuted = SDHC_FEVT_AC12NE_MASK, /*!< Auto CMD12 not executed error */
<> 144:ef7eb2e8f9f7 221 kSDHC_ForceEventAutoCommand12Timeout = SDHC_FEVT_AC12TOE_MASK, /*!< Auto CMD12 timeout error */
<> 144:ef7eb2e8f9f7 222 kSDHC_ForceEventAutoCommand12CrcError = SDHC_FEVT_AC12CE_MASK, /*!< Auto CMD12 CRC error */
<> 144:ef7eb2e8f9f7 223 kSDHC_ForceEventEndBitError = SDHC_FEVT_AC12EBE_MASK, /*!< Auto CMD12 end bit error */
<> 144:ef7eb2e8f9f7 224 kSDHC_ForceEventAutoCommand12IndexError = SDHC_FEVT_AC12IE_MASK, /*!< Auto CMD12 index error */
<> 144:ef7eb2e8f9f7 225 kSDHC_ForceEventAutoCommand12NotIssued = SDHC_FEVT_CNIBAC12E_MASK, /*!< Auto CMD12 not issued error */
<> 144:ef7eb2e8f9f7 226 kSDHC_ForceEventCommandTimeout = SDHC_FEVT_CTOE_MASK, /*!< Command timeout error */
<> 144:ef7eb2e8f9f7 227 kSDHC_ForceEventCommandCrcError = SDHC_FEVT_CCE_MASK, /*!< Command CRC error */
<> 144:ef7eb2e8f9f7 228 kSDHC_ForceEventCommandEndBitError = SDHC_FEVT_CEBE_MASK, /*!< Command end bit error */
<> 144:ef7eb2e8f9f7 229 kSDHC_ForceEventCommandIndexError = SDHC_FEVT_CIE_MASK, /*!< Command index error */
<> 144:ef7eb2e8f9f7 230 kSDHC_ForceEventDataTimeout = SDHC_FEVT_DTOE_MASK, /*!< Data timeout error */
<> 144:ef7eb2e8f9f7 231 kSDHC_ForceEventDataCrcError = SDHC_FEVT_DCE_MASK, /*!< Data CRC error */
<> 144:ef7eb2e8f9f7 232 kSDHC_ForceEventDataEndBitError = SDHC_FEVT_DEBE_MASK, /*!< Data end bit error */
<> 144:ef7eb2e8f9f7 233 kSDHC_ForceEventAutoCommand12Error = SDHC_FEVT_AC12E_MASK, /*!< Auto CMD12 error */
<> 144:ef7eb2e8f9f7 234 kSDHC_ForceEventCardInt = SDHC_FEVT_CINT_MASK, /*!< Card interrupt */
<> 144:ef7eb2e8f9f7 235 kSDHC_ForceEventDmaError = SDHC_FEVT_DMAE_MASK, /*!< Dma error */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 kSDHC_ForceEventsAll =
<> 144:ef7eb2e8f9f7 238 (kSDHC_ForceEventAutoCommand12NotExecuted | kSDHC_ForceEventAutoCommand12Timeout |
<> 144:ef7eb2e8f9f7 239 kSDHC_ForceEventAutoCommand12CrcError | kSDHC_ForceEventEndBitError | kSDHC_ForceEventAutoCommand12IndexError |
<> 144:ef7eb2e8f9f7 240 kSDHC_ForceEventAutoCommand12NotIssued | kSDHC_ForceEventCommandTimeout | kSDHC_ForceEventCommandCrcError |
<> 144:ef7eb2e8f9f7 241 kSDHC_ForceEventCommandEndBitError | kSDHC_ForceEventCommandIndexError | kSDHC_ForceEventDataTimeout |
<> 144:ef7eb2e8f9f7 242 kSDHC_ForceEventDataCrcError | kSDHC_ForceEventDataEndBitError | kSDHC_ForceEventAutoCommand12Error |
<> 144:ef7eb2e8f9f7 243 kSDHC_ForceEventCardInt | kSDHC_ForceEventDmaError), /*!< All force event flags mask */
<> 144:ef7eb2e8f9f7 244 };
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /*! @brief Data transfer width */
<> 144:ef7eb2e8f9f7 247 typedef enum _sdhc_data_bus_width
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 kSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */
<> 144:ef7eb2e8f9f7 250 kSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */
<> 144:ef7eb2e8f9f7 251 kSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */
<> 144:ef7eb2e8f9f7 252 } sdhc_data_bus_width_t;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /*! @brief Endian mode */
<> 144:ef7eb2e8f9f7 255 typedef enum _sdhc_endian_mode
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 kSDHC_EndianModeBig = 0U, /*!< Big endian mode */
<> 144:ef7eb2e8f9f7 258 kSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
<> 144:ef7eb2e8f9f7 259 kSDHC_EndianModeLittle = 2U, /*!< Little endian mode */
<> 144:ef7eb2e8f9f7 260 } sdhc_endian_mode_t;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /*! @brief DMA mode */
<> 144:ef7eb2e8f9f7 263 typedef enum _sdhc_dma_mode
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 kSDHC_DmaModeNo = 0U, /*!< No DMA */
<> 144:ef7eb2e8f9f7 266 kSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */
<> 144:ef7eb2e8f9f7 267 kSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */
<> 144:ef7eb2e8f9f7 268 } sdhc_dma_mode_t;
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /*! @brief SDIO control flag mask */
<> 144:ef7eb2e8f9f7 271 enum _sdhc_sdio_control_flag
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 kSDHC_StopAtBlockGapFlag = 0x01, /*!< Stop at block gap */
<> 144:ef7eb2e8f9f7 274 kSDHC_ReadWaitControlFlag = 0x02, /*!< Read wait control */
<> 144:ef7eb2e8f9f7 275 kSDHC_InterruptAtBlockGapFlag = 0x04, /*!< Interrupt at block gap */
<> 144:ef7eb2e8f9f7 276 kSDHC_ExactBlockNumberReadFlag = 0x08, /*!< Exact block number read */
<> 144:ef7eb2e8f9f7 277 };
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /*! @brief MMC card boot mode */
<> 144:ef7eb2e8f9f7 280 typedef enum _sdhc_boot_mode
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 kSDHC_BootModeNormal = 0U, /*!< Normal boot */
<> 144:ef7eb2e8f9f7 283 kSDHC_BootModeAlternative = 1U, /*!< Alternative boot */
<> 144:ef7eb2e8f9f7 284 } sdhc_boot_mode_t;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /*! @brief The command type */
<> 144:ef7eb2e8f9f7 287 typedef enum _sdhc_command_type
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 kSDHC_CommandTypeNormal = 0U, /*!< Normal command */
<> 144:ef7eb2e8f9f7 290 kSDHC_CommandTypeSuspend = 1U, /*!< Suspend command */
<> 144:ef7eb2e8f9f7 291 kSDHC_CommandTypeResume = 2U, /*!< Resume command */
<> 144:ef7eb2e8f9f7 292 kSDHC_CommandTypeAbort = 3U, /*!< Abort command */
<> 144:ef7eb2e8f9f7 293 } sdhc_command_type_t;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /*!
<> 144:ef7eb2e8f9f7 296 * @brief The command response type.
<> 144:ef7eb2e8f9f7 297 *
<> 144:ef7eb2e8f9f7 298 * Define the command response type from card to host controller.
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 typedef enum _sdhc_response_type
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 kSDHC_ResponseTypeNone = 0U, /*!< Response type: none */
<> 144:ef7eb2e8f9f7 303 kSDHC_ResponseTypeR1 = 1U, /*!< Response type: R1 */
<> 144:ef7eb2e8f9f7 304 kSDHC_ResponseTypeR1b = 2U, /*!< Response type: R1b */
<> 144:ef7eb2e8f9f7 305 kSDHC_ResponseTypeR2 = 3U, /*!< Response type: R2 */
<> 144:ef7eb2e8f9f7 306 kSDHC_ResponseTypeR3 = 4U, /*!< Response type: R3 */
<> 144:ef7eb2e8f9f7 307 kSDHC_ResponseTypeR4 = 5U, /*!< Response type: R4 */
<> 144:ef7eb2e8f9f7 308 kSDHC_ResponseTypeR5 = 6U, /*!< Response type: R5 */
<> 144:ef7eb2e8f9f7 309 kSDHC_ResponseTypeR5b = 7U, /*!< Response type: R5b */
<> 144:ef7eb2e8f9f7 310 kSDHC_ResponseTypeR6 = 8U, /*!< Response type: R6 */
<> 144:ef7eb2e8f9f7 311 kSDHC_ResponseTypeR7 = 9U, /*!< Response type: R7 */
<> 144:ef7eb2e8f9f7 312 } sdhc_response_type_t;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 315 #define SDHC_ADMA1_ADDRESS_ALIGN (4096U)
<> 144:ef7eb2e8f9f7 316 /*! @brief The alignment size for LENGTH field in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 317 #define SDHC_ADMA1_LENGTH_ALIGN (4096U)
<> 144:ef7eb2e8f9f7 318 /*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */
<> 144:ef7eb2e8f9f7 319 #define SDHC_ADMA2_ADDRESS_ALIGN (4U)
<> 144:ef7eb2e8f9f7 320 /*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */
<> 144:ef7eb2e8f9f7 321 #define SDHC_ADMA2_LENGTH_ALIGN (4U)
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* ADMA1 descriptor table
<> 144:ef7eb2e8f9f7 324 * |------------------------|---------|--------------------------|
<> 144:ef7eb2e8f9f7 325 * | Address/page field |Reserved | Attribute |
<> 144:ef7eb2e8f9f7 326 * |------------------------|---------|--------------------------|
<> 144:ef7eb2e8f9f7 327 * |31 12|11 6|05 |04 |03|02 |01 |00 |
<> 144:ef7eb2e8f9f7 328 * |------------------------|---------|----|----|--|---|---|-----|
<> 144:ef7eb2e8f9f7 329 * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
<> 144:ef7eb2e8f9f7 330 * |------------------------|---------|----|----|--|---|---|-----|
<> 144:ef7eb2e8f9f7 331 *
<> 144:ef7eb2e8f9f7 332 *
<> 144:ef7eb2e8f9f7 333 * |------|------|-----------------|-------|-------------|
<> 144:ef7eb2e8f9f7 334 * | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
<> 144:ef7eb2e8f9f7 335 * |------|------|-----------------|---------------------|
<> 144:ef7eb2e8f9f7 336 * | 0 | 0 | No op | Don't care |
<> 144:ef7eb2e8f9f7 337 * |------|------|-----------------|-------|-------------|
<> 144:ef7eb2e8f9f7 338 * | 0 | 1 | Set data length | 0000 | Data Length |
<> 144:ef7eb2e8f9f7 339 * |------|------|-----------------|-------|-------------|
<> 144:ef7eb2e8f9f7 340 * | 1 | 0 | Transfer data | Data address |
<> 144:ef7eb2e8f9f7 341 * |------|------|-----------------|---------------------|
<> 144:ef7eb2e8f9f7 342 * | 1 | 1 | Link descriptor | Descriptor address |
<> 144:ef7eb2e8f9f7 343 * |------|------|-----------------|---------------------|
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 /*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 346 #define SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U)
<> 144:ef7eb2e8f9f7 347 /*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 348 #define SDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
<> 144:ef7eb2e8f9f7 349 /*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 350 #define SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U)
<> 144:ef7eb2e8f9f7 351 /*! @brief The mask for LENGTH field in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 352 #define SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 353 /*! @brief The max value of LENGTH filed in ADMA1's descriptor */
<> 144:ef7eb2e8f9f7 354 #define SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U)
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /*! @brief The mask for the control/status field in ADMA1 descriptor */
<> 144:ef7eb2e8f9f7 357 enum _sdhc_adma1_descriptor_flag
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 kSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
<> 144:ef7eb2e8f9f7 360 kSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */
<> 144:ef7eb2e8f9f7 361 kSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */
<> 144:ef7eb2e8f9f7 362 kSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */
<> 144:ef7eb2e8f9f7 363 kSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */
<> 144:ef7eb2e8f9f7 364 kSDHC_Adma1DescriptorTypeNop = (kSDHC_Adma1DescriptorValidFlag), /*!< No operation */
<> 144:ef7eb2e8f9f7 365 kSDHC_Adma1DescriptorTypeTransfer =
<> 144:ef7eb2e8f9f7 366 (kSDHC_Adma1DescriptorActivity2Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */
<> 144:ef7eb2e8f9f7 367 kSDHC_Adma1DescriptorTypeLink = (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorActivity2Flag |
<> 144:ef7eb2e8f9f7 368 kSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */
<> 144:ef7eb2e8f9f7 369 kSDHC_Adma1DescriptorTypeSetLength =
<> 144:ef7eb2e8f9f7 370 (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Set data length */
<> 144:ef7eb2e8f9f7 371 };
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* ADMA2 descriptor table
<> 144:ef7eb2e8f9f7 374 * |----------------|---------------|-------------|--------------------------|
<> 144:ef7eb2e8f9f7 375 * | Address field | Length | Reserved | Attribute |
<> 144:ef7eb2e8f9f7 376 * |----------------|---------------|-------------|--------------------------|
<> 144:ef7eb2e8f9f7 377 * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
<> 144:ef7eb2e8f9f7 378 * |----------------|---------------|-------------|----|----|--|---|---|-----|
<> 144:ef7eb2e8f9f7 379 * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
<> 144:ef7eb2e8f9f7 380 * |----------------|---------------|-------------|----|----|--|---|---|-----|
<> 144:ef7eb2e8f9f7 381 *
<> 144:ef7eb2e8f9f7 382 *
<> 144:ef7eb2e8f9f7 383 * | Act2 | Act1 | Comment | Operation |
<> 144:ef7eb2e8f9f7 384 * |------|------|-----------------|-------------------------------------------------------------------|
<> 144:ef7eb2e8f9f7 385 * | 0 | 0 | No op | Don't care |
<> 144:ef7eb2e8f9f7 386 * |------|------|-----------------|-------------------------------------------------------------------|
<> 144:ef7eb2e8f9f7 387 * | 0 | 1 | Reserved | Read this line and go to next one |
<> 144:ef7eb2e8f9f7 388 * |------|------|-----------------|-------------------------------------------------------------------|
<> 144:ef7eb2e8f9f7 389 * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
<> 144:ef7eb2e8f9f7 390 * |------|------|-----------------|-------------------------------------------------------------------|
<> 144:ef7eb2e8f9f7 391 * | 1 | 1 | Link descriptor | Link to another descriptor |
<> 144:ef7eb2e8f9f7 392 * |------|------|-----------------|-------------------------------------------------------------------|
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 /*! @brief The bit shift for LENGTH field in ADMA2's descriptor */
<> 144:ef7eb2e8f9f7 395 #define SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U)
<> 144:ef7eb2e8f9f7 396 /*! @brief The bit mask for LENGTH field in ADMA2's descriptor */
<> 144:ef7eb2e8f9f7 397 #define SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 398 /*! @brief The max value of LENGTH field in ADMA2's descriptor */
<> 144:ef7eb2e8f9f7 399 #define SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK)
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /*! @brief ADMA1 descriptor control and status mask */
<> 144:ef7eb2e8f9f7 402 enum _sdhc_adma2_descriptor_flag
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 kSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
<> 144:ef7eb2e8f9f7 405 kSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */
<> 144:ef7eb2e8f9f7 406 kSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */
<> 144:ef7eb2e8f9f7 407 kSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */
<> 144:ef7eb2e8f9f7 408 kSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 kSDHC_Adma2DescriptorTypeNop = (kSDHC_Adma2DescriptorValidFlag), /*!< No operation */
<> 144:ef7eb2e8f9f7 411 kSDHC_Adma2DescriptorTypeReserved =
<> 144:ef7eb2e8f9f7 412 (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Reserved */
<> 144:ef7eb2e8f9f7 413 kSDHC_Adma2DescriptorTypeTransfer =
<> 144:ef7eb2e8f9f7 414 (kSDHC_Adma2DescriptorActivity2Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */
<> 144:ef7eb2e8f9f7 415 kSDHC_Adma2DescriptorTypeLink = (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorActivity2Flag |
<> 144:ef7eb2e8f9f7 416 kSDHC_Adma2DescriptorValidFlag), /*!< Link type */
<> 144:ef7eb2e8f9f7 417 };
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /*! @brief Define the adma1 descriptor structure. */
<> 144:ef7eb2e8f9f7 420 typedef uint32_t sdhc_adma1_descriptor_t;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /*! @brief Define the ADMA2 descriptor structure. */
<> 144:ef7eb2e8f9f7 423 typedef struct _sdhc_adma2_descriptor
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 uint32_t attribute; /*!< The control and status field */
<> 144:ef7eb2e8f9f7 426 const uint32_t *address; /*!< The address field */
<> 144:ef7eb2e8f9f7 427 } sdhc_adma2_descriptor_t;
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /*!
<> 144:ef7eb2e8f9f7 430 * @brief SDHC capability information.
<> 144:ef7eb2e8f9f7 431 *
<> 144:ef7eb2e8f9f7 432 * Define structure to save the capability information of SDHC.
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 typedef struct _sdhc_capability
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 uint32_t specVersion; /*!< Specification version */
<> 144:ef7eb2e8f9f7 437 uint32_t vendorVersion; /*!< Vendor version */
<> 144:ef7eb2e8f9f7 438 uint32_t maxBlockLength; /*!< Maximum block length united as byte */
<> 144:ef7eb2e8f9f7 439 uint32_t maxBlockCount; /*!< Maximum block count can be set one time */
<> 144:ef7eb2e8f9f7 440 uint32_t flags; /*!< Capability flags to indicate the support information(_sdhc_capability_flag) */
<> 144:ef7eb2e8f9f7 441 } sdhc_capability_t;
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /*! @brief Card transfer configuration.
<> 144:ef7eb2e8f9f7 444 *
<> 144:ef7eb2e8f9f7 445 * Define structure to configure the transfer-related command index/argument/flags and data block
<> 144:ef7eb2e8f9f7 446 * size/data block numbers. This structure needs to be filled each time a command is sent to the card.
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 typedef struct _sdhc_transfer_config
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 size_t dataBlockSize; /*!< Data block size */
<> 144:ef7eb2e8f9f7 451 uint32_t dataBlockCount; /*!< Data block count */
<> 144:ef7eb2e8f9f7 452 uint32_t commandArgument; /*!< Command argument */
<> 144:ef7eb2e8f9f7 453 uint32_t commandIndex; /*!< Command index */
<> 144:ef7eb2e8f9f7 454 uint32_t flags; /*!< Transfer flags(_sdhc_transfer_flag) */
<> 144:ef7eb2e8f9f7 455 } sdhc_transfer_config_t;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /*! @brief Data structure to configure the MMC boot feature */
<> 144:ef7eb2e8f9f7 458 typedef struct _sdhc_boot_config
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK */
<> 144:ef7eb2e8f9f7 461 sdhc_boot_mode_t bootMode; /*!< Boot mode selection. */
<> 144:ef7eb2e8f9f7 462 uint32_t blockCount; /*!< Stop at block gap value of automatic mode */
<> 144:ef7eb2e8f9f7 463 bool enableBootAck; /*!< Enable or disable boot ACK */
<> 144:ef7eb2e8f9f7 464 bool enableBoot; /*!< Enable or disable fast boot */
<> 144:ef7eb2e8f9f7 465 bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */
<> 144:ef7eb2e8f9f7 466 } sdhc_boot_config_t;
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /*! @brief Data structure to initialize the SDHC */
<> 144:ef7eb2e8f9f7 469 typedef struct _sdhc_config
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 bool cardDetectDat3; /*!< Enable DAT3 as card detection pin */
<> 144:ef7eb2e8f9f7 472 sdhc_endian_mode_t endianMode; /*!< Endian mode */
<> 144:ef7eb2e8f9f7 473 sdhc_dma_mode_t dmaMode; /*!< DMA mode */
<> 144:ef7eb2e8f9f7 474 uint32_t readWatermarkLevel; /*!< Watermark level for DMA read operation */
<> 144:ef7eb2e8f9f7 475 uint32_t writeWatermarkLevel; /*!< Watermark level for DMA write operation */
<> 144:ef7eb2e8f9f7 476 } sdhc_config_t;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /*!
<> 144:ef7eb2e8f9f7 479 * @brief Card data descriptor
<> 144:ef7eb2e8f9f7 480 *
<> 144:ef7eb2e8f9f7 481 * Define structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card driver
<> 144:ef7eb2e8f9f7 482 * want to ignore the error event to read/write all the data not to stop read/write immediately when error event
<> 144:ef7eb2e8f9f7 483 * happen for example bus testing procedure for MMC card.
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 typedef struct _sdhc_data
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 bool enableAutoCommand12; /*!< Enable auto CMD12 */
<> 144:ef7eb2e8f9f7 488 bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */
<> 144:ef7eb2e8f9f7 489 size_t blockSize; /*!< Block size */
<> 144:ef7eb2e8f9f7 490 uint32_t blockCount; /*!< Block count */
<> 144:ef7eb2e8f9f7 491 uint32_t *rxData; /*!< Buffer to save data read */
<> 144:ef7eb2e8f9f7 492 const uint32_t *txData; /*!< Data buffer to write */
<> 144:ef7eb2e8f9f7 493 } sdhc_data_t;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /*!
<> 144:ef7eb2e8f9f7 496 * @brief Card command descriptor
<> 144:ef7eb2e8f9f7 497 *
<> 144:ef7eb2e8f9f7 498 * Define card command-related attribute.
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 typedef struct _sdhc_command
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 uint32_t index; /*!< Command index */
<> 144:ef7eb2e8f9f7 503 uint32_t argument; /*!< Command argument */
<> 144:ef7eb2e8f9f7 504 sdhc_command_type_t type; /*!< Command type */
<> 144:ef7eb2e8f9f7 505 sdhc_response_type_t responseType; /*!< Command response type */
<> 144:ef7eb2e8f9f7 506 uint32_t response[4U]; /*!< Response for this command */
<> 144:ef7eb2e8f9f7 507 } sdhc_command_t;
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /*! @brief Transfer state */
<> 144:ef7eb2e8f9f7 510 typedef struct _sdhc_transfer
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 sdhc_data_t *data; /*!< Data to transfer */
<> 144:ef7eb2e8f9f7 513 sdhc_command_t *command; /*!< Command to send */
<> 144:ef7eb2e8f9f7 514 } sdhc_transfer_t;
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /*! @brief SDHC handle typedef */
<> 144:ef7eb2e8f9f7 517 typedef struct _sdhc_handle sdhc_handle_t;
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /*! @brief SDHC callback functions. */
<> 144:ef7eb2e8f9f7 520 typedef struct _sdhc_transfer_callback
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */
<> 144:ef7eb2e8f9f7 523 void (*CardRemoved)(void); /*!< Card removed occurs */
<> 144:ef7eb2e8f9f7 524 void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */
<> 144:ef7eb2e8f9f7 525 void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */
<> 144:ef7eb2e8f9f7 526 void (*TransferComplete)(SDHC_Type *base,
<> 144:ef7eb2e8f9f7 527 sdhc_handle_t *handle,
<> 144:ef7eb2e8f9f7 528 status_t status,
<> 144:ef7eb2e8f9f7 529 void *userData); /*!< Transfer complete callback */
<> 144:ef7eb2e8f9f7 530 } sdhc_transfer_callback_t;
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /*!
<> 144:ef7eb2e8f9f7 533 * @brief Host descriptor
<> 144:ef7eb2e8f9f7 534 *
<> 144:ef7eb2e8f9f7 535 * Define the structure to save the SDHC state information and callback function. The detail interrupt status when
<> 144:ef7eb2e8f9f7 536 * send command or transfer data can be got from interruptFlags field by using mask defined in sdhc_interrupt_flag_t;
<> 144:ef7eb2e8f9f7 537 *
<> 144:ef7eb2e8f9f7 538 * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 struct _sdhc_handle
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 /* Transfer parameter */
<> 144:ef7eb2e8f9f7 543 sdhc_data_t *volatile data; /*!< Data to transfer */
<> 144:ef7eb2e8f9f7 544 sdhc_command_t *volatile command; /*!< Command to send */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Transfer status */
<> 144:ef7eb2e8f9f7 547 volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */
<> 144:ef7eb2e8f9f7 548 volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Callback functions */
<> 144:ef7eb2e8f9f7 551 sdhc_transfer_callback_t callback; /*!< Callback function */
<> 144:ef7eb2e8f9f7 552 void *userData; /*!< Parameter for transfer complete callback */
<> 144:ef7eb2e8f9f7 553 };
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /*! @brief SDHC transfer function. */
<> 144:ef7eb2e8f9f7 556 typedef status_t (*sdhc_transfer_function_t)(SDHC_Type *base, sdhc_transfer_t *content);
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /*! @brief SDHC host descriptor */
<> 144:ef7eb2e8f9f7 559 typedef struct _sdhc_host
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 SDHC_Type *base; /*!< SDHC peripheral base address */
<> 144:ef7eb2e8f9f7 562 uint32_t sourceClock_Hz; /*!< SDHC source clock frequency united in Hz */
<> 144:ef7eb2e8f9f7 563 sdhc_config_t config; /*!< SDHC configuration */
<> 144:ef7eb2e8f9f7 564 sdhc_capability_t capability; /*!< SDHC capability information */
<> 144:ef7eb2e8f9f7 565 sdhc_transfer_function_t transfer; /*!< SDHC transfer function */
<> 144:ef7eb2e8f9f7 566 } sdhc_host_t;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 569 * API
<> 144:ef7eb2e8f9f7 570 ************************************************************************************************/
<> 144:ef7eb2e8f9f7 571 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 572 extern "C" {
<> 144:ef7eb2e8f9f7 573 #endif
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /*!
<> 144:ef7eb2e8f9f7 576 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 577 * @{
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /*!
<> 144:ef7eb2e8f9f7 581 * @brief SDHC module initialization function.
<> 144:ef7eb2e8f9f7 582 *
<> 144:ef7eb2e8f9f7 583 * Configure the SDHC according to the user configuration.
<> 144:ef7eb2e8f9f7 584 *
<> 144:ef7eb2e8f9f7 585 * Example:
<> 144:ef7eb2e8f9f7 586 @code
<> 144:ef7eb2e8f9f7 587 sdhc_config_t config;
<> 144:ef7eb2e8f9f7 588 config.enableDat3AsCDPin = false;
<> 144:ef7eb2e8f9f7 589 config.endianMode = kSDHC_EndianModeLittle;
<> 144:ef7eb2e8f9f7 590 config.dmaMode = kSDHC_DmaModeAdma2;
<> 144:ef7eb2e8f9f7 591 config.readWatermarkLevel = 512U;
<> 144:ef7eb2e8f9f7 592 config.writeWatermarkLevel = 512U;
<> 144:ef7eb2e8f9f7 593 SDHC_Init(SDHC, &config);
<> 144:ef7eb2e8f9f7 594 @endcode
<> 144:ef7eb2e8f9f7 595 *
<> 144:ef7eb2e8f9f7 596 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 597 * @param config SDHC configuration information.
<> 144:ef7eb2e8f9f7 598 * @retval kStatus_Success Operate successfully.
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /*!
<> 144:ef7eb2e8f9f7 603 * @brief Deinitialize the SDHC.
<> 144:ef7eb2e8f9f7 604 *
<> 144:ef7eb2e8f9f7 605 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 void SDHC_Deinit(SDHC_Type *base);
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /*!
<> 144:ef7eb2e8f9f7 610 * @brief Reset the SDHC.
<> 144:ef7eb2e8f9f7 611 *
<> 144:ef7eb2e8f9f7 612 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 613 * @param mask The reset type mask(_sdhc_reset).
<> 144:ef7eb2e8f9f7 614 * @param timeout Timeout for reset.
<> 144:ef7eb2e8f9f7 615 * @retval true Reset successfully.
<> 144:ef7eb2e8f9f7 616 * @retval false Reset failed.
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout);
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* @} */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /*!
<> 144:ef7eb2e8f9f7 623 * @name DMA Control
<> 144:ef7eb2e8f9f7 624 * @{
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /*!
<> 144:ef7eb2e8f9f7 628 * @brief Set ADMA descriptor table configuration.
<> 144:ef7eb2e8f9f7 629 *
<> 144:ef7eb2e8f9f7 630 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 631 * @param dmaMode DMA mode.
<> 144:ef7eb2e8f9f7 632 * @param table ADMA table address.
<> 144:ef7eb2e8f9f7 633 * @param tableWords ADMA table buffer length united as Words.
<> 144:ef7eb2e8f9f7 634 * @param data Data buffer address.
<> 144:ef7eb2e8f9f7 635 * @param dataBytes Data length united as bytes.
<> 144:ef7eb2e8f9f7 636 * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
<> 144:ef7eb2e8f9f7 637 * @retval kStatus_Success Operate successfully.
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639 status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
<> 144:ef7eb2e8f9f7 640 sdhc_dma_mode_t dmaMode,
<> 144:ef7eb2e8f9f7 641 uint32_t *table,
<> 144:ef7eb2e8f9f7 642 uint32_t tableWords,
<> 144:ef7eb2e8f9f7 643 const uint32_t *data,
<> 144:ef7eb2e8f9f7 644 uint32_t dataBytes);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* @} */
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /*!
<> 144:ef7eb2e8f9f7 649 * @name Interrupts
<> 144:ef7eb2e8f9f7 650 * @{
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /*!
<> 144:ef7eb2e8f9f7 654 * @brief Enable interrupt status
<> 144:ef7eb2e8f9f7 655 *
<> 144:ef7eb2e8f9f7 656 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 657 * @param mask Interrupt status flags mask(_sdhc_interrupt_status_flag).
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 static inline void SDHC_EnableInterruptStatus(SDHC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 base->IRQSTATEN |= mask;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /*!
<> 144:ef7eb2e8f9f7 665 * @brief Disable interrupt status.
<> 144:ef7eb2e8f9f7 666 *
<> 144:ef7eb2e8f9f7 667 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 668 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 static inline void SDHC_DisableInterruptStatus(SDHC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 base->IRQSTATEN &= ~mask;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /*!
<> 144:ef7eb2e8f9f7 676 * @brief Enable interrupts signal corresponding to the interrupt status flag.
<> 144:ef7eb2e8f9f7 677 *
<> 144:ef7eb2e8f9f7 678 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 679 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 static inline void SDHC_EnableInterruptSignal(SDHC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 base->IRQSIGEN |= mask;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /*!
<> 144:ef7eb2e8f9f7 687 * @brief Disable interrupts signal corresponding to the interrupt status flag.
<> 144:ef7eb2e8f9f7 688 *
<> 144:ef7eb2e8f9f7 689 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 690 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 static inline void SDHC_DisableInterruptSignal(SDHC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 base->IRQSIGEN &= ~mask;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* @} */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /*!
<> 144:ef7eb2e8f9f7 700 * @name Status
<> 144:ef7eb2e8f9f7 701 * @{
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /*!
<> 144:ef7eb2e8f9f7 705 * @brief Get current interrupt status.
<> 144:ef7eb2e8f9f7 706 *
<> 144:ef7eb2e8f9f7 707 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 708 * @return Current interrupt status flags mask(_sdhc_interrupt_status_flag).
<> 144:ef7eb2e8f9f7 709 */
<> 144:ef7eb2e8f9f7 710 static inline uint32_t SDHC_GetInterruptStatusFlags(SDHC_Type *base)
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 return base->IRQSTAT;
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /*!
<> 144:ef7eb2e8f9f7 716 * @brief Clear specified interrupt status.
<> 144:ef7eb2e8f9f7 717 *
<> 144:ef7eb2e8f9f7 718 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 719 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
<> 144:ef7eb2e8f9f7 720 */
<> 144:ef7eb2e8f9f7 721 static inline void SDHC_ClearInterruptStatusFlags(SDHC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 base->IRQSTAT = mask;
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /*!
<> 144:ef7eb2e8f9f7 727 * @brief Get the status of auto command 12 error.
<> 144:ef7eb2e8f9f7 728 *
<> 144:ef7eb2e8f9f7 729 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 730 * @return Auto command 12 error status flags mask(_sdhc_auto_command12_error_status_flag).
<> 144:ef7eb2e8f9f7 731 */
<> 144:ef7eb2e8f9f7 732 static inline uint32_t SDHC_GetAutoCommand12ErrorStatusFlags(SDHC_Type *base)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 return base->AC12ERR;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /*!
<> 144:ef7eb2e8f9f7 738 * @brief Get the status of ADMA error.
<> 144:ef7eb2e8f9f7 739 *
<> 144:ef7eb2e8f9f7 740 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 741 * @return ADMA error status flags mask(_sdhc_adma_error_status_flag).
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743 static inline uint32_t SDHC_GetAdmaErrorStatusFlags(SDHC_Type *base)
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 return base->ADMAES;
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /*!
<> 144:ef7eb2e8f9f7 749 * @brief Get present status.
<> 144:ef7eb2e8f9f7 750 *
<> 144:ef7eb2e8f9f7 751 * This function gets the present SDHC's status except for interrupt status and error status.
<> 144:ef7eb2e8f9f7 752 *
<> 144:ef7eb2e8f9f7 753 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 754 * @return Present SDHC's status flags mask(_sdhc_present_status_flag).
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756 static inline uint32_t SDHC_GetPresentStatusFlags(SDHC_Type *base)
<> 144:ef7eb2e8f9f7 757 {
<> 144:ef7eb2e8f9f7 758 return base->PRSSTAT;
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* @} */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /*!
<> 144:ef7eb2e8f9f7 764 * @name Bus Operations
<> 144:ef7eb2e8f9f7 765 * @{
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /*!
<> 144:ef7eb2e8f9f7 769 * @brief Get the capability information
<> 144:ef7eb2e8f9f7 770 *
<> 144:ef7eb2e8f9f7 771 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 772 * @param capability Structure to save capability information.
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability);
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /*!
<> 144:ef7eb2e8f9f7 777 * @brief Enable or disable SD bus clock.
<> 144:ef7eb2e8f9f7 778 *
<> 144:ef7eb2e8f9f7 779 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 780 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 781 */
<> 144:ef7eb2e8f9f7 782 static inline void SDHC_EnableSdClock(SDHC_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 if (enable)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788 else
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK;
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /*!
<> 144:ef7eb2e8f9f7 795 * @brief Set SD bus clock frequency.
<> 144:ef7eb2e8f9f7 796 *
<> 144:ef7eb2e8f9f7 797 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 798 * @param srcClock_Hz SDHC source clock frequency united in Hz.
<> 144:ef7eb2e8f9f7 799 * @param busClock_Hz SD bus clock frequency united in Hz.
<> 144:ef7eb2e8f9f7 800 *
<> 144:ef7eb2e8f9f7 801 * @return The nearest frequency of busClock_Hz configured to SD bus.
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /*!
<> 144:ef7eb2e8f9f7 806 * @brief Send 80 clocks to the card to set it to be active state.
<> 144:ef7eb2e8f9f7 807 *
<> 144:ef7eb2e8f9f7 808 * This function must be called after each time the card is inserted to make card can receive command correctly.
<> 144:ef7eb2e8f9f7 809 *
<> 144:ef7eb2e8f9f7 810 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 811 * @param timeout Timeout to initialize card.
<> 144:ef7eb2e8f9f7 812 * @retval true Set card active successfully.
<> 144:ef7eb2e8f9f7 813 * @retval false Set card active failed.
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /*!
<> 144:ef7eb2e8f9f7 818 * @brief Set the data transfer width.
<> 144:ef7eb2e8f9f7 819 *
<> 144:ef7eb2e8f9f7 820 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 821 * @param width Data transfer width.
<> 144:ef7eb2e8f9f7 822 */
<> 144:ef7eb2e8f9f7 823 static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t width)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 base->PROCTL = ((base->PROCTL & ~SDHC_PROCTL_DTW_MASK) | SDHC_PROCTL_DTW(width));
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /*!
<> 144:ef7eb2e8f9f7 829 * @brief Set card transfer-related configuration.
<> 144:ef7eb2e8f9f7 830 *
<> 144:ef7eb2e8f9f7 831 * This function fills card transfer-related command argument/transfer flag/data size. Command and data will be sent by
<> 144:ef7eb2e8f9f7 832 * SDHC after calling this function.
<> 144:ef7eb2e8f9f7 833 *
<> 144:ef7eb2e8f9f7 834 * Example:
<> 144:ef7eb2e8f9f7 835 @code
<> 144:ef7eb2e8f9f7 836 sdhc_transfer_config_t transferConfig;
<> 144:ef7eb2e8f9f7 837 transferConfig.dataBlockSize = 512U;
<> 144:ef7eb2e8f9f7 838 transferConfig.dataBlockCount = 2U;
<> 144:ef7eb2e8f9f7 839 transferConfig.commandArgument = 0x01AAU;
<> 144:ef7eb2e8f9f7 840 transferConfig.commandIndex = 8U;
<> 144:ef7eb2e8f9f7 841 transferConfig.flags |= (kSDHC_EnableDmaFlag | kSDHC_EnableAutoCommand12Flag | kSDHC_MultipleBlockFlag);
<> 144:ef7eb2e8f9f7 842 SDHC_SetTransferConfig(SDHC, &transferConfig);
<> 144:ef7eb2e8f9f7 843 @endcode
<> 144:ef7eb2e8f9f7 844 *
<> 144:ef7eb2e8f9f7 845 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 846 * @param config Command configuration structure.
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /*!
<> 144:ef7eb2e8f9f7 851 * @brief Get the command response.
<> 144:ef7eb2e8f9f7 852 *
<> 144:ef7eb2e8f9f7 853 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 854 * @param index The index of response register, range from 0 to 3.
<> 144:ef7eb2e8f9f7 855 * @return Response register transfer.
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 static inline uint32_t SDHC_GetCommandResponse(SDHC_Type *base, uint32_t index)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 assert(index < 4U);
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 return base->CMDRSP[index];
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /*!
<> 144:ef7eb2e8f9f7 865 * @brief Fill the the data port.
<> 144:ef7eb2e8f9f7 866 *
<> 144:ef7eb2e8f9f7 867 * This function is mainly used to implement the data transfer by Data Port instead of DMA.
<> 144:ef7eb2e8f9f7 868 *
<> 144:ef7eb2e8f9f7 869 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 870 * @param data The data about to be sent.
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872 static inline void SDHC_WriteData(SDHC_Type *base, uint32_t data)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 base->DATPORT = data;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /*!
<> 144:ef7eb2e8f9f7 878 * @brief Retrieve the data from the data port.
<> 144:ef7eb2e8f9f7 879 *
<> 144:ef7eb2e8f9f7 880 * This function is mainly used to implement the data transfer by Data Port instead of DMA.
<> 144:ef7eb2e8f9f7 881 *
<> 144:ef7eb2e8f9f7 882 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 883 * @return The data has been read.
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 static inline uint32_t SDHC_ReadData(SDHC_Type *base)
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 return base->DATPORT;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /*!
<> 144:ef7eb2e8f9f7 891 * @brief Enable or disable wakeup event in low power mode
<> 144:ef7eb2e8f9f7 892 *
<> 144:ef7eb2e8f9f7 893 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 894 * @param mask Wakeup events mask(_sdhc_wakeup_event).
<> 144:ef7eb2e8f9f7 895 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 static inline void SDHC_EnableWakeupEvent(SDHC_Type *base, uint32_t mask, bool enable)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 if (enable)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 base->PROCTL |= mask;
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903 else
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 base->PROCTL &= ~mask;
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /*!
<> 144:ef7eb2e8f9f7 910 * @brief Enable or disable card detection level for test.
<> 144:ef7eb2e8f9f7 911 *
<> 144:ef7eb2e8f9f7 912 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 913 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 914 */
<> 144:ef7eb2e8f9f7 915 static inline void SDHC_EnableCardDetectTest(SDHC_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 if (enable)
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 base->PROCTL |= SDHC_PROCTL_CDSS_MASK;
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921 else
<> 144:ef7eb2e8f9f7 922 {
<> 144:ef7eb2e8f9f7 923 base->PROCTL &= ~SDHC_PROCTL_CDSS_MASK;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /*!
<> 144:ef7eb2e8f9f7 928 * @brief Set card detection test level.
<> 144:ef7eb2e8f9f7 929 *
<> 144:ef7eb2e8f9f7 930 * This function set the card detection test level to indicate whether the card is inserted into SDHC when DAT[3]/
<> 144:ef7eb2e8f9f7 931 * CD pin is selected as card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is select
<> 144:ef7eb2e8f9f7 932 * as the card detection pin.
<> 144:ef7eb2e8f9f7 933 *
<> 144:ef7eb2e8f9f7 934 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 935 * @param high True to set the card detect level to high.
<> 144:ef7eb2e8f9f7 936 */
<> 144:ef7eb2e8f9f7 937 static inline void SDHC_SetCardDetectTestLevel(SDHC_Type *base, bool high)
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 if (high)
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 base->PROCTL |= SDHC_PROCTL_CDTL_MASK;
<> 144:ef7eb2e8f9f7 942 }
<> 144:ef7eb2e8f9f7 943 else
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 base->PROCTL &= ~SDHC_PROCTL_CDTL_MASK;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /*!
<> 144:ef7eb2e8f9f7 950 * @brief Enable or disable SDIO card control.
<> 144:ef7eb2e8f9f7 951 *
<> 144:ef7eb2e8f9f7 952 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 953 * @param mask SDIO card control flags mask(_sdhc_sdio_control_flag).
<> 144:ef7eb2e8f9f7 954 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 955 */
<> 144:ef7eb2e8f9f7 956 void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable);
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /*!
<> 144:ef7eb2e8f9f7 959 * @brief Restart a transaction which has stopped at the block gap for SDIO card.
<> 144:ef7eb2e8f9f7 960 *
<> 144:ef7eb2e8f9f7 961 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 static inline void SDHC_SetContinueRequest(SDHC_Type *base)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 base->PROCTL |= SDHC_PROCTL_CREQ_MASK;
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /*!
<> 144:ef7eb2e8f9f7 969 * @brief Configure the MMC boot feature.
<> 144:ef7eb2e8f9f7 970 *
<> 144:ef7eb2e8f9f7 971 * Example:
<> 144:ef7eb2e8f9f7 972 @code
<> 144:ef7eb2e8f9f7 973 sdhc_boot_config_t bootConfig;
<> 144:ef7eb2e8f9f7 974 bootConfig.ackTimeoutCount = 4;
<> 144:ef7eb2e8f9f7 975 bootConfig.bootMode = kSDHC_BootModeNormal;
<> 144:ef7eb2e8f9f7 976 bootConfig.blockCount = 5;
<> 144:ef7eb2e8f9f7 977 bootConfig.enableBootAck = true;
<> 144:ef7eb2e8f9f7 978 bootConfig.enableBoot = true;
<> 144:ef7eb2e8f9f7 979 enableBoot.enableAutoStopAtBlockGap = true;
<> 144:ef7eb2e8f9f7 980 SDHC_SetMmcBootConfig(SDHC, &bootConfig);
<> 144:ef7eb2e8f9f7 981 @endcode
<> 144:ef7eb2e8f9f7 982 *
<> 144:ef7eb2e8f9f7 983 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 984 * @param config The MMC boot configuration information.
<> 144:ef7eb2e8f9f7 985 */
<> 144:ef7eb2e8f9f7 986 void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /*!
<> 144:ef7eb2e8f9f7 989 * @brief Force to generate events according to the given mask.
<> 144:ef7eb2e8f9f7 990 *
<> 144:ef7eb2e8f9f7 991 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 992 * @param mask The force events mask(_sdhc_force_event).
<> 144:ef7eb2e8f9f7 993 */
<> 144:ef7eb2e8f9f7 994 static inline void SDHC_SetForceEvent(SDHC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 base->FEVT = mask;
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /* @} */
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /*!
<> 144:ef7eb2e8f9f7 1002 * @name Transactional
<> 144:ef7eb2e8f9f7 1003 * @{
<> 144:ef7eb2e8f9f7 1004 */
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /*!
<> 144:ef7eb2e8f9f7 1007 * @brief Transfer command/data using blocking way.
<> 144:ef7eb2e8f9f7 1008 *
<> 144:ef7eb2e8f9f7 1009 * This function waits until the command response/data is got or SDHC encounters error by polling the status flag.
<> 144:ef7eb2e8f9f7 1010 * Application must not call this API in multiple threads at the same time because of that this API doesn't support
<> 144:ef7eb2e8f9f7 1011 * reentry mechanism.
<> 144:ef7eb2e8f9f7 1012 *
<> 144:ef7eb2e8f9f7 1013 * @note Needn't to call the API 'SDHC_TransferCreateHandle' when calling this API.
<> 144:ef7eb2e8f9f7 1014 *
<> 144:ef7eb2e8f9f7 1015 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 1016 * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2.
<> 144:ef7eb2e8f9f7 1017 * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2.
<> 144:ef7eb2e8f9f7 1018 * @param transfer Transfer content.
<> 144:ef7eb2e8f9f7 1019 * @retval kStatus_InvalidArgument Argument is invalid.
<> 144:ef7eb2e8f9f7 1020 * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
<> 144:ef7eb2e8f9f7 1021 * @retval kStatus_SDHC_SendCommandFailed Send command failed.
<> 144:ef7eb2e8f9f7 1022 * @retval kStatus_SDHC_TransferDataFailed Transfer data failed.
<> 144:ef7eb2e8f9f7 1023 * @retval kStatus_Success Operate successfully.
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 status_t SDHC_TransferBlocking(SDHC_Type *base,
<> 144:ef7eb2e8f9f7 1026 uint32_t *admaTable,
<> 144:ef7eb2e8f9f7 1027 uint32_t admaTableWords,
<> 144:ef7eb2e8f9f7 1028 sdhc_transfer_t *transfer);
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /*!
<> 144:ef7eb2e8f9f7 1031 * @brief Create the SDHC handle.
<> 144:ef7eb2e8f9f7 1032 *
<> 144:ef7eb2e8f9f7 1033 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 1034 * @param handle SDHC handle pointer.
<> 144:ef7eb2e8f9f7 1035 * @param callback Structure pointer to contain all callback functions.
<> 144:ef7eb2e8f9f7 1036 * @param userData Callback function parameter.
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038 void SDHC_TransferCreateHandle(SDHC_Type *base,
<> 144:ef7eb2e8f9f7 1039 sdhc_handle_t *handle,
<> 144:ef7eb2e8f9f7 1040 const sdhc_transfer_callback_t *callback,
<> 144:ef7eb2e8f9f7 1041 void *userData);
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /*!
<> 144:ef7eb2e8f9f7 1044 * @brief Transfer command/data using interrupt and asynchronous way.
<> 144:ef7eb2e8f9f7 1045 *
<> 144:ef7eb2e8f9f7 1046 * This function send command and data and return immediately. It doesn't wait the transfer complete or encounter error.
<> 144:ef7eb2e8f9f7 1047 * Application must not call this API in multiple threads at the same time because of that this API doesn't support
<> 144:ef7eb2e8f9f7 1048 * reentry mechanism.
<> 144:ef7eb2e8f9f7 1049 *
<> 144:ef7eb2e8f9f7 1050 * @note Must call the API 'SDHC_TransferCreateHandle' when calling this API.
<> 144:ef7eb2e8f9f7 1051 *
<> 144:ef7eb2e8f9f7 1052 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 1053 * @param handle SDHC handle.
<> 144:ef7eb2e8f9f7 1054 * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2.
<> 144:ef7eb2e8f9f7 1055 * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2.
<> 144:ef7eb2e8f9f7 1056 * @param transfer Transfer content.
<> 144:ef7eb2e8f9f7 1057 * @retval kStatus_InvalidArgument Argument is invalid.
<> 144:ef7eb2e8f9f7 1058 * @retval kStatus_SDHC_BusyTransferring Busy transferring.
<> 144:ef7eb2e8f9f7 1059 * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
<> 144:ef7eb2e8f9f7 1060 * @retval kStatus_Success Operate successfully.
<> 144:ef7eb2e8f9f7 1061 */
<> 144:ef7eb2e8f9f7 1062 status_t SDHC_TransferNonBlocking(
<> 144:ef7eb2e8f9f7 1063 SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer);
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /*!
<> 144:ef7eb2e8f9f7 1066 * @brief IRQ handler for SDHC
<> 144:ef7eb2e8f9f7 1067 *
<> 144:ef7eb2e8f9f7 1068 * This function deals with IRQs on the given host controller.
<> 144:ef7eb2e8f9f7 1069 *
<> 144:ef7eb2e8f9f7 1070 * @param base SDHC peripheral base address.
<> 144:ef7eb2e8f9f7 1071 * @param handle SDHC handle.
<> 144:ef7eb2e8f9f7 1072 */
<> 144:ef7eb2e8f9f7 1073 void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle);
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* @} */
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079 #endif
<> 144:ef7eb2e8f9f7 1080 /*! @} */
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 #endif /* _FSL_SDHC_H_*/