Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_rnga.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_rnga.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*******************************************************************************
<> 144:ef7eb2e8f9f7 36 * Definitions
<> 144:ef7eb2e8f9f7 37 *******************************************************************************/
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /*******************************************************************************
<> 144:ef7eb2e8f9f7 40 * RNG_CR - RNGA Control Register
<> 144:ef7eb2e8f9f7 41 ******************************************************************************/
<> 144:ef7eb2e8f9f7 42 /*!
<> 144:ef7eb2e8f9f7 43 * @brief RNG_CR - RNGA Control Register (RW)
<> 144:ef7eb2e8f9f7 44 *
<> 144:ef7eb2e8f9f7 45 * Reset value: 0x00000000U
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * Controls the operation of RNGA.
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49 /*!
<> 144:ef7eb2e8f9f7 50 * @name Constants and macros for entire RNG_CR register
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 /*@{*/
<> 144:ef7eb2e8f9f7 53 #define RNG_CR_REG(base) ((base)->CR)
<> 144:ef7eb2e8f9f7 54 #define RNG_RD_CR(base) (RNG_CR_REG(base))
<> 144:ef7eb2e8f9f7 55 #define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value))
<> 144:ef7eb2e8f9f7 56 #define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
<> 144:ef7eb2e8f9f7 57 /*@}*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /*!
<> 144:ef7eb2e8f9f7 60 * @name Register RNG_CR, field GO[0] (RW)
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
<> 144:ef7eb2e8f9f7 63 * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
<> 144:ef7eb2e8f9f7 64 * OR[RANDOUT] with data.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * Values:
<> 144:ef7eb2e8f9f7 67 * - 0b0 - Disabled
<> 144:ef7eb2e8f9f7 68 * - 0b1 - Enabled
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 /*@{*/
<> 144:ef7eb2e8f9f7 71 /*! @brief Read current value of the RNG_CR_GO field. */
<> 144:ef7eb2e8f9f7 72 #define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /*! @brief Set the GO field to a new value. */
<> 144:ef7eb2e8f9f7 75 #define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
<> 144:ef7eb2e8f9f7 76 /*@}*/
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /*!
<> 144:ef7eb2e8f9f7 79 * @name Register RNG_CR, field SLP[4] (RW)
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
<> 144:ef7eb2e8f9f7 82 * mode by asserting the DOZE signal.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * Values:
<> 144:ef7eb2e8f9f7 85 * - 0b0 - Normal mode
<> 144:ef7eb2e8f9f7 86 * - 0b1 - Sleep (low-power) mode
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 /*@{*/
<> 144:ef7eb2e8f9f7 89 /*! @brief Read current value of the RNG_CR_SLP field. */
<> 144:ef7eb2e8f9f7 90 #define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*! @brief Set the SLP field to a new value. */
<> 144:ef7eb2e8f9f7 93 #define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
<> 144:ef7eb2e8f9f7 94 /*@}*/
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /*******************************************************************************
<> 144:ef7eb2e8f9f7 97 * RNG_SR - RNGA Status Register
<> 144:ef7eb2e8f9f7 98 ******************************************************************************/
<> 144:ef7eb2e8f9f7 99 #define RNG_SR_REG(base) ((base)->SR)
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /*!
<> 144:ef7eb2e8f9f7 102 * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 * Indicates the number of random-data words that are in OR[RANDOUT], which
<> 144:ef7eb2e8f9f7 105 * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
<> 144:ef7eb2e8f9f7 106 * is not 0, then the contents of a random number contained in OR[RANDOUT] are
<> 144:ef7eb2e8f9f7 107 * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * Values:
<> 144:ef7eb2e8f9f7 110 * - 0b00000000 - No words (empty)
<> 144:ef7eb2e8f9f7 111 * - 0b00000001 - One word (valid)
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 /*@{*/
<> 144:ef7eb2e8f9f7 114 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
<> 144:ef7eb2e8f9f7 115 #define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
<> 144:ef7eb2e8f9f7 116 /*@}*/
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /*!
<> 144:ef7eb2e8f9f7 119 * @name Register RNG_SR, field SLP[4] (RO)
<> 144:ef7eb2e8f9f7 120 *
<> 144:ef7eb2e8f9f7 121 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
<> 144:ef7eb2e8f9f7 122 * mode by asserting the DOZE signal.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 * Values:
<> 144:ef7eb2e8f9f7 125 * - 0b0 - Normal mode
<> 144:ef7eb2e8f9f7 126 * - 0b1 - Sleep (low-power) mode
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 /*@{*/
<> 144:ef7eb2e8f9f7 129 /*! @brief Read current value of the RNG_SR_SLP field. */
<> 144:ef7eb2e8f9f7 130 #define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
<> 144:ef7eb2e8f9f7 131 /*@}*/
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /*******************************************************************************
<> 144:ef7eb2e8f9f7 134 * RNG_OR - RNGA Output Register
<> 144:ef7eb2e8f9f7 135 ******************************************************************************/
<> 144:ef7eb2e8f9f7 136 /*!
<> 144:ef7eb2e8f9f7 137 * @brief RNG_OR - RNGA Output Register (RO)
<> 144:ef7eb2e8f9f7 138 *
<> 144:ef7eb2e8f9f7 139 * Reset value: 0x00000000U
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 * Stores a random-data word generated by RNGA.
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 /*!
<> 144:ef7eb2e8f9f7 144 * @name Constants and macros for entire RNG_OR register
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 /*@{*/
<> 144:ef7eb2e8f9f7 147 #define RNG_OR_REG(base) ((base)->OR)
<> 144:ef7eb2e8f9f7 148 #define RNG_RD_OR(base) (RNG_OR_REG(base))
<> 144:ef7eb2e8f9f7 149 /*@}*/
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /*******************************************************************************
<> 144:ef7eb2e8f9f7 152 * RNG_ER - RNGA Entropy Register
<> 144:ef7eb2e8f9f7 153 ******************************************************************************/
<> 144:ef7eb2e8f9f7 154 /*!
<> 144:ef7eb2e8f9f7 155 * @brief RNG_ER - RNGA Entropy Register (WORZ)
<> 144:ef7eb2e8f9f7 156 *
<> 144:ef7eb2e8f9f7 157 * Reset value: 0x00000000U
<> 144:ef7eb2e8f9f7 158 *
<> 144:ef7eb2e8f9f7 159 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
<> 144:ef7eb2e8f9f7 160 * to seed its pseudorandom algorithm. This is a write-only register; reads
<> 144:ef7eb2e8f9f7 161 * return all zeros.
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 /*!
<> 144:ef7eb2e8f9f7 164 * @name Constants and macros for entire RNG_ER register
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 /*@{*/
<> 144:ef7eb2e8f9f7 167 #define RNG_ER_REG(base) ((base)->ER)
<> 144:ef7eb2e8f9f7 168 #define RNG_RD_ER(base) (RNG_ER_REG(base))
<> 144:ef7eb2e8f9f7 169 #define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value))
<> 144:ef7eb2e8f9f7 170 /*@}*/
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /*******************************************************************************
<> 144:ef7eb2e8f9f7 173 * Prototypes
<> 144:ef7eb2e8f9f7 174 *******************************************************************************/
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 static uint32_t rnga_ReadEntropy(RNG_Type *base);
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /*******************************************************************************
<> 144:ef7eb2e8f9f7 179 * Code
<> 144:ef7eb2e8f9f7 180 ******************************************************************************/
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 void RNGA_Init(RNG_Type *base)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 /* Enable the clock gate. */
<> 144:ef7eb2e8f9f7 185 CLOCK_EnableClock(kCLOCK_Rnga0);
<> 144:ef7eb2e8f9f7 186 CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
<> 144:ef7eb2e8f9f7 187 CLOCK_EnableClock(kCLOCK_Rnga0);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Reset the registers for RNGA module to reset state. */
<> 144:ef7eb2e8f9f7 190 RNG_WR_CR(base, 0);
<> 144:ef7eb2e8f9f7 191 /* Enables the RNGA random data generation and loading.*/
<> 144:ef7eb2e8f9f7 192 RNG_WR_CR_GO(base, 1);
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 void RNGA_Deinit(RNG_Type *base)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 /* Disable the clock for RNGA module.*/
<> 144:ef7eb2e8f9f7 198 CLOCK_DisableClock(kCLOCK_Rnga0);
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /*!
<> 144:ef7eb2e8f9f7 202 * @brief Get a random data from RNGA.
<> 144:ef7eb2e8f9f7 203 *
<> 144:ef7eb2e8f9f7 204 * @param base RNGA base address
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 static uint32_t rnga_ReadEntropy(RNG_Type *base)
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 uint32_t data = 0;
<> 144:ef7eb2e8f9f7 209 if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 /* Wait for valid random-data.*/
<> 144:ef7eb2e8f9f7 212 while (RNG_RD_SR_OREG_LVL(base) == 0)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215 data = RNG_RD_OR(base);
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217 /* Get random-data word generated by RNGA.*/
<> 144:ef7eb2e8f9f7 218 return data;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 status_t result = kStatus_Success;
<> 144:ef7eb2e8f9f7 224 uint32_t random_32;
<> 144:ef7eb2e8f9f7 225 uint8_t *random_p;
<> 144:ef7eb2e8f9f7 226 uint32_t random_size;
<> 144:ef7eb2e8f9f7 227 uint8_t *data_p = (uint8_t *)data;
<> 144:ef7eb2e8f9f7 228 uint32_t i;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Check input parameters.*/
<> 144:ef7eb2e8f9f7 231 if (base && data && data_size)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 do
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Read Entropy.*/
<> 144:ef7eb2e8f9f7 236 random_32 = rnga_ReadEntropy(base);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 random_p = (uint8_t *)&random_32;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 if (data_size < sizeof(random_32))
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 random_size = data_size;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 else
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 random_size = sizeof(random_32);
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 for (i = 0; i < random_size; i++)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 *data_p++ = *random_p++;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 data_size -= random_size;
<> 144:ef7eb2e8f9f7 255 } while (data_size > 0);
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257 else
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 result = kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 return result;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 RNG_WR_CR_SLP(base, (uint32_t)mode);
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 rnga_mode_t RNGA_GetMode(RNG_Type *base)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 return (rnga_mode_t)RNG_RD_SR_SLP(base);
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 void RNGA_Seed(RNG_Type *base, uint32_t seed)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Write to RNGA Entropy Register.*/
<> 144:ef7eb2e8f9f7 278 RNG_WR_ER(base, seed);
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 #endif /* FSL_FEATURE_SOC_RNG_COUNT */