Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_port.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_PORT_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_PORT_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup port_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! Version 2.0.1. */
<> 144:ef7eb2e8f9f7 49 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief Internal resistor pull feature selection */
<> 144:ef7eb2e8f9f7 53 enum _port_pull
<> 144:ef7eb2e8f9f7 54 {
<> 144:ef7eb2e8f9f7 55 kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */
<> 144:ef7eb2e8f9f7 56 kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */
<> 144:ef7eb2e8f9f7 57 kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */
<> 144:ef7eb2e8f9f7 58 };
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /*! @brief Slew rate selection */
<> 144:ef7eb2e8f9f7 61 enum _port_slew_rate
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */
<> 144:ef7eb2e8f9f7 64 kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */
<> 144:ef7eb2e8f9f7 65 };
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
<> 144:ef7eb2e8f9f7 68 /*! @brief Internal resistor pull feature enable/disable */
<> 144:ef7eb2e8f9f7 69 enum _port_open_drain_enable
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */
<> 144:ef7eb2e8f9f7 72 kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */
<> 144:ef7eb2e8f9f7 73 };
<> 144:ef7eb2e8f9f7 74 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /*! @brief Passive filter feature enable/disable */
<> 144:ef7eb2e8f9f7 77 enum _port_passive_filter_enable
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */
<> 144:ef7eb2e8f9f7 80 kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */
<> 144:ef7eb2e8f9f7 81 };
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /*! @brief Configures the drive strength. */
<> 144:ef7eb2e8f9f7 84 enum _port_drive_strength
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */
<> 144:ef7eb2e8f9f7 87 kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */
<> 144:ef7eb2e8f9f7 88 };
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
<> 144:ef7eb2e8f9f7 91 /*! @brief Unlock/lock the pin control register field[15:0] */
<> 144:ef7eb2e8f9f7 92 enum _port_lock_register
<> 144:ef7eb2e8f9f7 93 {
<> 144:ef7eb2e8f9f7 94 kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
<> 144:ef7eb2e8f9f7 95 kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
<> 144:ef7eb2e8f9f7 96 };
<> 144:ef7eb2e8f9f7 97 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /*! @brief Pin mux selection */
<> 144:ef7eb2e8f9f7 100 typedef enum _port_mux
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */
<> 144:ef7eb2e8f9f7 103 kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */
<> 144:ef7eb2e8f9f7 104 kPORT_MuxAlt2 = 2U, /*!< chip-specific */
<> 144:ef7eb2e8f9f7 105 kPORT_MuxAlt3 = 3U, /*!< chip-specific */
<> 144:ef7eb2e8f9f7 106 kPORT_MuxAlt4 = 4U, /*!< chip-specific */
<> 144:ef7eb2e8f9f7 107 kPORT_MuxAlt5 = 5U, /*!< chip-specific */
<> 144:ef7eb2e8f9f7 108 kPORT_MuxAlt6 = 6U, /*!< chip-specific */
<> 144:ef7eb2e8f9f7 109 kPORT_MuxAlt7 = 7U, /*!< chip-specific */
<> 144:ef7eb2e8f9f7 110 } port_mux_t;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*! @brief Configures the interrupt generation condition. */
<> 144:ef7eb2e8f9f7 113 typedef enum _port_interrupt
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
<> 144:ef7eb2e8f9f7 116 #if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
<> 144:ef7eb2e8f9f7 117 kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
<> 144:ef7eb2e8f9f7 118 kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
<> 144:ef7eb2e8f9f7 119 kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
<> 144:ef7eb2e8f9f7 120 #endif
<> 144:ef7eb2e8f9f7 121 #if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
<> 144:ef7eb2e8f9f7 122 kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
<> 144:ef7eb2e8f9f7 123 kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
<> 144:ef7eb2e8f9f7 124 kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
<> 144:ef7eb2e8f9f7 125 #endif
<> 144:ef7eb2e8f9f7 126 kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
<> 144:ef7eb2e8f9f7 127 kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
<> 144:ef7eb2e8f9f7 128 kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
<> 144:ef7eb2e8f9f7 129 kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
<> 144:ef7eb2e8f9f7 130 kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
<> 144:ef7eb2e8f9f7 131 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
<> 144:ef7eb2e8f9f7 132 kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */
<> 144:ef7eb2e8f9f7 133 kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135 } port_interrupt_t;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
<> 144:ef7eb2e8f9f7 138 /*! @brief Digital filter clock source selection */
<> 144:ef7eb2e8f9f7 139 typedef enum _port_digital_filter_clock_source
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
<> 144:ef7eb2e8f9f7 142 kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
<> 144:ef7eb2e8f9f7 143 } port_digital_filter_clock_source_t;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /*! @brief PORT digital filter feature configuration definition */
<> 144:ef7eb2e8f9f7 146 typedef struct _port_digital_filter_config
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 uint32_t digitalFilterWidth; /*!< Set digital filter width */
<> 144:ef7eb2e8f9f7 149 port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
<> 144:ef7eb2e8f9f7 150 } port_digital_filter_config_t;
<> 144:ef7eb2e8f9f7 151 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /*! @brief PORT pin config structure */
<> 144:ef7eb2e8f9f7 154 typedef struct _port_pin_config
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */
<> 144:ef7eb2e8f9f7 157 uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */
<> 144:ef7eb2e8f9f7 158 uint16_t : 1;
<> 144:ef7eb2e8f9f7 159 uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */
<> 144:ef7eb2e8f9f7 160 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
<> 144:ef7eb2e8f9f7 161 uint16_t openDrainEnable : 1; /*!< open drain enable/disable */
<> 144:ef7eb2e8f9f7 162 #else
<> 144:ef7eb2e8f9f7 163 uint16_t : 1;
<> 144:ef7eb2e8f9f7 164 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
<> 144:ef7eb2e8f9f7 165 uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */
<> 144:ef7eb2e8f9f7 166 uint16_t : 1;
<> 144:ef7eb2e8f9f7 167 uint16_t mux : 3; /*!< pin mux Configure */
<> 144:ef7eb2e8f9f7 168 uint16_t : 4;
<> 144:ef7eb2e8f9f7 169 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
<> 144:ef7eb2e8f9f7 170 uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */
<> 144:ef7eb2e8f9f7 171 #else
<> 144:ef7eb2e8f9f7 172 uint16_t : 1;
<> 144:ef7eb2e8f9f7 173 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
<> 144:ef7eb2e8f9f7 174 } port_pin_config_t;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /*******************************************************************************
<> 144:ef7eb2e8f9f7 177 * API
<> 144:ef7eb2e8f9f7 178 ******************************************************************************/
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 181 extern "C" {
<> 144:ef7eb2e8f9f7 182 #endif
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /*! @name Configuration */
<> 144:ef7eb2e8f9f7 185 /*@{*/
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /*!
<> 144:ef7eb2e8f9f7 188 * @brief Sets the port PCR register.
<> 144:ef7eb2e8f9f7 189 *
<> 144:ef7eb2e8f9f7 190 * This is an example to define an input pin or output pin PCR configuration:
<> 144:ef7eb2e8f9f7 191 * @code
<> 144:ef7eb2e8f9f7 192 * // Define a digital input pin PCR configuration
<> 144:ef7eb2e8f9f7 193 * port_pin_config_t config = {
<> 144:ef7eb2e8f9f7 194 * kPORT_PullUp,
<> 144:ef7eb2e8f9f7 195 * kPORT_FastSlewRate,
<> 144:ef7eb2e8f9f7 196 * kPORT_PassiveFilterDisable,
<> 144:ef7eb2e8f9f7 197 * kPORT_OpenDrainDisable,
<> 144:ef7eb2e8f9f7 198 * kPORT_LowDriveStrength,
<> 144:ef7eb2e8f9f7 199 * kPORT_MuxAsGpio,
<> 144:ef7eb2e8f9f7 200 * kPORT_UnLockRegister,
<> 144:ef7eb2e8f9f7 201 * };
<> 144:ef7eb2e8f9f7 202 * @endcode
<> 144:ef7eb2e8f9f7 203 *
<> 144:ef7eb2e8f9f7 204 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 205 * @param pin PORT pin number.
<> 144:ef7eb2e8f9f7 206 * @param config PORT PCR register configure structure.
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 assert(config);
<> 144:ef7eb2e8f9f7 211 uint32_t addr = (uint32_t)&base->PCR[pin];
<> 144:ef7eb2e8f9f7 212 *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /*!
<> 144:ef7eb2e8f9f7 216 * @brief Sets the port PCR register for multiple pins.
<> 144:ef7eb2e8f9f7 217 *
<> 144:ef7eb2e8f9f7 218 * This is an example to define input pins or output pins PCR configuration:
<> 144:ef7eb2e8f9f7 219 * @code
<> 144:ef7eb2e8f9f7 220 * // Define a digital input pin PCR configuration
<> 144:ef7eb2e8f9f7 221 * port_pin_config_t config = {
<> 144:ef7eb2e8f9f7 222 * kPORT_PullUp ,
<> 144:ef7eb2e8f9f7 223 * kPORT_PullEnable,
<> 144:ef7eb2e8f9f7 224 * kPORT_FastSlewRate,
<> 144:ef7eb2e8f9f7 225 * kPORT_PassiveFilterDisable,
<> 144:ef7eb2e8f9f7 226 * kPORT_OpenDrainDisable,
<> 144:ef7eb2e8f9f7 227 * kPORT_LowDriveStrength,
<> 144:ef7eb2e8f9f7 228 * kPORT_MuxAsGpio,
<> 144:ef7eb2e8f9f7 229 * kPORT_UnlockRegister,
<> 144:ef7eb2e8f9f7 230 * };
<> 144:ef7eb2e8f9f7 231 * @endcode
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 234 * @param mask PORT pins' numbers macro.
<> 144:ef7eb2e8f9f7 235 * @param config PORT PCR register configure structure.
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 assert(config);
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 uint16_t pcrl = *((const uint16_t *)config);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 if (mask & 0xffffU)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 if (mask >> 16)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 base->GPCHR = (mask & 0xffff0000U) | pcrl;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /*!
<> 144:ef7eb2e8f9f7 254 * @brief Configures the pin muxing.
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 257 * @param pin PORT pin number.
<> 144:ef7eb2e8f9f7 258 * @param mux pin muxing slot selection.
<> 144:ef7eb2e8f9f7 259 * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
<> 144:ef7eb2e8f9f7 260 * - #kPORT_MuxAsGpio : Set as GPIO.
<> 144:ef7eb2e8f9f7 261 * - #kPORT_MuxAlt2 : chip-specific.
<> 144:ef7eb2e8f9f7 262 * - #kPORT_MuxAlt3 : chip-specific.
<> 144:ef7eb2e8f9f7 263 * - #kPORT_MuxAlt4 : chip-specific.
<> 144:ef7eb2e8f9f7 264 * - #kPORT_MuxAlt5 : chip-specific.
<> 144:ef7eb2e8f9f7 265 * - #kPORT_MuxAlt6 : chip-specific.
<> 144:ef7eb2e8f9f7 266 * - #kPORT_MuxAlt7 : chip-specific.
<> 144:ef7eb2e8f9f7 267 * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
<> 144:ef7eb2e8f9f7 268 * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will
<> 144:ef7eb2e8f9f7 269 * be reset to zero : kPORT_PinDisabledOrAnalog).
<> 144:ef7eb2e8f9f7 270 * This function is recommended to use in the case you just need to reset the pin mux
<> 144:ef7eb2e8f9f7 271 *
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /*!
<> 144:ef7eb2e8f9f7 281 * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
<> 144:ef7eb2e8f9f7 282 *
<> 144:ef7eb2e8f9f7 283 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 284 * @param mask PORT pins' numbers macro.
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 if (enable == true)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 base->DFER |= mask;
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292 else
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 base->DFER &= ~mask;
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /*!
<> 144:ef7eb2e8f9f7 299 * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
<> 144:ef7eb2e8f9f7 300 *
<> 144:ef7eb2e8f9f7 301 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 302 * @param config PORT digital filter configuration structure.
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 assert(config);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 base->DFCR = PORT_DFCR_CS(config->clockSource);
<> 144:ef7eb2e8f9f7 309 base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /*@}*/
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /*! @name Interrupt */
<> 144:ef7eb2e8f9f7 317 /*@{*/
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /*!
<> 144:ef7eb2e8f9f7 320 * @brief Configures the port pin interrupt/DMA request.
<> 144:ef7eb2e8f9f7 321 *
<> 144:ef7eb2e8f9f7 322 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 323 * @param pin PORT pin number.
<> 144:ef7eb2e8f9f7 324 * @param config PORT pin interrupt configuration.
<> 144:ef7eb2e8f9f7 325 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
<> 144:ef7eb2e8f9f7 326 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
<> 144:ef7eb2e8f9f7 327 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
<> 144:ef7eb2e8f9f7 328 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
<> 144:ef7eb2e8f9f7 329 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
<> 144:ef7eb2e8f9f7 330 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
<> 144:ef7eb2e8f9f7 331 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
<> 144:ef7eb2e8f9f7 332 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
<> 144:ef7eb2e8f9f7 333 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
<> 144:ef7eb2e8f9f7 334 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
<> 144:ef7eb2e8f9f7 335 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
<> 144:ef7eb2e8f9f7 336 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
<> 144:ef7eb2e8f9f7 337 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit).
<> 144:ef7eb2e8f9f7 338 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit).
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /*!
<> 144:ef7eb2e8f9f7 346 * @brief Reads the whole port status flag.
<> 144:ef7eb2e8f9f7 347 *
<> 144:ef7eb2e8f9f7 348 * If a pin is configured to generate the DMA request, the corresponding flag
<> 144:ef7eb2e8f9f7 349 * is cleared automatically at the completion of the requested DMA transfer.
<> 144:ef7eb2e8f9f7 350 * Otherwise, the flag remains set until a logic one is written to that flag.
<> 144:ef7eb2e8f9f7 351 * If configured for a level sensitive interrupt that remains asserted, the flag
<> 144:ef7eb2e8f9f7 352 * is set again immediately.
<> 144:ef7eb2e8f9f7 353 *
<> 144:ef7eb2e8f9f7 354 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 355 * @return Current port interrupt status flags, for example, 0x00010001 means the
<> 144:ef7eb2e8f9f7 356 * pin 0 and 17 have the interrupt.
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 return base->ISFR;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /*!
<> 144:ef7eb2e8f9f7 364 * @brief Clears the multiple pins' interrupt status flag.
<> 144:ef7eb2e8f9f7 365 *
<> 144:ef7eb2e8f9f7 366 * @param base PORT peripheral base pointer.
<> 144:ef7eb2e8f9f7 367 * @param mask PORT pins' numbers macro.
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 base->ISFR = mask;
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /*@}*/
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 #endif
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /*! @}*/
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 #endif /* _FSL_PORT_H_ */