Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_pit.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_PIT_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_PIT_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup pit_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 #define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
<> 144:ef7eb2e8f9f7 49 /*@}*/
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /*!
<> 144:ef7eb2e8f9f7 52 * @brief List of PIT channels
<> 144:ef7eb2e8f9f7 53 * @note Actual number of available channels is SoC dependent
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 typedef enum _pit_chnl
<> 144:ef7eb2e8f9f7 56 {
<> 144:ef7eb2e8f9f7 57 kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/
<> 144:ef7eb2e8f9f7 58 kPIT_Chnl_1, /*!< PIT channel number 1 */
<> 144:ef7eb2e8f9f7 59 kPIT_Chnl_2, /*!< PIT channel number 2 */
<> 144:ef7eb2e8f9f7 60 kPIT_Chnl_3, /*!< PIT channel number 3 */
<> 144:ef7eb2e8f9f7 61 } pit_chnl_t;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /*! @brief List of PIT interrupts */
<> 144:ef7eb2e8f9f7 64 typedef enum _pit_interrupt_enable
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/
<> 144:ef7eb2e8f9f7 67 } pit_interrupt_enable_t;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /*! @brief List of PIT status flags */
<> 144:ef7eb2e8f9f7 70 typedef enum _pit_status_flags
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */
<> 144:ef7eb2e8f9f7 73 } pit_status_flags_t;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /*!
<> 144:ef7eb2e8f9f7 76 * @brief PIT config structure
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * This structure holds the configuration settings for the PIT peripheral. To initialize this
<> 144:ef7eb2e8f9f7 79 * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a
<> 144:ef7eb2e8f9f7 80 * pointer to your config structure instance.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 * The config struct can be made const so it resides in flash
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 typedef struct _pit_config
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */
<> 144:ef7eb2e8f9f7 87 } pit_config_t;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /*******************************************************************************
<> 144:ef7eb2e8f9f7 90 * API
<> 144:ef7eb2e8f9f7 91 ******************************************************************************/
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 94 extern "C" {
<> 144:ef7eb2e8f9f7 95 #endif
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /*!
<> 144:ef7eb2e8f9f7 98 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /*!
<> 144:ef7eb2e8f9f7 103 * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation.
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 * @note This API should be called at the beginning of the application using the PIT driver.
<> 144:ef7eb2e8f9f7 106 *
<> 144:ef7eb2e8f9f7 107 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 108 * @param config Pointer to user's PIT config structure
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 void PIT_Init(PIT_Type *base, const pit_config_t *config);
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*!
<> 144:ef7eb2e8f9f7 113 * @brief Gate the PIT clock and disable the PIT module
<> 144:ef7eb2e8f9f7 114 *
<> 144:ef7eb2e8f9f7 115 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 void PIT_Deinit(PIT_Type *base);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /*!
<> 144:ef7eb2e8f9f7 120 * @brief Fill in the PIT config struct with the default settings
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * The default values are:
<> 144:ef7eb2e8f9f7 123 * @code
<> 144:ef7eb2e8f9f7 124 * config->enableRunInDebug = false;
<> 144:ef7eb2e8f9f7 125 * @endcode
<> 144:ef7eb2e8f9f7 126 * @param config Pointer to user's PIT config structure.
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 static inline void PIT_GetDefaultConfig(pit_config_t *config)
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 assert(config);
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Timers are stopped in Debug mode */
<> 144:ef7eb2e8f9f7 133 config->enableRunInDebug = false;
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 #if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /*!
<> 144:ef7eb2e8f9f7 139 * @brief Enables or disables chaining a timer with the previous timer.
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 * When a timer has a chain mode enabled, it only counts after the previous
<> 144:ef7eb2e8f9f7 142 * timer has expired. If the timer n-1 has counted down to 0, counter n
<> 144:ef7eb2e8f9f7 143 * decrements the value by one. Each timer is 32-bits, this allows the developers
<> 144:ef7eb2e8f9f7 144 * to chain timers together and form a longer timer (64-bits and larger). The first timer
<> 144:ef7eb2e8f9f7 145 * (timer 0) cannot be chained to any other timer.
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 148 * @param channel Timer channel number which is chained with the previous timer
<> 144:ef7eb2e8f9f7 149 * @param enable Enable or disable chain.
<> 144:ef7eb2e8f9f7 150 * true: Current timer is chained with the previous timer.
<> 144:ef7eb2e8f9f7 151 * false: Timer doesn't chain with other timers.
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable)
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 if (enable)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 else
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK;
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /*! @}*/
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /*!
<> 144:ef7eb2e8f9f7 170 * @name Interrupt Interface
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /*!
<> 144:ef7eb2e8f9f7 175 * @brief Enables the selected PIT interrupts.
<> 144:ef7eb2e8f9f7 176 *
<> 144:ef7eb2e8f9f7 177 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 178 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 179 * @param mask The interrupts to enable. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 180 * enumeration ::pit_interrupt_enable_t
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 base->CHANNEL[channel].TCTRL |= mask;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /*!
<> 144:ef7eb2e8f9f7 188 * @brief Disables the selected PIT interrupts.
<> 144:ef7eb2e8f9f7 189 *
<> 144:ef7eb2e8f9f7 190 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 191 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 192 * @param mask The interrupts to disable. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 193 * enumeration ::pit_interrupt_enable_t
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 base->CHANNEL[channel].TCTRL &= ~mask;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*!
<> 144:ef7eb2e8f9f7 201 * @brief Gets the enabled PIT interrupts.
<> 144:ef7eb2e8f9f7 202 *
<> 144:ef7eb2e8f9f7 203 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 204 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 205 *
<> 144:ef7eb2e8f9f7 206 * @return The enabled interrupts. This is the logical OR of members of the
<> 144:ef7eb2e8f9f7 207 * enumeration ::pit_interrupt_enable_t
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK);
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /*! @}*/
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /*!
<> 144:ef7eb2e8f9f7 217 * @name Status Interface
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /*!
<> 144:ef7eb2e8f9f7 222 * @brief Gets the PIT status flags
<> 144:ef7eb2e8f9f7 223 *
<> 144:ef7eb2e8f9f7 224 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 225 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 226 *
<> 144:ef7eb2e8f9f7 227 * @return The status flags. This is the logical OR of members of the
<> 144:ef7eb2e8f9f7 228 * enumeration ::pit_status_flags_t
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK);
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /*!
<> 144:ef7eb2e8f9f7 236 * @brief Clears the PIT status flags.
<> 144:ef7eb2e8f9f7 237 *
<> 144:ef7eb2e8f9f7 238 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 239 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 240 * @param mask The status flags to clear. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 241 * enumeration ::pit_status_flags_t
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 base->CHANNEL[channel].TFLG = mask;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /*! @}*/
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /*!
<> 144:ef7eb2e8f9f7 251 * @name Read and Write the timer period
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /*!
<> 144:ef7eb2e8f9f7 256 * @brief Sets the timer period in units of count.
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * Timers begin counting from the value set by this function until it reaches 0,
<> 144:ef7eb2e8f9f7 259 * then it will generate an interrupt and load this regiter value again.
<> 144:ef7eb2e8f9f7 260 * Writing a new value to this register will not restart the timer; instead the value
<> 144:ef7eb2e8f9f7 261 * will be loaded after the timer expires.
<> 144:ef7eb2e8f9f7 262 *
<> 144:ef7eb2e8f9f7 263 * @note User can call the utility macros provided in fsl_common.h to convert to ticks
<> 144:ef7eb2e8f9f7 264 *
<> 144:ef7eb2e8f9f7 265 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 266 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 267 * @param count Timer period in units of ticks
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 base->CHANNEL[channel].LDVAL = count;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /*!
<> 144:ef7eb2e8f9f7 275 * @brief Reads the current timer counting value.
<> 144:ef7eb2e8f9f7 276 *
<> 144:ef7eb2e8f9f7 277 * This function returns the real-time timer counting value, in a range from 0 to a
<> 144:ef7eb2e8f9f7 278 * timer period.
<> 144:ef7eb2e8f9f7 279 *
<> 144:ef7eb2e8f9f7 280 * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
<> 144:ef7eb2e8f9f7 281 *
<> 144:ef7eb2e8f9f7 282 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 283 * @param channel Timer channel number
<> 144:ef7eb2e8f9f7 284 *
<> 144:ef7eb2e8f9f7 285 * @return Current timer counting value in ticks
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 return base->CHANNEL[channel].CVAL;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /*! @}*/
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /*!
<> 144:ef7eb2e8f9f7 295 * @name Timer Start and Stop
<> 144:ef7eb2e8f9f7 296 * @{
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /*!
<> 144:ef7eb2e8f9f7 300 * @brief Starts the timer counting.
<> 144:ef7eb2e8f9f7 301 *
<> 144:ef7eb2e8f9f7 302 * After calling this function, timers load period value, count down to 0 and
<> 144:ef7eb2e8f9f7 303 * then load the respective start value again. Each time a timer reaches 0,
<> 144:ef7eb2e8f9f7 304 * it generates a trigger pulse and sets the timeout interrupt flag.
<> 144:ef7eb2e8f9f7 305 *
<> 144:ef7eb2e8f9f7 306 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 307 * @param channel Timer channel number.
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /*!
<> 144:ef7eb2e8f9f7 315 * @brief Stops the timer counting.
<> 144:ef7eb2e8f9f7 316 *
<> 144:ef7eb2e8f9f7 317 * This function stops every timer counting. Timers reload their periods
<> 144:ef7eb2e8f9f7 318 * respectively after the next time they call the PIT_DRV_StartTimer.
<> 144:ef7eb2e8f9f7 319 *
<> 144:ef7eb2e8f9f7 320 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 321 * @param channel Timer channel number.
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /*! @}*/
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /*!
<> 144:ef7eb2e8f9f7 333 * @brief Reads the current lifetime counter value.
<> 144:ef7eb2e8f9f7 334 *
<> 144:ef7eb2e8f9f7 335 * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
<> 144:ef7eb2e8f9f7 336 * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
<> 144:ef7eb2e8f9f7 337 * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
<> 144:ef7eb2e8f9f7 338 * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
<> 144:ef7eb2e8f9f7 339 * has the value of timer 0.
<> 144:ef7eb2e8f9f7 340 *
<> 144:ef7eb2e8f9f7 341 * @param base PIT peripheral base address
<> 144:ef7eb2e8f9f7 342 *
<> 144:ef7eb2e8f9f7 343 * @return Current lifetime timer value
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base);
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351 #endif
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /*! @}*/
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #endif /* _FSL_PIT_H_ */