Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_pdb.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef _FSL_PDB_H_
<> 144:ef7eb2e8f9f7 32 #define _FSL_PDB_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @addtogroup pdb
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*! @file */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*******************************************************************************
<> 144:ef7eb2e8f9f7 44 * Definitions
<> 144:ef7eb2e8f9f7 45 ******************************************************************************/
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 48 /*@{*/
<> 144:ef7eb2e8f9f7 49 /*! @brief PDB driver version 2.0.1. */
<> 144:ef7eb2e8f9f7 50 #define FSL_PDB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
<> 144:ef7eb2e8f9f7 51 /*@}*/
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*!
<> 144:ef7eb2e8f9f7 54 * @brief PDB flags.
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56 enum _pdb_status_flags
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 kPDB_LoadOKFlag = PDB_SC_LDOK_MASK, /*!< This flag is automatically cleared when the values in buffers are
<> 144:ef7eb2e8f9f7 59 loaded into the internal registers after the LDOK bit is set or the
<> 144:ef7eb2e8f9f7 60 PDBEN is cleared. */
<> 144:ef7eb2e8f9f7 61 kPDB_DelayEventFlag = PDB_SC_PDBIF_MASK, /*!< PDB timer delay event flag. */
<> 144:ef7eb2e8f9f7 62 };
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*!
<> 144:ef7eb2e8f9f7 65 * @brief PDB ADC PreTrigger channel flags.
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 enum _pdb_adc_pretrigger_flags
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 /* PDB PreTrigger channel match flags. */
<> 144:ef7eb2e8f9f7 70 kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-Trigger 0 flag. */
<> 144:ef7eb2e8f9f7 71 kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-Trigger 1 flag. */
<> 144:ef7eb2e8f9f7 72 #if (PDB_DLY_COUNT > 2)
<> 144:ef7eb2e8f9f7 73 kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-Trigger 2 flag. */
<> 144:ef7eb2e8f9f7 74 kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-Trigger 3 flag. */
<> 144:ef7eb2e8f9f7 75 #endif /* PDB_DLY_COUNT > 2 */
<> 144:ef7eb2e8f9f7 76 #if (PDB_DLY_COUNT > 4)
<> 144:ef7eb2e8f9f7 77 kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-Trigger 4 flag. */
<> 144:ef7eb2e8f9f7 78 kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-Trigger 5 flag. */
<> 144:ef7eb2e8f9f7 79 kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-Trigger 6 flag. */
<> 144:ef7eb2e8f9f7 80 kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-Trigger 7 flag. */
<> 144:ef7eb2e8f9f7 81 #endif /* PDB_DLY_COUNT > 4 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* PDB PreTrigger channel error flags. */
<> 144:ef7eb2e8f9f7 84 kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-Trigger 0 Error. */
<> 144:ef7eb2e8f9f7 85 kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-Trigger 1 Error. */
<> 144:ef7eb2e8f9f7 86 #if (PDB_DLY_COUNT > 2)
<> 144:ef7eb2e8f9f7 87 kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-Trigger 2 Error. */
<> 144:ef7eb2e8f9f7 88 kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-Trigger 3 Error. */
<> 144:ef7eb2e8f9f7 89 #endif /* PDB_DLY_COUNT > 2 */
<> 144:ef7eb2e8f9f7 90 #if (PDB_DLY_COUNT > 4)
<> 144:ef7eb2e8f9f7 91 kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-Trigger 4 Error. */
<> 144:ef7eb2e8f9f7 92 kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-Trigger 5 Error. */
<> 144:ef7eb2e8f9f7 93 kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-Trigger 6 Error. */
<> 144:ef7eb2e8f9f7 94 kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-Trigger 7 Error. */
<> 144:ef7eb2e8f9f7 95 #endif /* PDB_DLY_COUNT > 4 */
<> 144:ef7eb2e8f9f7 96 };
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*!
<> 144:ef7eb2e8f9f7 99 * @brief PDB buffer interrupts.
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 enum _pdb_interrupt_enable
<> 144:ef7eb2e8f9f7 102 {
<> 144:ef7eb2e8f9f7 103 kPDB_SequenceErrorInterruptEnable = PDB_SC_PDBEIE_MASK, /*!< PDB sequence error interrupt enable. */
<> 144:ef7eb2e8f9f7 104 kPDB_DelayInterruptEnable = PDB_SC_PDBIE_MASK, /*!< PDB delay interrupt enable. */
<> 144:ef7eb2e8f9f7 105 };
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /*!
<> 144:ef7eb2e8f9f7 108 * @brief PDB load value mode.
<> 144:ef7eb2e8f9f7 109 *
<> 144:ef7eb2e8f9f7 110 * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]).
<> 144:ef7eb2e8f9f7 111 * These values are for:
<> 144:ef7eb2e8f9f7 112 * - PDB counter (PDBx_MOD, PDBx_IDLY)
<> 144:ef7eb2e8f9f7 113 * - ADC trigger (PDBx_CHnDLYm)
<> 144:ef7eb2e8f9f7 114 * - DAC trigger (PDBx_DACINTx)
<> 144:ef7eb2e8f9f7 115 * - CMP trigger (PDBx_POyDLY)
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 typedef enum _pdb_load_value_mode
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 kPDB_LoadValueImmediately = 0U, /*!< Load immediately after 1 is written to LDOK. */
<> 144:ef7eb2e8f9f7 120 kPDB_LoadValueOnCounterOverflow = 1U, /*!< Load when the PDB counter overflows (reaches the MOD
<> 144:ef7eb2e8f9f7 121 register value). */
<> 144:ef7eb2e8f9f7 122 kPDB_LoadValueOnTriggerInput = 2U, /*!< Load a trigger input event is detected. */
<> 144:ef7eb2e8f9f7 123 kPDB_LoadValueOnCounterOverflowOrTriggerInput = 3U, /*!< Load either when the PDB counter overflows or a trigger
<> 144:ef7eb2e8f9f7 124 input is detected. */
<> 144:ef7eb2e8f9f7 125 } pdb_load_value_mode_t;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*!
<> 144:ef7eb2e8f9f7 128 * @brief Prescaler divider.
<> 144:ef7eb2e8f9f7 129 *
<> 144:ef7eb2e8f9f7 130 * Counting uses the peripheral clock divided by multiplication factor selected by times of MULT.
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 typedef enum _pdb_prescaler_divider
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 kPDB_PrescalerDivider1 = 0U, /*!< Divider x1. */
<> 144:ef7eb2e8f9f7 135 kPDB_PrescalerDivider2 = 1U, /*!< Divider x2. */
<> 144:ef7eb2e8f9f7 136 kPDB_PrescalerDivider4 = 2U, /*!< Divider x4. */
<> 144:ef7eb2e8f9f7 137 kPDB_PrescalerDivider8 = 3U, /*!< Divider x8. */
<> 144:ef7eb2e8f9f7 138 kPDB_PrescalerDivider16 = 4U, /*!< Divider x16. */
<> 144:ef7eb2e8f9f7 139 kPDB_PrescalerDivider32 = 5U, /*!< Divider x32. */
<> 144:ef7eb2e8f9f7 140 kPDB_PrescalerDivider64 = 6U, /*!< Divider x64. */
<> 144:ef7eb2e8f9f7 141 kPDB_PrescalerDivider128 = 7U, /*!< Divider x128. */
<> 144:ef7eb2e8f9f7 142 } pdb_prescaler_divider_t;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /*!
<> 144:ef7eb2e8f9f7 145 * @brief Multiplication factor select for prescaler.
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 * Selects the multiplication factor of the prescaler divider for the counter clock.
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 typedef enum _pdb_divider_multiplication_factor
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 kPDB_DividerMultiplicationFactor1 = 0U, /*!< Multiplication factor is 1. */
<> 144:ef7eb2e8f9f7 152 kPDB_DividerMultiplicationFactor10 = 1U, /*!< Multiplication factor is 10. */
<> 144:ef7eb2e8f9f7 153 kPDB_DividerMultiplicationFactor20 = 2U, /*!< Multiplication factor is 20. */
<> 144:ef7eb2e8f9f7 154 kPDB_DividerMultiplicationFactor40 = 3U, /*!< Multiplication factor is 40. */
<> 144:ef7eb2e8f9f7 155 } pdb_divider_multiplication_factor_t;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /*!
<> 144:ef7eb2e8f9f7 158 * @brief Trigger input source
<> 144:ef7eb2e8f9f7 159 *
<> 144:ef7eb2e8f9f7 160 * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or
<> 144:ef7eb2e8f9f7 161 * the software trigger. Refer to chip configuration details for the actual PDB input trigger connections.
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 typedef enum _pdb_trigger_input_source
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 kPDB_TriggerInput0 = 0U, /*!< Trigger-In 0. */
<> 144:ef7eb2e8f9f7 166 kPDB_TriggerInput1 = 1U, /*!< Trigger-In 1. */
<> 144:ef7eb2e8f9f7 167 kPDB_TriggerInput2 = 2U, /*!< Trigger-In 2. */
<> 144:ef7eb2e8f9f7 168 kPDB_TriggerInput3 = 3U, /*!< Trigger-In 3. */
<> 144:ef7eb2e8f9f7 169 kPDB_TriggerInput4 = 4U, /*!< Trigger-In 4. */
<> 144:ef7eb2e8f9f7 170 kPDB_TriggerInput5 = 5U, /*!< Trigger-In 5. */
<> 144:ef7eb2e8f9f7 171 kPDB_TriggerInput6 = 6U, /*!< Trigger-In 6. */
<> 144:ef7eb2e8f9f7 172 kPDB_TriggerInput7 = 7U, /*!< Trigger-In 7. */
<> 144:ef7eb2e8f9f7 173 kPDB_TriggerInput8 = 8U, /*!< Trigger-In 8. */
<> 144:ef7eb2e8f9f7 174 kPDB_TriggerInput9 = 9U, /*!< Trigger-In 9. */
<> 144:ef7eb2e8f9f7 175 kPDB_TriggerInput10 = 10U, /*!< Trigger-In 10. */
<> 144:ef7eb2e8f9f7 176 kPDB_TriggerInput11 = 11U, /*!< Trigger-In 11. */
<> 144:ef7eb2e8f9f7 177 kPDB_TriggerInput12 = 12U, /*!< Trigger-In 12. */
<> 144:ef7eb2e8f9f7 178 kPDB_TriggerInput13 = 13U, /*!< Trigger-In 13. */
<> 144:ef7eb2e8f9f7 179 kPDB_TriggerInput14 = 14U, /*!< Trigger-In 14. */
<> 144:ef7eb2e8f9f7 180 kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15. */
<> 144:ef7eb2e8f9f7 181 } pdb_trigger_input_source_t;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /*!
<> 144:ef7eb2e8f9f7 184 * @brief PDB module configuration.
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 typedef struct _pdb_config
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 pdb_load_value_mode_t loadValueMode; /*!< Select the load value mode. */
<> 144:ef7eb2e8f9f7 189 pdb_prescaler_divider_t prescalerDivider; /*!< Select the prescaler divider. */
<> 144:ef7eb2e8f9f7 190 pdb_divider_multiplication_factor_t dividerMultiplicationFactor; /*!< Multiplication factor select for prescaler. */
<> 144:ef7eb2e8f9f7 191 pdb_trigger_input_source_t triggerInputSource; /*!< Select the trigger input source. */
<> 144:ef7eb2e8f9f7 192 bool enableContinuousMode; /*!< Enable the PDB operation in Continuous mode.*/
<> 144:ef7eb2e8f9f7 193 } pdb_config_t;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /*!
<> 144:ef7eb2e8f9f7 196 * @brief PDB ADC Pre-Trigger configuration.
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 typedef struct _pdb_adc_pretrigger_config
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 uint32_t enablePreTriggerMask; /*!< PDB Channel Pre-Trigger Enable. */
<> 144:ef7eb2e8f9f7 201 uint32_t enableOutputMask; /*!< PDB Channel Pre-Trigger Output Select.
<> 144:ef7eb2e8f9f7 202 PDB channel's corresponding pre-trigger asserts when the counter
<> 144:ef7eb2e8f9f7 203 reaches the channel delay register. */
<> 144:ef7eb2e8f9f7 204 uint32_t enableBackToBackOperationMask; /*!< PDB Channel Pre-Trigger Back-to-Back Operation Enable.
<> 144:ef7eb2e8f9f7 205 Back-to-back operation enables the ADC conversions complete to trigger
<> 144:ef7eb2e8f9f7 206 the next PDB channel pre-trigger and trigger output, so that the ADC
<> 144:ef7eb2e8f9f7 207 conversions can be triggered on next set of configuration and results
<> 144:ef7eb2e8f9f7 208 registers.*/
<> 144:ef7eb2e8f9f7 209 } pdb_adc_pretrigger_config_t;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /*!
<> 144:ef7eb2e8f9f7 212 * @brief PDB DAC trigger configuration.
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 typedef struct _pdb_dac_trigger_config
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 bool enableExternalTriggerInput; /*!< Enables the external trigger for DAC interval counter. */
<> 144:ef7eb2e8f9f7 217 bool enableIntervalTrigger; /*!< Enables the DAC interval trigger. */
<> 144:ef7eb2e8f9f7 218 } pdb_dac_trigger_config_t;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /*******************************************************************************
<> 144:ef7eb2e8f9f7 221 * API
<> 144:ef7eb2e8f9f7 222 ******************************************************************************/
<> 144:ef7eb2e8f9f7 223 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 224 extern "C" {
<> 144:ef7eb2e8f9f7 225 #endif
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /*!
<> 144:ef7eb2e8f9f7 228 * @name Initialization
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /*!
<> 144:ef7eb2e8f9f7 233 * @brief Initializes the PDB module.
<> 144:ef7eb2e8f9f7 234 *
<> 144:ef7eb2e8f9f7 235 * This function is to make the initialization for PDB module. The operations includes are:
<> 144:ef7eb2e8f9f7 236 * - Enable the clock for PDB instance.
<> 144:ef7eb2e8f9f7 237 * - Configure the PDB module.
<> 144:ef7eb2e8f9f7 238 * - Enable the PDB module.
<> 144:ef7eb2e8f9f7 239 *
<> 144:ef7eb2e8f9f7 240 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 241 * @param config Pointer to configuration structure. See "pdb_config_t".
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 void PDB_Init(PDB_Type *base, const pdb_config_t *config);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /*!
<> 144:ef7eb2e8f9f7 246 * @brief De-initializes the PDB module.
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 void PDB_Deinit(PDB_Type *base);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /*!
<> 144:ef7eb2e8f9f7 253 * @brief Initializes the PDB user configure structure.
<> 144:ef7eb2e8f9f7 254 *
<> 144:ef7eb2e8f9f7 255 * This function initializes the user configure structure to default value. the default value are:
<> 144:ef7eb2e8f9f7 256 * @code
<> 144:ef7eb2e8f9f7 257 * config->loadValueMode = kPDB_LoadValueImmediately;
<> 144:ef7eb2e8f9f7 258 * config->prescalerDivider = kPDB_PrescalerDivider1;
<> 144:ef7eb2e8f9f7 259 * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1;
<> 144:ef7eb2e8f9f7 260 * config->triggerInputSource = kPDB_TriggerSoftware;
<> 144:ef7eb2e8f9f7 261 * config->enableContinuousMode = false;
<> 144:ef7eb2e8f9f7 262 * @endcode
<> 144:ef7eb2e8f9f7 263 * @param config Pointer to configuration structure. See "pdb_config_t".
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 void PDB_GetDefaultConfig(pdb_config_t *config);
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /*!
<> 144:ef7eb2e8f9f7 268 * @brief Enables the PDB module.
<> 144:ef7eb2e8f9f7 269 *
<> 144:ef7eb2e8f9f7 270 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 271 * @param enable Enable the module or not.
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 static inline void PDB_Enable(PDB_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 if (enable)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 base->SC |= PDB_SC_PDBEN_MASK;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 else
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 base->SC &= ~PDB_SC_PDBEN_MASK;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* @} */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /*!
<> 144:ef7eb2e8f9f7 288 * @name Basic Counter
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /*!
<> 144:ef7eb2e8f9f7 293 * @brief Triggers the PDB counter by software.
<> 144:ef7eb2e8f9f7 294 *
<> 144:ef7eb2e8f9f7 295 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 static inline void PDB_DoSoftwareTrigger(PDB_Type *base)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 base->SC |= PDB_SC_SWTRIG_MASK;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /*!
<> 144:ef7eb2e8f9f7 303 * @brief Loads the counter values.
<> 144:ef7eb2e8f9f7 304 *
<> 144:ef7eb2e8f9f7 305 * This function is to load the counter values from their internal buffer.
<> 144:ef7eb2e8f9f7 306 * See "pdb_load_value_mode_t" about PDB's load mode.
<> 144:ef7eb2e8f9f7 307 *
<> 144:ef7eb2e8f9f7 308 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 static inline void PDB_DoLoadValues(PDB_Type *base)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 base->SC |= PDB_SC_LDOK_MASK;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /*!
<> 144:ef7eb2e8f9f7 316 * @brief Enables the DMA for the PDB module.
<> 144:ef7eb2e8f9f7 317 *
<> 144:ef7eb2e8f9f7 318 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 319 * @param enable Enable the feature or not.
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 static inline void PDB_EnableDMA(PDB_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 if (enable)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 base->SC |= PDB_SC_DMAEN_MASK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 else
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 base->SC &= ~PDB_SC_DMAEN_MASK;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /*!
<> 144:ef7eb2e8f9f7 334 * @brief Enables the interrupts for the PDB module.
<> 144:ef7eb2e8f9f7 335 *
<> 144:ef7eb2e8f9f7 336 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 337 * @param mask Mask value for interrupts. See "_pdb_interrupt_enable".
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 static inline void PDB_EnableInterrupts(PDB_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK)));
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 base->SC |= mask;
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /*!
<> 144:ef7eb2e8f9f7 347 * @brief Disables the interrupts for the PDB module.
<> 144:ef7eb2e8f9f7 348 *
<> 144:ef7eb2e8f9f7 349 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 350 * @param mask Mask value for interrupts. See "_pdb_interrupt_enable".
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 static inline void PDB_DisableInterrupts(PDB_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK)));
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 base->SC &= ~mask;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /*!
<> 144:ef7eb2e8f9f7 360 * @brief Gets the status flags of the PDB module.
<> 144:ef7eb2e8f9f7 361 *
<> 144:ef7eb2e8f9f7 362 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 363 *
<> 144:ef7eb2e8f9f7 364 * @return Mask value for asserted flags. See "_pdb_status_flags".
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 static inline uint32_t PDB_GetStatusFlags(PDB_Type *base)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 return base->SC & (PDB_SC_PDBIF_MASK | PDB_SC_LDOK_MASK);
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /*!
<> 144:ef7eb2e8f9f7 372 * @brief Clears the status flags of the PDB module.
<> 144:ef7eb2e8f9f7 373 *
<> 144:ef7eb2e8f9f7 374 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 375 * @param mask Mask value of flags. See "_pdb_status_flags".
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 assert(0U == (mask & ~PDB_SC_PDBIF_MASK));
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 base->SC &= ~mask;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /*!
<> 144:ef7eb2e8f9f7 385 * @brief Specifies the period of the counter.
<> 144:ef7eb2e8f9f7 386 *
<> 144:ef7eb2e8f9f7 387 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 388 * @param value Setting value for the modulus. 16-bit is available.
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 base->MOD = PDB_MOD_MOD(value);
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /*!
<> 144:ef7eb2e8f9f7 396 * @brief Gets the PDB counter's current value.
<> 144:ef7eb2e8f9f7 397 *
<> 144:ef7eb2e8f9f7 398 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 399 *
<> 144:ef7eb2e8f9f7 400 * @return PDB counter's current value.
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 static inline uint32_t PDB_GetCounterValue(PDB_Type *base)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return base->CNT;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*!
<> 144:ef7eb2e8f9f7 408 * @brief Sets the value for PDB counter delay event.
<> 144:ef7eb2e8f9f7 409 *
<> 144:ef7eb2e8f9f7 410 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 411 * @param value Setting value for PDB counter delay event. 16-bit is available.
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value)
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 base->IDLY = PDB_IDLY_IDLY(value);
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 /* @} */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /*!
<> 144:ef7eb2e8f9f7 420 * @name ADC Pre-Trigger
<> 144:ef7eb2e8f9f7 421 * @{
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /*!
<> 144:ef7eb2e8f9f7 425 * @brief Configures the ADC PreTrigger in PDB module.
<> 144:ef7eb2e8f9f7 426 *
<> 144:ef7eb2e8f9f7 427 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 428 * @param channel Channel index for ADC instance.
<> 144:ef7eb2e8f9f7 429 * @param config Pointer to configuration structure. See "pdb_adc_pretrigger_config_t".
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 assert(channel < PDB_C1_COUNT);
<> 144:ef7eb2e8f9f7 434 assert(NULL != config);
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) |
<> 144:ef7eb2e8f9f7 437 PDB_C1_EN(config->enableOutputMask);
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /*!
<> 144:ef7eb2e8f9f7 441 * @brief Sets the value for ADC Pre-Trigger delay event.
<> 144:ef7eb2e8f9f7 442 *
<> 144:ef7eb2e8f9f7 443 * This function is to set the value for ADC Pre-Trigger delay event. IT Specifies the delay value for the channel's
<> 144:ef7eb2e8f9f7 444 * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the setting value here.
<> 144:ef7eb2e8f9f7 445 *
<> 144:ef7eb2e8f9f7 446 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 447 * @param channel Channel index for ADC instance.
<> 144:ef7eb2e8f9f7 448 * @param preChannel Channel group index for ADC instance.
<> 144:ef7eb2e8f9f7 449 * @param value Setting value for ADC Pre-Trigger delay event. 16-bit is available.
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value)
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 assert(channel < PDB_C1_COUNT);
<> 144:ef7eb2e8f9f7 454 assert(preChannel < PDB_DLY_COUNT);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value);
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /*!
<> 144:ef7eb2e8f9f7 460 * @brief Gets the ADC Pre-Trigger's status flags.
<> 144:ef7eb2e8f9f7 461 *
<> 144:ef7eb2e8f9f7 462 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 463 * @param channel Channel index for ADC instance.
<> 144:ef7eb2e8f9f7 464 *
<> 144:ef7eb2e8f9f7 465 * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags".
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467 static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 assert(channel < PDB_C1_COUNT);
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 return base->CH[channel].S;
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /*!
<> 144:ef7eb2e8f9f7 475 * @brief Clears the ADC Pre-Trigger's status flags.
<> 144:ef7eb2e8f9f7 476 *
<> 144:ef7eb2e8f9f7 477 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 478 * @param channel Channel index for ADC instance.
<> 144:ef7eb2e8f9f7 479 * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags".
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 assert(channel < PDB_C1_COUNT);
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 base->CH[channel].S &= ~mask;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* @} */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 #if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC
<> 144:ef7eb2e8f9f7 491 /*!
<> 144:ef7eb2e8f9f7 492 * @name DAC Interval Trigger
<> 144:ef7eb2e8f9f7 493 * @{
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /*!
<> 144:ef7eb2e8f9f7 497 * @brief Configures the DAC trigger in PDB module.
<> 144:ef7eb2e8f9f7 498 *
<> 144:ef7eb2e8f9f7 499 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 500 * @param channel Channel index for DAC instance.
<> 144:ef7eb2e8f9f7 501 * @param config Pointer to configuration structure. See "pdb_dac_trigger_config_t".
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503 void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /*!
<> 144:ef7eb2e8f9f7 506 * @brief Sets the value for the DAC interval event.
<> 144:ef7eb2e8f9f7 507 *
<> 144:ef7eb2e8f9f7 508 * This fucntion is to set the value for DAC interval event. DAC interval trigger would trigger the DAC module to update
<> 144:ef7eb2e8f9f7 509 * buffer when the DAC interval counter is equal to the setting value here.
<> 144:ef7eb2e8f9f7 510 *
<> 144:ef7eb2e8f9f7 511 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 512 * @param channel Channel index for DAC instance.
<> 144:ef7eb2e8f9f7 513 * @param value Setting value for the DAC interval event.
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 assert(channel < PDB_INT_COUNT);
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 base->DAC[channel].INT = PDB_INT_INT(value);
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* @} */
<> 144:ef7eb2e8f9f7 523 #endif /* FSL_FEATURE_PDB_HAS_DAC */
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /*!
<> 144:ef7eb2e8f9f7 526 * @name Pulse-Out Trigger
<> 144:ef7eb2e8f9f7 527 * @{
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /*!
<> 144:ef7eb2e8f9f7 531 * @brief Enables the pulse out trigger channels.
<> 144:ef7eb2e8f9f7 532 *
<> 144:ef7eb2e8f9f7 533 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 534 * @param channelMask Channel mask value for multiple pulse out trigger channel.
<> 144:ef7eb2e8f9f7 535 * @param enable Enable the feature or not.
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 if (enable)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 base->POEN |= PDB_POEN_POEN(channelMask);
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543 else
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 base->POEN &= ~(PDB_POEN_POEN(channelMask));
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /*!
<> 144:ef7eb2e8f9f7 550 * @brief Sets event values for pulse out trigger.
<> 144:ef7eb2e8f9f7 551 *
<> 144:ef7eb2e8f9f7 552 * This function is used to set event values for pulse output trigger.
<> 144:ef7eb2e8f9f7 553 * These pulse output trigger delay values specify the delay for the PDB Pulse-Out. Pulse-Out goes high when the PDB
<> 144:ef7eb2e8f9f7 554 * counter is equal to the pulse output high value (value1). Pulse-Out goes low when the PDB counter is equal to the
<> 144:ef7eb2e8f9f7 555 * pulse output low value (value2).
<> 144:ef7eb2e8f9f7 556 *
<> 144:ef7eb2e8f9f7 557 * @param base PDB peripheral base address.
<> 144:ef7eb2e8f9f7 558 * @param channel Channel index for pulse out trigger channel.
<> 144:ef7eb2e8f9f7 559 * @param value1 Setting value for pulse out high.
<> 144:ef7eb2e8f9f7 560 * @param value2 Setting value for pulse out low.
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562 static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 assert(channel < PDB_PODLY_COUNT);
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 base->PODLY[channel] = PDB_PODLY_DLY1(value1) | PDB_PODLY_DLY2(value2);
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* @} */
<> 144:ef7eb2e8f9f7 570 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 #endif
<> 144:ef7eb2e8f9f7 573 /*!
<> 144:ef7eb2e8f9f7 574 * @}
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 #endif /* _FSL_PDB_H_ */