Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_lpuart.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_LPUART_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_LPUART_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup lpuart_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file*/
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief LPUART driver version 2.1.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief Error codes for the LPUART driver. */
<> 144:ef7eb2e8f9f7 53 enum _lpuart_status
<> 144:ef7eb2e8f9f7 54 {
<> 144:ef7eb2e8f9f7 55 kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
<> 144:ef7eb2e8f9f7 56 kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
<> 144:ef7eb2e8f9f7 57 kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
<> 144:ef7eb2e8f9f7 58 kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
<> 144:ef7eb2e8f9f7 59 kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */
<> 144:ef7eb2e8f9f7 60 kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */
<> 144:ef7eb2e8f9f7 61 kStatus_LPUART_FlagCannotClearManually =
<> 144:ef7eb2e8f9f7 62 MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
<> 144:ef7eb2e8f9f7 63 kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
<> 144:ef7eb2e8f9f7 64 kStatus_LPUART_RxRingBufferOverrun =
<> 144:ef7eb2e8f9f7 65 MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
<> 144:ef7eb2e8f9f7 66 kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
<> 144:ef7eb2e8f9f7 67 kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
<> 144:ef7eb2e8f9f7 68 kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
<> 144:ef7eb2e8f9f7 69 kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
<> 144:ef7eb2e8f9f7 70 };
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /*! @brief LPUART parity mode. */
<> 144:ef7eb2e8f9f7 73 typedef enum _lpuart_parity_mode
<> 144:ef7eb2e8f9f7 74 {
<> 144:ef7eb2e8f9f7 75 kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
<> 144:ef7eb2e8f9f7 76 kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
<> 144:ef7eb2e8f9f7 77 kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
<> 144:ef7eb2e8f9f7 78 } lpuart_parity_mode_t;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /*! @brief LPUART stop bit count. */
<> 144:ef7eb2e8f9f7 81 typedef enum _lpuart_stop_bit_count
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 kLPUART_OneStopBit = 0U, /*!< One stop bit */
<> 144:ef7eb2e8f9f7 84 kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
<> 144:ef7eb2e8f9f7 85 } lpuart_stop_bit_count_t;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*!
<> 144:ef7eb2e8f9f7 88 * @brief LPUART interrupt configuration structure, default settings all disabled.
<> 144:ef7eb2e8f9f7 89 *
<> 144:ef7eb2e8f9f7 90 * This structure contains the settings for all LPUART interrupt configurations.
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 enum _lpuart_interrupt_enable
<> 144:ef7eb2e8f9f7 93 {
<> 144:ef7eb2e8f9f7 94 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 144:ef7eb2e8f9f7 95 kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
<> 144:ef7eb2e8f9f7 96 #endif
<> 144:ef7eb2e8f9f7 97 kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
<> 144:ef7eb2e8f9f7 98 kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */
<> 144:ef7eb2e8f9f7 99 kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
<> 144:ef7eb2e8f9f7 100 kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */
<> 144:ef7eb2e8f9f7 101 kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */
<> 144:ef7eb2e8f9f7 102 kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */
<> 144:ef7eb2e8f9f7 103 kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */
<> 144:ef7eb2e8f9f7 104 kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */
<> 144:ef7eb2e8f9f7 105 kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */
<> 144:ef7eb2e8f9f7 106 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 144:ef7eb2e8f9f7 107 kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */
<> 144:ef7eb2e8f9f7 108 kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
<> 144:ef7eb2e8f9f7 109 #endif
<> 144:ef7eb2e8f9f7 110 };
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*!
<> 144:ef7eb2e8f9f7 113 * @brief LPUART status flags.
<> 144:ef7eb2e8f9f7 114 *
<> 144:ef7eb2e8f9f7 115 * This provides constants for the LPUART status flags for use in the LPUART functions.
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 enum _lpuart_flags
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 kLPUART_TxDataRegEmptyFlag =
<> 144:ef7eb2e8f9f7 120 (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
<> 144:ef7eb2e8f9f7 121 kLPUART_TransmissionCompleteFlag =
<> 144:ef7eb2e8f9f7 122 (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
<> 144:ef7eb2e8f9f7 123 kLPUART_RxDataRegFullFlag =
<> 144:ef7eb2e8f9f7 124 (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
<> 144:ef7eb2e8f9f7 125 kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
<> 144:ef7eb2e8f9f7 126 kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is
<> 144:ef7eb2e8f9f7 127 read from receive register */
<> 144:ef7eb2e8f9f7 128 kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these
<> 144:ef7eb2e8f9f7 129 samples differ, noise flag sets */
<> 144:ef7eb2e8f9f7 130 kLPUART_FramingErrorFlag =
<> 144:ef7eb2e8f9f7 131 (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
<> 144:ef7eb2e8f9f7 132 kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
<> 144:ef7eb2e8f9f7 133 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 144:ef7eb2e8f9f7 134 kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
<> 144:ef7eb2e8f9f7 135 detected and LIN circuit enabled */
<> 144:ef7eb2e8f9f7 136 #endif
<> 144:ef7eb2e8f9f7 137 kLPUART_RxActiveEdgeFlag =
<> 144:ef7eb2e8f9f7 138 (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
<> 144:ef7eb2e8f9f7 139 kLPUART_RxActiveFlag =
<> 144:ef7eb2e8f9f7 140 (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
<> 144:ef7eb2e8f9f7 141 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 144:ef7eb2e8f9f7 142 kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
<> 144:ef7eb2e8f9f7 143 kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
<> 144:ef7eb2e8f9f7 144 #endif
<> 144:ef7eb2e8f9f7 145 #if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
<> 144:ef7eb2e8f9f7 146 kLPUART_NoiseErrorInRxDataRegFlag =
<> 144:ef7eb2e8f9f7 147 (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
<> 144:ef7eb2e8f9f7 148 kLPUART_ParityErrorInRxDataRegFlag =
<> 144:ef7eb2e8f9f7 149 (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
<> 144:ef7eb2e8f9f7 150 #endif
<> 144:ef7eb2e8f9f7 151 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 144:ef7eb2e8f9f7 152 kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
<> 144:ef7eb2e8f9f7 153 kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
<> 144:ef7eb2e8f9f7 154 kLPUART_TxFifoOverflowFlag =
<> 144:ef7eb2e8f9f7 155 (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
<> 144:ef7eb2e8f9f7 156 kLPUART_RxFifoUnderflowFlag =
<> 144:ef7eb2e8f9f7 157 (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
<> 144:ef7eb2e8f9f7 158 #endif
<> 144:ef7eb2e8f9f7 159 };
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /*! @brief LPUART configure structure. */
<> 144:ef7eb2e8f9f7 162 typedef struct _lpuart_config
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 uint32_t baudRate_Bps; /*!< LPUART baud rate */
<> 144:ef7eb2e8f9f7 165 lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
<> 144:ef7eb2e8f9f7 166 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 144:ef7eb2e8f9f7 167 lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
<> 144:ef7eb2e8f9f7 168 #endif
<> 144:ef7eb2e8f9f7 169 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 144:ef7eb2e8f9f7 170 uint8_t txFifoWatermark; /*!< TX FIFO watermark */
<> 144:ef7eb2e8f9f7 171 uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
<> 144:ef7eb2e8f9f7 172 #endif
<> 144:ef7eb2e8f9f7 173 bool enableTx; /*!< Enable TX */
<> 144:ef7eb2e8f9f7 174 bool enableRx; /*!< Enable RX */
<> 144:ef7eb2e8f9f7 175 } lpuart_config_t;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /*! @brief LPUART transfer structure. */
<> 144:ef7eb2e8f9f7 178 typedef struct _lpuart_transfer
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 uint8_t *data; /*!< The buffer of data to be transfer.*/
<> 144:ef7eb2e8f9f7 181 size_t dataSize; /*!< The byte count to be transfer. */
<> 144:ef7eb2e8f9f7 182 } lpuart_transfer_t;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Forward declaration of the handle typedef. */
<> 144:ef7eb2e8f9f7 185 typedef struct _lpuart_handle lpuart_handle_t;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /*! @brief LPUART transfer callback function. */
<> 144:ef7eb2e8f9f7 188 typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /*! @brief LPUART handle structure. */
<> 144:ef7eb2e8f9f7 191 struct _lpuart_handle
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 uint8_t *volatile txData; /*!< Address of remaining data to send. */
<> 144:ef7eb2e8f9f7 194 volatile size_t txDataSize; /*!< Size of the remaining data to send. */
<> 144:ef7eb2e8f9f7 195 size_t txDataSizeAll; /*!< Size of the data to send out. */
<> 144:ef7eb2e8f9f7 196 uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
<> 144:ef7eb2e8f9f7 197 volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
<> 144:ef7eb2e8f9f7 198 size_t rxDataSizeAll; /*!< Size of the data to receive. */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
<> 144:ef7eb2e8f9f7 201 size_t rxRingBufferSize; /*!< Size of the ring buffer. */
<> 144:ef7eb2e8f9f7 202 volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
<> 144:ef7eb2e8f9f7 203 volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 lpuart_transfer_callback_t callback; /*!< Callback function. */
<> 144:ef7eb2e8f9f7 206 void *userData; /*!< LPUART callback function parameter.*/
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 volatile uint8_t txState; /*!< TX transfer state. */
<> 144:ef7eb2e8f9f7 209 volatile uint8_t rxState; /*!< RX transfer state */
<> 144:ef7eb2e8f9f7 210 };
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /*******************************************************************************
<> 144:ef7eb2e8f9f7 213 * API
<> 144:ef7eb2e8f9f7 214 ******************************************************************************/
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 217 extern "C" {
<> 144:ef7eb2e8f9f7 218 #endif /* _cplusplus */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /*!
<> 144:ef7eb2e8f9f7 221 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /*!
<> 144:ef7eb2e8f9f7 226 * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
<> 144:ef7eb2e8f9f7 227 *
<> 144:ef7eb2e8f9f7 228 * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
<> 144:ef7eb2e8f9f7 229 * to configure the configuration structure and get the default configuration.
<> 144:ef7eb2e8f9f7 230 * The example below shows how to use this API to configure the LPUART.
<> 144:ef7eb2e8f9f7 231 * @code
<> 144:ef7eb2e8f9f7 232 * lpuart_config_t lpuartConfig;
<> 144:ef7eb2e8f9f7 233 * lpuartConfig.baudRate_Bps = 115200U;
<> 144:ef7eb2e8f9f7 234 * lpuartConfig.parityMode = kLPUART_ParityDisabled;
<> 144:ef7eb2e8f9f7 235 * lpuartConfig.stopBitCount = kLPUART_OneStopBit;
<> 144:ef7eb2e8f9f7 236 * lpuartConfig.txFifoWatermark = 0;
<> 144:ef7eb2e8f9f7 237 * lpuartConfig.rxFifoWatermark = 1;
<> 144:ef7eb2e8f9f7 238 * LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
<> 144:ef7eb2e8f9f7 239 * @endcode
<> 144:ef7eb2e8f9f7 240 *
<> 144:ef7eb2e8f9f7 241 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 242 * @param config Pointer to a user-defined configuration structure.
<> 144:ef7eb2e8f9f7 243 * @param srcClock_Hz LPUART clock source frequency in HZ.
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /*!
<> 144:ef7eb2e8f9f7 248 * @brief Deinitializes a LPUART instance.
<> 144:ef7eb2e8f9f7 249 *
<> 144:ef7eb2e8f9f7 250 * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 void LPUART_Deinit(LPUART_Type *base);
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /*!
<> 144:ef7eb2e8f9f7 257 * @brief Gets the default configuration structure.
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * This function initializes the LPUART configuration structure to a default value. The default
<> 144:ef7eb2e8f9f7 260 * values are:
<> 144:ef7eb2e8f9f7 261 * lpuartConfig->baudRate_Bps = 115200U;
<> 144:ef7eb2e8f9f7 262 * lpuartConfig->parityMode = kLPUART_ParityDisabled;
<> 144:ef7eb2e8f9f7 263 * lpuartConfig->stopBitCount = kLPUART_OneStopBit;
<> 144:ef7eb2e8f9f7 264 * lpuartConfig->txFifoWatermark = 0;
<> 144:ef7eb2e8f9f7 265 * lpuartConfig->rxFifoWatermark = 1;
<> 144:ef7eb2e8f9f7 266 * lpuartConfig->enableTx = false;
<> 144:ef7eb2e8f9f7 267 * lpuartConfig->enableRx = false;
<> 144:ef7eb2e8f9f7 268 *
<> 144:ef7eb2e8f9f7 269 * @param config Pointer to a configuration structure.
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 void LPUART_GetDefaultConfig(lpuart_config_t *config);
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /*!
<> 144:ef7eb2e8f9f7 274 * @brief Sets the LPUART instance baudrate.
<> 144:ef7eb2e8f9f7 275 *
<> 144:ef7eb2e8f9f7 276 * This function configures the LPUART module baudrate. This function is used to update
<> 144:ef7eb2e8f9f7 277 * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
<> 144:ef7eb2e8f9f7 278 * @code
<> 144:ef7eb2e8f9f7 279 * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
<> 144:ef7eb2e8f9f7 280 * @endcode
<> 144:ef7eb2e8f9f7 281 *
<> 144:ef7eb2e8f9f7 282 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 283 * @param baudRate_Bps LPUART baudrate to be set.
<> 144:ef7eb2e8f9f7 284 * @param srcClock_Hz LPUART clock source frequency in HZ.
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* @} */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /*!
<> 144:ef7eb2e8f9f7 291 * @name Status
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /*!
<> 144:ef7eb2e8f9f7 296 * @brief Gets LPUART status flags.
<> 144:ef7eb2e8f9f7 297 *
<> 144:ef7eb2e8f9f7 298 * This function gets all LPUART status flags. The flags are returned as the logical
<> 144:ef7eb2e8f9f7 299 * OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
<> 144:ef7eb2e8f9f7 300 * compare the return value with enumerators in the @ref _lpuart_flags.
<> 144:ef7eb2e8f9f7 301 * For example, to check whether the TX is empty:
<> 144:ef7eb2e8f9f7 302 * @code
<> 144:ef7eb2e8f9f7 303 * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
<> 144:ef7eb2e8f9f7 304 * {
<> 144:ef7eb2e8f9f7 305 * ...
<> 144:ef7eb2e8f9f7 306 * }
<> 144:ef7eb2e8f9f7 307 * @endcode
<> 144:ef7eb2e8f9f7 308 *
<> 144:ef7eb2e8f9f7 309 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 310 * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /*!
<> 144:ef7eb2e8f9f7 315 * @brief Clears status flags with a provided mask.
<> 144:ef7eb2e8f9f7 316 *
<> 144:ef7eb2e8f9f7 317 * This function clears LPUART status flags with a provided mask. Automatically cleared flags
<> 144:ef7eb2e8f9f7 318 * can't be cleared by this function.
<> 144:ef7eb2e8f9f7 319 * Flags that can only cleared or set by hardware are:
<> 144:ef7eb2e8f9f7 320 * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
<> 144:ef7eb2e8f9f7 321 * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
<> 144:ef7eb2e8f9f7 322 * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
<> 144:ef7eb2e8f9f7 323 * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
<> 144:ef7eb2e8f9f7 324 *
<> 144:ef7eb2e8f9f7 325 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 326 * @param mask the status flags to be cleared. The user can use the enumerators in the
<> 144:ef7eb2e8f9f7 327 * _lpuart_status_flag_t to do the OR operation and get the mask.
<> 144:ef7eb2e8f9f7 328 * @return 0 succeed, others failed.
<> 144:ef7eb2e8f9f7 329 * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
<> 144:ef7eb2e8f9f7 330 * it is cleared automatically by hardware.
<> 144:ef7eb2e8f9f7 331 * @retval kStatus_Success Status in the mask are cleared.
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* @} */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /*!
<> 144:ef7eb2e8f9f7 338 * @name Interrupts
<> 144:ef7eb2e8f9f7 339 * @{
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /*!
<> 144:ef7eb2e8f9f7 343 * @brief Enables LPUART interrupts according to a provided mask.
<> 144:ef7eb2e8f9f7 344 *
<> 144:ef7eb2e8f9f7 345 * This function enables the LPUART interrupts according to a provided mask. The mask
<> 144:ef7eb2e8f9f7 346 * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
<> 144:ef7eb2e8f9f7 347 * This examples shows how to enable TX empty interrupt and RX full interrupt:
<> 144:ef7eb2e8f9f7 348 * @code
<> 144:ef7eb2e8f9f7 349 * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
<> 144:ef7eb2e8f9f7 350 * @endcode
<> 144:ef7eb2e8f9f7 351 *
<> 144:ef7eb2e8f9f7 352 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 353 * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /*!
<> 144:ef7eb2e8f9f7 358 * @brief Disables LPUART interrupts according to a provided mask.
<> 144:ef7eb2e8f9f7 359 *
<> 144:ef7eb2e8f9f7 360 * This function disables the LPUART interrupts according to a provided mask. The mask
<> 144:ef7eb2e8f9f7 361 * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
<> 144:ef7eb2e8f9f7 362 * This example shows how to disable the TX empty interrupt and RX full interrupt:
<> 144:ef7eb2e8f9f7 363 * @code
<> 144:ef7eb2e8f9f7 364 * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
<> 144:ef7eb2e8f9f7 365 * @endcode
<> 144:ef7eb2e8f9f7 366 *
<> 144:ef7eb2e8f9f7 367 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 368 * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /*!
<> 144:ef7eb2e8f9f7 373 * @brief Gets enabled LPUART interrupts.
<> 144:ef7eb2e8f9f7 374 *
<> 144:ef7eb2e8f9f7 375 * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
<> 144:ef7eb2e8f9f7 376 * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
<> 144:ef7eb2e8f9f7 377 * a specific interrupt enable status, compare the return value with enumerators
<> 144:ef7eb2e8f9f7 378 * in @ref _lpuart_interrupt_enable.
<> 144:ef7eb2e8f9f7 379 * For example, to check whether the TX empty interrupt is enabled:
<> 144:ef7eb2e8f9f7 380 * @code
<> 144:ef7eb2e8f9f7 381 * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
<> 144:ef7eb2e8f9f7 382 *
<> 144:ef7eb2e8f9f7 383 * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
<> 144:ef7eb2e8f9f7 384 * {
<> 144:ef7eb2e8f9f7 385 * ...
<> 144:ef7eb2e8f9f7 386 * }
<> 144:ef7eb2e8f9f7 387 * @endcode
<> 144:ef7eb2e8f9f7 388 *
<> 144:ef7eb2e8f9f7 389 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 390 * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 #if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
<> 144:ef7eb2e8f9f7 395 /*!
<> 144:ef7eb2e8f9f7 396 * @brief Gets the LPUART data register address.
<> 144:ef7eb2e8f9f7 397 *
<> 144:ef7eb2e8f9f7 398 * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
<> 144:ef7eb2e8f9f7 399 *
<> 144:ef7eb2e8f9f7 400 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 401 * @return LPUART data register addresses which are used both by the transmitter and receiver.
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 return (uint32_t) & (base->DATA);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /*!
<> 144:ef7eb2e8f9f7 409 * @brief Enables or disables the LPUART transmitter DMA request.
<> 144:ef7eb2e8f9f7 410 *
<> 144:ef7eb2e8f9f7 411 * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
<> 144:ef7eb2e8f9f7 412 *
<> 144:ef7eb2e8f9f7 413 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 414 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 if (enable)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 base->BAUD |= LPUART_BAUD_TDMAE_MASK;
<> 144:ef7eb2e8f9f7 421 base->CTRL |= LPUART_CTRL_TIE_MASK;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 else
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
<> 144:ef7eb2e8f9f7 426 base->CTRL &= ~LPUART_CTRL_TIE_MASK;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /*!
<> 144:ef7eb2e8f9f7 431 * @brief Enables or disables the LPUART receiver DMA.
<> 144:ef7eb2e8f9f7 432 *
<> 144:ef7eb2e8f9f7 433 * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
<> 144:ef7eb2e8f9f7 434 *
<> 144:ef7eb2e8f9f7 435 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 436 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 if (enable)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 base->BAUD |= LPUART_BAUD_RDMAE_MASK;
<> 144:ef7eb2e8f9f7 443 base->CTRL |= LPUART_CTRL_RIE_MASK;
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445 else
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
<> 144:ef7eb2e8f9f7 448 base->CTRL &= ~LPUART_CTRL_RIE_MASK;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* @} */
<> 144:ef7eb2e8f9f7 453 #endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /*!
<> 144:ef7eb2e8f9f7 456 * @name Bus Operations
<> 144:ef7eb2e8f9f7 457 * @{
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /*!
<> 144:ef7eb2e8f9f7 461 * @brief Enables or disables the LPUART transmitter.
<> 144:ef7eb2e8f9f7 462 *
<> 144:ef7eb2e8f9f7 463 * This function enables or disables the LPUART transmitter.
<> 144:ef7eb2e8f9f7 464 *
<> 144:ef7eb2e8f9f7 465 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 466 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 if (enable)
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 base->CTRL |= LPUART_CTRL_TE_MASK;
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474 else
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 base->CTRL &= ~LPUART_CTRL_TE_MASK;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /*!
<> 144:ef7eb2e8f9f7 481 * @brief Enables or disables the LPUART receiver.
<> 144:ef7eb2e8f9f7 482 *
<> 144:ef7eb2e8f9f7 483 * This function enables or disables the LPUART receiver.
<> 144:ef7eb2e8f9f7 484 *
<> 144:ef7eb2e8f9f7 485 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 486 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 if (enable)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 base->CTRL |= LPUART_CTRL_RE_MASK;
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494 else
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 base->CTRL &= ~LPUART_CTRL_RE_MASK;
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /*!
<> 144:ef7eb2e8f9f7 501 * @brief Writes to the transmitter register.
<> 144:ef7eb2e8f9f7 502 *
<> 144:ef7eb2e8f9f7 503 * This function writes data to the transmitter register directly. The upper layer must
<> 144:ef7eb2e8f9f7 504 * ensure that the TX register is empty or that the TX FIFO has room before calling this function.
<> 144:ef7eb2e8f9f7 505 *
<> 144:ef7eb2e8f9f7 506 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 507 * @param data Data write to the TX register.
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509 static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 base->DATA = data;
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /*!
<> 144:ef7eb2e8f9f7 515 * @brief Reads the RX register.
<> 144:ef7eb2e8f9f7 516 *
<> 144:ef7eb2e8f9f7 517 * This function reads data from the TX register directly. The upper layer must
<> 144:ef7eb2e8f9f7 518 * ensure that the RX register is full or that the TX FIFO has data before calling this function.
<> 144:ef7eb2e8f9f7 519 *
<> 144:ef7eb2e8f9f7 520 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 521 * @return Data read from data register.
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 return base->DATA;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /*!
<> 144:ef7eb2e8f9f7 529 * @brief Writes to transmitter register using a blocking method.
<> 144:ef7eb2e8f9f7 530 *
<> 144:ef7eb2e8f9f7 531 * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have
<> 144:ef7eb2e8f9f7 532 * room and then writes data to the transmitter buffer.
<> 144:ef7eb2e8f9f7 533 *
<> 144:ef7eb2e8f9f7 534 * @note This function does not check whether all data has been sent out to the bus.
<> 144:ef7eb2e8f9f7 535 * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
<> 144:ef7eb2e8f9f7 536 * finished.
<> 144:ef7eb2e8f9f7 537 *
<> 144:ef7eb2e8f9f7 538 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 539 * @param data Start address of the data to write.
<> 144:ef7eb2e8f9f7 540 * @param length Size of the data to write.
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /*!
<> 144:ef7eb2e8f9f7 545 * @brief Reads the RX data register using a blocking method.
<> 144:ef7eb2e8f9f7 546 *
<> 144:ef7eb2e8f9f7 547 * This function polls the RX register, waits for the RX register full or RX FIFO
<> 144:ef7eb2e8f9f7 548 * has data then reads data from the TX register.
<> 144:ef7eb2e8f9f7 549 *
<> 144:ef7eb2e8f9f7 550 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 551 * @param data Start address of the buffer to store the received data.
<> 144:ef7eb2e8f9f7 552 * @param length Size of the buffer.
<> 144:ef7eb2e8f9f7 553 * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
<> 144:ef7eb2e8f9f7 554 * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
<> 144:ef7eb2e8f9f7 555 * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
<> 144:ef7eb2e8f9f7 556 * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
<> 144:ef7eb2e8f9f7 557 * @retval kStatus_Success Successfully received all data.
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* @} */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /*!
<> 144:ef7eb2e8f9f7 564 * @name Transactional
<> 144:ef7eb2e8f9f7 565 * @{
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /*!
<> 144:ef7eb2e8f9f7 569 * @brief Initializes the LPUART handle.
<> 144:ef7eb2e8f9f7 570 *
<> 144:ef7eb2e8f9f7 571 * This function initializes the LPUART handle, which can be used for other LPUART
<> 144:ef7eb2e8f9f7 572 * transactional APIs. Usually, for a specified LPUART instance,
<> 144:ef7eb2e8f9f7 573 * call this API once to get the initialized handle.
<> 144:ef7eb2e8f9f7 574 *
<> 144:ef7eb2e8f9f7 575 * The LPUART driver supports the "background" receiving, which means that user can set up
<> 144:ef7eb2e8f9f7 576 * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
<> 144:ef7eb2e8f9f7 577 * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
<> 144:ef7eb2e8f9f7 578 * in the ring buffer, the user can get the received data from the ring buffer directly.
<> 144:ef7eb2e8f9f7 579 * The ring buffer is disabled if passing NULL as @p ringBuffer.
<> 144:ef7eb2e8f9f7 580 *
<> 144:ef7eb2e8f9f7 581 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 582 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 583 * @param callback Callback function.
<> 144:ef7eb2e8f9f7 584 * @param userData User data.
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 void LPUART_TransferCreateHandle(LPUART_Type *base,
<> 144:ef7eb2e8f9f7 587 lpuart_handle_t *handle,
<> 144:ef7eb2e8f9f7 588 lpuart_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 589 void *userData);
<> 144:ef7eb2e8f9f7 590 /*!
<> 144:ef7eb2e8f9f7 591 * @brief Transmits a buffer of data using the interrupt method.
<> 144:ef7eb2e8f9f7 592 *
<> 144:ef7eb2e8f9f7 593 * This function send data using an interrupt method. This is a non-blocking function, which
<> 144:ef7eb2e8f9f7 594 * returns directly without waiting for all data written to the transmitter register. When
<> 144:ef7eb2e8f9f7 595 * all data is written to the TX register in the ISR, the LPUART driver calls the callback
<> 144:ef7eb2e8f9f7 596 * function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
<> 144:ef7eb2e8f9f7 597 *
<> 144:ef7eb2e8f9f7 598 * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
<> 144:ef7eb2e8f9f7 599 * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
<> 144:ef7eb2e8f9f7 600 * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
<> 144:ef7eb2e8f9f7 601 *
<> 144:ef7eb2e8f9f7 602 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 603 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 604 * @param xfer LPUART transfer structure, refer to #lpuart_transfer_t.
<> 144:ef7eb2e8f9f7 605 * @retval kStatus_Success Successfully start the data transmission.
<> 144:ef7eb2e8f9f7 606 * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
<> 144:ef7eb2e8f9f7 607 * @retval kStatus_InvalidArgument Invalid argument.
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /*!
<> 144:ef7eb2e8f9f7 612 * @brief Sets up the RX ring buffer.
<> 144:ef7eb2e8f9f7 613 *
<> 144:ef7eb2e8f9f7 614 * This function sets up the RX ring buffer to a specific UART handle.
<> 144:ef7eb2e8f9f7 615 *
<> 144:ef7eb2e8f9f7 616 * When the RX ring buffer is used, data received is stored into the ring buffer even when
<> 144:ef7eb2e8f9f7 617 * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
<> 144:ef7eb2e8f9f7 618 * in the ring buffer, the user can get the received data from the ring buffer directly.
<> 144:ef7eb2e8f9f7 619 *
<> 144:ef7eb2e8f9f7 620 * @note When using RX ring buffer, one byte is reserved for internal use. In other
<> 144:ef7eb2e8f9f7 621 * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
<> 144:ef7eb2e8f9f7 622 *
<> 144:ef7eb2e8f9f7 623 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 624 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 625 * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
<> 144:ef7eb2e8f9f7 626 * @param ringBufferSize size of the ring buffer.
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
<> 144:ef7eb2e8f9f7 629 lpuart_handle_t *handle,
<> 144:ef7eb2e8f9f7 630 uint8_t *ringBuffer,
<> 144:ef7eb2e8f9f7 631 size_t ringBufferSize);
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /*!
<> 144:ef7eb2e8f9f7 634 * @brief Abort the background transfer and uninstall the ring buffer.
<> 144:ef7eb2e8f9f7 635 *
<> 144:ef7eb2e8f9f7 636 * This function aborts the background transfer and uninstalls the ring buffer.
<> 144:ef7eb2e8f9f7 637 *
<> 144:ef7eb2e8f9f7 638 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 639 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /*!
<> 144:ef7eb2e8f9f7 644 * @brief Aborts the interrupt-driven data transmit.
<> 144:ef7eb2e8f9f7 645 *
<> 144:ef7eb2e8f9f7 646 * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
<> 144:ef7eb2e8f9f7 647 * how many bytes are still not sent out.
<> 144:ef7eb2e8f9f7 648 *
<> 144:ef7eb2e8f9f7 649 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 650 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /*!
<> 144:ef7eb2e8f9f7 655 * @brief Get the number of bytes that have been written to LPUART TX register.
<> 144:ef7eb2e8f9f7 656 *
<> 144:ef7eb2e8f9f7 657 * This function gets the number of bytes that have been written to LPUART TX
<> 144:ef7eb2e8f9f7 658 * register by interrupt method.
<> 144:ef7eb2e8f9f7 659 *
<> 144:ef7eb2e8f9f7 660 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 661 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 662 * @param count Send bytes count.
<> 144:ef7eb2e8f9f7 663 * @retval kStatus_NoTransferInProgress No send in progress.
<> 144:ef7eb2e8f9f7 664 * @retval kStatus_InvalidArgument Parameter is invalid.
<> 144:ef7eb2e8f9f7 665 * @retval kStatus_Success Get successfully through the parameter \p count;
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /*!
<> 144:ef7eb2e8f9f7 670 * @brief Receives a buffer of data using the interrupt method.
<> 144:ef7eb2e8f9f7 671 *
<> 144:ef7eb2e8f9f7 672 * This function receives data using an interrupt method. This is a non-blocking function
<> 144:ef7eb2e8f9f7 673 * which returns without waiting to ensure that all data are received.
<> 144:ef7eb2e8f9f7 674 * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
<> 144:ef7eb2e8f9f7 675 * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
<> 144:ef7eb2e8f9f7 676 * After copying, if the data in the ring buffer is not enough for read, the receive
<> 144:ef7eb2e8f9f7 677 * request is saved by the LPUART driver. When the new data arrives, the receive request
<> 144:ef7eb2e8f9f7 678 * is serviced first. When all data is received, the LPUART driver notifies the upper layer
<> 144:ef7eb2e8f9f7 679 * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
<> 144:ef7eb2e8f9f7 680 * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
<> 144:ef7eb2e8f9f7 681 * The 5 bytes are copied to xfer->data, which returns with the
<> 144:ef7eb2e8f9f7 682 * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
<> 144:ef7eb2e8f9f7 683 * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
<> 144:ef7eb2e8f9f7 684 * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
<> 144:ef7eb2e8f9f7 685 * to receive data to xfer->data. When all data is received, the upper layer is notified.
<> 144:ef7eb2e8f9f7 686 *
<> 144:ef7eb2e8f9f7 687 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 688 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 689 * @param xfer LPUART transfer structure, refer to #uart_transfer_t.
<> 144:ef7eb2e8f9f7 690 * @param receivedBytes Bytes received from the ring buffer directly.
<> 144:ef7eb2e8f9f7 691 * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
<> 144:ef7eb2e8f9f7 692 * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
<> 144:ef7eb2e8f9f7 693 * @retval kStatus_InvalidArgument Invalid argument.
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
<> 144:ef7eb2e8f9f7 696 lpuart_handle_t *handle,
<> 144:ef7eb2e8f9f7 697 lpuart_transfer_t *xfer,
<> 144:ef7eb2e8f9f7 698 size_t *receivedBytes);
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /*!
<> 144:ef7eb2e8f9f7 701 * @brief Aborts the interrupt-driven data receiving.
<> 144:ef7eb2e8f9f7 702 *
<> 144:ef7eb2e8f9f7 703 * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
<> 144:ef7eb2e8f9f7 704 * how many bytes not received yet.
<> 144:ef7eb2e8f9f7 705 *
<> 144:ef7eb2e8f9f7 706 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 707 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /*!
<> 144:ef7eb2e8f9f7 712 * @brief Get the number of bytes that have been received.
<> 144:ef7eb2e8f9f7 713 *
<> 144:ef7eb2e8f9f7 714 * This function gets the number of bytes that have been received.
<> 144:ef7eb2e8f9f7 715 *
<> 144:ef7eb2e8f9f7 716 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 717 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 718 * @param count Receive bytes count.
<> 144:ef7eb2e8f9f7 719 * @retval kStatus_NoTransferInProgress No receive in progress.
<> 144:ef7eb2e8f9f7 720 * @retval kStatus_InvalidArgument Parameter is invalid.
<> 144:ef7eb2e8f9f7 721 * @retval kStatus_Success Get successfully through the parameter \p count;
<> 144:ef7eb2e8f9f7 722 */
<> 144:ef7eb2e8f9f7 723 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /*!
<> 144:ef7eb2e8f9f7 726 * @brief LPUART IRQ handle function.
<> 144:ef7eb2e8f9f7 727 *
<> 144:ef7eb2e8f9f7 728 * This function handles the LPUART transmit and receive IRQ request.
<> 144:ef7eb2e8f9f7 729 *
<> 144:ef7eb2e8f9f7 730 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 731 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /*!
<> 144:ef7eb2e8f9f7 736 * @brief LPUART Error IRQ handle function.
<> 144:ef7eb2e8f9f7 737 *
<> 144:ef7eb2e8f9f7 738 * This function handles the LPUART error IRQ request.
<> 144:ef7eb2e8f9f7 739 *
<> 144:ef7eb2e8f9f7 740 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 741 * @param handle LPUART handle pointer.
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* @} */
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749 #endif
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /*! @}*/
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 #endif /* _FSL_LPUART_H_ */