added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef _FSL_DMAMUX_H_
<> 144:ef7eb2e8f9f7 32 #define _FSL_DMAMUX_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @addtogroup dmamux
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*! @file */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*******************************************************************************
<> 144:ef7eb2e8f9f7 44 * Definitions
<> 144:ef7eb2e8f9f7 45 ******************************************************************************/
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 48 /*@{*/
<> 144:ef7eb2e8f9f7 49 /*! @brief DMAMUX driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 50 #define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 51 /*@}*/
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*******************************************************************************
<> 144:ef7eb2e8f9f7 54 * API
<> 144:ef7eb2e8f9f7 55 ******************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 58 extern "C" {
<> 144:ef7eb2e8f9f7 59 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*!
<> 144:ef7eb2e8f9f7 62 * @name DMAMUX Initialize and De-initialize
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /*!
<> 144:ef7eb2e8f9f7 67 * @brief Initializes DMAMUX peripheral.
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 * This function ungate the DMAMUX clock.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 void DMAMUX_Init(DMAMUX_Type *base);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /*!
<> 144:ef7eb2e8f9f7 77 * @brief Deinitializes DMAMUX peripheral.
<> 144:ef7eb2e8f9f7 78 *
<> 144:ef7eb2e8f9f7 79 * This function gate the DMAMUX clock.
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 void DMAMUX_Deinit(DMAMUX_Type *base);
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* @} */
<> 144:ef7eb2e8f9f7 86 /*!
<> 144:ef7eb2e8f9f7 87 * @name DMAMUX Channel Operation
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /*!
<> 144:ef7eb2e8f9f7 92 * @brief Enable DMAMUX channel.
<> 144:ef7eb2e8f9f7 93 *
<> 144:ef7eb2e8f9f7 94 * This function enable DMAMUX channel to work.
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 97 * @param channel DMAMUX channel number.
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /*!
<> 144:ef7eb2e8f9f7 107 * @brief Disable DMAMUX channel.
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * This function disable DMAMUX channel.
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * @note User must disable DMAMUX channel before configure it.
<> 144:ef7eb2e8f9f7 112 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 113 * @param channel DMAMUX channel number.
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115 static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 116 {
<> 144:ef7eb2e8f9f7 117 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /*!
<> 144:ef7eb2e8f9f7 123 * @brief Configure DMAMUX channel source.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 126 * @param channel DMAMUX channel number.
<> 144:ef7eb2e8f9f7 127 * @param source Channel source which is used to trigger DMA transfer.
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
<> 144:ef7eb2e8f9f7 137 /*!
<> 144:ef7eb2e8f9f7 138 * @brief Enable DMAMUX period trigger.
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 * This function enable DMAMUX period trigger feature.
<> 144:ef7eb2e8f9f7 141 *
<> 144:ef7eb2e8f9f7 142 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 143 * @param channel DMAMUX channel number.
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /*!
<> 144:ef7eb2e8f9f7 153 * @brief Disable DMAMUX period trigger.
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 * This function disable DMAMUX period trigger.
<> 144:ef7eb2e8f9f7 156 *
<> 144:ef7eb2e8f9f7 157 * @param base DMAMUX peripheral base address.
<> 144:ef7eb2e8f9f7 158 * @param channel DMAMUX channel number.
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166 #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* @} */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* @} */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #endif /* _FSL_DMAMUX_H_ */