Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_adc16.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef _FSL_ADC16_H_
<> 144:ef7eb2e8f9f7 32 #define _FSL_ADC16_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @addtogroup adc16
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*! @file */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*******************************************************************************
<> 144:ef7eb2e8f9f7 44 * Definitions
<> 144:ef7eb2e8f9f7 45 ******************************************************************************/
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 48 /*@{*/
<> 144:ef7eb2e8f9f7 49 /*! @brief ADC16 driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 50 #define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 51 /*@}*/
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*!
<> 144:ef7eb2e8f9f7 54 * @brief Channel status flags.
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56 enum _adc16_channel_status_flags
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
<> 144:ef7eb2e8f9f7 59 };
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*!
<> 144:ef7eb2e8f9f7 62 * @brief Converter status flags.
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 enum _adc16_status_flags
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
<> 144:ef7eb2e8f9f7 67 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 144:ef7eb2e8f9f7 68 kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
<> 144:ef7eb2e8f9f7 69 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 144:ef7eb2e8f9f7 70 };
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
<> 144:ef7eb2e8f9f7 73 /*!
<> 144:ef7eb2e8f9f7 74 * @brief Channel multiplexer mode for each channel.
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
<> 144:ef7eb2e8f9f7 77 * are the different channels but share the same channel number.
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef enum _adc_channel_mux_mode
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
<> 144:ef7eb2e8f9f7 82 kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
<> 144:ef7eb2e8f9f7 83 } adc16_channel_mux_mode_t;
<> 144:ef7eb2e8f9f7 84 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /*!
<> 144:ef7eb2e8f9f7 87 * @brief Clock divider for the converter.
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 typedef enum _adc16_clock_divider
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
<> 144:ef7eb2e8f9f7 92 kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
<> 144:ef7eb2e8f9f7 93 kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
<> 144:ef7eb2e8f9f7 94 kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
<> 144:ef7eb2e8f9f7 95 } adc16_clock_divider_t;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /*!
<> 144:ef7eb2e8f9f7 98 *@brief Converter's resolution.
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 typedef enum _adc16_resolution
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 /* This group of enumeration is for internal use which is related to register setting. */
<> 144:ef7eb2e8f9f7 103 kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */
<> 144:ef7eb2e8f9f7 104 kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
<> 144:ef7eb2e8f9f7 105 kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /* This group of enumeration is for public user. */
<> 144:ef7eb2e8f9f7 108 kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */
<> 144:ef7eb2e8f9f7 109 kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
<> 144:ef7eb2e8f9f7 110 kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
<> 144:ef7eb2e8f9f7 111 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 144:ef7eb2e8f9f7 112 kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */
<> 144:ef7eb2e8f9f7 113 kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
<> 144:ef7eb2e8f9f7 114 kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
<> 144:ef7eb2e8f9f7 115 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
<> 144:ef7eb2e8f9f7 118 /* 16-bit is supported by default. */
<> 144:ef7eb2e8f9f7 119 kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */
<> 144:ef7eb2e8f9f7 120 kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
<> 144:ef7eb2e8f9f7 121 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 144:ef7eb2e8f9f7 122 kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
<> 144:ef7eb2e8f9f7 123 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 144:ef7eb2e8f9f7 124 #endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
<> 144:ef7eb2e8f9f7 125 } adc16_resolution_t;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*!
<> 144:ef7eb2e8f9f7 128 * @brief Clock source.
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 typedef enum _adc16_clock_source
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
<> 144:ef7eb2e8f9f7 133 kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
<> 144:ef7eb2e8f9f7 134 kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
<> 144:ef7eb2e8f9f7 135 kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Chip defined clock source */
<> 144:ef7eb2e8f9f7 138 kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
<> 144:ef7eb2e8f9f7 139 } adc16_clock_source_t;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /*!
<> 144:ef7eb2e8f9f7 142 * @brief Long sample mode.
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 typedef enum _adc16_long_sample_mode
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
<> 144:ef7eb2e8f9f7 147 kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
<> 144:ef7eb2e8f9f7 148 kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
<> 144:ef7eb2e8f9f7 149 kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
<> 144:ef7eb2e8f9f7 150 kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
<> 144:ef7eb2e8f9f7 151 } adc16_long_sample_mode_t;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /*!
<> 144:ef7eb2e8f9f7 154 * @brief Reference voltage source.
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 typedef enum _adc16_reference_voltage_source
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
<> 144:ef7eb2e8f9f7 159 kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
<> 144:ef7eb2e8f9f7 160 } adc16_reference_voltage_source_t;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
<> 144:ef7eb2e8f9f7 163 /*!
<> 144:ef7eb2e8f9f7 164 * @brief Hardware average mode.
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 typedef enum _adc16_hardware_average_mode
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
<> 144:ef7eb2e8f9f7 169 kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
<> 144:ef7eb2e8f9f7 170 kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
<> 144:ef7eb2e8f9f7 171 kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
<> 144:ef7eb2e8f9f7 172 kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
<> 144:ef7eb2e8f9f7 173 } adc16_hardware_average_mode_t;
<> 144:ef7eb2e8f9f7 174 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /*!
<> 144:ef7eb2e8f9f7 177 * @brief Hardware compare mode.
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 typedef enum _adc16_hardware_compare_mode
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
<> 144:ef7eb2e8f9f7 182 kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
<> 144:ef7eb2e8f9f7 183 kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
<> 144:ef7eb2e8f9f7 184 else, value1 > x > value2. */
<> 144:ef7eb2e8f9f7 185 kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
<> 144:ef7eb2e8f9f7 186 else x >= value1 || x <= value2. */
<> 144:ef7eb2e8f9f7 187 } adc16_hardware_compare_mode_t;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 144:ef7eb2e8f9f7 190 /*!
<> 144:ef7eb2e8f9f7 191 * @brief PGA's Gain mode.
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 typedef enum _adc16_pga_gain
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */
<> 144:ef7eb2e8f9f7 196 kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */
<> 144:ef7eb2e8f9f7 197 kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */
<> 144:ef7eb2e8f9f7 198 kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */
<> 144:ef7eb2e8f9f7 199 kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
<> 144:ef7eb2e8f9f7 200 kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
<> 144:ef7eb2e8f9f7 201 kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
<> 144:ef7eb2e8f9f7 202 } adc16_pga_gain_t;
<> 144:ef7eb2e8f9f7 203 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /*!
<> 144:ef7eb2e8f9f7 206 * @brief ADC16 converter configuration .
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 typedef struct _adc16_config
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
<> 144:ef7eb2e8f9f7 211 adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */
<> 144:ef7eb2e8f9f7 212 bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */
<> 144:ef7eb2e8f9f7 213 adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */
<> 144:ef7eb2e8f9f7 214 adc16_resolution_t resolution; /*!< Select the sample resolution mode. */
<> 144:ef7eb2e8f9f7 215 adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */
<> 144:ef7eb2e8f9f7 216 bool enableHighSpeed; /*!< Enable the high-speed mode. */
<> 144:ef7eb2e8f9f7 217 bool enableLowPower; /*!< Enable low power. */
<> 144:ef7eb2e8f9f7 218 bool enableContinuousConversion; /*!< Enable continuous conversion mode. */
<> 144:ef7eb2e8f9f7 219 } adc16_config_t;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /*!
<> 144:ef7eb2e8f9f7 222 * @brief ADC16 Hardware compare configuration.
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 typedef struct _adc16_hardware_compare_config
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
<> 144:ef7eb2e8f9f7 227 See "adc16_hardware_compare_mode_t". */
<> 144:ef7eb2e8f9f7 228 int16_t value1; /*!< Setting value1 for hardware compare mode. */
<> 144:ef7eb2e8f9f7 229 int16_t value2; /*!< Setting value2 for hardware compare mode. */
<> 144:ef7eb2e8f9f7 230 } adc16_hardware_compare_config_t;
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /*!
<> 144:ef7eb2e8f9f7 233 * @brief ADC16 channel conversion configuration.
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 typedef struct _adc16_channel_config
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
<> 144:ef7eb2e8f9f7 238 See channel connection information for each chip in Reference
<> 144:ef7eb2e8f9f7 239 Manual document. */
<> 144:ef7eb2e8f9f7 240 bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */
<> 144:ef7eb2e8f9f7 241 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 144:ef7eb2e8f9f7 242 bool enableDifferentialConversion; /*!< Using Differential sample mode. */
<> 144:ef7eb2e8f9f7 243 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 144:ef7eb2e8f9f7 244 } adc16_channel_config_t;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 144:ef7eb2e8f9f7 247 /*!
<> 144:ef7eb2e8f9f7 248 * @brief ADC16 programmable gain amplifier configuration.
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 typedef struct _adc16_pga_config
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */
<> 144:ef7eb2e8f9f7 253 bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
<> 144:ef7eb2e8f9f7 254 #if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
<> 144:ef7eb2e8f9f7 255 bool disablePgaChopping; /*!< Disable the PGA chopping function.
<> 144:ef7eb2e8f9f7 256 The PGA employs chopping to remove/reduce offset and 1/f noise and offers
<> 144:ef7eb2e8f9f7 257 an offset measurement configuration that aids the offset calibration. */
<> 144:ef7eb2e8f9f7 258 #endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
<> 144:ef7eb2e8f9f7 259 #if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
<> 144:ef7eb2e8f9f7 260 bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
<> 144:ef7eb2e8f9f7 261 When this feature is enabled, the PGA disconnects itself from the external
<> 144:ef7eb2e8f9f7 262 inputs and auto-configures into offset measurement mode. With this field
<> 144:ef7eb2e8f9f7 263 set, run the ADC in the recommended settings and enable the maximum hardware
<> 144:ef7eb2e8f9f7 264 averaging to get the PGA offset number. The output is the
<> 144:ef7eb2e8f9f7 265 (PGA offset * (64+1)) for the given PGA setting. */
<> 144:ef7eb2e8f9f7 266 #endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
<> 144:ef7eb2e8f9f7 267 } adc16_pga_config_t;
<> 144:ef7eb2e8f9f7 268 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 271 extern "C" {
<> 144:ef7eb2e8f9f7 272 #endif
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /*******************************************************************************
<> 144:ef7eb2e8f9f7 275 * API
<> 144:ef7eb2e8f9f7 276 ******************************************************************************/
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /*!
<> 144:ef7eb2e8f9f7 279 * @name Initialization
<> 144:ef7eb2e8f9f7 280 * @{
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /*!
<> 144:ef7eb2e8f9f7 284 * @brief Initializes the ADC16 module.
<> 144:ef7eb2e8f9f7 285 *
<> 144:ef7eb2e8f9f7 286 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 287 * @param config Pointer to configuration structure. See "adc16_config_t".
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /*!
<> 144:ef7eb2e8f9f7 292 * @brief De-initializes the ADC16 module.
<> 144:ef7eb2e8f9f7 293 *
<> 144:ef7eb2e8f9f7 294 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 void ADC16_Deinit(ADC_Type *base);
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /*!
<> 144:ef7eb2e8f9f7 299 * @brief Gets an available pre-defined settings for converter's configuration.
<> 144:ef7eb2e8f9f7 300 *
<> 144:ef7eb2e8f9f7 301 * This function initializes the converter configuration structure with an available settings. The default values are:
<> 144:ef7eb2e8f9f7 302 * @code
<> 144:ef7eb2e8f9f7 303 * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
<> 144:ef7eb2e8f9f7 304 * config->clockSource = kADC16_ClockSourceAsynchronousClock;
<> 144:ef7eb2e8f9f7 305 * config->enableAsynchronousClock = true;
<> 144:ef7eb2e8f9f7 306 * config->clockDivider = kADC16_ClockDivider8;
<> 144:ef7eb2e8f9f7 307 * config->resolution = kADC16_ResolutionSE12Bit;
<> 144:ef7eb2e8f9f7 308 * config->longSampleMode = kADC16_LongSampleDisabled;
<> 144:ef7eb2e8f9f7 309 * config->enableHighSpeed = false;
<> 144:ef7eb2e8f9f7 310 * config->enableLowPower = false;
<> 144:ef7eb2e8f9f7 311 * config->enableContinuousConversion = false;
<> 144:ef7eb2e8f9f7 312 * @endcode
<> 144:ef7eb2e8f9f7 313 * @param config Pointer to configuration structure.
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 void ADC16_GetDefaultConfig(adc16_config_t *config);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 144:ef7eb2e8f9f7 318 /*!
<> 144:ef7eb2e8f9f7 319 * @brief Automates the hardware calibration.
<> 144:ef7eb2e8f9f7 320 *
<> 144:ef7eb2e8f9f7 321 * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation.
<> 144:ef7eb2e8f9f7 322 * Execute the calibration before using the converter. Note that the hardware trigger should be used
<> 144:ef7eb2e8f9f7 323 * during calibration.
<> 144:ef7eb2e8f9f7 324 *
<> 144:ef7eb2e8f9f7 325 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 326 *
<> 144:ef7eb2e8f9f7 327 * @return Execution status.
<> 144:ef7eb2e8f9f7 328 * @retval kStatus_Success Calibration is done successfully.
<> 144:ef7eb2e8f9f7 329 * @retval kStatus_Fail Calibration is failed.
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 status_t ADC16_DoAutoCalibration(ADC_Type *base);
<> 144:ef7eb2e8f9f7 332 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 #if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
<> 144:ef7eb2e8f9f7 335 /*!
<> 144:ef7eb2e8f9f7 336 * @brief Sets the offset value for the conversion result.
<> 144:ef7eb2e8f9f7 337 *
<> 144:ef7eb2e8f9f7 338 * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
<> 144:ef7eb2e8f9f7 339 * is subtracted by it. Note, the hardware calibration fills the offset value automatically.
<> 144:ef7eb2e8f9f7 340 *
<> 144:ef7eb2e8f9f7 341 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 342 * @param value Setting offset value.
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 base->OFS = (uint32_t)(value);
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348 #endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* @} */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /*!
<> 144:ef7eb2e8f9f7 353 * @name Advanced Feature
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
<> 144:ef7eb2e8f9f7 358 /*!
<> 144:ef7eb2e8f9f7 359 * @brief Enables generating the DMA trigger when conversion is completed.
<> 144:ef7eb2e8f9f7 360 *
<> 144:ef7eb2e8f9f7 361 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 362 * @param enable Switcher of DMA feature. "true" means to enable, "false" means not.
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 if (enable)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 base->SC2 |= ADC_SC2_DMAEN_MASK;
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370 else
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 base->SC2 &= ~ADC_SC2_DMAEN_MASK;
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375 #endif /* FSL_FEATURE_ADC16_HAS_DMA */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /*!
<> 144:ef7eb2e8f9f7 378 * @brief Enables the hardware trigger mode.
<> 144:ef7eb2e8f9f7 379 *
<> 144:ef7eb2e8f9f7 380 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 381 * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not.
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 if (enable)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 base->SC2 |= ADC_SC2_ADTRG_MASK;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 else
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 base->SC2 &= ~ADC_SC2_ADTRG_MASK;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
<> 144:ef7eb2e8f9f7 396 /*!
<> 144:ef7eb2e8f9f7 397 * @brief Sets the channel mux mode.
<> 144:ef7eb2e8f9f7 398 *
<> 144:ef7eb2e8f9f7 399 * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
<> 144:ef7eb2e8f9f7 400 * indicated channel.
<> 144:ef7eb2e8f9f7 401 *
<> 144:ef7eb2e8f9f7 402 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 403 * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
<> 144:ef7eb2e8f9f7 406 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /*!
<> 144:ef7eb2e8f9f7 409 * @brief Configures the hardware compare mode.
<> 144:ef7eb2e8f9f7 410 *
<> 144:ef7eb2e8f9f7 411 * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result
<> 144:ef7eb2e8f9f7 412 * in
<> 144:ef7eb2e8f9f7 413 * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference
<> 144:ef7eb2e8f9f7 414 * manual document for more detailed information.
<> 144:ef7eb2e8f9f7 415 *
<> 144:ef7eb2e8f9f7 416 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 417 * @param config Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature.
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
<> 144:ef7eb2e8f9f7 422 /*!
<> 144:ef7eb2e8f9f7 423 * @brief Sets the hardware average mode.
<> 144:ef7eb2e8f9f7 424 *
<> 144:ef7eb2e8f9f7 425 * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple
<> 144:ef7eb2e8f9f7 426 * conversion results are accumulated and averaged internally. This aids reading results.
<> 144:ef7eb2e8f9f7 427 *
<> 144:ef7eb2e8f9f7 428 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 429 * @param mode Setting hardware average mode. See "adc16_hardware_average_mode_t".
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
<> 144:ef7eb2e8f9f7 432 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 144:ef7eb2e8f9f7 435 /*!
<> 144:ef7eb2e8f9f7 436 * @brief Configures the PGA for converter's front end.
<> 144:ef7eb2e8f9f7 437 *
<> 144:ef7eb2e8f9f7 438 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 439 * @param config Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature.
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
<> 144:ef7eb2e8f9f7 442 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /*!
<> 144:ef7eb2e8f9f7 445 * @brief Gets the status flags of the converter.
<> 144:ef7eb2e8f9f7 446 *
<> 144:ef7eb2e8f9f7 447 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 448 *
<> 144:ef7eb2e8f9f7 449 * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 uint32_t ADC16_GetStatusFlags(ADC_Type *base);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /*!
<> 144:ef7eb2e8f9f7 454 * @brief Clears the status flags of the converter.
<> 144:ef7eb2e8f9f7 455 *
<> 144:ef7eb2e8f9f7 456 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 457 * @param mask Mask value for the cleared flags. See "_adc16_status_flags".
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* @} */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /*!
<> 144:ef7eb2e8f9f7 464 * @name Conversion Channel
<> 144:ef7eb2e8f9f7 465 * @{
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /*!
<> 144:ef7eb2e8f9f7 469 * @brief Configures the conversion channel.
<> 144:ef7eb2e8f9f7 470 *
<> 144:ef7eb2e8f9f7 471 * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API
<> 144:ef7eb2e8f9f7 472 * configures the channel while the external trigger source helps to trigger the conversion.
<> 144:ef7eb2e8f9f7 473 *
<> 144:ef7eb2e8f9f7 474 * Note that the "Channel Group" has a detailed description.
<> 144:ef7eb2e8f9f7 475 * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one
<> 144:ef7eb2e8f9f7 476 * group of status and control register, one for each conversion. The channel group parameter indicates which group of
<> 144:ef7eb2e8f9f7 477 * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers. The
<> 144:ef7eb2e8f9f7 478 * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
<> 144:ef7eb2e8f9f7 479 * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware
<> 144:ef7eb2e8f9f7 480 * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for
<> 144:ef7eb2e8f9f7 481 * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the
<> 144:ef7eb2e8f9f7 482 * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
<> 144:ef7eb2e8f9f7 483 * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion.
<> 144:ef7eb2e8f9f7 484 * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and
<> 144:ef7eb2e8f9f7 485 * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
<> 144:ef7eb2e8f9f7 486 * conversion aborts the current conversion.
<> 144:ef7eb2e8f9f7 487 *
<> 144:ef7eb2e8f9f7 488 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 489 * @param channelGroup Channel group index.
<> 144:ef7eb2e8f9f7 490 * @param config Pointer to "adc16_channel_config_t" structure for conversion channel.
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /*!
<> 144:ef7eb2e8f9f7 495 * @brief Gets the conversion value.
<> 144:ef7eb2e8f9f7 496 *
<> 144:ef7eb2e8f9f7 497 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 498 * @param channelGroup Channel group index.
<> 144:ef7eb2e8f9f7 499 *
<> 144:ef7eb2e8f9f7 500 * @return Conversion value.
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 assert(channelGroup < ADC_R_COUNT);
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 return base->R[channelGroup];
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /*!
<> 144:ef7eb2e8f9f7 510 * @brief Gets the status flags of channel.
<> 144:ef7eb2e8f9f7 511 *
<> 144:ef7eb2e8f9f7 512 * @param base ADC16 peripheral base address.
<> 144:ef7eb2e8f9f7 513 * @param channelGroup Channel group index.
<> 144:ef7eb2e8f9f7 514 *
<> 144:ef7eb2e8f9f7 515 * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* @} */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 #endif
<> 144:ef7eb2e8f9f7 524 /*!
<> 144:ef7eb2e8f9f7 525 * @}
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 #endif /* _FSL_ADC16_H_ */