Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 * ----------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16 * File: apspi.h
<> 144:ef7eb2e8f9f7 17 * Release: Version 2.0
<> 144:ef7eb2e8f9f7 18 * ----------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * SSP interface Support
<> 144:ef7eb2e8f9f7 21 * =====================
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
<> 144:ef7eb2e8f9f7 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
<> 144:ef7eb2e8f9f7 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
<> 144:ef7eb2e8f9f7 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
<> 144:ef7eb2e8f9f7 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
<> 144:ef7eb2e8f9f7 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
<> 144:ef7eb2e8f9f7 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
<> 144:ef7eb2e8f9f7 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
<> 144:ef7eb2e8f9f7 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
<> 144:ef7eb2e8f9f7 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
<> 144:ef7eb2e8f9f7 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
<> 144:ef7eb2e8f9f7 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 // SSPCR0 Control register 0
<> 144:ef7eb2e8f9f7 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
<> 144:ef7eb2e8f9f7 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
<> 144:ef7eb2e8f9f7 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
<> 144:ef7eb2e8f9f7 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
<> 144:ef7eb2e8f9f7 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
<> 144:ef7eb2e8f9f7 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 // SSPCR1 Control register 1
<> 144:ef7eb2e8f9f7 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
<> 144:ef7eb2e8f9f7 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
<> 144:ef7eb2e8f9f7 50 #define SSPCR1_SSE 0x0002 // Serial port enable
<> 144:ef7eb2e8f9f7 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // SSPSR Status register
<> 144:ef7eb2e8f9f7 54 #define SSPSR_BSY 0x0010 // Busy
<> 144:ef7eb2e8f9f7 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
<> 144:ef7eb2e8f9f7 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
<> 144:ef7eb2e8f9f7 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
<> 144:ef7eb2e8f9f7 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 // SSPCPSR Clock prescale register
<> 144:ef7eb2e8f9f7 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 // SSPIMSC Interrupt mask set and clear register
<> 144:ef7eb2e8f9f7 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
<> 144:ef7eb2e8f9f7 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
<> 144:ef7eb2e8f9f7 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
<> 144:ef7eb2e8f9f7 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 // SSPRIS Raw interrupt status register
<> 144:ef7eb2e8f9f7 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
<> 144:ef7eb2e8f9f7 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
<> 144:ef7eb2e8f9f7 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
<> 144:ef7eb2e8f9f7 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 // SSPMIS Masked interrupt status register
<> 144:ef7eb2e8f9f7 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
<> 144:ef7eb2e8f9f7 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
<> 144:ef7eb2e8f9f7 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
<> 144:ef7eb2e8f9f7 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 // SSPICR Interrupt clear register
<> 144:ef7eb2e8f9f7 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
<> 144:ef7eb2e8f9f7 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 // SSPDMACR DMA control register
<> 144:ef7eb2e8f9f7 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
<> 144:ef7eb2e8f9f7 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // SPICS register (0=Chip Select low)
<> 144:ef7eb2e8f9f7 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 // SPI defaults
<> 144:ef7eb2e8f9f7 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 // EEPROM instruction set
<> 144:ef7eb2e8f9f7 96 #define EEWRSR 0x0001 // Write status
<> 144:ef7eb2e8f9f7 97 #define EEWRITE 0x0002 // Write data
<> 144:ef7eb2e8f9f7 98 #define EEREAD 0x0003 // Read data
<> 144:ef7eb2e8f9f7 99 #define EEWDI 0x0004 // Write disable
<> 144:ef7eb2e8f9f7 100 #define EEWREN 0x0006 // Write enable
<> 144:ef7eb2e8f9f7 101 #define EERDSR 0x0005 // Read status
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // EEPROM status register flags
<> 144:ef7eb2e8f9f7 104 #define EERDSR_WIP 0x0001 // Write in process
<> 144:ef7eb2e8f9f7 105 #define EERDSR_WEL 0x0002 // Write enable latch
<> 144:ef7eb2e8f9f7 106 #define EERDSR_BP0 0x0004 // Block protect 0
<> 144:ef7eb2e8f9f7 107 #define EERDSR_BP1 0x0008 // Block protect 1
<> 144:ef7eb2e8f9f7 108 #define EERDSR_WPEN 0x0080 // Write protect enable
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* ----------------------------------------------------------------
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * Color LCD Support
<> 144:ef7eb2e8f9f7 113 * =================
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // Color LCD Controller Internal Register addresses
<> 144:ef7eb2e8f9f7 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
<> 144:ef7eb2e8f9f7 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
<> 144:ef7eb2e8f9f7 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
<> 144:ef7eb2e8f9f7 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
<> 144:ef7eb2e8f9f7 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
<> 144:ef7eb2e8f9f7 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
<> 144:ef7eb2e8f9f7 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
<> 144:ef7eb2e8f9f7 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
<> 144:ef7eb2e8f9f7 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
<> 144:ef7eb2e8f9f7 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
<> 144:ef7eb2e8f9f7 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
<> 144:ef7eb2e8f9f7 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 // LSSPCR0 Control register 0
<> 144:ef7eb2e8f9f7 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
<> 144:ef7eb2e8f9f7 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
<> 144:ef7eb2e8f9f7 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
<> 144:ef7eb2e8f9f7 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
<> 144:ef7eb2e8f9f7 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
<> 144:ef7eb2e8f9f7 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 // LSSPCR1 Control register 1
<> 144:ef7eb2e8f9f7 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
<> 144:ef7eb2e8f9f7 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
<> 144:ef7eb2e8f9f7 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
<> 144:ef7eb2e8f9f7 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 // LSSPSR Status register
<> 144:ef7eb2e8f9f7 147 #define LSSPSR_BSY 0x0010 // Busy
<> 144:ef7eb2e8f9f7 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
<> 144:ef7eb2e8f9f7 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
<> 144:ef7eb2e8f9f7 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
<> 144:ef7eb2e8f9f7 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 // LSSPCPSR Clock prescale register
<> 144:ef7eb2e8f9f7 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 // SPICS register
<> 144:ef7eb2e8f9f7 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
<> 144:ef7eb2e8f9f7 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
<> 144:ef7eb2e8f9f7 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
<> 144:ef7eb2e8f9f7 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
<> 144:ef7eb2e8f9f7 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
<> 144:ef7eb2e8f9f7 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 // SPI defaults
<> 144:ef7eb2e8f9f7 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
<> 144:ef7eb2e8f9f7 166 #define LSPI_START (0x70) // Start byte for SPI transfer
<> 144:ef7eb2e8f9f7 167 #define LSPI_RD (0x01) // WR bit 1 within start
<> 144:ef7eb2e8f9f7 168 #define LSPI_WR (0x00) // WR bit 0 within start
<> 144:ef7eb2e8f9f7 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
<> 144:ef7eb2e8f9f7 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 // Screen size
<> 144:ef7eb2e8f9f7 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
<> 144:ef7eb2e8f9f7 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)