Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
80:bdf1132a57cf 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 80:bdf1132a57cf 1 /* mbed Microcontroller Library
mbed_official 80:bdf1132a57cf 2 * Copyright (c) 2006-2015 ARM Limited
mbed_official 80:bdf1132a57cf 3 *
mbed_official 80:bdf1132a57cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 80:bdf1132a57cf 5 * you may not use this file except in compliance with the License.
mbed_official 80:bdf1132a57cf 6 * You may obtain a copy of the License at
mbed_official 80:bdf1132a57cf 7 *
mbed_official 80:bdf1132a57cf 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 80:bdf1132a57cf 9 *
mbed_official 80:bdf1132a57cf 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 80:bdf1132a57cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 80:bdf1132a57cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 80:bdf1132a57cf 13 * See the License for the specific language governing permissions and
mbed_official 80:bdf1132a57cf 14 * limitations under the License.
mbed_official 80:bdf1132a57cf 15 * ----------------------------------------------------------------
mbed_official 80:bdf1132a57cf 16 * File: apspi.h
mbed_official 80:bdf1132a57cf 17 * Release: Version 2.0
mbed_official 80:bdf1132a57cf 18 * ----------------------------------------------------------------
mbed_official 80:bdf1132a57cf 19 *
mbed_official 80:bdf1132a57cf 20 * SSP interface Support
mbed_official 80:bdf1132a57cf 21 * =====================
mbed_official 80:bdf1132a57cf 22 */
mbed_official 80:bdf1132a57cf 23
mbed_official 80:bdf1132a57cf 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
mbed_official 80:bdf1132a57cf 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
mbed_official 80:bdf1132a57cf 26
mbed_official 80:bdf1132a57cf 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
mbed_official 80:bdf1132a57cf 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
mbed_official 80:bdf1132a57cf 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
mbed_official 80:bdf1132a57cf 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
mbed_official 80:bdf1132a57cf 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
mbed_official 80:bdf1132a57cf 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
mbed_official 80:bdf1132a57cf 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
mbed_official 80:bdf1132a57cf 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
mbed_official 80:bdf1132a57cf 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
mbed_official 80:bdf1132a57cf 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
mbed_official 80:bdf1132a57cf 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
mbed_official 80:bdf1132a57cf 38
mbed_official 80:bdf1132a57cf 39 // SSPCR0 Control register 0
mbed_official 80:bdf1132a57cf 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
mbed_official 80:bdf1132a57cf 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
mbed_official 80:bdf1132a57cf 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
mbed_official 80:bdf1132a57cf 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
mbed_official 80:bdf1132a57cf 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
mbed_official 80:bdf1132a57cf 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
mbed_official 80:bdf1132a57cf 46
mbed_official 80:bdf1132a57cf 47 // SSPCR1 Control register 1
mbed_official 80:bdf1132a57cf 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
mbed_official 80:bdf1132a57cf 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
mbed_official 80:bdf1132a57cf 50 #define SSPCR1_SSE 0x0002 // Serial port enable
mbed_official 80:bdf1132a57cf 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
mbed_official 80:bdf1132a57cf 52
mbed_official 80:bdf1132a57cf 53 // SSPSR Status register
mbed_official 80:bdf1132a57cf 54 #define SSPSR_BSY 0x0010 // Busy
mbed_official 80:bdf1132a57cf 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
mbed_official 80:bdf1132a57cf 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
mbed_official 80:bdf1132a57cf 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
mbed_official 80:bdf1132a57cf 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
mbed_official 80:bdf1132a57cf 59
mbed_official 80:bdf1132a57cf 60 // SSPCPSR Clock prescale register
mbed_official 80:bdf1132a57cf 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
mbed_official 80:bdf1132a57cf 62
mbed_official 80:bdf1132a57cf 63 // SSPIMSC Interrupt mask set and clear register
mbed_official 80:bdf1132a57cf 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
mbed_official 80:bdf1132a57cf 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
mbed_official 80:bdf1132a57cf 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
mbed_official 80:bdf1132a57cf 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
mbed_official 80:bdf1132a57cf 68
mbed_official 80:bdf1132a57cf 69 // SSPRIS Raw interrupt status register
mbed_official 80:bdf1132a57cf 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
mbed_official 80:bdf1132a57cf 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
mbed_official 80:bdf1132a57cf 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
mbed_official 80:bdf1132a57cf 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
mbed_official 80:bdf1132a57cf 74
mbed_official 80:bdf1132a57cf 75 // SSPMIS Masked interrupt status register
mbed_official 80:bdf1132a57cf 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
mbed_official 80:bdf1132a57cf 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
mbed_official 80:bdf1132a57cf 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
mbed_official 80:bdf1132a57cf 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
mbed_official 80:bdf1132a57cf 80
mbed_official 80:bdf1132a57cf 81 // SSPICR Interrupt clear register
mbed_official 80:bdf1132a57cf 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
mbed_official 80:bdf1132a57cf 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
mbed_official 80:bdf1132a57cf 84
mbed_official 80:bdf1132a57cf 85 // SSPDMACR DMA control register
mbed_official 80:bdf1132a57cf 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
mbed_official 80:bdf1132a57cf 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
mbed_official 80:bdf1132a57cf 88
mbed_official 80:bdf1132a57cf 89 // SPICS register (0=Chip Select low)
mbed_official 80:bdf1132a57cf 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
mbed_official 80:bdf1132a57cf 91
mbed_official 80:bdf1132a57cf 92 // SPI defaults
mbed_official 80:bdf1132a57cf 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
mbed_official 80:bdf1132a57cf 94
mbed_official 80:bdf1132a57cf 95 // EEPROM instruction set
mbed_official 80:bdf1132a57cf 96 #define EEWRSR 0x0001 // Write status
mbed_official 80:bdf1132a57cf 97 #define EEWRITE 0x0002 // Write data
mbed_official 80:bdf1132a57cf 98 #define EEREAD 0x0003 // Read data
mbed_official 80:bdf1132a57cf 99 #define EEWDI 0x0004 // Write disable
mbed_official 80:bdf1132a57cf 100 #define EEWREN 0x0006 // Write enable
mbed_official 80:bdf1132a57cf 101 #define EERDSR 0x0005 // Read status
mbed_official 80:bdf1132a57cf 102
mbed_official 80:bdf1132a57cf 103 // EEPROM status register flags
mbed_official 80:bdf1132a57cf 104 #define EERDSR_WIP 0x0001 // Write in process
mbed_official 80:bdf1132a57cf 105 #define EERDSR_WEL 0x0002 // Write enable latch
mbed_official 80:bdf1132a57cf 106 #define EERDSR_BP0 0x0004 // Block protect 0
mbed_official 80:bdf1132a57cf 107 #define EERDSR_BP1 0x0008 // Block protect 1
mbed_official 80:bdf1132a57cf 108 #define EERDSR_WPEN 0x0080 // Write protect enable
mbed_official 80:bdf1132a57cf 109
mbed_official 80:bdf1132a57cf 110 /* ----------------------------------------------------------------
mbed_official 80:bdf1132a57cf 111 *
mbed_official 80:bdf1132a57cf 112 * Color LCD Support
mbed_official 80:bdf1132a57cf 113 * =================
mbed_official 80:bdf1132a57cf 114 */
mbed_official 80:bdf1132a57cf 115
mbed_official 80:bdf1132a57cf 116 // Color LCD Controller Internal Register addresses
mbed_official 80:bdf1132a57cf 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
mbed_official 80:bdf1132a57cf 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
mbed_official 80:bdf1132a57cf 119
mbed_official 80:bdf1132a57cf 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
mbed_official 80:bdf1132a57cf 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
mbed_official 80:bdf1132a57cf 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
mbed_official 80:bdf1132a57cf 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
mbed_official 80:bdf1132a57cf 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
mbed_official 80:bdf1132a57cf 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
mbed_official 80:bdf1132a57cf 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
mbed_official 80:bdf1132a57cf 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
mbed_official 80:bdf1132a57cf 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
mbed_official 80:bdf1132a57cf 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
mbed_official 80:bdf1132a57cf 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
mbed_official 80:bdf1132a57cf 131
mbed_official 80:bdf1132a57cf 132 // LSSPCR0 Control register 0
mbed_official 80:bdf1132a57cf 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
mbed_official 80:bdf1132a57cf 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
mbed_official 80:bdf1132a57cf 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
mbed_official 80:bdf1132a57cf 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
mbed_official 80:bdf1132a57cf 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
mbed_official 80:bdf1132a57cf 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
mbed_official 80:bdf1132a57cf 139
mbed_official 80:bdf1132a57cf 140 // LSSPCR1 Control register 1
mbed_official 80:bdf1132a57cf 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
mbed_official 80:bdf1132a57cf 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
mbed_official 80:bdf1132a57cf 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
mbed_official 80:bdf1132a57cf 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
mbed_official 80:bdf1132a57cf 145
mbed_official 80:bdf1132a57cf 146 // LSSPSR Status register
mbed_official 80:bdf1132a57cf 147 #define LSSPSR_BSY 0x0010 // Busy
mbed_official 80:bdf1132a57cf 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
mbed_official 80:bdf1132a57cf 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
mbed_official 80:bdf1132a57cf 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
mbed_official 80:bdf1132a57cf 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
mbed_official 80:bdf1132a57cf 152
mbed_official 80:bdf1132a57cf 153 // LSSPCPSR Clock prescale register
mbed_official 80:bdf1132a57cf 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
mbed_official 80:bdf1132a57cf 155
mbed_official 80:bdf1132a57cf 156 // SPICS register
mbed_official 80:bdf1132a57cf 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
mbed_official 80:bdf1132a57cf 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
mbed_official 80:bdf1132a57cf 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
mbed_official 80:bdf1132a57cf 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
mbed_official 80:bdf1132a57cf 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
mbed_official 80:bdf1132a57cf 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
mbed_official 80:bdf1132a57cf 163
mbed_official 80:bdf1132a57cf 164 // SPI defaults
mbed_official 80:bdf1132a57cf 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
mbed_official 80:bdf1132a57cf 166 #define LSPI_START (0x70) // Start byte for SPI transfer
mbed_official 80:bdf1132a57cf 167 #define LSPI_RD (0x01) // WR bit 1 within start
mbed_official 80:bdf1132a57cf 168 #define LSPI_WR (0x00) // WR bit 0 within start
mbed_official 80:bdf1132a57cf 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
mbed_official 80:bdf1132a57cf 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
mbed_official 80:bdf1132a57cf 171
mbed_official 80:bdf1132a57cf 172 // Screen size
mbed_official 80:bdf1132a57cf 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
mbed_official 80:bdf1132a57cf 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)