Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/core_cmFunc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_cmFunc.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M Core Function Access Header File
<> 144:ef7eb2e8f9f7 4 * @version V4.10
<> 144:ef7eb2e8f9f7 5 * @date 18. March 2015
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #ifndef __CORE_CMFUNC_H
<> 144:ef7eb2e8f9f7 39 #define __CORE_CMFUNC_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* ########################### Core Function Access ########################### */
<> 144:ef7eb2e8f9f7 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 144:ef7eb2e8f9f7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 144:ef7eb2e8f9f7 45 @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 144:ef7eb2e8f9f7 49 /* ARM armcc specific functions */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #if (__ARMCC_VERSION < 400677)
<> 144:ef7eb2e8f9f7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 144:ef7eb2e8f9f7 53 #endif
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* intrinsic void __enable_irq(); */
<> 144:ef7eb2e8f9f7 56 /* intrinsic void __disable_irq(); */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** \brief Get Control Register
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 This function returns the content of the Control Register.
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 \return Control Register value
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 register uint32_t __regControl __ASM("control");
<> 144:ef7eb2e8f9f7 67 return(__regControl);
<> 144:ef7eb2e8f9f7 68 }
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /** \brief Set Control Register
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 This function writes the given value to the Control Register.
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 \param [in] control Control Register value to set
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 register uint32_t __regControl __ASM("control");
<> 144:ef7eb2e8f9f7 80 __regControl = control;
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /** \brief Get IPSR Register
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 This function returns the content of the IPSR Register.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 \return IPSR Register value
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90 __STATIC_INLINE uint32_t __get_IPSR(void)
<> 144:ef7eb2e8f9f7 91 {
<> 144:ef7eb2e8f9f7 92 register uint32_t __regIPSR __ASM("ipsr");
<> 144:ef7eb2e8f9f7 93 return(__regIPSR);
<> 144:ef7eb2e8f9f7 94 }
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** \brief Get APSR Register
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 This function returns the content of the APSR Register.
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 \return APSR Register value
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 __STATIC_INLINE uint32_t __get_APSR(void)
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 register uint32_t __regAPSR __ASM("apsr");
<> 144:ef7eb2e8f9f7 106 return(__regAPSR);
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** \brief Get xPSR Register
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 This function returns the content of the xPSR Register.
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 \return xPSR Register value
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 __STATIC_INLINE uint32_t __get_xPSR(void)
<> 144:ef7eb2e8f9f7 117 {
<> 144:ef7eb2e8f9f7 118 register uint32_t __regXPSR __ASM("xpsr");
<> 144:ef7eb2e8f9f7 119 return(__regXPSR);
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** \brief Get Process Stack Pointer
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 This function returns the current value of the Process Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 \return PSP Register value
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 __STATIC_INLINE uint32_t __get_PSP(void)
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 register uint32_t __regProcessStackPointer __ASM("psp");
<> 144:ef7eb2e8f9f7 132 return(__regProcessStackPointer);
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /** \brief Set Process Stack Pointer
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 This function assigns the given value to the Process Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 \param [in] topOfProcStack Process Stack Pointer value to set
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 register uint32_t __regProcessStackPointer __ASM("psp");
<> 144:ef7eb2e8f9f7 145 __regProcessStackPointer = topOfProcStack;
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** \brief Get Main Stack Pointer
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 This function returns the current value of the Main Stack Pointer (MSP).
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 \return MSP Register value
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 __STATIC_INLINE uint32_t __get_MSP(void)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 register uint32_t __regMainStackPointer __ASM("msp");
<> 144:ef7eb2e8f9f7 158 return(__regMainStackPointer);
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** \brief Set Main Stack Pointer
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 This function assigns the given value to the Main Stack Pointer (MSP).
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 \param [in] topOfMainStack Main Stack Pointer value to set
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 register uint32_t __regMainStackPointer __ASM("msp");
<> 144:ef7eb2e8f9f7 171 __regMainStackPointer = topOfMainStack;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** \brief Get Priority Mask
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 \return Priority Mask value
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 register uint32_t __regPriMask __ASM("primask");
<> 144:ef7eb2e8f9f7 184 return(__regPriMask);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /** \brief Set Priority Mask
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 This function assigns the given value to the Priority Mask Register.
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 \param [in] priMask Priority Mask
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 register uint32_t __regPriMask __ASM("primask");
<> 144:ef7eb2e8f9f7 197 __regPriMask = (priMask);
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** \brief Enable FIQ
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 206 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 #define __enable_fault_irq __enable_fiq
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** \brief Disable FIQ
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 214 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define __disable_fault_irq __disable_fiq
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /** \brief Get Base Priority
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 This function returns the current value of the Base Priority register.
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 \return Base Priority register value
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 register uint32_t __regBasePri __ASM("basepri");
<> 144:ef7eb2e8f9f7 228 return(__regBasePri);
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** \brief Set Base Priority
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 This function assigns the given value to the Base Priority register.
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 \param [in] basePri Base Priority value to set
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 register uint32_t __regBasePri __ASM("basepri");
<> 144:ef7eb2e8f9f7 241 __regBasePri = (basePri & 0xff);
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** \brief Set Base Priority with condition
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 144:ef7eb2e8f9f7 248 or the new value increases the BASEPRI priority level.
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 \param [in] basePri Base Priority value to set
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 register uint32_t __regBasePriMax __ASM("basepri_max");
<> 144:ef7eb2e8f9f7 255 __regBasePriMax = (basePri & 0xff);
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** \brief Get Fault Mask
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 This function returns the current value of the Fault Mask register.
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 \return Fault Mask register value
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 register uint32_t __regFaultMask __ASM("faultmask");
<> 144:ef7eb2e8f9f7 268 return(__regFaultMask);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /** \brief Set Fault Mask
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 This function assigns the given value to the Fault Mask register.
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 \param [in] faultMask Fault Mask value to set
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 register uint32_t __regFaultMask __ASM("faultmask");
<> 144:ef7eb2e8f9f7 281 __regFaultMask = (faultMask & (uint32_t)1);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** \brief Get FPSCR
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 This function returns the current value of the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 \return Floating Point Status/Control register value
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 298 register uint32_t __regfpscr __ASM("fpscr");
<> 144:ef7eb2e8f9f7 299 return(__regfpscr);
<> 144:ef7eb2e8f9f7 300 #else
<> 144:ef7eb2e8f9f7 301 return(0);
<> 144:ef7eb2e8f9f7 302 #endif
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** \brief Set FPSCR
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 This function assigns the given value to the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 \param [in] fpscr Floating Point Status/Control value to set
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 315 register uint32_t __regfpscr __ASM("fpscr");
<> 144:ef7eb2e8f9f7 316 __regfpscr = (fpscr);
<> 144:ef7eb2e8f9f7 317 #endif
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 324 /* GNU gcc specific functions */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** \brief Enable IRQ Interrupts
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
<> 144:ef7eb2e8f9f7 329 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 __ASM volatile ("cpsie i" : : : "memory");
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /** \brief Disable IRQ Interrupts
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 144:ef7eb2e8f9f7 340 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 __ASM volatile ("cpsid i" : : : "memory");
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /** \brief Get Control Register
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 This function returns the content of the Control Register.
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 \return Control Register value
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 uint32_t result;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
<> 144:ef7eb2e8f9f7 359 return(result);
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** \brief Set Control Register
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 This function writes the given value to the Control Register.
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 \param [in] control Control Register value to set
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** \brief Get IPSR Register
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 This function returns the content of the IPSR Register.
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 \return IPSR Register value
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 uint32_t result;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
<> 144:ef7eb2e8f9f7 386 return(result);
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /** \brief Get APSR Register
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 This function returns the content of the APSR Register.
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 \return APSR Register value
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 uint32_t result;
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
<> 144:ef7eb2e8f9f7 401 return(result);
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /** \brief Get xPSR Register
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 This function returns the content of the xPSR Register.
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 \return xPSR Register value
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 uint32_t result;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
<> 144:ef7eb2e8f9f7 416 return(result);
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /** \brief Get Process Stack Pointer
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 This function returns the current value of the Process Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 \return PSP Register value
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 register uint32_t result;
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
<> 144:ef7eb2e8f9f7 431 return(result);
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** \brief Set Process Stack Pointer
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 This function assigns the given value to the Process Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 \param [in] topOfProcStack Process Stack Pointer value to set
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /** \brief Get Main Stack Pointer
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 This function returns the current value of the Main Stack Pointer (MSP).
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 \return MSP Register value
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 register uint32_t result;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
<> 144:ef7eb2e8f9f7 458 return(result);
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** \brief Set Main Stack Pointer
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 This function assigns the given value to the Main Stack Pointer (MSP).
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 \param [in] topOfMainStack Main Stack Pointer value to set
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /** \brief Get Priority Mask
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 \return Priority Mask value
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 uint32_t result;
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
<> 144:ef7eb2e8f9f7 485 return(result);
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /** \brief Set Priority Mask
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 This function assigns the given value to the Priority Mask Register.
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 \param [in] priMask Priority Mask
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 #if (__CORTEX_M >= 0x03)
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /** \brief Enable FIQ
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 506 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 __ASM volatile ("cpsie f" : : : "memory");
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /** \brief Disable FIQ
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 517 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 __ASM volatile ("cpsid f" : : : "memory");
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /** \brief Get Base Priority
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 This function returns the current value of the Base Priority register.
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 \return Base Priority register value
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 uint32_t result;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
<> 144:ef7eb2e8f9f7 536 return(result);
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /** \brief Set Base Priority
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 This function assigns the given value to the Base Priority register.
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 \param [in] basePri Base Priority value to set
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /** \brief Set Base Priority with condition
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 144:ef7eb2e8f9f7 555 or the new value increases the BASEPRI priority level.
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 \param [in] basePri Base Priority value to set
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /** \brief Get Fault Mask
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 This function returns the current value of the Fault Mask register.
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 \return Fault Mask register value
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 uint32_t result;
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
<> 144:ef7eb2e8f9f7 576 return(result);
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /** \brief Set Fault Mask
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 This function assigns the given value to the Fault Mask register.
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 \param [in] faultMask Fault Mask value to set
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #endif /* (__CORTEX_M >= 0x03) */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /** \brief Get FPSCR
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 This function returns the current value of the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 \return Floating Point Status/Control register value
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 605 uint32_t result;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Empty asm statement works as a scheduling barrier */
<> 144:ef7eb2e8f9f7 608 __ASM volatile ("");
<> 144:ef7eb2e8f9f7 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
<> 144:ef7eb2e8f9f7 610 __ASM volatile ("");
<> 144:ef7eb2e8f9f7 611 return(result);
<> 144:ef7eb2e8f9f7 612 #else
<> 144:ef7eb2e8f9f7 613 return(0);
<> 144:ef7eb2e8f9f7 614 #endif
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /** \brief Set FPSCR
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 This function assigns the given value to the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 \param [in] fpscr Floating Point Status/Control value to set
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 627 /* Empty asm statement works as a scheduling barrier */
<> 144:ef7eb2e8f9f7 628 __ASM volatile ("");
<> 144:ef7eb2e8f9f7 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
<> 144:ef7eb2e8f9f7 630 __ASM volatile ("");
<> 144:ef7eb2e8f9f7 631 #endif
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 638 /* IAR iccarm specific functions */
<> 144:ef7eb2e8f9f7 639 #include <cmsis_iar.h>
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 144:ef7eb2e8f9f7 643 /* TI CCS specific functions */
<> 144:ef7eb2e8f9f7 644 #include <cmsis_ccs.h>
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 144:ef7eb2e8f9f7 648 /* TASKING carm specific functions */
<> 144:ef7eb2e8f9f7 649 /*
<> 144:ef7eb2e8f9f7 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 144:ef7eb2e8f9f7 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 144:ef7eb2e8f9f7 652 * Including the CMSIS ones.
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 657 /* Cosmic specific functions */
<> 144:ef7eb2e8f9f7 658 #include <cmsis_csm.h>
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 #endif
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /*@} end of CMSIS_Core_RegAccFunctions */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #endif /* __CORE_CMFUNC_H */