Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 144:ef7eb2e8f9f7 2
<> 144:ef7eb2e8f9f7 3 All rights reserved.
<> 144:ef7eb2e8f9f7 4 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 5 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 6 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 7 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 8 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 9 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 10 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 11 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 12 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 13 specific prior written permission.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 18 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 25 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 26 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29 * Functions
<> 144:ef7eb2e8f9f7 30 *---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 31 .text
<> 144:ef7eb2e8f9f7 32 .global __v7_all_cache
<> 144:ef7eb2e8f9f7 33 /*
<> 144:ef7eb2e8f9f7 34 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36 __v7_all_cache:
<> 144:ef7eb2e8f9f7 37 .arm
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 PUSH {R4-R11}
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
<> 144:ef7eb2e8f9f7 42 ANDS R3, R6, #0x07000000 /* Extract coherency level */
<> 144:ef7eb2e8f9f7 43 MOV R3, R3, LSR #23 /* Total cache levels << 1 */
<> 144:ef7eb2e8f9f7 44 BEQ Finished /* If 0, no need to clean */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 MOV R10, #0 /* R10 holds current cache level << 1 */
<> 144:ef7eb2e8f9f7 47 Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
<> 144:ef7eb2e8f9f7 48 MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
<> 144:ef7eb2e8f9f7 49 AND R1, R1, #7 /* Isolate those lower 3 bits */
<> 144:ef7eb2e8f9f7 50 CMP R1, #2
<> 144:ef7eb2e8f9f7 51 BLT Skip /* No cache or only instruction cache at this level */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
<> 144:ef7eb2e8f9f7 54 ISB /* ISB to sync the change to the CacheSizeID reg */
<> 144:ef7eb2e8f9f7 55 MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
<> 144:ef7eb2e8f9f7 56 AND R2, R1, #7 /* Extract the line length field */
<> 144:ef7eb2e8f9f7 57 ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
<> 144:ef7eb2e8f9f7 58 LDR R4, =0x3FF
<> 144:ef7eb2e8f9f7 59 ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
<> 144:ef7eb2e8f9f7 60 CLZ R5, R4 /* R5 is the bit position of the way size increment */
<> 144:ef7eb2e8f9f7 61 LDR R7, =0x7FFF
<> 144:ef7eb2e8f9f7 62 ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
<> 144:ef7eb2e8f9f7 67 ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
<> 144:ef7eb2e8f9f7 68 CMP R0, #0
<> 144:ef7eb2e8f9f7 69 BNE Dccsw
<> 144:ef7eb2e8f9f7 70 MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
<> 144:ef7eb2e8f9f7 71 B cont
<> 144:ef7eb2e8f9f7 72 Dccsw: CMP R0, #1
<> 144:ef7eb2e8f9f7 73 BNE Dccisw
<> 144:ef7eb2e8f9f7 74 MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
<> 144:ef7eb2e8f9f7 75 B cont
<> 144:ef7eb2e8f9f7 76 Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
<> 144:ef7eb2e8f9f7 77 cont: SUBS R9, R9, #1 /* Decrement the Way number */
<> 144:ef7eb2e8f9f7 78 BGE Loop3
<> 144:ef7eb2e8f9f7 79 SUBS R7, R7, #1 /* Decrement the Set number */
<> 144:ef7eb2e8f9f7 80 BGE Loop2
<> 144:ef7eb2e8f9f7 81 Skip: ADD R10, R10, #2 /* increment the cache number */
<> 144:ef7eb2e8f9f7 82 CMP R3, R10
<> 144:ef7eb2e8f9f7 83 BGT Loop1
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 Finished:
<> 144:ef7eb2e8f9f7 86 DSB
<> 144:ef7eb2e8f9f7 87 POP {R4-R11}
<> 144:ef7eb2e8f9f7 88 BX lr
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 .END
<> 144:ef7eb2e8f9f7 92 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 93 * end of file
<> 144:ef7eb2e8f9f7 94 *---------------------------------------------------------------------------*/