Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/*****************************************************************************
<> 144:ef7eb2e8f9f7 2 ; * @file: startup_LPC8xx.s
<> 144:ef7eb2e8f9f7 3 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
<> 144:ef7eb2e8f9f7 4 ; * for the NXP LPC8xx Device Series
<> 144:ef7eb2e8f9f7 5 ; * @version: V1.0
<> 144:ef7eb2e8f9f7 6 ; * @date: 16. Aug. 2012
<> 144:ef7eb2e8f9f7 7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 8 ; *
<> 144:ef7eb2e8f9f7 9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
<> 144:ef7eb2e8f9f7 11 ; * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 12 ; * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 13 ; *
<> 144:ef7eb2e8f9f7 14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 ; *
<> 144:ef7eb2e8f9f7 20 ; *****************************************************************************/
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 24 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 25 ; </h>
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 28 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 __initial_sp EQU 0x10002000
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 34 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 35 ; </h>
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 Heap_Size EQU 0x00000000
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 40 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 41 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 __heap_base
<> 144:ef7eb2e8f9f7 44 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 45 __heap_limit
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 PRESERVE8
<> 144:ef7eb2e8f9f7 48 THUMB
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 54 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 57 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 58 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 59 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 60 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 61 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 64 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 65 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 66 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 67 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 68 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 69 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 70 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 71 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 ; External Interrupts
<> 144:ef7eb2e8f9f7 74 DCD SPI0_IRQHandler ; SPI0 controller
<> 144:ef7eb2e8f9f7 75 DCD SPI1_IRQHandler ; SPI1 controller
<> 144:ef7eb2e8f9f7 76 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 77 DCD UART0_IRQHandler ; UART0
<> 144:ef7eb2e8f9f7 78 DCD UART1_IRQHandler ; UART1
<> 144:ef7eb2e8f9f7 79 DCD UART2_IRQHandler ; UART2
<> 144:ef7eb2e8f9f7 80 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 81 DCD I2C1_IRQHandler ; I2C1 controller
<> 144:ef7eb2e8f9f7 82 DCD I2C0_IRQHandler ; I2C0 controller
<> 144:ef7eb2e8f9f7 83 DCD SCT_IRQHandler ; Smart Counter Timer
<> 144:ef7eb2e8f9f7 84 DCD MRT_IRQHandler ; Multi-Rate Timer
<> 144:ef7eb2e8f9f7 85 DCD CMP_IRQHandler ; Comparator
<> 144:ef7eb2e8f9f7 86 DCD WDT_IRQHandler ; PIO1 (0:11)
<> 144:ef7eb2e8f9f7 87 DCD BOD_IRQHandler ; Brown Out Detect
<> 144:ef7eb2e8f9f7 88 DCD Flash_IRQHandler ; Flash interrupt
<> 144:ef7eb2e8f9f7 89 DCD WKT_IRQHandler ; Wakeup timer
<> 144:ef7eb2e8f9f7 90 DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
<> 144:ef7eb2e8f9f7 91 DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
<> 144:ef7eb2e8f9f7 92 DCD ADC_THCMP_IRQHandler ; ADC threshold compare
<> 144:ef7eb2e8f9f7 93 DCD ADC_OVR_IRQHandler ; ADC overrun
<> 144:ef7eb2e8f9f7 94 DCD DMA__RQHandler ; DMA interrupt
<> 144:ef7eb2e8f9f7 95 DCD I2C2_IRQHandler ; I2C2 controller
<> 144:ef7eb2e8f9f7 96 DCD I2C3_IRQHandler ; I2C3 controller
<> 144:ef7eb2e8f9f7 97 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 98 DCD PININT0_IRQHandler ; PIO INT0
<> 144:ef7eb2e8f9f7 99 DCD PININT1_IRQHandler ; PIO INT1
<> 144:ef7eb2e8f9f7 100 DCD PININT2_IRQHandler ; PIO INT2
<> 144:ef7eb2e8f9f7 101 DCD PININT3_IRQHandler ; PIO INT3
<> 144:ef7eb2e8f9f7 102 DCD PININT4_IRQHandler ; PIO INT4
<> 144:ef7eb2e8f9f7 103 DCD PININT5_IRQHandler ; PIO INT5
<> 144:ef7eb2e8f9f7 104 DCD PININT6_IRQHandler ; PIO INT6
<> 144:ef7eb2e8f9f7 105 DCD PININT7_IRQHandler ; PIO INT7
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 IF :LNOT::DEF:NO_CRP
<> 144:ef7eb2e8f9f7 109 AREA |.ARM.__at_0x02FC|, CODE, READONLY
<> 144:ef7eb2e8f9f7 110 CRP_Key DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 111 ENDIF
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 ; Reset Handler
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 119 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 120 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 121 IMPORT __main
<> 144:ef7eb2e8f9f7 122 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 123 BLX R0
<> 144:ef7eb2e8f9f7 124 LDR R0, =__main
<> 144:ef7eb2e8f9f7 125 BX R0
<> 144:ef7eb2e8f9f7 126 ENDP
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 HardFault_Handler\
<> 144:ef7eb2e8f9f7 132 PROC
<> 144:ef7eb2e8f9f7 133 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 134 B .
<> 144:ef7eb2e8f9f7 135 ENDP
<> 144:ef7eb2e8f9f7 136 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 137 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 B .
<> 144:ef7eb2e8f9f7 139 ENDP
<> 144:ef7eb2e8f9f7 140 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 141 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 142 B .
<> 144:ef7eb2e8f9f7 143 ENDP
<> 144:ef7eb2e8f9f7 144 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 145 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 146 B .
<> 144:ef7eb2e8f9f7 147 ENDP
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 Default_Handler PROC
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT SPI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT SCT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT MRT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT CMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT BOD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT Flash_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT WKT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 EXPORT ADC_SEQA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 167 EXPORT ADC_SEQB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 168 EXPORT ADC_THCMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 169 EXPORT ADC_OVR_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 170 EXPORT DMA__RQHandler [WEAK]
<> 144:ef7eb2e8f9f7 171 EXPORT I2C2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 172 EXPORT I2C3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT PININT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT PININT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT PININT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT PININT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT PININT4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT PININT5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT PININT6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT PININT7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 NMI_Handler
<> 144:ef7eb2e8f9f7 183 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 184 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 185 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 186 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 187 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 188 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 189 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 190 SCT_IRQHandler
<> 144:ef7eb2e8f9f7 191 MRT_IRQHandler
<> 144:ef7eb2e8f9f7 192 CMP_IRQHandler
<> 144:ef7eb2e8f9f7 193 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 194 BOD_IRQHandler
<> 144:ef7eb2e8f9f7 195 Flash_IRQHandler
<> 144:ef7eb2e8f9f7 196 WKT_IRQHandler
<> 144:ef7eb2e8f9f7 197 ADC_SEQA_IRQHandler
<> 144:ef7eb2e8f9f7 198 ADC_SEQB_IRQHandler
<> 144:ef7eb2e8f9f7 199 ADC_THCMP_IRQHandler
<> 144:ef7eb2e8f9f7 200 ADC_OVR_IRQHandler
<> 144:ef7eb2e8f9f7 201 DMA__RQHandler
<> 144:ef7eb2e8f9f7 202 I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 203 I2C3_IRQHandler
<> 144:ef7eb2e8f9f7 204 PININT0_IRQHandler
<> 144:ef7eb2e8f9f7 205 PININT1_IRQHandler
<> 144:ef7eb2e8f9f7 206 PININT2_IRQHandler
<> 144:ef7eb2e8f9f7 207 PININT3_IRQHandler
<> 144:ef7eb2e8f9f7 208 PININT4_IRQHandler
<> 144:ef7eb2e8f9f7 209 PININT5_IRQHandler
<> 144:ef7eb2e8f9f7 210 PININT6_IRQHandler
<> 144:ef7eb2e8f9f7 211 PININT7_IRQHandler
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 B .
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 ENDP
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 ALIGN
<> 144:ef7eb2e8f9f7 218 END