Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* File: startup_ARMCM0.S
<> 144:ef7eb2e8f9f7 2 * Purpose: startup file for Cortex-M0 devices. Should use with
<> 144:ef7eb2e8f9f7 3 * GCC for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 * Version: V1.2
<> 144:ef7eb2e8f9f7 5 * Date: 15 Nov 2011
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * Copyright (c) 2011, ARM Limited
<> 144:ef7eb2e8f9f7 8 * All rights reserved.
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 11 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 12 * Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 13 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 14 * Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 15 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 16 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 17 * Neither the name of the ARM Limited nor the
<> 144:ef7eb2e8f9f7 18 names of its contributors may be used to endorse or promote products
<> 144:ef7eb2e8f9f7 19 derived from this software without specific prior written permission.
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
<> 144:ef7eb2e8f9f7 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
<> 144:ef7eb2e8f9f7 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 31 */
<> 144:ef7eb2e8f9f7 32 .syntax unified
<> 144:ef7eb2e8f9f7 33 .arch armv6-m
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /* Memory Model
<> 144:ef7eb2e8f9f7 36 The HEAP starts at the end of the DATA section and grows upward.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 The STACK starts at the end of the RAM and grows downward.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 The HEAP and stack STACK are only checked at compile time:
<> 144:ef7eb2e8f9f7 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 This is just a check for the bare minimum for the Heap+Stack area before
<> 144:ef7eb2e8f9f7 44 aborting compilation, it is not the run time limit:
<> 144:ef7eb2e8f9f7 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47 .section .stack
<> 144:ef7eb2e8f9f7 48 .align 3
<> 144:ef7eb2e8f9f7 49 #ifdef __STACK_SIZE
<> 144:ef7eb2e8f9f7 50 .equ Stack_Size, __STACK_SIZE
<> 144:ef7eb2e8f9f7 51 #else
<> 144:ef7eb2e8f9f7 52 .equ Stack_Size, 0x80
<> 144:ef7eb2e8f9f7 53 #endif
<> 144:ef7eb2e8f9f7 54 .globl __StackTop
<> 144:ef7eb2e8f9f7 55 .globl __StackLimit
<> 144:ef7eb2e8f9f7 56 __StackLimit:
<> 144:ef7eb2e8f9f7 57 .space Stack_Size
<> 144:ef7eb2e8f9f7 58 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 59 __StackTop:
<> 144:ef7eb2e8f9f7 60 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 .section .heap
<> 144:ef7eb2e8f9f7 63 .align 3
<> 144:ef7eb2e8f9f7 64 #ifdef __HEAP_SIZE
<> 144:ef7eb2e8f9f7 65 .equ Heap_Size, __HEAP_SIZE
<> 144:ef7eb2e8f9f7 66 #else
<> 144:ef7eb2e8f9f7 67 .equ Heap_Size, 0x80
<> 144:ef7eb2e8f9f7 68 #endif
<> 144:ef7eb2e8f9f7 69 .globl __HeapBase
<> 144:ef7eb2e8f9f7 70 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 71 __HeapBase:
<> 144:ef7eb2e8f9f7 72 .space Heap_Size
<> 144:ef7eb2e8f9f7 73 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 74 __HeapLimit:
<> 144:ef7eb2e8f9f7 75 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 .section .isr_vector
<> 144:ef7eb2e8f9f7 78 .align 2
<> 144:ef7eb2e8f9f7 79 .globl __isr_vector
<> 144:ef7eb2e8f9f7 80 __isr_vector:
<> 144:ef7eb2e8f9f7 81 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 82 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 83 .long NMI_Handler /* NMI Handler */
<> 144:ef7eb2e8f9f7 84 .long HardFault_Handler /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 85 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 86 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 87 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 88 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 89 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 90 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 91 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 92 .long SVC_Handler /* SVCall Handler */
<> 144:ef7eb2e8f9f7 93 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 94 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 95 .long PendSV_Handler /* PendSV Handler */
<> 144:ef7eb2e8f9f7 96 .long SysTick_Handler /* SysTick Handler */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* LPC824 interrupts */
<> 144:ef7eb2e8f9f7 99 .long SPI0_IRQHandler // SPI0 controller
<> 144:ef7eb2e8f9f7 100 .long SPI1_IRQHandler // SPI1 controller
<> 144:ef7eb2e8f9f7 101 .long 0 // Reserved
<> 144:ef7eb2e8f9f7 102 .long UART0_IRQHandler // UART0
<> 144:ef7eb2e8f9f7 103 .long UART1_IRQHandler // UART1
<> 144:ef7eb2e8f9f7 104 .long UART2_IRQHandler // UART2
<> 144:ef7eb2e8f9f7 105 .long 0 // Reserved
<> 144:ef7eb2e8f9f7 106 .long I2C1_IRQHandler // I2C ch1 controller
<> 144:ef7eb2e8f9f7 107 .long I2C0_IRQHandler // I2C ch0 controller
<> 144:ef7eb2e8f9f7 108 .long SCT_IRQHandler // Smart Counter Timer
<> 144:ef7eb2e8f9f7 109 .long MRT_IRQHandler // Multi-Rate Timer
<> 144:ef7eb2e8f9f7 110 .long CMP_IRQHandler // Comparator
<> 144:ef7eb2e8f9f7 111 .long WDT_IRQHandler // PIO1 (0:11)
<> 144:ef7eb2e8f9f7 112 .long BOD_IRQHandler // Brown Out Detect
<> 144:ef7eb2e8f9f7 113 .long Flash_IRQHandler // Flash interrupt
<> 144:ef7eb2e8f9f7 114 .long WKT_IRQHandler // Wakeup timer
<> 144:ef7eb2e8f9f7 115 .long ADC_SEQA_IRQHandler // ADC sequence A completion
<> 144:ef7eb2e8f9f7 116 .long ADC_SEQB_IRQHandler // ADC sequence B completion
<> 144:ef7eb2e8f9f7 117 .long ADC_THCMP_IRQHandler // ADC threshold compare
<> 144:ef7eb2e8f9f7 118 .long ADC_OVR_IRQHandler // ADC overrun
<> 144:ef7eb2e8f9f7 119 .long DMA_IRQHandler // DMA interrupt
<> 144:ef7eb2e8f9f7 120 .long I2C2_IRQHandler // I2C2 controller
<> 144:ef7eb2e8f9f7 121 .long I2C3_IRQHandler // I2C3 controller
<> 144:ef7eb2e8f9f7 122 .long 0 // Reserved
<> 144:ef7eb2e8f9f7 123 .long PININT0_IRQHandler // PIO INT0
<> 144:ef7eb2e8f9f7 124 .long PININT1_IRQHandler // PIO INT1
<> 144:ef7eb2e8f9f7 125 .long PININT2_IRQHandler // PIO INT2
<> 144:ef7eb2e8f9f7 126 .long PININT3_IRQHandler // PIO INT3
<> 144:ef7eb2e8f9f7 127 .long PININT4_IRQHandler // PIO INT4
<> 144:ef7eb2e8f9f7 128 .long PININT5_IRQHandler // PIO INT5
<> 144:ef7eb2e8f9f7 129 .long PININT6_IRQHandler // PIO INT6
<> 144:ef7eb2e8f9f7 130 .long PININT7_IRQHandler // PIO INT7
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 135 .thumb
<> 144:ef7eb2e8f9f7 136 .thumb_func
<> 144:ef7eb2e8f9f7 137 .align 2
<> 144:ef7eb2e8f9f7 138 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 139 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 140 Reset_Handler:
<> 144:ef7eb2e8f9f7 141 /* Loop to copy data from read only memory to RAM. The ranges
<> 144:ef7eb2e8f9f7 142 * of copy from/to are specified by following symbols evaluated in
<> 144:ef7eb2e8f9f7 143 * linker script.
<> 144:ef7eb2e8f9f7 144 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 144:ef7eb2e8f9f7 145 * __data_start__/__data_end__: RAM address range that data should be
<> 144:ef7eb2e8f9f7 146 * copied to. Both must be aligned to 4 bytes boundary. */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 149 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 150 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 subs r3, r2
<> 144:ef7eb2e8f9f7 153 ble .Lflash_to_ram_loop_end
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 movs r4, 0
<> 144:ef7eb2e8f9f7 156 .Lflash_to_ram_loop:
<> 144:ef7eb2e8f9f7 157 ldr r0, [r1,r4]
<> 144:ef7eb2e8f9f7 158 str r0, [r2,r4]
<> 144:ef7eb2e8f9f7 159 adds r4, 4
<> 144:ef7eb2e8f9f7 160 cmp r4, r3
<> 144:ef7eb2e8f9f7 161 blt .Lflash_to_ram_loop
<> 144:ef7eb2e8f9f7 162 .Lflash_to_ram_loop_end:
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 165 blx r0
<> 144:ef7eb2e8f9f7 166 ldr r0, =_start
<> 144:ef7eb2e8f9f7 167 bx r0
<> 144:ef7eb2e8f9f7 168 .pool
<> 144:ef7eb2e8f9f7 169 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 .text
<> 144:ef7eb2e8f9f7 172 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 173 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 174 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 175 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 176 .align 1
<> 144:ef7eb2e8f9f7 177 .thumb_func
<> 144:ef7eb2e8f9f7 178 .weak \handler_name
<> 144:ef7eb2e8f9f7 179 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 180 \handler_name :
<> 144:ef7eb2e8f9f7 181 b .
<> 144:ef7eb2e8f9f7 182 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 183 .endm
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 def_default_handler NMI_Handler
<> 144:ef7eb2e8f9f7 186 def_default_handler HardFault_Handler
<> 144:ef7eb2e8f9f7 187 def_default_handler SVC_Handler
<> 144:ef7eb2e8f9f7 188 def_default_handler PendSV_Handler
<> 144:ef7eb2e8f9f7 189 def_default_handler SysTick_Handler
<> 144:ef7eb2e8f9f7 190 def_default_handler Default_Handler
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 .macro def_irq_default_handler handler_name
<> 144:ef7eb2e8f9f7 193 .weak \handler_name
<> 144:ef7eb2e8f9f7 194 .set \handler_name, Default_Handler
<> 144:ef7eb2e8f9f7 195 .endm
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 def_irq_default_handler SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 198 def_irq_default_handler SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 199 def_irq_default_handler UART0_IRQHandler
<> 144:ef7eb2e8f9f7 200 def_irq_default_handler UART1_IRQHandler
<> 144:ef7eb2e8f9f7 201 def_irq_default_handler UART2_IRQHandler
<> 144:ef7eb2e8f9f7 202 def_irq_default_handler I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 203 def_irq_default_handler I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 204 def_irq_default_handler I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 205 def_irq_default_handler I2C3_IRQHandler
<> 144:ef7eb2e8f9f7 206 def_irq_default_handler SCT_IRQHandler
<> 144:ef7eb2e8f9f7 207 def_irq_default_handler MRT_IRQHandler
<> 144:ef7eb2e8f9f7 208 def_irq_default_handler CMP_IRQHandler
<> 144:ef7eb2e8f9f7 209 def_irq_default_handler WDT_IRQHandler
<> 144:ef7eb2e8f9f7 210 def_irq_default_handler BOD_IRQHandler
<> 144:ef7eb2e8f9f7 211 def_irq_default_handler Flash_IRQHandler
<> 144:ef7eb2e8f9f7 212 def_irq_default_handler WKT_IRQHandler
<> 144:ef7eb2e8f9f7 213 def_irq_default_handler ADC_SEQA_IRQHandler
<> 144:ef7eb2e8f9f7 214 def_irq_default_handler ADC_SEQB_IRQHandler
<> 144:ef7eb2e8f9f7 215 def_irq_default_handler ADC_THCMP_IRQHandler
<> 144:ef7eb2e8f9f7 216 def_irq_default_handler ADC_OVR_IRQHandler
<> 144:ef7eb2e8f9f7 217 def_irq_default_handler DMA_IRQHandler
<> 144:ef7eb2e8f9f7 218 def_irq_default_handler PININT0_IRQHandler
<> 144:ef7eb2e8f9f7 219 def_irq_default_handler PININT1_IRQHandler
<> 144:ef7eb2e8f9f7 220 def_irq_default_handler PININT2_IRQHandler
<> 144:ef7eb2e8f9f7 221 def_irq_default_handler PININT3_IRQHandler
<> 144:ef7eb2e8f9f7 222 def_irq_default_handler PININT4_IRQHandler
<> 144:ef7eb2e8f9f7 223 def_irq_default_handler PININT5_IRQHandler
<> 144:ef7eb2e8f9f7 224 def_irq_default_handler PININT6_IRQHandler
<> 144:ef7eb2e8f9f7 225 def_irq_default_handler PININT7_IRQHandler
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 .end
<> 144:ef7eb2e8f9f7 228