Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/*****************************************************************************
<> 144:ef7eb2e8f9f7 2 ; * @file: startup_LPC8xx.s
<> 144:ef7eb2e8f9f7 3 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
<> 144:ef7eb2e8f9f7 4 ; * for the NXP LPC8xx Device Series
<> 144:ef7eb2e8f9f7 5 ; * @version: V1.0
<> 144:ef7eb2e8f9f7 6 ; * @date: 16. Aug. 2012
<> 144:ef7eb2e8f9f7 7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 8 ; *
<> 144:ef7eb2e8f9f7 9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
<> 144:ef7eb2e8f9f7 11 ; * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 12 ; * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 13 ; *
<> 144:ef7eb2e8f9f7 14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 ; *
<> 144:ef7eb2e8f9f7 20 ; *****************************************************************************/
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 24 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 25 ; </h>
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 Stack_Size EQU 0x00000200
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 30 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 33 __initial_sp EQU 0x10001000
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 37 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 38 ; </h>
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 Heap_Size EQU 0x00000000
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 43 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 44 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 __heap_base
<> 144:ef7eb2e8f9f7 47 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 48 __heap_limit
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 PRESERVE8
<> 144:ef7eb2e8f9f7 51 THUMB
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 57 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 60 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 61 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 62 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 63 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 64 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 65 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 66 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 67 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 68 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 69 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 70 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 71 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 72 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 73 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 74 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 ; External Interrupts
<> 144:ef7eb2e8f9f7 77 DCD SPI0_IRQHandler ; SPI0 controller
<> 144:ef7eb2e8f9f7 78 DCD SPI1_IRQHandler ; SPI1 controller
<> 144:ef7eb2e8f9f7 79 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 80 DCD UART0_IRQHandler ; UART0
<> 144:ef7eb2e8f9f7 81 DCD UART1_IRQHandler ; UART1
<> 144:ef7eb2e8f9f7 82 DCD UART2_IRQHandler ; UART2
<> 144:ef7eb2e8f9f7 83 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 84 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 85 DCD I2C_IRQHandler ; I2C controller
<> 144:ef7eb2e8f9f7 86 DCD SCT_IRQHandler ; Smart Counter Timer
<> 144:ef7eb2e8f9f7 87 DCD MRT_IRQHandler ; Multi-Rate Timer
<> 144:ef7eb2e8f9f7 88 DCD CMP_IRQHandler ; Comparator
<> 144:ef7eb2e8f9f7 89 DCD WDT_IRQHandler ; PIO1 (0:11)
<> 144:ef7eb2e8f9f7 90 DCD BOD_IRQHandler ; Brown Out Detect
<> 144:ef7eb2e8f9f7 91 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 92 DCD WKT_IRQHandler ; Wakeup timer
<> 144:ef7eb2e8f9f7 93 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 94 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 95 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 96 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 97 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 98 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 99 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 100 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 101 DCD PININT0_IRQHandler ; PIO INT0
<> 144:ef7eb2e8f9f7 102 DCD PININT1_IRQHandler ; PIO INT1
<> 144:ef7eb2e8f9f7 103 DCD PININT2_IRQHandler ; PIO INT2
<> 144:ef7eb2e8f9f7 104 DCD PININT3_IRQHandler ; PIO INT3
<> 144:ef7eb2e8f9f7 105 DCD PININT4_IRQHandler ; PIO INT4
<> 144:ef7eb2e8f9f7 106 DCD PININT5_IRQHandler ; PIO INT5
<> 144:ef7eb2e8f9f7 107 DCD PININT6_IRQHandler ; PIO INT6
<> 144:ef7eb2e8f9f7 108 DCD PININT7_IRQHandler ; PIO INT7
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 IF :LNOT::DEF:NO_CRP
<> 144:ef7eb2e8f9f7 112 AREA |.ARM.__at_0x02FC|, CODE, READONLY
<> 144:ef7eb2e8f9f7 113 CRP_Key DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 114 ENDIF
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 ; Reset Handler
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 123 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 124 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 125 IMPORT __main
<> 144:ef7eb2e8f9f7 126 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 127 BLX R0
<> 144:ef7eb2e8f9f7 128 LDR R0, =__main
<> 144:ef7eb2e8f9f7 129 BX R0
<> 144:ef7eb2e8f9f7 130 ENDP
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 134 ; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
<> 144:ef7eb2e8f9f7 135 ; for particular peripheral.
<> 144:ef7eb2e8f9f7 136 ;NMI_Handler PROC
<> 144:ef7eb2e8f9f7 137 ; EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 ; B .
<> 144:ef7eb2e8f9f7 139 ; ENDP
<> 144:ef7eb2e8f9f7 140 HardFault_Handler\
<> 144:ef7eb2e8f9f7 141 PROC
<> 144:ef7eb2e8f9f7 142 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 143 B .
<> 144:ef7eb2e8f9f7 144 ENDP
<> 144:ef7eb2e8f9f7 145 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 146 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 147 B .
<> 144:ef7eb2e8f9f7 148 ENDP
<> 144:ef7eb2e8f9f7 149 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 150 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 151 B .
<> 144:ef7eb2e8f9f7 152 ENDP
<> 144:ef7eb2e8f9f7 153 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 154 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 155 B .
<> 144:ef7eb2e8f9f7 156 ENDP
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 Default_Handler PROC
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT SPI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 EXPORT I2C_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 167 EXPORT SCT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 168 EXPORT MRT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 169 EXPORT CMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 170 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 171 EXPORT BOD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 EXPORT WKT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 EXPORT PININT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT PININT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT PININT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT PININT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT PININT4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT PININT5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 181 EXPORT PININT6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 182 EXPORT PININT7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 NMI_Handler
<> 144:ef7eb2e8f9f7 185 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 186 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 187 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 188 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 189 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 190 I2C_IRQHandler
<> 144:ef7eb2e8f9f7 191 SCT_IRQHandler
<> 144:ef7eb2e8f9f7 192 MRT_IRQHandler
<> 144:ef7eb2e8f9f7 193 CMP_IRQHandler
<> 144:ef7eb2e8f9f7 194 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 195 BOD_IRQHandler
<> 144:ef7eb2e8f9f7 196 WKT_IRQHandler
<> 144:ef7eb2e8f9f7 197 PININT0_IRQHandler
<> 144:ef7eb2e8f9f7 198 PININT1_IRQHandler
<> 144:ef7eb2e8f9f7 199 PININT2_IRQHandler
<> 144:ef7eb2e8f9f7 200 PININT3_IRQHandler
<> 144:ef7eb2e8f9f7 201 PININT4_IRQHandler
<> 144:ef7eb2e8f9f7 202 PININT5_IRQHandler
<> 144:ef7eb2e8f9f7 203 PININT6_IRQHandler
<> 144:ef7eb2e8f9f7 204 PININT7_IRQHandler
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 B .
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 ENDP
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 ALIGN
<> 144:ef7eb2e8f9f7 211 END