Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /****************************************************************************
<> 144:ef7eb2e8f9f7 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
<> 144:ef7eb2e8f9f7 3 * Project: NXP LPC8xx software example
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Description:
<> 144:ef7eb2e8f9f7 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 7 * NXP LPC800 Device Series
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ****************************************************************************
<> 144:ef7eb2e8f9f7 10 * Software that is described herein is for illustrative purposes only
<> 144:ef7eb2e8f9f7 11 * which provides customers with programming information regarding the
<> 144:ef7eb2e8f9f7 12 * products. This software is supplied "AS IS" without any warranties.
<> 144:ef7eb2e8f9f7 13 * NXP Semiconductors assumes no responsibility or liability for the
<> 144:ef7eb2e8f9f7 14 * use of the software, conveys no license or title under any patent,
<> 144:ef7eb2e8f9f7 15 * copyright, or mask work right to the product. NXP Semiconductors
<> 144:ef7eb2e8f9f7 16 * reserves the right to make changes in the software without
<> 144:ef7eb2e8f9f7 17 * notification. NXP Semiconductors also make no representation or
<> 144:ef7eb2e8f9f7 18 * warranty that such application will be suitable for the specified
<> 144:ef7eb2e8f9f7 19 * use without further testing or modification.
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 * Permission to use, copy, modify, and distribute this software and its
<> 144:ef7eb2e8f9f7 22 * documentation is hereby granted, under NXP Semiconductors'
<> 144:ef7eb2e8f9f7 23 * relevant copyright in the software, without fee, provided that it
<> 144:ef7eb2e8f9f7 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
<> 144:ef7eb2e8f9f7 25 * copyright, permission, and disclaimer notice must appear in all copies of
<> 144:ef7eb2e8f9f7 26 * this code.
<> 144:ef7eb2e8f9f7 27 ****************************************************************************/
<> 144:ef7eb2e8f9f7 28 #ifndef __LPC8xx_H__
<> 144:ef7eb2e8f9f7 29 #define __LPC8xx_H__
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 32 extern "C" {
<> 144:ef7eb2e8f9f7 33 #endif
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
<> 144:ef7eb2e8f9f7 36 This file defines all structures and symbols for LPC8xx:
<> 144:ef7eb2e8f9f7 37 - Registers and bitfields
<> 144:ef7eb2e8f9f7 38 - peripheral base address
<> 144:ef7eb2e8f9f7 39 - PIO definitions
<> 144:ef7eb2e8f9f7 40 @{
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /******************************************************************************/
<> 144:ef7eb2e8f9f7 45 /* Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 46 /******************************************************************************/
<> 144:ef7eb2e8f9f7 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
<> 144:ef7eb2e8f9f7 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 49 @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*
<> 144:ef7eb2e8f9f7 53 * ==========================================================================
<> 144:ef7eb2e8f9f7 54 * ---------- Interrupt Number Definition -----------------------------------
<> 144:ef7eb2e8f9f7 55 * ==========================================================================
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57 typedef enum IRQn
<> 144:ef7eb2e8f9f7 58 {
<> 144:ef7eb2e8f9f7 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
<> 144:ef7eb2e8f9f7 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
<> 144:ef7eb2e8f9f7 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
<> 144:ef7eb2e8f9f7 68 SPI0_IRQn = 0, /*!< SPI0 */
<> 144:ef7eb2e8f9f7 69 SPI1_IRQn = 1, /*!< SPI1 */
<> 144:ef7eb2e8f9f7 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 71 UART0_IRQn = 3, /*!< USART0 */
<> 144:ef7eb2e8f9f7 72 UART1_IRQn = 4, /*!< USART1 */
<> 144:ef7eb2e8f9f7 73 UART2_IRQn = 5, /*!< USART2 */
<> 144:ef7eb2e8f9f7 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 76 I2C_IRQn = 8, /*!< I2C */
<> 144:ef7eb2e8f9f7 77 SCT_IRQn = 9, /*!< SCT */
<> 144:ef7eb2e8f9f7 78 MRT_IRQn = 10, /*!< MRT */
<> 144:ef7eb2e8f9f7 79 CMP_IRQn = 11, /*!< CMP */
<> 144:ef7eb2e8f9f7 80 WDT_IRQn = 12, /*!< WDT */
<> 144:ef7eb2e8f9f7 81 BOD_IRQn = 13, /*!< BOD */
<> 144:ef7eb2e8f9f7 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 83 WKT_IRQn = 15, /*!< WKT Interrupt */
<> 144:ef7eb2e8f9f7 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
<> 144:ef7eb2e8f9f7 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
<> 144:ef7eb2e8f9f7 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
<> 144:ef7eb2e8f9f7 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
<> 144:ef7eb2e8f9f7 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
<> 144:ef7eb2e8f9f7 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
<> 144:ef7eb2e8f9f7 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
<> 144:ef7eb2e8f9f7 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
<> 144:ef7eb2e8f9f7 100 } IRQn_Type;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /*
<> 144:ef7eb2e8f9f7 103 * ==========================================================================
<> 144:ef7eb2e8f9f7 104 * ----------- Processor and Core Peripheral Section ------------------------
<> 144:ef7eb2e8f9f7 105 * ==========================================================================
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
<> 144:ef7eb2e8f9f7 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /*@}*/ /* end of group LPC8xx_CMSIS */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
<> 144:ef7eb2e8f9f7 118 #include "system_LPC8xx.h" /* System Header */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /******************************************************************************/
<> 144:ef7eb2e8f9f7 122 /* Device Specific Peripheral Registers structures */
<> 144:ef7eb2e8f9f7 123 /******************************************************************************/
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 126 #pragma anon_unions
<> 144:ef7eb2e8f9f7 127 #endif
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /*------------- System Control (SYSCON) --------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
<> 144:ef7eb2e8f9f7 131 @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 typedef struct
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
<> 144:ef7eb2e8f9f7 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
<> 144:ef7eb2e8f9f7 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
<> 144:ef7eb2e8f9f7 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
<> 144:ef7eb2e8f9f7 139 uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
<> 144:ef7eb2e8f9f7 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
<> 144:ef7eb2e8f9f7 143 uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
<> 144:ef7eb2e8f9f7 145 uint32_t RESERVED2[3];
<> 144:ef7eb2e8f9f7 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
<> 144:ef7eb2e8f9f7 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 148 uint32_t RESERVED3[10];
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
<> 144:ef7eb2e8f9f7 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
<> 144:ef7eb2e8f9f7 153 uint32_t RESERVED4[1];
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
<> 144:ef7eb2e8f9f7 156 uint32_t RESERVED5[4];
<> 144:ef7eb2e8f9f7 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
<> 144:ef7eb2e8f9f7 158 uint32_t RESERVED6[18];
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
<> 144:ef7eb2e8f9f7 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
<> 144:ef7eb2e8f9f7 163 uint32_t RESERVED7;
<> 144:ef7eb2e8f9f7 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
<> 144:ef7eb2e8f9f7 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
<> 144:ef7eb2e8f9f7 166 uint32_t RESERVED8[1];
<> 144:ef7eb2e8f9f7 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
<> 144:ef7eb2e8f9f7 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
<> 144:ef7eb2e8f9f7 169 uint32_t RESERVED9[12];
<> 144:ef7eb2e8f9f7 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
<> 144:ef7eb2e8f9f7 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
<> 144:ef7eb2e8f9f7 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
<> 144:ef7eb2e8f9f7 173 uint32_t RESERVED10[6];
<> 144:ef7eb2e8f9f7 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
<> 144:ef7eb2e8f9f7 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
<> 144:ef7eb2e8f9f7 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 177 uint32_t RESERVED11[27];
<> 144:ef7eb2e8f9f7 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 179 uint32_t RESERVED12[3];
<> 144:ef7eb2e8f9f7 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 181 uint32_t RESERVED13[6];
<> 144:ef7eb2e8f9f7 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
<> 144:ef7eb2e8f9f7 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
<> 144:ef7eb2e8f9f7 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
<> 144:ef7eb2e8f9f7 185 uint32_t RESERVED14[110];
<> 144:ef7eb2e8f9f7 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
<> 144:ef7eb2e8f9f7 187 } LPC_SYSCON_TypeDef;
<> 144:ef7eb2e8f9f7 188 /*@}*/ /* end of group LPC8xx_SYSCON */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
<> 144:ef7eb2e8f9f7 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
<> 144:ef7eb2e8f9f7 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
<> 144:ef7eb2e8f9f7 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
<> 144:ef7eb2e8f9f7 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
<> 144:ef7eb2e8f9f7 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
<> 144:ef7eb2e8f9f7 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
<> 144:ef7eb2e8f9f7 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
<> 144:ef7eb2e8f9f7 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
<> 144:ef7eb2e8f9f7 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
<> 144:ef7eb2e8f9f7 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
<> 144:ef7eb2e8f9f7 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
<> 144:ef7eb2e8f9f7 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
<> 144:ef7eb2e8f9f7 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
<> 144:ef7eb2e8f9f7 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
<> 144:ef7eb2e8f9f7 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
<> 144:ef7eb2e8f9f7 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
<> 144:ef7eb2e8f9f7 215 } LPC_IOCON_TypeDef;
<> 144:ef7eb2e8f9f7 216 /*@}*/ /* end of group LPC8xx_IOCON */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
<> 144:ef7eb2e8f9f7 222 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
<> 144:ef7eb2e8f9f7 224 __I uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
<> 144:ef7eb2e8f9f7 227 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 228 __I uint32_t FMSW0;
<> 144:ef7eb2e8f9f7 229 } LPC_FLASHCTRL_TypeDef;
<> 144:ef7eb2e8f9f7 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /*------------- Power Management Unit (PMU) --------------------------*/
<> 144:ef7eb2e8f9f7 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
<> 144:ef7eb2e8f9f7 235 @{
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 typedef struct
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
<> 144:ef7eb2e8f9f7 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
<> 144:ef7eb2e8f9f7 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
<> 144:ef7eb2e8f9f7 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
<> 144:ef7eb2e8f9f7 245 } LPC_PMU_TypeDef;
<> 144:ef7eb2e8f9f7 246 /*@}*/ /* end of group LPC8xx_PMU */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /*------------- Switch Matrix Port --------------------------*/
<> 144:ef7eb2e8f9f7 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
<> 144:ef7eb2e8f9f7 251 @{
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253 typedef struct
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 union {
<> 144:ef7eb2e8f9f7 256 __IO uint32_t PINASSIGN[9];
<> 144:ef7eb2e8f9f7 257 struct {
<> 144:ef7eb2e8f9f7 258 __IO uint32_t PINASSIGN0;
<> 144:ef7eb2e8f9f7 259 __IO uint32_t PINASSIGN1;
<> 144:ef7eb2e8f9f7 260 __IO uint32_t PINASSIGN2;
<> 144:ef7eb2e8f9f7 261 __IO uint32_t PINASSIGN3;
<> 144:ef7eb2e8f9f7 262 __IO uint32_t PINASSIGN4;
<> 144:ef7eb2e8f9f7 263 __IO uint32_t PINASSIGN5;
<> 144:ef7eb2e8f9f7 264 __IO uint32_t PINASSIGN6;
<> 144:ef7eb2e8f9f7 265 __IO uint32_t PINASSIGN7;
<> 144:ef7eb2e8f9f7 266 __IO uint32_t PINASSIGN8;
<> 144:ef7eb2e8f9f7 267 };
<> 144:ef7eb2e8f9f7 268 };
<> 144:ef7eb2e8f9f7 269 __I uint32_t RESERVED0[103];
<> 144:ef7eb2e8f9f7 270 __IO uint32_t PINENABLE0;
<> 144:ef7eb2e8f9f7 271 } LPC_SWM_TypeDef;
<> 144:ef7eb2e8f9f7 272 /*@}*/ /* end of group LPC8xx_SWM */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 276 // ----- GPIO_PORT -----
<> 144:ef7eb2e8f9f7 277 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 typedef struct {
<> 144:ef7eb2e8f9f7 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
<> 144:ef7eb2e8f9f7 285 __I uint16_t RESERVED0[2039];
<> 144:ef7eb2e8f9f7 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 287 uint32_t RESERVED1[1006];
<> 144:ef7eb2e8f9f7 288 __IO uint32_t DIR0; /* 0x2000 */
<> 144:ef7eb2e8f9f7 289 uint32_t RESERVED2[31];
<> 144:ef7eb2e8f9f7 290 __IO uint32_t MASK0; /* 0x2080 */
<> 144:ef7eb2e8f9f7 291 uint32_t RESERVED3[31];
<> 144:ef7eb2e8f9f7 292 __IO uint32_t PIN0; /* 0x2100 */
<> 144:ef7eb2e8f9f7 293 uint32_t RESERVED4[31];
<> 144:ef7eb2e8f9f7 294 __IO uint32_t MPIN0; /* 0x2180 */
<> 144:ef7eb2e8f9f7 295 uint32_t RESERVED5[31];
<> 144:ef7eb2e8f9f7 296 __IO uint32_t SET0; /* 0x2200 */
<> 144:ef7eb2e8f9f7 297 uint32_t RESERVED6[31];
<> 144:ef7eb2e8f9f7 298 __O uint32_t CLR0; /* 0x2280 */
<> 144:ef7eb2e8f9f7 299 uint32_t RESERVED7[31];
<> 144:ef7eb2e8f9f7 300 __O uint32_t NOT0; /* 0x2300 */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 } LPC_GPIO_PORT_TypeDef;
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 306 // ----- PIN_INT -----
<> 144:ef7eb2e8f9f7 307 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
<> 144:ef7eb2e8f9f7 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
<> 144:ef7eb2e8f9f7 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
<> 144:ef7eb2e8f9f7 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
<> 144:ef7eb2e8f9f7 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
<> 144:ef7eb2e8f9f7 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
<> 144:ef7eb2e8f9f7 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
<> 144:ef7eb2e8f9f7 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
<> 144:ef7eb2e8f9f7 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
<> 144:ef7eb2e8f9f7 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
<> 144:ef7eb2e8f9f7 327 } LPC_PIN_INT_TypeDef;
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
<> 144:ef7eb2e8f9f7 331 /** @addtogroup LPC8xx_CRC
<> 144:ef7eb2e8f9f7 332 @{
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 typedef struct
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 __IO uint32_t MODE;
<> 144:ef7eb2e8f9f7 337 __IO uint32_t SEED;
<> 144:ef7eb2e8f9f7 338 union {
<> 144:ef7eb2e8f9f7 339 __I uint32_t SUM;
<> 144:ef7eb2e8f9f7 340 __O uint32_t WR_DATA_DWORD;
<> 144:ef7eb2e8f9f7 341 __O uint16_t WR_DATA_WORD;
<> 144:ef7eb2e8f9f7 342 uint16_t RESERVED_WORD;
<> 144:ef7eb2e8f9f7 343 __O uint8_t WR_DATA_BYTE;
<> 144:ef7eb2e8f9f7 344 uint8_t RESERVED_BYTE[3];
<> 144:ef7eb2e8f9f7 345 };
<> 144:ef7eb2e8f9f7 346 } LPC_CRC_TypeDef;
<> 144:ef7eb2e8f9f7 347 /*@}*/ /* end of group LPC8xx_CRC */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /*------------- Comparator (CMP) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
<> 144:ef7eb2e8f9f7 351 @{
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
<> 144:ef7eb2e8f9f7 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
<> 144:ef7eb2e8f9f7 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
<> 144:ef7eb2e8f9f7 356 } LPC_CMP_TypeDef;
<> 144:ef7eb2e8f9f7 357 /*@}*/ /* end of group LPC8xx_CMP */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 361 /** @addtogroup LPC8xx_WKT
<> 144:ef7eb2e8f9f7 362 @{
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
<> 144:ef7eb2e8f9f7 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
<> 144:ef7eb2e8f9f7 366 uint32_t Reserved[2];
<> 144:ef7eb2e8f9f7 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
<> 144:ef7eb2e8f9f7 368 } LPC_WKT_TypeDef;
<> 144:ef7eb2e8f9f7 369 /*@}*/ /* end of group LPC8xx_WKT */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 372 //New, Copied from lpc824
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Multi-Rate Timer (MRT) (MRT)
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 typedef struct { /*!< (@ 0x40004000) MRT Structure */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 378 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 379 __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 380 value of the down-counter. */
<> 144:ef7eb2e8f9f7 381 __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 382 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 383 __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 384 __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 385 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 386 __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 387 value of the down-counter. */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 389 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 390 __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 391 __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 392 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 393 __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 394 value of the down-counter. */
<> 144:ef7eb2e8f9f7 395 __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 396 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 397 __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 398 __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 399 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 400 __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 401 value of the down-counter. */
<> 144:ef7eb2e8f9f7 402 __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 403 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 404 __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 405 __I uint32_t RESERVED0[45];
<> 144:ef7eb2e8f9f7 406 __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
<> 144:ef7eb2e8f9f7 407 the number of the first idle channel. */
<> 144:ef7eb2e8f9f7 408 __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
<> 144:ef7eb2e8f9f7 409 } LPC_MRT_TypeDef;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
<> 144:ef7eb2e8f9f7 412 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
<> 144:ef7eb2e8f9f7 413 @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 typedef struct
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 __IO uint32_t CFG; /* 0x00 */
<> 144:ef7eb2e8f9f7 421 __IO uint32_t CTRL;
<> 144:ef7eb2e8f9f7 422 __IO uint32_t STAT;
<> 144:ef7eb2e8f9f7 423 __IO uint32_t INTENSET;
<> 144:ef7eb2e8f9f7 424 __O uint32_t INTENCLR; /* 0x10 */
<> 144:ef7eb2e8f9f7 425 __I uint32_t RXDATA;
<> 144:ef7eb2e8f9f7 426 __I uint32_t RXDATA_STAT;
<> 144:ef7eb2e8f9f7 427 __IO uint32_t TXDATA;
<> 144:ef7eb2e8f9f7 428 __IO uint32_t BRG; /* 0x20 */
<> 144:ef7eb2e8f9f7 429 __IO uint32_t INTSTAT;
<> 144:ef7eb2e8f9f7 430 } LPC_USART_TypeDef;
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /*@}*/ /* end of group LPC8xx_USART */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
<> 144:ef7eb2e8f9f7 436 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
<> 144:ef7eb2e8f9f7 437 @{
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 typedef struct
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 __IO uint32_t CFG; /* 0x00 */
<> 144:ef7eb2e8f9f7 442 __IO uint32_t DLY;
<> 144:ef7eb2e8f9f7 443 __IO uint32_t STAT;
<> 144:ef7eb2e8f9f7 444 __IO uint32_t INTENSET;
<> 144:ef7eb2e8f9f7 445 __O uint32_t INTENCLR; /* 0x10 */
<> 144:ef7eb2e8f9f7 446 __I uint32_t RXDAT;
<> 144:ef7eb2e8f9f7 447 __IO uint32_t TXDATCTL;
<> 144:ef7eb2e8f9f7 448 __IO uint32_t TXDAT;
<> 144:ef7eb2e8f9f7 449 __IO uint32_t TXCTRL; /* 0x20 */
<> 144:ef7eb2e8f9f7 450 __IO uint32_t DIV;
<> 144:ef7eb2e8f9f7 451 __I uint32_t INTSTAT;
<> 144:ef7eb2e8f9f7 452 } LPC_SPI_TypeDef;
<> 144:ef7eb2e8f9f7 453 /*@}*/ /* end of group LPC8xx_SPI */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
<> 144:ef7eb2e8f9f7 457 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
<> 144:ef7eb2e8f9f7 458 @{
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460 typedef struct
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 __IO uint32_t CFG; /* 0x00 */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t STAT;
<> 144:ef7eb2e8f9f7 464 __IO uint32_t INTENSET;
<> 144:ef7eb2e8f9f7 465 __O uint32_t INTENCLR;
<> 144:ef7eb2e8f9f7 466 __IO uint32_t TIMEOUT; /* 0x10 */
<> 144:ef7eb2e8f9f7 467 __IO uint32_t DIV;
<> 144:ef7eb2e8f9f7 468 __IO uint32_t INTSTAT;
<> 144:ef7eb2e8f9f7 469 uint32_t Reserved0[1];
<> 144:ef7eb2e8f9f7 470 __IO uint32_t MSTCTL; /* 0x20 */
<> 144:ef7eb2e8f9f7 471 __IO uint32_t MSTTIME;
<> 144:ef7eb2e8f9f7 472 __IO uint32_t MSTDAT;
<> 144:ef7eb2e8f9f7 473 uint32_t Reserved1[5];
<> 144:ef7eb2e8f9f7 474 __IO uint32_t SLVCTL; /* 0x40 */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t SLVDAT;
<> 144:ef7eb2e8f9f7 476 __IO uint32_t SLVADR0;
<> 144:ef7eb2e8f9f7 477 __IO uint32_t SLVADR1;
<> 144:ef7eb2e8f9f7 478 __IO uint32_t SLVADR2; /* 0x50 */
<> 144:ef7eb2e8f9f7 479 __IO uint32_t SLVADR3;
<> 144:ef7eb2e8f9f7 480 __IO uint32_t SLVQUAL0;
<> 144:ef7eb2e8f9f7 481 uint32_t Reserved2[9];
<> 144:ef7eb2e8f9f7 482 __I uint32_t MONRXDAT; /* 0x80 */
<> 144:ef7eb2e8f9f7 483 } LPC_I2C_TypeDef;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /*@}*/ /* end of group LPC8xx_I2C */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief State Configurable Timer (SCT) (SCT)
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 #define CONFIG_SCT_nEV (6) /* Number of events */
<> 144:ef7eb2e8f9f7 496 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
<> 144:ef7eb2e8f9f7 497 #define CONFIG_SCT_nOU (4) /* Number of outputs */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 typedef struct
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
<> 144:ef7eb2e8f9f7 502 union {
<> 144:ef7eb2e8f9f7 503 __IO uint32_t CTRL_U; /* 0x004 Control Register */
<> 144:ef7eb2e8f9f7 504 struct {
<> 144:ef7eb2e8f9f7 505 __IO uint16_t CTRL_L; /* 0x004 low control register */
<> 144:ef7eb2e8f9f7 506 __IO uint16_t CTRL_H; /* 0x006 high control register */
<> 144:ef7eb2e8f9f7 507 };
<> 144:ef7eb2e8f9f7 508 };
<> 144:ef7eb2e8f9f7 509 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
<> 144:ef7eb2e8f9f7 510 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
<> 144:ef7eb2e8f9f7 511 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
<> 144:ef7eb2e8f9f7 512 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
<> 144:ef7eb2e8f9f7 513 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
<> 144:ef7eb2e8f9f7 514 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
<> 144:ef7eb2e8f9f7 515 __IO uint16_t START_L; /* 0x014 start register for counter L */
<> 144:ef7eb2e8f9f7 516 __IO uint16_t START_H; /* 0x016 start register for counter H */
<> 144:ef7eb2e8f9f7 517 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
<> 144:ef7eb2e8f9f7 518 union {
<> 144:ef7eb2e8f9f7 519 __IO uint32_t COUNT_U; /* 0x040 counter register */
<> 144:ef7eb2e8f9f7 520 struct {
<> 144:ef7eb2e8f9f7 521 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
<> 144:ef7eb2e8f9f7 522 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
<> 144:ef7eb2e8f9f7 523 };
<> 144:ef7eb2e8f9f7 524 };
<> 144:ef7eb2e8f9f7 525 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
<> 144:ef7eb2e8f9f7 526 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
<> 144:ef7eb2e8f9f7 527 __I uint32_t INPUT; /* 0x048 input register */
<> 144:ef7eb2e8f9f7 528 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
<> 144:ef7eb2e8f9f7 529 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
<> 144:ef7eb2e8f9f7 530 __IO uint32_t OUTPUT; /* 0x050 output register */
<> 144:ef7eb2e8f9f7 531 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
<> 144:ef7eb2e8f9f7 532 __IO uint32_t RES; /* 0x058 conflict resolution register */
<> 144:ef7eb2e8f9f7 533 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
<> 144:ef7eb2e8f9f7 534 __IO uint32_t EVEN; /* 0x0F0 event enable register */
<> 144:ef7eb2e8f9f7 535 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
<> 144:ef7eb2e8f9f7 536 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
<> 144:ef7eb2e8f9f7 537 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 union {
<> 144:ef7eb2e8f9f7 540 __IO union { /* 0x100-... Match / Capture value */
<> 144:ef7eb2e8f9f7 541 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
<> 144:ef7eb2e8f9f7 542 struct {
<> 144:ef7eb2e8f9f7 543 uint16_t L; /* SCTMATCH[i].L Access to L value */
<> 144:ef7eb2e8f9f7 544 uint16_t H; /* SCTMATCH[i].H Access to H value */
<> 144:ef7eb2e8f9f7 545 };
<> 144:ef7eb2e8f9f7 546 } MATCH[CONFIG_SCT_nRG];
<> 144:ef7eb2e8f9f7 547 __I union {
<> 144:ef7eb2e8f9f7 548 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
<> 144:ef7eb2e8f9f7 549 struct {
<> 144:ef7eb2e8f9f7 550 uint16_t L; /* SCTCAP[i].L Access to H value */
<> 144:ef7eb2e8f9f7 551 uint16_t H; /* SCTCAP[i].H Access to H value */
<> 144:ef7eb2e8f9f7 552 };
<> 144:ef7eb2e8f9f7 553 } CAP[CONFIG_SCT_nRG];
<> 144:ef7eb2e8f9f7 554 };
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 union {
<> 144:ef7eb2e8f9f7 560 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
<> 144:ef7eb2e8f9f7 561 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
<> 144:ef7eb2e8f9f7 562 };
<> 144:ef7eb2e8f9f7 563 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
<> 144:ef7eb2e8f9f7 564 union {
<> 144:ef7eb2e8f9f7 565 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
<> 144:ef7eb2e8f9f7 566 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
<> 144:ef7eb2e8f9f7 567 };
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 union {
<> 144:ef7eb2e8f9f7 573 __IO union { /* 0x200-... Match Reload / Capture Control value */
<> 144:ef7eb2e8f9f7 574 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
<> 144:ef7eb2e8f9f7 575 struct {
<> 144:ef7eb2e8f9f7 576 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
<> 144:ef7eb2e8f9f7 577 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
<> 144:ef7eb2e8f9f7 578 };
<> 144:ef7eb2e8f9f7 579 } MATCHREL[CONFIG_SCT_nRG];
<> 144:ef7eb2e8f9f7 580 __IO union {
<> 144:ef7eb2e8f9f7 581 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
<> 144:ef7eb2e8f9f7 582 struct {
<> 144:ef7eb2e8f9f7 583 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
<> 144:ef7eb2e8f9f7 584 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
<> 144:ef7eb2e8f9f7 585 };
<> 144:ef7eb2e8f9f7 586 } CAPCTRL[CONFIG_SCT_nRG];
<> 144:ef7eb2e8f9f7 587 };
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 union {
<> 144:ef7eb2e8f9f7 592 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
<> 144:ef7eb2e8f9f7 593 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
<> 144:ef7eb2e8f9f7 594 };
<> 144:ef7eb2e8f9f7 595 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
<> 144:ef7eb2e8f9f7 596 union {
<> 144:ef7eb2e8f9f7 597 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
<> 144:ef7eb2e8f9f7 598 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
<> 144:ef7eb2e8f9f7 599 };
<> 144:ef7eb2e8f9f7 600 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
<> 144:ef7eb2e8f9f7 603 uint32_t STATE; /* Event State Register */
<> 144:ef7eb2e8f9f7 604 uint32_t CTRL; /* Event Control Register */
<> 144:ef7eb2e8f9f7 605 } EVENT[CONFIG_SCT_nEV];
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
<> 144:ef7eb2e8f9f7 610 uint32_t SET; /* Output n Set Register */
<> 144:ef7eb2e8f9f7 611 uint32_t CLR; /* Output n Clear Register */
<> 144:ef7eb2e8f9f7 612 } OUT[CONFIG_SCT_nOU];
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 } LPC_SCT_TypeDef;
<> 144:ef7eb2e8f9f7 619 /*@}*/ /* end of group LPC8xx_SCT */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
<> 144:ef7eb2e8f9f7 623 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
<> 144:ef7eb2e8f9f7 624 @{
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626 typedef struct
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
<> 144:ef7eb2e8f9f7 629 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
<> 144:ef7eb2e8f9f7 630 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
<> 144:ef7eb2e8f9f7 631 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
<> 144:ef7eb2e8f9f7 632 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
<> 144:ef7eb2e8f9f7 633 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
<> 144:ef7eb2e8f9f7 634 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
<> 144:ef7eb2e8f9f7 635 } LPC_WWDT_TypeDef;
<> 144:ef7eb2e8f9f7 636 /*@}*/ /* end of group LPC8xx_WDT */
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 640 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 641 #endif
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /******************************************************************************/
<> 144:ef7eb2e8f9f7 644 /* Peripheral memory map */
<> 144:ef7eb2e8f9f7 645 /******************************************************************************/
<> 144:ef7eb2e8f9f7 646 /* Base addresses */
<> 144:ef7eb2e8f9f7 647 #define LPC_FLASH_BASE (0x00000000UL)
<> 144:ef7eb2e8f9f7 648 #define LPC_RAM_BASE (0x10000000UL)
<> 144:ef7eb2e8f9f7 649 #define LPC_ROM_BASE (0x1FFF0000UL)
<> 144:ef7eb2e8f9f7 650 #define LPC_APB0_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 651 #define LPC_AHB_BASE (0x50000000UL)
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* APB0 peripherals */
<> 144:ef7eb2e8f9f7 654 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 655 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
<> 144:ef7eb2e8f9f7 656 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
<> 144:ef7eb2e8f9f7 657 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
<> 144:ef7eb2e8f9f7 658 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
<> 144:ef7eb2e8f9f7 659 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
<> 144:ef7eb2e8f9f7 662 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
<> 144:ef7eb2e8f9f7 663 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
<> 144:ef7eb2e8f9f7 664 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
<> 144:ef7eb2e8f9f7 665 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
<> 144:ef7eb2e8f9f7 666 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
<> 144:ef7eb2e8f9f7 667 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
<> 144:ef7eb2e8f9f7 668 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
<> 144:ef7eb2e8f9f7 669 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* AHB peripherals */
<> 144:ef7eb2e8f9f7 672 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 673 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 #define LPC_GPIO_PORT_BASE (0xA0000000)
<> 144:ef7eb2e8f9f7 676 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /******************************************************************************/
<> 144:ef7eb2e8f9f7 679 /* Peripheral declaration */
<> 144:ef7eb2e8f9f7 680 /******************************************************************************/
<> 144:ef7eb2e8f9f7 681 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
<> 144:ef7eb2e8f9f7 682 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
<> 144:ef7eb2e8f9f7 686 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
<> 144:ef7eb2e8f9f7 687 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
<> 144:ef7eb2e8f9f7 688 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
<> 144:ef7eb2e8f9f7 691 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
<> 144:ef7eb2e8f9f7 692 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
<> 144:ef7eb2e8f9f7 693 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
<> 144:ef7eb2e8f9f7 694 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
<> 144:ef7eb2e8f9f7 695 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
<> 144:ef7eb2e8f9f7 696 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
<> 144:ef7eb2e8f9f7 697 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
<> 144:ef7eb2e8f9f7 698 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
<> 144:ef7eb2e8f9f7 701 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
<> 144:ef7eb2e8f9f7 704 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 #endif
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #endif /* __LPC8xx_H__ */