Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* File: startup_ARMCM4.S
<> 144:ef7eb2e8f9f7 2 * Purpose: startup file for Cortex-M4 devices. Should use with
<> 144:ef7eb2e8f9f7 3 * GCC for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 * Version: V1.4
<> 144:ef7eb2e8f9f7 5 * Date: 20 Dezember 2012
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 */
<> 144:ef7eb2e8f9f7 8 /* Copyright (c) 2011 - 2012 ARM LIMITED
<> 144:ef7eb2e8f9f7 9
<> 144:ef7eb2e8f9f7 10 All rights reserved.
<> 144:ef7eb2e8f9f7 11 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 12 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 14 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 17 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 19 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 20 specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 32 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 .syntax unified
<> 144:ef7eb2e8f9f7 37 .arch armv7-m
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 .section .stack
<> 144:ef7eb2e8f9f7 40 .align 3
<> 144:ef7eb2e8f9f7 41 .ifdef __STACK_SIZE
<> 144:ef7eb2e8f9f7 42 .equ Stack_Size, __STACK_SIZE
<> 144:ef7eb2e8f9f7 43 .else
<> 144:ef7eb2e8f9f7 44 .equ Stack_Size, 0x00000400
<> 144:ef7eb2e8f9f7 45 .endif
<> 144:ef7eb2e8f9f7 46 .globl __StackTop
<> 144:ef7eb2e8f9f7 47 .globl __StackLimit
<> 144:ef7eb2e8f9f7 48 __StackLimit:
<> 144:ef7eb2e8f9f7 49 .space Stack_Size
<> 144:ef7eb2e8f9f7 50 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 51 __StackTop:
<> 144:ef7eb2e8f9f7 52 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 .section .heap
<> 144:ef7eb2e8f9f7 55 .align 3
<> 144:ef7eb2e8f9f7 56 .ifdef __HEAP_SIZE
<> 144:ef7eb2e8f9f7 57 .equ Heap_Size, __HEAP_SIZE
<> 144:ef7eb2e8f9f7 58 .else
<> 144:ef7eb2e8f9f7 59 .equ Heap_Size, 0x00000C00
<> 144:ef7eb2e8f9f7 60 .endif
<> 144:ef7eb2e8f9f7 61 .globl __HeapBase
<> 144:ef7eb2e8f9f7 62 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 63 __HeapBase:
<> 144:ef7eb2e8f9f7 64 .if Heap_Size
<> 144:ef7eb2e8f9f7 65 .space Heap_Size
<> 144:ef7eb2e8f9f7 66 .endif
<> 144:ef7eb2e8f9f7 67 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 68 __HeapLimit:
<> 144:ef7eb2e8f9f7 69 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 .section .isr_vector
<> 144:ef7eb2e8f9f7 72 .align 2
<> 144:ef7eb2e8f9f7 73 .globl __isr_vector
<> 144:ef7eb2e8f9f7 74 __isr_vector:
<> 144:ef7eb2e8f9f7 75 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 76 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 77 .long NMI_Handler /* NMI Handler */
<> 144:ef7eb2e8f9f7 78 .long HardFault_Handler /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 79 .long MemManage_Handler /* MPU Fault Handler */
<> 144:ef7eb2e8f9f7 80 .long BusFault_Handler /* Bus Fault Handler */
<> 144:ef7eb2e8f9f7 81 .long UsageFault_Handler /* Usage Fault Handler */
<> 144:ef7eb2e8f9f7 82 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 83 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 84 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 85 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 86 .long SVC_Handler /* SVCall Handler */
<> 144:ef7eb2e8f9f7 87 .long DebugMon_Handler /* Debug Monitor Handler */
<> 144:ef7eb2e8f9f7 88 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 89 .long PendSV_Handler /* PendSV Handler */
<> 144:ef7eb2e8f9f7 90 .long SysTick_Handler /* SysTick Handler */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* External interrupts */
<> 144:ef7eb2e8f9f7 93 .long DAC_IRQHandler /* 0: DAC */
<> 144:ef7eb2e8f9f7 94 .long M0CORE_IRQHandler /* 1: M4-M0 communication */
<> 144:ef7eb2e8f9f7 95 .long DMA_IRQHandler /* 2: - */
<> 144:ef7eb2e8f9f7 96 .long 0 /* 3: Reserved */
<> 144:ef7eb2e8f9f7 97 .long FLASHEEPROM_IRQHandler/* 4: ORed flash bank A/B, EEPROM int */
<> 144:ef7eb2e8f9f7 98 .long ETHERNET_IRQHandler /* 5: Ethernet interrupt */
<> 144:ef7eb2e8f9f7 99 .long SDIO_IRQHandler /* 6: SD/MMC interrupt */
<> 144:ef7eb2e8f9f7 100 .long LCD_IRQHandler /* 7: - */
<> 144:ef7eb2e8f9f7 101 .long USB0_IRQHandler /* 8: OTG interrupt */
<> 144:ef7eb2e8f9f7 102 .long USB1_IRQHandler /* 9: - */
<> 144:ef7eb2e8f9f7 103 .long SCT_IRQHandler /* 10: SCT combined interrupt */
<> 144:ef7eb2e8f9f7 104 .long RITIMER_IRQHandler /* 11: - */
<> 144:ef7eb2e8f9f7 105 .long TIMER0_IRQHandler /* 12: - */
<> 144:ef7eb2e8f9f7 106 .long TIMER1_IRQHandler /* 13: - */
<> 144:ef7eb2e8f9f7 107 .long TIMER2_IRQHandler /* 14: - */
<> 144:ef7eb2e8f9f7 108 .long TIMER3_IRQHandler /* 15: - */
<> 144:ef7eb2e8f9f7 109 .long MCPWM_IRQHandler /* 16: Motor control PWM */
<> 144:ef7eb2e8f9f7 110 .long ADC0_IRQHandler /* 17: - */
<> 144:ef7eb2e8f9f7 111 .long I2C0_IRQHandler /* 18: - */
<> 144:ef7eb2e8f9f7 112 .long I2C1_IRQHandler /* 19: - */
<> 144:ef7eb2e8f9f7 113 .long SPI_IRQHandler /* 20: - */
<> 144:ef7eb2e8f9f7 114 .long ADC1_IRQHandler /* 21: - */
<> 144:ef7eb2e8f9f7 115 .long SSP0_IRQHandler /* 22: - */
<> 144:ef7eb2e8f9f7 116 .long SSP1_IRQHandler /* 23: - */
<> 144:ef7eb2e8f9f7 117 .long USART0_IRQHandler /* 24: - */
<> 144:ef7eb2e8f9f7 118 .long UART1_IRQHandler /* 25: Combined UART int w Modem int */
<> 144:ef7eb2e8f9f7 119 .long USART2_IRQHandler /* 26: - */
<> 144:ef7eb2e8f9f7 120 .long USART3_IRQHandler /* 27: combined USART int w IrDA int */
<> 144:ef7eb2e8f9f7 121 .long I2S0_IRQHandler /* 28: - */
<> 144:ef7eb2e8f9f7 122 .long I2S1_IRQHandler /* 29: - */
<> 144:ef7eb2e8f9f7 123 .long SPIFI_IRQHandler /* 30: - */
<> 144:ef7eb2e8f9f7 124 .long SGPIO_IRQHandler /* 31: - */
<> 144:ef7eb2e8f9f7 125 .long PIN_INT0_IRQHandler /* 32: GPIO pin interrupt 0 */
<> 144:ef7eb2e8f9f7 126 .long PIN_INT1_IRQHandler /* 33: GPIO pin interrupt 1 */
<> 144:ef7eb2e8f9f7 127 .long PIN_INT2_IRQHandler /* 34: GPIO pin interrupt 2 */
<> 144:ef7eb2e8f9f7 128 .long PIN_INT3_IRQHandler /* 35: GPIO pin interrupt 3 */
<> 144:ef7eb2e8f9f7 129 .long PIN_INT4_IRQHandler /* 36: GPIO pin interrupt 4 */
<> 144:ef7eb2e8f9f7 130 .long PIN_INT5_IRQHandler /* 37: GPIO pin interrupt 5 */
<> 144:ef7eb2e8f9f7 131 .long PIN_INT6_IRQHandler /* 38: GPIO pin interrupt 6 */
<> 144:ef7eb2e8f9f7 132 .long PIN_INT7_IRQHandler /* 39: GPIO pin interrupt 7 */
<> 144:ef7eb2e8f9f7 133 .long GINT0_IRQHandler /* 40: GPIO global interrupt 0 */
<> 144:ef7eb2e8f9f7 134 .long GINT1_IRQHandler /* 41: GPIO global interrupt 1 */
<> 144:ef7eb2e8f9f7 135 .long EVENTROUTER_IRQHandler/* 42: Event router interrupt */
<> 144:ef7eb2e8f9f7 136 .long C_CAN1_IRQHandler /* 43: - */
<> 144:ef7eb2e8f9f7 137 .long 0 /* 44: Reserved */
<> 144:ef7eb2e8f9f7 138 .long 0 /* 45: Reserved */
<> 144:ef7eb2e8f9f7 139 .long ATIMER_IRQHandler /* 46: Alarm timer interuupt */
<> 144:ef7eb2e8f9f7 140 .long RTC_IRQHandler /* 47: - */
<> 144:ef7eb2e8f9f7 141 .long 0 /* 48: Reserved */
<> 144:ef7eb2e8f9f7 142 .long WWDT_IRQHandler /* 49: - */
<> 144:ef7eb2e8f9f7 143 .long 0 /* 50: Reserved */
<> 144:ef7eb2e8f9f7 144 .long C_CAN0_IRQHandler /* 51: - */
<> 144:ef7eb2e8f9f7 145 .long QEI_IRQHandler /* 52: - */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 .text
<> 144:ef7eb2e8f9f7 150 .thumb
<> 144:ef7eb2e8f9f7 151 .thumb_func
<> 144:ef7eb2e8f9f7 152 .align 2
<> 144:ef7eb2e8f9f7 153 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 154 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 155 Reset_Handler:
<> 144:ef7eb2e8f9f7 156 /* Loop to copy data from read only memory to RAM. The ranges
<> 144:ef7eb2e8f9f7 157 * of copy from/to are specified by following symbols evaluated in
<> 144:ef7eb2e8f9f7 158 * linker script.
<> 144:ef7eb2e8f9f7 159 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 144:ef7eb2e8f9f7 160 * __data_start__/__data_end__: RAM address range that data should be
<> 144:ef7eb2e8f9f7 161 * copied to. Both must be aligned to 4 bytes boundary. */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 164 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 165 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 .LC0:
<> 144:ef7eb2e8f9f7 168 cmp r2, r3
<> 144:ef7eb2e8f9f7 169 ittt lt
<> 144:ef7eb2e8f9f7 170 ldrlt r0, [r1], #4
<> 144:ef7eb2e8f9f7 171 strlt r0, [r2], #4
<> 144:ef7eb2e8f9f7 172 blt .LC0
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 175 blx r0
<> 144:ef7eb2e8f9f7 176 ldr r0, =_start
<> 144:ef7eb2e8f9f7 177 bx r0
<> 144:ef7eb2e8f9f7 178 .pool
<> 144:ef7eb2e8f9f7 179 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 .text
<> 144:ef7eb2e8f9f7 182 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 183 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 184 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 185 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 186 .align 1
<> 144:ef7eb2e8f9f7 187 .thumb_func
<> 144:ef7eb2e8f9f7 188 .weak \handler_name
<> 144:ef7eb2e8f9f7 189 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 190 \handler_name :
<> 144:ef7eb2e8f9f7 191 b .
<> 144:ef7eb2e8f9f7 192 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 193 .endm
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 def_default_handler NMI_Handler
<> 144:ef7eb2e8f9f7 196 def_default_handler HardFault_Handler
<> 144:ef7eb2e8f9f7 197 def_default_handler MemManage_Handler
<> 144:ef7eb2e8f9f7 198 def_default_handler BusFault_Handler
<> 144:ef7eb2e8f9f7 199 def_default_handler UsageFault_Handler
<> 144:ef7eb2e8f9f7 200 def_default_handler SVC_Handler
<> 144:ef7eb2e8f9f7 201 def_default_handler DebugMon_Handler
<> 144:ef7eb2e8f9f7 202 def_default_handler PendSV_Handler
<> 144:ef7eb2e8f9f7 203 def_default_handler SysTick_Handler
<> 144:ef7eb2e8f9f7 204 def_default_handler Default_Handler
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 .macro def_irq_default_handler handler_name
<> 144:ef7eb2e8f9f7 207 .weak \handler_name
<> 144:ef7eb2e8f9f7 208 .set \handler_name, Default_Handler
<> 144:ef7eb2e8f9f7 209 .endm
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 def_irq_default_handler DAC_IRQHandler
<> 144:ef7eb2e8f9f7 212 def_irq_default_handler M0CORE_IRQHandler
<> 144:ef7eb2e8f9f7 213 def_irq_default_handler DMA_IRQHandler
<> 144:ef7eb2e8f9f7 214 def_irq_default_handler FLASHEEPROM_IRQHandler
<> 144:ef7eb2e8f9f7 215 def_irq_default_handler ETHERNET_IRQHandler
<> 144:ef7eb2e8f9f7 216 def_irq_default_handler SDIO_IRQHandler
<> 144:ef7eb2e8f9f7 217 def_irq_default_handler LCD_IRQHandler
<> 144:ef7eb2e8f9f7 218 def_irq_default_handler USB0_IRQHandler
<> 144:ef7eb2e8f9f7 219 def_irq_default_handler USB1_IRQHandler
<> 144:ef7eb2e8f9f7 220 def_irq_default_handler SCT_IRQHandler
<> 144:ef7eb2e8f9f7 221 def_irq_default_handler RITIMER_IRQHandler
<> 144:ef7eb2e8f9f7 222 def_irq_default_handler TIMER0_IRQHandler
<> 144:ef7eb2e8f9f7 223 def_irq_default_handler TIMER1_IRQHandler
<> 144:ef7eb2e8f9f7 224 def_irq_default_handler TIMER2_IRQHandler
<> 144:ef7eb2e8f9f7 225 def_irq_default_handler TIMER3_IRQHandler
<> 144:ef7eb2e8f9f7 226 def_irq_default_handler MCPWM_IRQHandler
<> 144:ef7eb2e8f9f7 227 def_irq_default_handler ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 228 def_irq_default_handler I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 229 def_irq_default_handler I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 230 def_irq_default_handler SPI_IRQHandler
<> 144:ef7eb2e8f9f7 231 def_irq_default_handler ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 232 def_irq_default_handler SSP0_IRQHandler
<> 144:ef7eb2e8f9f7 233 def_irq_default_handler SSP1_IRQHandler
<> 144:ef7eb2e8f9f7 234 def_irq_default_handler USART0_IRQHandler
<> 144:ef7eb2e8f9f7 235 def_irq_default_handler UART1_IRQHandler
<> 144:ef7eb2e8f9f7 236 def_irq_default_handler USART2_IRQHandler
<> 144:ef7eb2e8f9f7 237 def_irq_default_handler USART3_IRQHandler
<> 144:ef7eb2e8f9f7 238 def_irq_default_handler I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 239 def_irq_default_handler I2S1_IRQHandler
<> 144:ef7eb2e8f9f7 240 def_irq_default_handler SPIFI_IRQHandler
<> 144:ef7eb2e8f9f7 241 def_irq_default_handler SGPIO_IRQHandler
<> 144:ef7eb2e8f9f7 242 def_irq_default_handler PIN_INT0_IRQHandler
<> 144:ef7eb2e8f9f7 243 def_irq_default_handler PIN_INT1_IRQHandler
<> 144:ef7eb2e8f9f7 244 def_irq_default_handler PIN_INT2_IRQHandler
<> 144:ef7eb2e8f9f7 245 def_irq_default_handler PIN_INT3_IRQHandler
<> 144:ef7eb2e8f9f7 246 def_irq_default_handler PIN_INT4_IRQHandler
<> 144:ef7eb2e8f9f7 247 def_irq_default_handler PIN_INT5_IRQHandler
<> 144:ef7eb2e8f9f7 248 def_irq_default_handler PIN_INT6_IRQHandler
<> 144:ef7eb2e8f9f7 249 def_irq_default_handler PIN_INT7_IRQHandler
<> 144:ef7eb2e8f9f7 250 def_irq_default_handler GINT0_IRQHandler
<> 144:ef7eb2e8f9f7 251 def_irq_default_handler GINT1_IRQHandler
<> 144:ef7eb2e8f9f7 252 def_irq_default_handler EVENTROUTER_IRQHandler
<> 144:ef7eb2e8f9f7 253 def_irq_default_handler C_CAN1_IRQHandler
<> 144:ef7eb2e8f9f7 254 def_irq_default_handler ATIMER_IRQHandler
<> 144:ef7eb2e8f9f7 255 def_irq_default_handler RTC_IRQHandler
<> 144:ef7eb2e8f9f7 256 def_irq_default_handler WWDT_IRQHandler
<> 144:ef7eb2e8f9f7 257 def_irq_default_handler C_CAN0_IRQHandler
<> 144:ef7eb2e8f9f7 258 def_irq_default_handler QEI_IRQHandler
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 .end