added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (C) 2008-2015 ARM Limited. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! |
<> | 144:ef7eb2e8f9f7 | 5 | * based on core_cm3.h, V1.20 |
<> | 144:ef7eb2e8f9f7 | 6 | */ |
<> | 144:ef7eb2e8f9f7 | 7 | |
<> | 144:ef7eb2e8f9f7 | 8 | #ifndef __ARM7_CORE_H__ |
<> | 144:ef7eb2e8f9f7 | 9 | #define __ARM7_CORE_H__ |
<> | 144:ef7eb2e8f9f7 | 10 | |
<> | 144:ef7eb2e8f9f7 | 11 | #include "vector_defns.h" |
<> | 144:ef7eb2e8f9f7 | 12 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 13 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 14 | #endif |
<> | 144:ef7eb2e8f9f7 | 15 | //#include "cmsis_nvic.h" |
<> | 144:ef7eb2e8f9f7 | 16 | |
<> | 144:ef7eb2e8f9f7 | 17 | #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ |
<> | 144:ef7eb2e8f9f7 | 18 | #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ |
<> | 144:ef7eb2e8f9f7 | 19 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | #define __CORTEX_M (0x00) /*!< Cortex core */ |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | /** |
<> | 144:ef7eb2e8f9f7 | 24 | * Lint configuration \n |
<> | 144:ef7eb2e8f9f7 | 25 | * ----------------------- \n |
<> | 144:ef7eb2e8f9f7 | 26 | * |
<> | 144:ef7eb2e8f9f7 | 27 | * The following Lint messages will be suppressed and not shown: \n |
<> | 144:ef7eb2e8f9f7 | 28 | * \n |
<> | 144:ef7eb2e8f9f7 | 29 | * --- Error 10: --- \n |
<> | 144:ef7eb2e8f9f7 | 30 | * register uint32_t __regBasePri __asm("basepri"); \n |
<> | 144:ef7eb2e8f9f7 | 31 | * Error 10: Expecting ';' \n |
<> | 144:ef7eb2e8f9f7 | 32 | * \n |
<> | 144:ef7eb2e8f9f7 | 33 | * --- Error 530: --- \n |
<> | 144:ef7eb2e8f9f7 | 34 | * return(__regBasePri); \n |
<> | 144:ef7eb2e8f9f7 | 35 | * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n |
<> | 144:ef7eb2e8f9f7 | 36 | * \n |
<> | 144:ef7eb2e8f9f7 | 37 | * --- Error 550: --- \n |
<> | 144:ef7eb2e8f9f7 | 38 | * __regBasePri = (basePri & 0x1ff); \n |
<> | 144:ef7eb2e8f9f7 | 39 | * } \n |
<> | 144:ef7eb2e8f9f7 | 40 | * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n |
<> | 144:ef7eb2e8f9f7 | 41 | * \n |
<> | 144:ef7eb2e8f9f7 | 42 | * --- Error 754: --- \n |
<> | 144:ef7eb2e8f9f7 | 43 | * uint32_t RESERVED0[24]; \n |
<> | 144:ef7eb2e8f9f7 | 44 | * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n |
<> | 144:ef7eb2e8f9f7 | 45 | * \n |
<> | 144:ef7eb2e8f9f7 | 46 | * --- Error 750: --- \n |
<> | 144:ef7eb2e8f9f7 | 47 | * #define __CM3_CORE_H__ \n |
<> | 144:ef7eb2e8f9f7 | 48 | * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n |
<> | 144:ef7eb2e8f9f7 | 49 | * \n |
<> | 144:ef7eb2e8f9f7 | 50 | * --- Error 528: --- \n |
<> | 144:ef7eb2e8f9f7 | 51 | * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n |
<> | 144:ef7eb2e8f9f7 | 52 | * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n |
<> | 144:ef7eb2e8f9f7 | 53 | * \n |
<> | 144:ef7eb2e8f9f7 | 54 | * --- Error 751: --- \n |
<> | 144:ef7eb2e8f9f7 | 55 | * } InterruptType_Type; \n |
<> | 144:ef7eb2e8f9f7 | 56 | * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n |
<> | 144:ef7eb2e8f9f7 | 57 | * \n |
<> | 144:ef7eb2e8f9f7 | 58 | * \n |
<> | 144:ef7eb2e8f9f7 | 59 | * Note: To re-enable a Message, insert a space before 'lint' * \n |
<> | 144:ef7eb2e8f9f7 | 60 | * |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | /*lint -save */ |
<> | 144:ef7eb2e8f9f7 | 64 | /*lint -e10 */ |
<> | 144:ef7eb2e8f9f7 | 65 | /*lint -e530 */ |
<> | 144:ef7eb2e8f9f7 | 66 | /*lint -e550 */ |
<> | 144:ef7eb2e8f9f7 | 67 | /*lint -e754 */ |
<> | 144:ef7eb2e8f9f7 | 68 | /*lint -e750 */ |
<> | 144:ef7eb2e8f9f7 | 69 | /*lint -e528 */ |
<> | 144:ef7eb2e8f9f7 | 70 | /*lint -e751 */ |
<> | 144:ef7eb2e8f9f7 | 71 | |
<> | 144:ef7eb2e8f9f7 | 72 | #include <stdint.h> /* Include standard types */ |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | #if defined ( __CC_ARM ) |
<> | 144:ef7eb2e8f9f7 | 75 | /** |
<> | 144:ef7eb2e8f9f7 | 76 | * @brief Return the Main Stack Pointer (current ARM7 stack) |
<> | 144:ef7eb2e8f9f7 | 77 | * |
<> | 144:ef7eb2e8f9f7 | 78 | * @param none |
<> | 144:ef7eb2e8f9f7 | 79 | * @return uint32_t Main Stack Pointer |
<> | 144:ef7eb2e8f9f7 | 80 | * |
<> | 144:ef7eb2e8f9f7 | 81 | * Return the current value of the MSP (main stack pointer) |
<> | 144:ef7eb2e8f9f7 | 82 | * Cortex processor register |
<> | 144:ef7eb2e8f9f7 | 83 | */ |
<> | 144:ef7eb2e8f9f7 | 84 | extern uint32_t __get_MSP(void); |
<> | 144:ef7eb2e8f9f7 | 85 | #endif |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | #if defined (__ICCARM__) |
<> | 144:ef7eb2e8f9f7 | 89 | #include <intrinsics.h> /* IAR Intrinsics */ |
<> | 144:ef7eb2e8f9f7 | 90 | #endif |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | #ifndef __NVIC_PRIO_BITS |
<> | 144:ef7eb2e8f9f7 | 94 | #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ |
<> | 144:ef7eb2e8f9f7 | 95 | #endif |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 98 | { |
<> | 144:ef7eb2e8f9f7 | 99 | uint32_t IRQStatus; |
<> | 144:ef7eb2e8f9f7 | 100 | uint32_t FIQStatus; |
<> | 144:ef7eb2e8f9f7 | 101 | uint32_t RawIntr; |
<> | 144:ef7eb2e8f9f7 | 102 | uint32_t IntSelect; |
<> | 144:ef7eb2e8f9f7 | 103 | uint32_t IntEnable; |
<> | 144:ef7eb2e8f9f7 | 104 | uint32_t IntEnClr; |
<> | 144:ef7eb2e8f9f7 | 105 | uint32_t SoftInt; |
<> | 144:ef7eb2e8f9f7 | 106 | uint32_t SoftIntClr; |
<> | 144:ef7eb2e8f9f7 | 107 | uint32_t Protection; |
<> | 144:ef7eb2e8f9f7 | 108 | uint32_t SWPriorityMask; |
<> | 144:ef7eb2e8f9f7 | 109 | uint32_t RESERVED0[54]; |
<> | 144:ef7eb2e8f9f7 | 110 | uint32_t VectAddr[32]; |
<> | 144:ef7eb2e8f9f7 | 111 | uint32_t RESERVED1[32]; |
<> | 144:ef7eb2e8f9f7 | 112 | uint32_t VectPriority[32]; |
<> | 144:ef7eb2e8f9f7 | 113 | uint32_t RESERVED2[800]; |
<> | 144:ef7eb2e8f9f7 | 114 | uint32_t Address; |
<> | 144:ef7eb2e8f9f7 | 115 | } NVIC_TypeDef; |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | #define NVIC_BASE (0xFFFFF000) |
<> | 144:ef7eb2e8f9f7 | 118 | #define NVIC (( NVIC_TypeDef *) NVIC_BASE) |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | /** |
<> | 144:ef7eb2e8f9f7 | 123 | * IO definitions |
<> | 144:ef7eb2e8f9f7 | 124 | * |
<> | 144:ef7eb2e8f9f7 | 125 | * define access restrictions to peripheral registers |
<> | 144:ef7eb2e8f9f7 | 126 | */ |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 129 | #define __I volatile /*!< defines 'read only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 130 | #else |
<> | 144:ef7eb2e8f9f7 | 131 | #define __I volatile const /*!< defines 'read only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 132 | #endif |
<> | 144:ef7eb2e8f9f7 | 133 | #define __O volatile /*!< defines 'write only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 134 | #define __IO volatile /*!< defines 'read / write' permissions */ |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | #if defined ( __CC_ARM ) |
<> | 144:ef7eb2e8f9f7 | 141 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
<> | 144:ef7eb2e8f9f7 | 142 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | #elif defined ( __ICCARM__ ) |
<> | 144:ef7eb2e8f9f7 | 145 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
<> | 144:ef7eb2e8f9f7 | 146 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | #elif defined ( __GNUC__ ) |
<> | 144:ef7eb2e8f9f7 | 149 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
<> | 144:ef7eb2e8f9f7 | 150 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | #elif defined ( __TASKING__ ) |
<> | 144:ef7eb2e8f9f7 | 153 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
<> | 144:ef7eb2e8f9f7 | 154 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
<> | 144:ef7eb2e8f9f7 | 155 | |
<> | 144:ef7eb2e8f9f7 | 156 | #endif |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | /* ################### Compiler specific Intrinsics ########################### */ |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
<> | 144:ef7eb2e8f9f7 | 162 | /* ARM armcc specific functions */ |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | #define __enable_fault_irq __enable_fiq |
<> | 144:ef7eb2e8f9f7 | 165 | #define __disable_fault_irq __disable_fiq |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | #define __NOP __nop |
<> | 144:ef7eb2e8f9f7 | 168 | //#define __WFI __wfi |
<> | 144:ef7eb2e8f9f7 | 169 | //#define __WFE __wfe |
<> | 144:ef7eb2e8f9f7 | 170 | //#define __SEV __sev |
<> | 144:ef7eb2e8f9f7 | 171 | //#define __ISB() __isb(0) |
<> | 144:ef7eb2e8f9f7 | 172 | //#define __DSB() __dsb(0) |
<> | 144:ef7eb2e8f9f7 | 173 | //#define __DMB() __dmb(0) |
<> | 144:ef7eb2e8f9f7 | 174 | //#define __REV __rev |
<> | 144:ef7eb2e8f9f7 | 175 | //#define __RBIT __rbit |
<> | 144:ef7eb2e8f9f7 | 176 | #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) |
<> | 144:ef7eb2e8f9f7 | 177 | #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) |
<> | 144:ef7eb2e8f9f7 | 178 | #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) |
<> | 144:ef7eb2e8f9f7 | 179 | #define __STREXB(value, ptr) __strex(value, ptr) |
<> | 144:ef7eb2e8f9f7 | 180 | #define __STREXH(value, ptr) __strex(value, ptr) |
<> | 144:ef7eb2e8f9f7 | 181 | #define __STREXW(value, ptr) __strex(value, ptr) |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \ |
<> | 144:ef7eb2e8f9f7 | 184 | LPC_VIC->IntEnClr = 0xffffffff |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ |
<> | 144:ef7eb2e8f9f7 | 191 | #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ |
<> | 144:ef7eb2e8f9f7 | 192 | #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | static __INLINE void __enable_irq() { |
<> | 144:ef7eb2e8f9f7 | 197 | unsigned long temp; |
<> | 144:ef7eb2e8f9f7 | 198 | __asm__ __volatile__("mrs %0, cpsr\n" |
<> | 144:ef7eb2e8f9f7 | 199 | "bic %0, %0, #0x80\n" |
<> | 144:ef7eb2e8f9f7 | 200 | "msr cpsr_c, %0" |
<> | 144:ef7eb2e8f9f7 | 201 | : "=r" (temp) |
<> | 144:ef7eb2e8f9f7 | 202 | : |
<> | 144:ef7eb2e8f9f7 | 203 | : "memory"); |
<> | 144:ef7eb2e8f9f7 | 204 | } |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | static __INLINE uint32_t __disable_irq() { |
<> | 144:ef7eb2e8f9f7 | 207 | unsigned long old,temp; |
<> | 144:ef7eb2e8f9f7 | 208 | __asm__ __volatile__("mrs %0, cpsr\n" |
<> | 144:ef7eb2e8f9f7 | 209 | "orr %1, %0, #0xc0\n" |
<> | 144:ef7eb2e8f9f7 | 210 | "msr cpsr_c, %1" |
<> | 144:ef7eb2e8f9f7 | 211 | : "=r" (old), "=r" (temp) |
<> | 144:ef7eb2e8f9f7 | 212 | : |
<> | 144:ef7eb2e8f9f7 | 213 | : "memory"); |
<> | 144:ef7eb2e8f9f7 | 214 | return (old & 0x80) == 0; |
<> | 144:ef7eb2e8f9f7 | 215 | } |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | static __INLINE void __NOP() { __ASM volatile ("nop"); } |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | /** \brief Get Control Bits of Status Register |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | This function returns the content of the Control Bits from the Program Status Register. |
<> | 144:ef7eb2e8f9f7 | 222 | |
<> | 144:ef7eb2e8f9f7 | 223 | \return Control Bits value |
<> | 144:ef7eb2e8f9f7 | 224 | */ |
<> | 144:ef7eb2e8f9f7 | 225 | __attribute__( ( always_inline ) ) static inline uint32_t __get_CONTROL(void) |
<> | 144:ef7eb2e8f9f7 | 226 | { |
<> | 144:ef7eb2e8f9f7 | 227 | uint32_t result; |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | __asm__ __volatile__ ("MRS %0, CPSR \n" |
<> | 144:ef7eb2e8f9f7 | 230 | "AND %0,%0,#31" : "=r" (result) ); |
<> | 144:ef7eb2e8f9f7 | 231 | return(result); |
<> | 144:ef7eb2e8f9f7 | 232 | } |
<> | 144:ef7eb2e8f9f7 | 233 | #define MODE_USER 0x10 |
<> | 144:ef7eb2e8f9f7 | 234 | #define MODE_FIQ 0x11 |
<> | 144:ef7eb2e8f9f7 | 235 | #define MODE_IRQ 0x12 |
<> | 144:ef7eb2e8f9f7 | 236 | #define MODE_SUPERVISOR 0x13 |
<> | 144:ef7eb2e8f9f7 | 237 | #define MODE_ABORT 0x17 |
<> | 144:ef7eb2e8f9f7 | 238 | #define MODE_UNDEFINED 0x1B |
<> | 144:ef7eb2e8f9f7 | 239 | #define MODE_SYSTEM 0x1F |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
<> | 144:ef7eb2e8f9f7 | 243 | /* TASKING carm specific functions */ |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | /* |
<> | 144:ef7eb2e8f9f7 | 246 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
<> | 144:ef7eb2e8f9f7 | 247 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
<> | 144:ef7eb2e8f9f7 | 248 | * Including the CMSIS ones. |
<> | 144:ef7eb2e8f9f7 | 249 | */ |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | #endif |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | /** |
<> | 144:ef7eb2e8f9f7 | 255 | * @brief Enable Interrupt in NVIC Interrupt Controller |
<> | 144:ef7eb2e8f9f7 | 256 | * |
<> | 144:ef7eb2e8f9f7 | 257 | * @param IRQn_Type IRQn specifies the interrupt number |
<> | 144:ef7eb2e8f9f7 | 258 | * @return none |
<> | 144:ef7eb2e8f9f7 | 259 | * |
<> | 144:ef7eb2e8f9f7 | 260 | * Enable a device specific interupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 261 | * The interrupt number cannot be a negative value. |
<> | 144:ef7eb2e8f9f7 | 262 | */ |
<> | 144:ef7eb2e8f9f7 | 263 | static __INLINE void NVIC_EnableIRQ(uint32_t IRQn) |
<> | 144:ef7eb2e8f9f7 | 264 | { |
<> | 144:ef7eb2e8f9f7 | 265 | NVIC->IntEnable = 1 << (uint32_t)IRQn; |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | /** |
<> | 144:ef7eb2e8f9f7 | 270 | * @brief Disable the interrupt line for external interrupt specified |
<> | 144:ef7eb2e8f9f7 | 271 | * |
<> | 144:ef7eb2e8f9f7 | 272 | * @param IRQn_Type IRQn is the positive number of the external interrupt |
<> | 144:ef7eb2e8f9f7 | 273 | * @return none |
<> | 144:ef7eb2e8f9f7 | 274 | * |
<> | 144:ef7eb2e8f9f7 | 275 | * Disable a device specific interupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 276 | * The interrupt number cannot be a negative value. |
<> | 144:ef7eb2e8f9f7 | 277 | */ |
<> | 144:ef7eb2e8f9f7 | 278 | static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) |
<> | 144:ef7eb2e8f9f7 | 279 | { |
<> | 144:ef7eb2e8f9f7 | 280 | NVIC->IntEnClr = 1 << (uint32_t)IRQn; |
<> | 144:ef7eb2e8f9f7 | 281 | } |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | /** |
<> | 144:ef7eb2e8f9f7 | 284 | * @brief Pend Interrupt in NVIC Interrupt Controller |
<> | 144:ef7eb2e8f9f7 | 285 | * |
<> | 144:ef7eb2e8f9f7 | 286 | * @param IRQn_Type IRQn specifies the interrupt number |
<> | 144:ef7eb2e8f9f7 | 287 | * @return none |
<> | 144:ef7eb2e8f9f7 | 288 | * |
<> | 144:ef7eb2e8f9f7 | 289 | * Force software a device specific interupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 290 | * The interrupt number cannot be a negative value. |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | static __INLINE void NVIC_PendIRQ(uint32_t IRQn) |
<> | 144:ef7eb2e8f9f7 | 293 | { |
<> | 144:ef7eb2e8f9f7 | 294 | NVIC->SoftInt = 1 << (uint32_t)IRQn; |
<> | 144:ef7eb2e8f9f7 | 295 | } |
<> | 144:ef7eb2e8f9f7 | 296 | |
<> | 144:ef7eb2e8f9f7 | 297 | |
<> | 144:ef7eb2e8f9f7 | 298 | /** |
<> | 144:ef7eb2e8f9f7 | 299 | * @brief Unpend the interrupt in NVIC Interrupt Controller |
<> | 144:ef7eb2e8f9f7 | 300 | * |
<> | 144:ef7eb2e8f9f7 | 301 | * @param IRQn_Type IRQn is the positive number of the external interrupt |
<> | 144:ef7eb2e8f9f7 | 302 | * @return none |
<> | 144:ef7eb2e8f9f7 | 303 | * |
<> | 144:ef7eb2e8f9f7 | 304 | * Clear software device specific interupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 305 | * The interrupt number cannot be a negative value. |
<> | 144:ef7eb2e8f9f7 | 306 | */ |
<> | 144:ef7eb2e8f9f7 | 307 | static __INLINE void NVIC_UnpendIRQ(uint32_t IRQn) |
<> | 144:ef7eb2e8f9f7 | 308 | { |
<> | 144:ef7eb2e8f9f7 | 309 | NVIC->SoftIntClr = 1 << (uint32_t)IRQn; |
<> | 144:ef7eb2e8f9f7 | 310 | } |
<> | 144:ef7eb2e8f9f7 | 311 | |
<> | 144:ef7eb2e8f9f7 | 312 | /** |
<> | 144:ef7eb2e8f9f7 | 313 | * @brief Is IRQ pending |
<> | 144:ef7eb2e8f9f7 | 314 | * |
<> | 144:ef7eb2e8f9f7 | 315 | * @param IRQn_Type IRQn is the positive number of the external interrupt |
<> | 144:ef7eb2e8f9f7 | 316 | * @return 0 if IRQ is not pending |
<> | 144:ef7eb2e8f9f7 | 317 | * 1 if IRQ is pending |
<> | 144:ef7eb2e8f9f7 | 318 | * |
<> | 144:ef7eb2e8f9f7 | 319 | * Returns software device specific interupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 320 | * The interrupt number cannot be a negative value. |
<> | 144:ef7eb2e8f9f7 | 321 | */ |
<> | 144:ef7eb2e8f9f7 | 322 | static __INLINE uint32_t NVIC_Pending(uint32_t IRQn) |
<> | 144:ef7eb2e8f9f7 | 323 | { |
<> | 144:ef7eb2e8f9f7 | 324 | return (NVIC->SoftInt & (1 << (uint32_t)IRQn)) != 0; |
<> | 144:ef7eb2e8f9f7 | 325 | } |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | static __INLINE uint32_t __get_IPSR(void) |
<> | 144:ef7eb2e8f9f7 | 328 | { |
<> | 144:ef7eb2e8f9f7 | 329 | unsigned i; |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | for(i = 0; i < 32; i ++) |
<> | 144:ef7eb2e8f9f7 | 332 | if(NVIC->Address == NVIC->VectAddr[i]) |
<> | 144:ef7eb2e8f9f7 | 333 | return i; |
<> | 144:ef7eb2e8f9f7 | 334 | return 1; // 1 is an invalid entry in the interrupt table on LPC2460 |
<> | 144:ef7eb2e8f9f7 | 335 | } |
<> | 144:ef7eb2e8f9f7 | 336 | |
<> | 144:ef7eb2e8f9f7 | 337 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 338 | } |
<> | 144:ef7eb2e8f9f7 | 339 | #endif |
<> | 144:ef7eb2e8f9f7 | 340 | |
<> | 144:ef7eb2e8f9f7 | 341 | #endif /* __ARM7_CORE_H__ */ |
<> | 144:ef7eb2e8f9f7 | 342 | |
<> | 144:ef7eb2e8f9f7 | 343 | /*lint -restore */ |