mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

Users » JojoS » Code » mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:: JojoS
Date:: Sat Sep 10 15:32:04 2016 +0000
Revision:: 147:ba84b7dc41a7
Parent:: 144:ef7eb2e8f9f7

added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1
<>	144:ef7eb2e8f9f7	2	/**************************************************************************************************//
<>	144:ef7eb2e8f9f7	3	* @file LPC15xx.h
<>	144:ef7eb2e8f9f7	4	*
<>	144:ef7eb2e8f9f7	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
<>	144:ef7eb2e8f9f7	6	* LPC15xx from .
<>	144:ef7eb2e8f9f7	7	*
<>	144:ef7eb2e8f9f7	8	* @version V0.3
<>	144:ef7eb2e8f9f7	9	* @date 17. July 2013
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* @note Generated with SVDConv V2.80
<>	144:ef7eb2e8f9f7	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
<>	144:ef7eb2e8f9f7	13	*
<>	144:ef7eb2e8f9f7	14	* modified by Keil
<>	144:ef7eb2e8f9f7	15	* modified by ytsuboi
<>	144:ef7eb2e8f9f7	16	*******************************************************************************************************/
<>	144:ef7eb2e8f9f7	17
<>	144:ef7eb2e8f9f7	18
<>	144:ef7eb2e8f9f7	19
<>	144:ef7eb2e8f9f7	20	/** @addtogroup (null)
<>	144:ef7eb2e8f9f7	21	* @{
<>	144:ef7eb2e8f9f7	22	*/
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	/** @addtogroup LPC15xx
<>	144:ef7eb2e8f9f7	25	* @{
<>	144:ef7eb2e8f9f7	26	*/
<>	144:ef7eb2e8f9f7	27
<>	144:ef7eb2e8f9f7	28	#ifndef LPC15XX_H
<>	144:ef7eb2e8f9f7	29	#define LPC15XX_H
<>	144:ef7eb2e8f9f7	30
<>	144:ef7eb2e8f9f7	31	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	32	extern "C" {
<>	144:ef7eb2e8f9f7	33	#endif
<>	144:ef7eb2e8f9f7	34
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* ------------------------- Interrupt Number Definition ------------------------ */
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	typedef enum {
<>	144:ef7eb2e8f9f7	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
<>	144:ef7eb2e8f9f7	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
<>	144:ef7eb2e8f9f7	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
<>	144:ef7eb2e8f9f7	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
<>	144:ef7eb2e8f9f7	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
<>	144:ef7eb2e8f9f7	44	and No Match */
<>	144:ef7eb2e8f9f7	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
<>	144:ef7eb2e8f9f7	46	related Fault */
<>	144:ef7eb2e8f9f7	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
<>	144:ef7eb2e8f9f7	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
<>	144:ef7eb2e8f9f7	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
<>	144:ef7eb2e8f9f7	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
<>	144:ef7eb2e8f9f7	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
<>	144:ef7eb2e8f9f7	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
<>	144:ef7eb2e8f9f7	53	WDT_IRQn = 0, /!< 0 WDT /
<>	144:ef7eb2e8f9f7	54	BOD_IRQn = 1, /!< 1 BOD /
<>	144:ef7eb2e8f9f7	55	FLASH_IRQn = 2, /!< 2 FLASH /
<>	144:ef7eb2e8f9f7	56	EE_IRQn = 3, /!< 3 EE /
<>	144:ef7eb2e8f9f7	57	DMA_IRQn = 4, /!< 4 DMA /
<>	144:ef7eb2e8f9f7	58	GINT0_IRQn = 5, /!< 5 GINT0 /
<>	144:ef7eb2e8f9f7	59	GINT1_IRQn = 6, /!< 6 GINT1 /
<>	144:ef7eb2e8f9f7	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
<>	144:ef7eb2e8f9f7	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
<>	144:ef7eb2e8f9f7	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
<>	144:ef7eb2e8f9f7	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
<>	144:ef7eb2e8f9f7	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
<>	144:ef7eb2e8f9f7	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
<>	144:ef7eb2e8f9f7	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
<>	144:ef7eb2e8f9f7	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
<>	144:ef7eb2e8f9f7	68	RIT_IRQn = 15, /!< 15 RIT /
<>	144:ef7eb2e8f9f7	69	SCT0_IRQn = 16, /!< 16 SCT0 /
<>	144:ef7eb2e8f9f7	70	SCT1_IRQn = 17, /!< 17 SCT1 /
<>	144:ef7eb2e8f9f7	71	SCT2_IRQn = 18, /!< 18 SCT2 /
<>	144:ef7eb2e8f9f7	72	SCT3_IRQn = 19, /!< 19 SCT3 /
<>	144:ef7eb2e8f9f7	73	MRT_IRQn = 20, /!< 20 MRT /
<>	144:ef7eb2e8f9f7	74	UART0_IRQn = 21, /!< 21 UART0 /
<>	144:ef7eb2e8f9f7	75	UART1_IRQn = 22, /!< 22 UART1 /
<>	144:ef7eb2e8f9f7	76	UART2_IRQn = 23, /!< 23 UART2 /
<>	144:ef7eb2e8f9f7	77	I2C0_IRQn = 24, /!< 24 I2C0 /
<>	144:ef7eb2e8f9f7	78	SPI0_IRQn = 25, /!< 25 SPI0 /
<>	144:ef7eb2e8f9f7	79	SPI1_IRQn = 26, /!< 26 SPI1 /
<>	144:ef7eb2e8f9f7	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
<>	144:ef7eb2e8f9f7	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
<>	144:ef7eb2e8f9f7	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
<>	144:ef7eb2e8f9f7	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
<>	144:ef7eb2e8f9f7	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
<>	144:ef7eb2e8f9f7	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
<>	144:ef7eb2e8f9f7	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
<>	144:ef7eb2e8f9f7	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
<>	144:ef7eb2e8f9f7	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
<>	144:ef7eb2e8f9f7	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
<>	144:ef7eb2e8f9f7	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
<>	144:ef7eb2e8f9f7	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
<>	144:ef7eb2e8f9f7	92	DAC_IRQn = 39, /!< 39 DAC /
<>	144:ef7eb2e8f9f7	93	CMP0_IRQn = 40, /!< 40 CMP0 /
<>	144:ef7eb2e8f9f7	94	CMP1_IRQn = 41, /!< 41 CMP1 /
<>	144:ef7eb2e8f9f7	95	CMP2_IRQn = 42, /!< 42 CMP2 /
<>	144:ef7eb2e8f9f7	96	CMP3_IRQn = 43, /!< 43 CMP3 /
<>	144:ef7eb2e8f9f7	97	QEI_IRQn = 44, /!< 44 QEI /
<>	144:ef7eb2e8f9f7	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
<>	144:ef7eb2e8f9f7	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
<>	144:ef7eb2e8f9f7	100	} IRQn_Type;
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	/** @addtogroup Configuration_of_CMSIS
<>	144:ef7eb2e8f9f7	104	* @{
<>	144:ef7eb2e8f9f7	105	*/
<>	144:ef7eb2e8f9f7	106
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	109	/* ================ Processor and Core Peripheral Section ================ */
<>	144:ef7eb2e8f9f7	110	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
<>	144:ef7eb2e8f9f7	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
<>	144:ef7eb2e8f9f7	114	#define __MPU_PRESENT 0 /!< MPU present or not /
<>	144:ef7eb2e8f9f7	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
<>	144:ef7eb2e8f9f7	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
<>	144:ef7eb2e8f9f7	117	/** @} / / End of group Configuration_of_CMSIS */
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
<>	144:ef7eb2e8f9f7	120	#include "system_LPC15xx.h" /!< LPC15xx System /
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	124	/* ================ Device Specific Peripheral Section ================ */
<>	144:ef7eb2e8f9f7	125	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	126
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	/** @addtogroup Device_Peripheral_Registers
<>	144:ef7eb2e8f9f7	129	* @{
<>	144:ef7eb2e8f9f7	130	*/
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	/* ------------------- Start of section using anonymous unions ------------------ */
<>	144:ef7eb2e8f9f7	134	#if defined(__CC_ARM)
<>	144:ef7eb2e8f9f7	135	#pragma push
<>	144:ef7eb2e8f9f7	136	#pragma anon_unions
<>	144:ef7eb2e8f9f7	137	#elif defined(__ICCARM__)
<>	144:ef7eb2e8f9f7	138	#pragma language=extended
<>	144:ef7eb2e8f9f7	139	#elif defined(__GNUC__)
<>	144:ef7eb2e8f9f7	140	/* anonymous unions are enabled by default */
<>	144:ef7eb2e8f9f7	141	#elif defined(__TMS470__)
<>	144:ef7eb2e8f9f7	142	/* anonymous unions are enabled by default */
<>	144:ef7eb2e8f9f7	143	#elif defined(__TASKING__)
<>	144:ef7eb2e8f9f7	144	#pragma warning 586
<>	144:ef7eb2e8f9f7	145	#else
<>	144:ef7eb2e8f9f7	146	#warning Not supported compiler type
<>	144:ef7eb2e8f9f7	147	#endif
<>	144:ef7eb2e8f9f7	148
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150
<>	144:ef7eb2e8f9f7	151	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	152	/* ================ GPIO_PORT ================ */
<>	144:ef7eb2e8f9f7	153	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/**
<>	144:ef7eb2e8f9f7	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
<>	144:ef7eb2e8f9f7	158	*/
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	typedef struct { /!< GPIO_PORT Structure /
<>	144:ef7eb2e8f9f7	161	__IO uint8_t B[76]; /!< Byte pin registers /
<>	144:ef7eb2e8f9f7	162	__I uint32_t RESERVED0[1005];
<>	144:ef7eb2e8f9f7	163	__IO uint32_t W[76]; /!< Word pin registers /
<>	144:ef7eb2e8f9f7	164	__I uint32_t RESERVED1[948];
<>	144:ef7eb2e8f9f7	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
<>	144:ef7eb2e8f9f7	166	__I uint32_t RESERVED2[29];
<>	144:ef7eb2e8f9f7	167	__IO uint32_t MASK[3]; /!< Port Mask register /
<>	144:ef7eb2e8f9f7	168	__I uint32_t RESERVED3[29];
<>	144:ef7eb2e8f9f7	169	__IO uint32_t PIN[3]; /!< Port pin register /
<>	144:ef7eb2e8f9f7	170	__I uint32_t RESERVED4[29];
<>	144:ef7eb2e8f9f7	171	__IO uint32_t MPIN[3]; /!< Masked port register /
<>	144:ef7eb2e8f9f7	172	__I uint32_t RESERVED5[29];
<>	144:ef7eb2e8f9f7	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
<>	144:ef7eb2e8f9f7	174	__I uint32_t RESERVED6[29];
<>	144:ef7eb2e8f9f7	175	__O uint32_t CLR[3]; /!< Clear port /
<>	144:ef7eb2e8f9f7	176	__I uint32_t RESERVED7[29];
<>	144:ef7eb2e8f9f7	177	__O uint32_t NOT[3]; /!< Toggle port /
<>	144:ef7eb2e8f9f7	178	} LPC_GPIO_PORT_Type;
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	182	/* ================ DMA ================ */
<>	144:ef7eb2e8f9f7	183	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	/**
<>	144:ef7eb2e8f9f7	187	* @brief DMA controller (DMA)
<>	144:ef7eb2e8f9f7	188	*/
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	typedef struct { /!< DMA Structure /
<>	144:ef7eb2e8f9f7	191	__IO uint32_t CTRL; /!< DMA control. /
<>	144:ef7eb2e8f9f7	192	__I uint32_t INTSTAT; /!< Interrupt status. /
<>	144:ef7eb2e8f9f7	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
<>	144:ef7eb2e8f9f7	194	__I uint32_t RESERVED0[5];
<>	144:ef7eb2e8f9f7	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
<>	144:ef7eb2e8f9f7	196	__I uint32_t RESERVED1;
<>	144:ef7eb2e8f9f7	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
<>	144:ef7eb2e8f9f7	198	__I uint32_t RESERVED2;
<>	144:ef7eb2e8f9f7	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
<>	144:ef7eb2e8f9f7	200	__I uint32_t RESERVED3;
<>	144:ef7eb2e8f9f7	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
<>	144:ef7eb2e8f9f7	202	__I uint32_t RESERVED4;
<>	144:ef7eb2e8f9f7	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
<>	144:ef7eb2e8f9f7	204	__I uint32_t RESERVED5;
<>	144:ef7eb2e8f9f7	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
<>	144:ef7eb2e8f9f7	206	__I uint32_t RESERVED6;
<>	144:ef7eb2e8f9f7	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
<>	144:ef7eb2e8f9f7	208	__I uint32_t RESERVED7;
<>	144:ef7eb2e8f9f7	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
<>	144:ef7eb2e8f9f7	210	__I uint32_t RESERVED8;
<>	144:ef7eb2e8f9f7	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
<>	144:ef7eb2e8f9f7	212	__I uint32_t RESERVED9;
<>	144:ef7eb2e8f9f7	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
<>	144:ef7eb2e8f9f7	214	__I uint32_t RESERVED10;
<>	144:ef7eb2e8f9f7	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
<>	144:ef7eb2e8f9f7	216	__I uint32_t RESERVED11;
<>	144:ef7eb2e8f9f7	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
<>	144:ef7eb2e8f9f7	218	__I uint32_t RESERVED12[225];
<>	144:ef7eb2e8f9f7	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	222	__I uint32_t RESERVED13;
<>	144:ef7eb2e8f9f7	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	226	__I uint32_t RESERVED14;
<>	144:ef7eb2e8f9f7	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	230	__I uint32_t RESERVED15;
<>	144:ef7eb2e8f9f7	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	234	__I uint32_t RESERVED16;
<>	144:ef7eb2e8f9f7	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	238	__I uint32_t RESERVED17;
<>	144:ef7eb2e8f9f7	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	242	__I uint32_t RESERVED18;
<>	144:ef7eb2e8f9f7	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	246	__I uint32_t RESERVED19;
<>	144:ef7eb2e8f9f7	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	250	__I uint32_t RESERVED20;
<>	144:ef7eb2e8f9f7	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	254	__I uint32_t RESERVED21;
<>	144:ef7eb2e8f9f7	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	258	__I uint32_t RESERVED22;
<>	144:ef7eb2e8f9f7	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	262	__I uint32_t RESERVED23;
<>	144:ef7eb2e8f9f7	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	266	__I uint32_t RESERVED24;
<>	144:ef7eb2e8f9f7	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	270	__I uint32_t RESERVED25;
<>	144:ef7eb2e8f9f7	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	274	__I uint32_t RESERVED26;
<>	144:ef7eb2e8f9f7	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	278	__I uint32_t RESERVED27;
<>	144:ef7eb2e8f9f7	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	282	__I uint32_t RESERVED28;
<>	144:ef7eb2e8f9f7	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	286	__I uint32_t RESERVED29;
<>	144:ef7eb2e8f9f7	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
<>	144:ef7eb2e8f9f7	290	} LPC_DMA_Type;
<>	144:ef7eb2e8f9f7	291
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	294	/* ================ USB ================ */
<>	144:ef7eb2e8f9f7	295	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	/**
<>	144:ef7eb2e8f9f7	299	* @brief USB device controller (USB)
<>	144:ef7eb2e8f9f7	300	*/
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	typedef struct { /!< USB Structure /
<>	144:ef7eb2e8f9f7	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
<>	144:ef7eb2e8f9f7	304	__IO uint32_t INFO; /!< USB Info register /
<>	144:ef7eb2e8f9f7	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
<>	144:ef7eb2e8f9f7	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
<>	144:ef7eb2e8f9f7	307	__IO uint32_t LPM; /!< Link Power Management register /
<>	144:ef7eb2e8f9f7	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
<>	144:ef7eb2e8f9f7	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
<>	144:ef7eb2e8f9f7	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
<>	144:ef7eb2e8f9f7	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
<>	144:ef7eb2e8f9f7	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
<>	144:ef7eb2e8f9f7	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
<>	144:ef7eb2e8f9f7	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
<>	144:ef7eb2e8f9f7	315	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
<>	144:ef7eb2e8f9f7	317	} LPC_USB_Type;
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	321	/* ================ CRC ================ */
<>	144:ef7eb2e8f9f7	322	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/**
<>	144:ef7eb2e8f9f7	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	typedef struct { /!< CRC Structure /
<>	144:ef7eb2e8f9f7	330	__IO uint32_t MODE; /!< CRC mode register /
<>	144:ef7eb2e8f9f7	331	__IO uint32_t SEED; /!< CRC seed register /
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	union {
<>	144:ef7eb2e8f9f7	334	__O uint32_t WR_DATA; /!< CRC data register /
<>	144:ef7eb2e8f9f7	335	__I uint32_t SUM; /!< CRC checksum register /
<>	144:ef7eb2e8f9f7	336	};
<>	144:ef7eb2e8f9f7	337	} LPC_CRC_Type;
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	341	/* ================ SCT0 ================ */
<>	144:ef7eb2e8f9f7	342	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344
<>	144:ef7eb2e8f9f7	345	/**
<>	144:ef7eb2e8f9f7	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
<>	144:ef7eb2e8f9f7	347	*/
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	typedef struct { /!< SCT0 Structure /
<>	144:ef7eb2e8f9f7	350	__IO uint32_t CONFIG; /!< SCT configuration register /
<>	144:ef7eb2e8f9f7	351	__IO uint32_t CTRL; /!< SCT control register /
<>	144:ef7eb2e8f9f7	352	__IO uint32_t LIMIT; /!< SCT limit register /
<>	144:ef7eb2e8f9f7	353	__IO uint32_t HALT; /!< SCT halt condition register /
<>	144:ef7eb2e8f9f7	354	__IO uint32_t STOP; /!< SCT stop condition register /
<>	144:ef7eb2e8f9f7	355	__IO uint32_t START; /!< SCT start condition register /
<>	144:ef7eb2e8f9f7	356	__IO uint32_t DITHER; /!< SCT dither condition register /
<>	144:ef7eb2e8f9f7	357	__I uint32_t RESERVED0[9];
<>	144:ef7eb2e8f9f7	358	__IO uint32_t COUNT; /!< SCT counter register /
<>	144:ef7eb2e8f9f7	359	__IO uint32_t STATE; /!< SCT state register /
<>	144:ef7eb2e8f9f7	360	__I uint32_t INPUT; /!< SCT input register /
<>	144:ef7eb2e8f9f7	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
<>	144:ef7eb2e8f9f7	362	__IO uint32_t OUTPUT; /!< SCT output register /
<>	144:ef7eb2e8f9f7	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
<>	144:ef7eb2e8f9f7	364	__IO uint32_t RES; /!< SCT conflict resolution register /
<>	144:ef7eb2e8f9f7	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
<>	144:ef7eb2e8f9f7	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
<>	144:ef7eb2e8f9f7	367	__I uint32_t RESERVED1[35];
<>	144:ef7eb2e8f9f7	368	__IO uint32_t EVEN; /!< SCT event enable register /
<>	144:ef7eb2e8f9f7	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
<>	144:ef7eb2e8f9f7	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
<>	144:ef7eb2e8f9f7	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	union {
<>	144:ef7eb2e8f9f7	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	375	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	377	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	378	};
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	union {
<>	144:ef7eb2e8f9f7	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	382	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	384	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	385	};
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	union {
<>	144:ef7eb2e8f9f7	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	389	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	391	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	392	};
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	union {
<>	144:ef7eb2e8f9f7	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	396	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	398	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	399	};
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	union {
<>	144:ef7eb2e8f9f7	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	403	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	405	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	406	};
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	union {
<>	144:ef7eb2e8f9f7	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	410	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	412	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	413	};
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	union {
<>	144:ef7eb2e8f9f7	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	417	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	419	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	420	};
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	union {
<>	144:ef7eb2e8f9f7	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	424	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	426	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	427	};
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	union {
<>	144:ef7eb2e8f9f7	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	431	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	433	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	434	};
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	union {
<>	144:ef7eb2e8f9f7	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	438	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	440	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	441	};
<>	144:ef7eb2e8f9f7	442
<>	144:ef7eb2e8f9f7	443	union {
<>	144:ef7eb2e8f9f7	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	445	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	447	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	448	};
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	union {
<>	144:ef7eb2e8f9f7	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	452	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	454	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	455	};
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	union {
<>	144:ef7eb2e8f9f7	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	459	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	461	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	462	};
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	union {
<>	144:ef7eb2e8f9f7	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	466	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	468	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	469	};
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	union {
<>	144:ef7eb2e8f9f7	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	473	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	475	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	476	};
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	union {
<>	144:ef7eb2e8f9f7	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	144:ef7eb2e8f9f7	480	to REGMODE15 = 0 */
<>	144:ef7eb2e8f9f7	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	144:ef7eb2e8f9f7	482	REGMODE15 = 1 */
<>	144:ef7eb2e8f9f7	483	};
<>	144:ef7eb2e8f9f7	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	144:ef7eb2e8f9f7	485	0 to 5. */
<>	144:ef7eb2e8f9f7	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	144:ef7eb2e8f9f7	487	0 to 5. */
<>	144:ef7eb2e8f9f7	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	144:ef7eb2e8f9f7	489	0 to 5. */
<>	144:ef7eb2e8f9f7	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	144:ef7eb2e8f9f7	491	0 to 5. */
<>	144:ef7eb2e8f9f7	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	144:ef7eb2e8f9f7	493	0 to 5. */
<>	144:ef7eb2e8f9f7	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	144:ef7eb2e8f9f7	495	0 to 5. */
<>	144:ef7eb2e8f9f7	496	__I uint32_t RESERVED2[42];
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	union {
<>	144:ef7eb2e8f9f7	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	500	= 1 */
<>	144:ef7eb2e8f9f7	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	502	= 0 */
<>	144:ef7eb2e8f9f7	503	};
<>	144:ef7eb2e8f9f7	504
<>	144:ef7eb2e8f9f7	505	union {
<>	144:ef7eb2e8f9f7	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	507	= 0 */
<>	144:ef7eb2e8f9f7	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	509	= 1 */
<>	144:ef7eb2e8f9f7	510	};
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	union {
<>	144:ef7eb2e8f9f7	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	514	= 0 */
<>	144:ef7eb2e8f9f7	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	516	= 1 */
<>	144:ef7eb2e8f9f7	517	};
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	union {
<>	144:ef7eb2e8f9f7	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	521	= 1 */
<>	144:ef7eb2e8f9f7	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	523	= 0 */
<>	144:ef7eb2e8f9f7	524	};
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	union {
<>	144:ef7eb2e8f9f7	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	528	= 1 */
<>	144:ef7eb2e8f9f7	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	530	= 0 */
<>	144:ef7eb2e8f9f7	531	};
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	union {
<>	144:ef7eb2e8f9f7	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	535	= 1 */
<>	144:ef7eb2e8f9f7	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	537	= 0 */
<>	144:ef7eb2e8f9f7	538	};
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	union {
<>	144:ef7eb2e8f9f7	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	542	= 0 */
<>	144:ef7eb2e8f9f7	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	544	= 1 */
<>	144:ef7eb2e8f9f7	545	};
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	union {
<>	144:ef7eb2e8f9f7	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	549	= 0 */
<>	144:ef7eb2e8f9f7	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	551	= 1 */
<>	144:ef7eb2e8f9f7	552	};
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	union {
<>	144:ef7eb2e8f9f7	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	556	= 1 */
<>	144:ef7eb2e8f9f7	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	558	= 0 */
<>	144:ef7eb2e8f9f7	559	};
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	union {
<>	144:ef7eb2e8f9f7	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	563	= 1 */
<>	144:ef7eb2e8f9f7	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	565	= 0 */
<>	144:ef7eb2e8f9f7	566	};
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	union {
<>	144:ef7eb2e8f9f7	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	570	= 1 */
<>	144:ef7eb2e8f9f7	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	572	= 0 */
<>	144:ef7eb2e8f9f7	573	};
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	union {
<>	144:ef7eb2e8f9f7	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	577	= 1 */
<>	144:ef7eb2e8f9f7	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	579	= 0 */
<>	144:ef7eb2e8f9f7	580	};
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	union {
<>	144:ef7eb2e8f9f7	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	584	= 0 */
<>	144:ef7eb2e8f9f7	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	586	= 1 */
<>	144:ef7eb2e8f9f7	587	};
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	union {
<>	144:ef7eb2e8f9f7	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	591	= 0 */
<>	144:ef7eb2e8f9f7	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	593	= 1 */
<>	144:ef7eb2e8f9f7	594	};
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596	union {
<>	144:ef7eb2e8f9f7	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	598	= 1 */
<>	144:ef7eb2e8f9f7	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	600	= 0 */
<>	144:ef7eb2e8f9f7	601	};
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	union {
<>	144:ef7eb2e8f9f7	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	144:ef7eb2e8f9f7	605	= 1 */
<>	144:ef7eb2e8f9f7	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	144:ef7eb2e8f9f7	607	= 0 */
<>	144:ef7eb2e8f9f7	608	};
<>	144:ef7eb2e8f9f7	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	144:ef7eb2e8f9f7	610	registers 0 to 5. */
<>	144:ef7eb2e8f9f7	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	144:ef7eb2e8f9f7	612	registers 0 to 5. */
<>	144:ef7eb2e8f9f7	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	144:ef7eb2e8f9f7	614	registers 0 to 5. */
<>	144:ef7eb2e8f9f7	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	144:ef7eb2e8f9f7	616	registers 0 to 5. */
<>	144:ef7eb2e8f9f7	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	144:ef7eb2e8f9f7	618	registers 0 to 5. */
<>	144:ef7eb2e8f9f7	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	144:ef7eb2e8f9f7	620	registers 0 to 5. */
<>	144:ef7eb2e8f9f7	621	__I uint32_t RESERVED3[42];
<>	144:ef7eb2e8f9f7	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	654	__I uint32_t RESERVED4[96];
<>	144:ef7eb2e8f9f7	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	675	} LPC_SCT0_Type;
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677
<>	144:ef7eb2e8f9f7	678	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	679	/* ================ SCT2 ================ */
<>	144:ef7eb2e8f9f7	680	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/**
<>	144:ef7eb2e8f9f7	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
<>	144:ef7eb2e8f9f7	685	*/
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	typedef struct { /!< SCT2 Structure /
<>	144:ef7eb2e8f9f7	688	__IO uint32_t CONFIG; /!< SCT configuration register /
<>	144:ef7eb2e8f9f7	689	__IO uint32_t CTRL; /!< SCT control register /
<>	144:ef7eb2e8f9f7	690	__IO uint32_t LIMIT; /!< SCT limit register /
<>	144:ef7eb2e8f9f7	691	__IO uint32_t HALT; /!< SCT halt condition register /
<>	144:ef7eb2e8f9f7	692	__IO uint32_t STOP; /!< SCT stop condition register /
<>	144:ef7eb2e8f9f7	693	__IO uint32_t START; /!< SCT start condition register /
<>	144:ef7eb2e8f9f7	694	__I uint32_t RESERVED0[10];
<>	144:ef7eb2e8f9f7	695	__IO uint32_t COUNT; /!< SCT counter register /
<>	144:ef7eb2e8f9f7	696	__IO uint32_t STATE; /!< SCT state register /
<>	144:ef7eb2e8f9f7	697	__I uint32_t INPUT; /!< SCT input register /
<>	144:ef7eb2e8f9f7	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
<>	144:ef7eb2e8f9f7	699	__IO uint32_t OUTPUT; /!< SCT output register /
<>	144:ef7eb2e8f9f7	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
<>	144:ef7eb2e8f9f7	701	__IO uint32_t RES; /!< SCT conflict resolution register /
<>	144:ef7eb2e8f9f7	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
<>	144:ef7eb2e8f9f7	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
<>	144:ef7eb2e8f9f7	704	__I uint32_t RESERVED1[35];
<>	144:ef7eb2e8f9f7	705	__IO uint32_t EVEN; /!< SCT event enable register /
<>	144:ef7eb2e8f9f7	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
<>	144:ef7eb2e8f9f7	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
<>	144:ef7eb2e8f9f7	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	union {
<>	144:ef7eb2e8f9f7	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	712	= 1 */
<>	144:ef7eb2e8f9f7	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	714	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	715	};
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	union {
<>	144:ef7eb2e8f9f7	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	719	= 1 */
<>	144:ef7eb2e8f9f7	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	721	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	722	};
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	union {
<>	144:ef7eb2e8f9f7	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	726	= 1 */
<>	144:ef7eb2e8f9f7	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	728	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	729	};
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	union {
<>	144:ef7eb2e8f9f7	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	733	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	735	= 1 */
<>	144:ef7eb2e8f9f7	736	};
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	union {
<>	144:ef7eb2e8f9f7	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	740	= 1 */
<>	144:ef7eb2e8f9f7	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	742	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	743	};
<>	144:ef7eb2e8f9f7	744
<>	144:ef7eb2e8f9f7	745	union {
<>	144:ef7eb2e8f9f7	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	747	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	749	= 1 */
<>	144:ef7eb2e8f9f7	750	};
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752	union {
<>	144:ef7eb2e8f9f7	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	754	= 1 */
<>	144:ef7eb2e8f9f7	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	756	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	757	};
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	union {
<>	144:ef7eb2e8f9f7	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	144:ef7eb2e8f9f7	761	= 1 */
<>	144:ef7eb2e8f9f7	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	144:ef7eb2e8f9f7	763	REGMODE7 = 0 */
<>	144:ef7eb2e8f9f7	764	};
<>	144:ef7eb2e8f9f7	765	__I uint32_t RESERVED2[56];
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	union {
<>	144:ef7eb2e8f9f7	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	769	= 1 */
<>	144:ef7eb2e8f9f7	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	771	= 0 */
<>	144:ef7eb2e8f9f7	772	};
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	union {
<>	144:ef7eb2e8f9f7	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	776	= 1 */
<>	144:ef7eb2e8f9f7	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	778	= 0 */
<>	144:ef7eb2e8f9f7	779	};
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781	union {
<>	144:ef7eb2e8f9f7	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	783	= 1 */
<>	144:ef7eb2e8f9f7	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	785	= 0 */
<>	144:ef7eb2e8f9f7	786	};
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	union {
<>	144:ef7eb2e8f9f7	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	790	= 0 */
<>	144:ef7eb2e8f9f7	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	792	= 1 */
<>	144:ef7eb2e8f9f7	793	};
<>	144:ef7eb2e8f9f7	794
<>	144:ef7eb2e8f9f7	795	union {
<>	144:ef7eb2e8f9f7	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	797	= 1 */
<>	144:ef7eb2e8f9f7	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	799	= 0 */
<>	144:ef7eb2e8f9f7	800	};
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	union {
<>	144:ef7eb2e8f9f7	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	804	= 0 */
<>	144:ef7eb2e8f9f7	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	806	= 1 */
<>	144:ef7eb2e8f9f7	807	};
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	union {
<>	144:ef7eb2e8f9f7	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	811	= 1 */
<>	144:ef7eb2e8f9f7	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	813	= 0 */
<>	144:ef7eb2e8f9f7	814	};
<>	144:ef7eb2e8f9f7	815
<>	144:ef7eb2e8f9f7	816	union {
<>	144:ef7eb2e8f9f7	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	144:ef7eb2e8f9f7	818	= 1 */
<>	144:ef7eb2e8f9f7	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	144:ef7eb2e8f9f7	820	= 0 */
<>	144:ef7eb2e8f9f7	821	};
<>	144:ef7eb2e8f9f7	822	__I uint32_t RESERVED3[56];
<>	144:ef7eb2e8f9f7	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
<>	144:ef7eb2e8f9f7	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
<>	144:ef7eb2e8f9f7	843	__I uint32_t RESERVED4[108];
<>	144:ef7eb2e8f9f7	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
<>	144:ef7eb2e8f9f7	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
<>	144:ef7eb2e8f9f7	856	} LPC_SCT2_Type;
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	860	/* ================ ADC0 ================ */
<>	144:ef7eb2e8f9f7	861	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	/**
<>	144:ef7eb2e8f9f7	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	typedef struct { /!< ADC0 Structure /
<>	144:ef7eb2e8f9f7	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
<>	144:ef7eb2e8f9f7	870	bits for each sequence and the A/D power-down bit. */
<>	144:ef7eb2e8f9f7	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
<>	144:ef7eb2e8f9f7	872	internal source for various channels */
<>	144:ef7eb2e8f9f7	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
<>	144:ef7eb2e8f9f7	874	and channel selection for conversion sequence-A. Also specifies
<>	144:ef7eb2e8f9f7	875	interrupt mode for sequence-A. */
<>	144:ef7eb2e8f9f7	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
<>	144:ef7eb2e8f9f7	877	and channel selection for conversion sequence-B. Also specifies
<>	144:ef7eb2e8f9f7	878	interrupt mode for sequence-B. */
<>	144:ef7eb2e8f9f7	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
<>	144:ef7eb2e8f9f7	880	the result of the most recent A/D conversion performed under
<>	144:ef7eb2e8f9f7	881	sequence-A */
<>	144:ef7eb2e8f9f7	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
<>	144:ef7eb2e8f9f7	883	the result of the most recent A/D conversion performed under
<>	144:ef7eb2e8f9f7	884	sequence-B */
<>	144:ef7eb2e8f9f7	885	__I uint32_t RESERVED0[2];
<>	144:ef7eb2e8f9f7	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
<>	144:ef7eb2e8f9f7	887	of the most recent conversion completed on channel 0. */
<>	144:ef7eb2e8f9f7	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
<>	144:ef7eb2e8f9f7	889	level for automatic threshold comparison for any channels linked
<>	144:ef7eb2e8f9f7	890	to threshold pair 0. */
<>	144:ef7eb2e8f9f7	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
<>	144:ef7eb2e8f9f7	892	level for automatic threshold comparison for any channels linked
<>	144:ef7eb2e8f9f7	893	to threshold pair 1. */
<>	144:ef7eb2e8f9f7	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
<>	144:ef7eb2e8f9f7	895	level for automatic threshold comparison for any channels linked
<>	144:ef7eb2e8f9f7	896	to threshold pair 0. */
<>	144:ef7eb2e8f9f7	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
<>	144:ef7eb2e8f9f7	898	level for automatic threshold comparison for any channels linked
<>	144:ef7eb2e8f9f7	899	to threshold pair 1. */
<>	144:ef7eb2e8f9f7	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
<>	144:ef7eb2e8f9f7	901	threshold compare registers are to be used for each channel */
<>	144:ef7eb2e8f9f7	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
<>	144:ef7eb2e8f9f7	903	bits that enable the sequence-A, sequence-B, threshold compare
<>	144:ef7eb2e8f9f7	904	and data overrun interrupts to be generated. */
<>	144:ef7eb2e8f9f7	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
<>	144:ef7eb2e8f9f7	906	and the individual component overrun and threshold-compare flags.
<>	144:ef7eb2e8f9f7	907	(The overrun bits replicate information stored in the result
<>	144:ef7eb2e8f9f7	908	registers). */
<>	144:ef7eb2e8f9f7	909	__IO uint32_t TRM; /!< ADC trim register. /
<>	144:ef7eb2e8f9f7	910	} LPC_ADC0_Type;
<>	144:ef7eb2e8f9f7	911
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	914	/* ================ DAC ================ */
<>	144:ef7eb2e8f9f7	915	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917
<>	144:ef7eb2e8f9f7	918	/**
<>	144:ef7eb2e8f9f7	919	* @brief 12-bit DAC Modification (DAC)
<>	144:ef7eb2e8f9f7	920	*/
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	typedef struct { /!< DAC Structure /
<>	144:ef7eb2e8f9f7	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
<>	144:ef7eb2e8f9f7	924	value to be converted to analog. */
<>	144:ef7eb2e8f9f7	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
<>	144:ef7eb2e8f9f7	926	DAC operation and the interrupt/dma request flag. */
<>	144:ef7eb2e8f9f7	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
<>	144:ef7eb2e8f9f7	928	value for the internal DAC DMA/Interrupt timer. */
<>	144:ef7eb2e8f9f7	929	} LPC_DAC_Type;
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	933	/* ================ ACMP ================ */
<>	144:ef7eb2e8f9f7	934	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936
<>	144:ef7eb2e8f9f7	937	/**
<>	144:ef7eb2e8f9f7	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
<>	144:ef7eb2e8f9f7	939	*/
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	typedef struct { /!< ACMP Structure /
<>	144:ef7eb2e8f9f7	942	__IO uint32_t CTRL; /!< Comparator block control register /
<>	144:ef7eb2e8f9f7	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
<>	144:ef7eb2e8f9f7	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
<>	144:ef7eb2e8f9f7	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
<>	144:ef7eb2e8f9f7	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
<>	144:ef7eb2e8f9f7	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
<>	144:ef7eb2e8f9f7	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
<>	144:ef7eb2e8f9f7	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
<>	144:ef7eb2e8f9f7	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
<>	144:ef7eb2e8f9f7	951	} LPC_ACMP_Type;
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	955	/* ================ INMUX ================ */
<>	144:ef7eb2e8f9f7	956	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958
<>	144:ef7eb2e8f9f7	959	/**
<>	144:ef7eb2e8f9f7	960	* @brief Input multiplexing (INMUX) (INMUX)
<>	144:ef7eb2e8f9f7	961	*/
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	typedef struct { /!< INMUX Structure /
<>	144:ef7eb2e8f9f7	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
<>	144:ef7eb2e8f9f7	965	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
<>	144:ef7eb2e8f9f7	967	__I uint32_t RESERVED1;
<>	144:ef7eb2e8f9f7	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
<>	144:ef7eb2e8f9f7	969	__I uint32_t RESERVED2[5];
<>	144:ef7eb2e8f9f7	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
<>	144:ef7eb2e8f9f7	971	__I uint32_t RESERVED3[21];
<>	144:ef7eb2e8f9f7	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
<>	144:ef7eb2e8f9f7	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
<>	144:ef7eb2e8f9f7	974	__I uint32_t RESERVED4[14];
<>	144:ef7eb2e8f9f7	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
<>	144:ef7eb2e8f9f7	976	clock */
<>	144:ef7eb2e8f9f7	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
<>	144:ef7eb2e8f9f7	978	} LPC_INMUX_Type;
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980
<>	144:ef7eb2e8f9f7	981	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	982	/* ================ RTC ================ */
<>	144:ef7eb2e8f9f7	983	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/**
<>	144:ef7eb2e8f9f7	987	* @brief Real-Time Clock (RTC) (RTC)
<>	144:ef7eb2e8f9f7	988	*/
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	typedef struct { /!< RTC Structure /
<>	144:ef7eb2e8f9f7	991	__IO uint32_t CTRL; /!< RTC control register /
<>	144:ef7eb2e8f9f7	992	__IO uint32_t MATCH; /!< RTC match register /
<>	144:ef7eb2e8f9f7	993	__IO uint32_t COUNT; /!< RTC counter register /
<>	144:ef7eb2e8f9f7	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
<>	144:ef7eb2e8f9f7	995	} LPC_RTC_Type;
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	999	/* ================ WWDT ================ */
<>	144:ef7eb2e8f9f7	1000	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/**
<>	144:ef7eb2e8f9f7	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
<>	144:ef7eb2e8f9f7	1005	*/
<>	144:ef7eb2e8f9f7	1006
<>	144:ef7eb2e8f9f7	1007	typedef struct { /!< WWDT Structure /
<>	144:ef7eb2e8f9f7	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
<>	144:ef7eb2e8f9f7	1009	and status of the Watchdog Timer. */
<>	144:ef7eb2e8f9f7	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
<>	144:ef7eb2e8f9f7	1011	the time-out value. */
<>	144:ef7eb2e8f9f7	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
<>	144:ef7eb2e8f9f7	1013	to this register reloads the Watchdog timer with the value contained
<>	144:ef7eb2e8f9f7	1014	in WDTC. */
<>	144:ef7eb2e8f9f7	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
<>	144:ef7eb2e8f9f7	1016	the current value of the Watchdog timer. */
<>	144:ef7eb2e8f9f7	1017	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
<>	144:ef7eb2e8f9f7	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
<>	144:ef7eb2e8f9f7	1020	} LPC_WWDT_Type;
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1024	/* ================ SWM ================ */
<>	144:ef7eb2e8f9f7	1025	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1026
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	/**
<>	144:ef7eb2e8f9f7	1029	* @brief Switch Matrix (SWM) (SWM)
<>	144:ef7eb2e8f9f7	1030	*/
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	typedef struct { /!< SWM Structure /
<>	144:ef7eb2e8f9f7	1033	union {
<>	144:ef7eb2e8f9f7	1034	__IO uint32_t PINASSIGN[16];
<>	144:ef7eb2e8f9f7	1035	struct {
<>	144:ef7eb2e8f9f7	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
<>	144:ef7eb2e8f9f7	1037	U0_RTS, U0_CTS. */
<>	144:ef7eb2e8f9f7	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
<>	144:ef7eb2e8f9f7	1039	U1_RXD, U1_RTS. */
<>	144:ef7eb2e8f9f7	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
<>	144:ef7eb2e8f9f7	1041	U2_TXD, U2_RXD. */
<>	144:ef7eb2e8f9f7	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
<>	144:ef7eb2e8f9f7	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
<>	144:ef7eb2e8f9f7	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
<>	144:ef7eb2e8f9f7	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
<>	144:ef7eb2e8f9f7	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
<>	144:ef7eb2e8f9f7	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
<>	144:ef7eb2e8f9f7	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
<>	144:ef7eb2e8f9f7	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
<>	144:ef7eb2e8f9f7	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
<>	144:ef7eb2e8f9f7	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
<>	144:ef7eb2e8f9f7	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
<>	144:ef7eb2e8f9f7	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
<>	144:ef7eb2e8f9f7	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
<>	144:ef7eb2e8f9f7	1055	};
<>	144:ef7eb2e8f9f7	1056	};
<>	144:ef7eb2e8f9f7	1057	__I uint32_t RESERVED0[96];
<>	144:ef7eb2e8f9f7	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
<>	144:ef7eb2e8f9f7	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
<>	144:ef7eb2e8f9f7	1060	} LPC_SWM_Type;
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062
<>	144:ef7eb2e8f9f7	1063	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1064	/* ================ PMU ================ */
<>	144:ef7eb2e8f9f7	1065	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1066
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	/**
<>	144:ef7eb2e8f9f7	1069	* @brief Power Management Unit (PMU) (PMU)
<>	144:ef7eb2e8f9f7	1070	*/
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	typedef struct { /!< PMU Structure /
<>	144:ef7eb2e8f9f7	1073	__IO uint32_t PCON; /!< Power control register /
<>	144:ef7eb2e8f9f7	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
<>	144:ef7eb2e8f9f7	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
<>	144:ef7eb2e8f9f7	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
<>	144:ef7eb2e8f9f7	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
<>	144:ef7eb2e8f9f7	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
<>	144:ef7eb2e8f9f7	1079	} LPC_PMU_Type;
<>	144:ef7eb2e8f9f7	1080
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1083	/* ================ USART0 ================ */
<>	144:ef7eb2e8f9f7	1084	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/**
<>	144:ef7eb2e8f9f7	1088	* @brief USART0 (USART0)
<>	144:ef7eb2e8f9f7	1089	*/
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	typedef struct { /!< USART0 Structure /
<>	144:ef7eb2e8f9f7	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
<>	144:ef7eb2e8f9f7	1093	that typically are not changed during operation. */
<>	144:ef7eb2e8f9f7	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
<>	144:ef7eb2e8f9f7	1095	likely to change during operation. */
<>	144:ef7eb2e8f9f7	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
<>	144:ef7eb2e8f9f7	1097	here. Writing ones clears some bits in the register. Some bits
<>	144:ef7eb2e8f9f7	1098	can be cleared by writing a 1 to them. */
<>	144:ef7eb2e8f9f7	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
<>	144:ef7eb2e8f9f7	1100	interrupt enable bit for each potential USART interrupt. A complete
<>	144:ef7eb2e8f9f7	1101	value may be read from this register. Writing a 1 to any implemented
<>	144:ef7eb2e8f9f7	1102	bit position causes that bit to be set. */
<>	144:ef7eb2e8f9f7	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
<>	144:ef7eb2e8f9f7	1104	of bits in the INTENSET register. Writing a 1 to any implemented
<>	144:ef7eb2e8f9f7	1105	bit position causes the corresponding bit to be cleared. */
<>	144:ef7eb2e8f9f7	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
<>	144:ef7eb2e8f9f7	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
<>	144:ef7eb2e8f9f7	1108	received with the current USART receive status. Allows DMA or
<>	144:ef7eb2e8f9f7	1109	software to recover incoming data and status together. */
<>	144:ef7eb2e8f9f7	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
<>	144:ef7eb2e8f9f7	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
<>	144:ef7eb2e8f9f7	1112	value. */
<>	144:ef7eb2e8f9f7	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
<>	144:ef7eb2e8f9f7	1114	enabled. */
<>	144:ef7eb2e8f9f7	1115	} LPC_USART0_Type;
<>	144:ef7eb2e8f9f7	1116
<>	144:ef7eb2e8f9f7	1117
<>	144:ef7eb2e8f9f7	1118	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1119	/* ================ SPI0 ================ */
<>	144:ef7eb2e8f9f7	1120	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/**
<>	144:ef7eb2e8f9f7	1124	* @brief SPI0 (SPI0)
<>	144:ef7eb2e8f9f7	1125	*/
<>	144:ef7eb2e8f9f7	1126
<>	144:ef7eb2e8f9f7	1127	typedef struct { /!< SPI0 Structure /
<>	144:ef7eb2e8f9f7	1128	__IO uint32_t CFG; /!< SPI Configuration register /
<>	144:ef7eb2e8f9f7	1129	__IO uint32_t DLY; /!< SPI Delay register /
<>	144:ef7eb2e8f9f7	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
<>	144:ef7eb2e8f9f7	1131	to that bit position */
<>	144:ef7eb2e8f9f7	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
<>	144:ef7eb2e8f9f7	1133	from this register. Writing a 1 to any implemented bit position
<>	144:ef7eb2e8f9f7	1134	causes that bit to be set. */
<>	144:ef7eb2e8f9f7	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
<>	144:ef7eb2e8f9f7	1136	position causes the corresponding bit in INTENSET to be cleared. */
<>	144:ef7eb2e8f9f7	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
<>	144:ef7eb2e8f9f7	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
<>	144:ef7eb2e8f9f7	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
<>	144:ef7eb2e8f9f7	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
<>	144:ef7eb2e8f9f7	1141	__IO uint32_t DIV; /!< SPI clock Divider /
<>	144:ef7eb2e8f9f7	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
<>	144:ef7eb2e8f9f7	1143	} LPC_SPI0_Type;
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1147	/* ================ I2C0 ================ */
<>	144:ef7eb2e8f9f7	1148	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150
<>	144:ef7eb2e8f9f7	1151	/**
<>	144:ef7eb2e8f9f7	1152	* @brief I2C-bus interface (I2C0)
<>	144:ef7eb2e8f9f7	1153	*/
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	typedef struct { /!< I2C0 Structure /
<>	144:ef7eb2e8f9f7	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
<>	144:ef7eb2e8f9f7	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
<>	144:ef7eb2e8f9f7	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
<>	144:ef7eb2e8f9f7	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
<>	144:ef7eb2e8f9f7	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
<>	144:ef7eb2e8f9f7	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
<>	144:ef7eb2e8f9f7	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
<>	144:ef7eb2e8f9f7	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
<>	144:ef7eb2e8f9f7	1164	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1165	__IO uint32_t MSTCTL; /!< Master control register. /
<>	144:ef7eb2e8f9f7	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
<>	144:ef7eb2e8f9f7	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
<>	144:ef7eb2e8f9f7	1168	__I uint32_t RESERVED1[5];
<>	144:ef7eb2e8f9f7	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
<>	144:ef7eb2e8f9f7	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
<>	144:ef7eb2e8f9f7	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
<>	144:ef7eb2e8f9f7	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
<>	144:ef7eb2e8f9f7	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
<>	144:ef7eb2e8f9f7	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
<>	144:ef7eb2e8f9f7	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
<>	144:ef7eb2e8f9f7	1176	__I uint32_t RESERVED2[9];
<>	144:ef7eb2e8f9f7	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
<>	144:ef7eb2e8f9f7	1178	} LPC_I2C0_Type;
<>	144:ef7eb2e8f9f7	1179
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1182	/* ================ QEI ================ */
<>	144:ef7eb2e8f9f7	1183	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/**
<>	144:ef7eb2e8f9f7	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
<>	144:ef7eb2e8f9f7	1188	*/
<>	144:ef7eb2e8f9f7	1189
<>	144:ef7eb2e8f9f7	1190	typedef struct { /!< QEI Structure /
<>	144:ef7eb2e8f9f7	1191	__O uint32_t CON; /!< Control register /
<>	144:ef7eb2e8f9f7	1192	__I uint32_t STAT; /!< Encoder status register /
<>	144:ef7eb2e8f9f7	1193	__IO uint32_t CONF; /!< Configuration register /
<>	144:ef7eb2e8f9f7	1194	__I uint32_t POS; /!< Position register /
<>	144:ef7eb2e8f9f7	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
<>	144:ef7eb2e8f9f7	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
<>	144:ef7eb2e8f9f7	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
<>	144:ef7eb2e8f9f7	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
<>	144:ef7eb2e8f9f7	1199	__I uint32_t INXCNT; /!< Index count register /
<>	144:ef7eb2e8f9f7	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
<>	144:ef7eb2e8f9f7	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
<>	144:ef7eb2e8f9f7	1202	__I uint32_t TIME; /!< Velocity timer register /
<>	144:ef7eb2e8f9f7	1203	__I uint32_t VEL; /!< Velocity counter register /
<>	144:ef7eb2e8f9f7	1204	__I uint32_t CAP; /!< Velocity capture register /
<>	144:ef7eb2e8f9f7	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
<>	144:ef7eb2e8f9f7	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
<>	144:ef7eb2e8f9f7	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
<>	144:ef7eb2e8f9f7	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
<>	144:ef7eb2e8f9f7	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
<>	144:ef7eb2e8f9f7	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
<>	144:ef7eb2e8f9f7	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
<>	144:ef7eb2e8f9f7	1212	__I uint32_t RESERVED0[993];
<>	144:ef7eb2e8f9f7	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
<>	144:ef7eb2e8f9f7	1214	__O uint32_t IES; /!< Interrupt enable set register /
<>	144:ef7eb2e8f9f7	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
<>	144:ef7eb2e8f9f7	1216	__O uint32_t IE; /!< Interrupt enable clear register /
<>	144:ef7eb2e8f9f7	1217	__O uint32_t CLR; /!< Interrupt status clear register /
<>	144:ef7eb2e8f9f7	1218	__O uint32_t SET; /!< Interrupt status set register /
<>	144:ef7eb2e8f9f7	1219	} LPC_QEI_Type;
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221
<>	144:ef7eb2e8f9f7	1222	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1223	/* ================ SYSCON ================ */
<>	144:ef7eb2e8f9f7	1224	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1225
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/**
<>	144:ef7eb2e8f9f7	1228	* @brief System configuration (SYSCON) (SYSCON)
<>	144:ef7eb2e8f9f7	1229	*/
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	typedef struct { /!< SYSCON Structure /
<>	144:ef7eb2e8f9f7	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
<>	144:ef7eb2e8f9f7	1233	__I uint32_t RESERVED0[4];
<>	144:ef7eb2e8f9f7	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
<>	144:ef7eb2e8f9f7	1235	__I uint32_t RESERVED1;
<>	144:ef7eb2e8f9f7	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
<>	144:ef7eb2e8f9f7	1237	__I uint32_t RESERVED2[8];
<>	144:ef7eb2e8f9f7	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
<>	144:ef7eb2e8f9f7	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
<>	144:ef7eb2e8f9f7	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
<>	144:ef7eb2e8f9f7	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
<>	144:ef7eb2e8f9f7	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
<>	144:ef7eb2e8f9f7	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
<>	144:ef7eb2e8f9f7	1244	__I uint32_t RESERVED3[10];
<>	144:ef7eb2e8f9f7	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
<>	144:ef7eb2e8f9f7	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
<>	144:ef7eb2e8f9f7	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
<>	144:ef7eb2e8f9f7	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
<>	144:ef7eb2e8f9f7	1249	__I uint32_t RESERVED4;
<>	144:ef7eb2e8f9f7	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
<>	144:ef7eb2e8f9f7	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
<>	144:ef7eb2e8f9f7	1252	__I uint32_t RESERVED5;
<>	144:ef7eb2e8f9f7	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
<>	144:ef7eb2e8f9f7	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
<>	144:ef7eb2e8f9f7	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
<>	144:ef7eb2e8f9f7	1256	__I uint32_t RESERVED6[5];
<>	144:ef7eb2e8f9f7	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
<>	144:ef7eb2e8f9f7	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
<>	144:ef7eb2e8f9f7	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
<>	144:ef7eb2e8f9f7	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
<>	144:ef7eb2e8f9f7	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
<>	144:ef7eb2e8f9f7	1262	baud rate generator. */
<>	144:ef7eb2e8f9f7	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
<>	144:ef7eb2e8f9f7	1264	filter */
<>	144:ef7eb2e8f9f7	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
<>	144:ef7eb2e8f9f7	1266	__I uint32_t RESERVED7[4];
<>	144:ef7eb2e8f9f7	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
<>	144:ef7eb2e8f9f7	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
<>	144:ef7eb2e8f9f7	1269	__I uint32_t RESERVED8;
<>	144:ef7eb2e8f9f7	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
<>	144:ef7eb2e8f9f7	1271	__I uint32_t RESERVED9[11];
<>	144:ef7eb2e8f9f7	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
<>	144:ef7eb2e8f9f7	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
<>	144:ef7eb2e8f9f7	1274	__IO uint32_t USBCLKST; /!< USB clock status /
<>	144:ef7eb2e8f9f7	1275	__I uint32_t RESERVED10[19];
<>	144:ef7eb2e8f9f7	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
<>	144:ef7eb2e8f9f7	1277	__I uint32_t RESERVED11;
<>	144:ef7eb2e8f9f7	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
<>	144:ef7eb2e8f9f7	1279	__I uint32_t RESERVED12;
<>	144:ef7eb2e8f9f7	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
<>	144:ef7eb2e8f9f7	1281	__I uint32_t RESERVED13;
<>	144:ef7eb2e8f9f7	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
<>	144:ef7eb2e8f9f7	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
<>	144:ef7eb2e8f9f7	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
<>	144:ef7eb2e8f9f7	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
<>	144:ef7eb2e8f9f7	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
<>	144:ef7eb2e8f9f7	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
<>	144:ef7eb2e8f9f7	1288	__I uint32_t RESERVED14[21];
<>	144:ef7eb2e8f9f7	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
<>	144:ef7eb2e8f9f7	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
<>	144:ef7eb2e8f9f7	1291	__I uint32_t RESERVED15[3];
<>	144:ef7eb2e8f9f7	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
<>	144:ef7eb2e8f9f7	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
<>	144:ef7eb2e8f9f7	1294	} LPC_SYSCON_Type;
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1298	/* ================ MRT ================ */
<>	144:ef7eb2e8f9f7	1299	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	/**
<>	144:ef7eb2e8f9f7	1303	* @brief Multi-Rate Timer (MRT) (MRT)
<>	144:ef7eb2e8f9f7	1304	*/
<>	144:ef7eb2e8f9f7	1305
<>	144:ef7eb2e8f9f7	1306	typedef struct { /!< MRT Structure /
<>	144:ef7eb2e8f9f7	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
<>	144:ef7eb2e8f9f7	1308	the TIMER0 register. */
<>	144:ef7eb2e8f9f7	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	144:ef7eb2e8f9f7	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	144:ef7eb2e8f9f7	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
<>	144:ef7eb2e8f9f7	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
<>	144:ef7eb2e8f9f7	1313	the TIMER0 register. */
<>	144:ef7eb2e8f9f7	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	144:ef7eb2e8f9f7	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	144:ef7eb2e8f9f7	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
<>	144:ef7eb2e8f9f7	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
<>	144:ef7eb2e8f9f7	1318	the TIMER0 register. */
<>	144:ef7eb2e8f9f7	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	144:ef7eb2e8f9f7	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	144:ef7eb2e8f9f7	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
<>	144:ef7eb2e8f9f7	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
<>	144:ef7eb2e8f9f7	1323	the TIMER0 register. */
<>	144:ef7eb2e8f9f7	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	144:ef7eb2e8f9f7	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	144:ef7eb2e8f9f7	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
<>	144:ef7eb2e8f9f7	1327	__I uint32_t RESERVED0[45];
<>	144:ef7eb2e8f9f7	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
<>	144:ef7eb2e8f9f7	1329	first idle channel. */
<>	144:ef7eb2e8f9f7	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
<>	144:ef7eb2e8f9f7	1331	} LPC_MRT_Type;
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333
<>	144:ef7eb2e8f9f7	1334	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1335	/* ================ PINT ================ */
<>	144:ef7eb2e8f9f7	1336	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1337
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	/**
<>	144:ef7eb2e8f9f7	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
<>	144:ef7eb2e8f9f7	1341	*/
<>	144:ef7eb2e8f9f7	1342
<>	144:ef7eb2e8f9f7	1343	typedef struct { /!< PINT Structure /
<>	144:ef7eb2e8f9f7	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
<>	144:ef7eb2e8f9f7	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
<>	144:ef7eb2e8f9f7	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
<>	144:ef7eb2e8f9f7	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
<>	144:ef7eb2e8f9f7	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
<>	144:ef7eb2e8f9f7	1349	register */
<>	144:ef7eb2e8f9f7	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
<>	144:ef7eb2e8f9f7	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
<>	144:ef7eb2e8f9f7	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
<>	144:ef7eb2e8f9f7	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
<>	144:ef7eb2e8f9f7	1354	__IO uint32_t IST; /!< Pin interrupt status register /
<>	144:ef7eb2e8f9f7	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
<>	144:ef7eb2e8f9f7	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
<>	144:ef7eb2e8f9f7	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
<>	144:ef7eb2e8f9f7	1358	} LPC_PINT_Type;
<>	144:ef7eb2e8f9f7	1359
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1362	/* ================ GINT0 ================ */
<>	144:ef7eb2e8f9f7	1363	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365
<>	144:ef7eb2e8f9f7	1366	/**
<>	144:ef7eb2e8f9f7	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
<>	144:ef7eb2e8f9f7	1368	*/
<>	144:ef7eb2e8f9f7	1369
<>	144:ef7eb2e8f9f7	1370	typedef struct { /!< GINT0 Structure /
<>	144:ef7eb2e8f9f7	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
<>	144:ef7eb2e8f9f7	1372	__I uint32_t RESERVED0[7];
<>	144:ef7eb2e8f9f7	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
<>	144:ef7eb2e8f9f7	1374	__I uint32_t RESERVED1[5];
<>	144:ef7eb2e8f9f7	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
<>	144:ef7eb2e8f9f7	1376	} LPC_GINT0_Type;
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378
<>	144:ef7eb2e8f9f7	1379	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1380	/* ================ RIT ================ */
<>	144:ef7eb2e8f9f7	1381	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383
<>	144:ef7eb2e8f9f7	1384	/**
<>	144:ef7eb2e8f9f7	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
<>	144:ef7eb2e8f9f7	1386	*/
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	typedef struct { /!< RIT Structure /
<>	144:ef7eb2e8f9f7	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
<>	144:ef7eb2e8f9f7	1390	value. */
<>	144:ef7eb2e8f9f7	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
<>	144:ef7eb2e8f9f7	1392	value. A 1 written to any bit will force a compare on the corresponding
<>	144:ef7eb2e8f9f7	1393	bit of the counter and compare register. */
<>	144:ef7eb2e8f9f7	1394	__IO uint32_t CTRL; /!< Control register. /
<>	144:ef7eb2e8f9f7	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
<>	144:ef7eb2e8f9f7	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
<>	144:ef7eb2e8f9f7	1397	value. */
<>	144:ef7eb2e8f9f7	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
<>	144:ef7eb2e8f9f7	1399	value. A 1 written to any bit will force a compare on the corresponding
<>	144:ef7eb2e8f9f7	1400	bit of the counter and compare register. */
<>	144:ef7eb2e8f9f7	1401	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
<>	144:ef7eb2e8f9f7	1403	} LPC_RIT_Type;
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405
<>	144:ef7eb2e8f9f7	1406	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1407	/* ================ SCTIPU ================ */
<>	144:ef7eb2e8f9f7	1408	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410
<>	144:ef7eb2e8f9f7	1411	/**
<>	144:ef7eb2e8f9f7	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
<>	144:ef7eb2e8f9f7	1413	*/
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415	typedef struct { /!< SCTIPU Structure /
<>	144:ef7eb2e8f9f7	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
<>	144:ef7eb2e8f9f7	1417	latch/sample-enable mux selects, and sample overrride bits for
<>	144:ef7eb2e8f9f7	1418	the SAMPLE module. */
<>	144:ef7eb2e8f9f7	1419	__I uint32_t RESERVED0[7];
<>	144:ef7eb2e8f9f7	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	144:ef7eb2e8f9f7	1421	to ORed Abort Output 0. */
<>	144:ef7eb2e8f9f7	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
<>	144:ef7eb2e8f9f7	1423	input source caused abort output 0. */
<>	144:ef7eb2e8f9f7	1424	__I uint32_t RESERVED1[6];
<>	144:ef7eb2e8f9f7	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	144:ef7eb2e8f9f7	1426	to ORed Abort Output 0. */
<>	144:ef7eb2e8f9f7	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
<>	144:ef7eb2e8f9f7	1428	input source caused abort output 0. */
<>	144:ef7eb2e8f9f7	1429	__I uint32_t RESERVED2[6];
<>	144:ef7eb2e8f9f7	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	144:ef7eb2e8f9f7	1431	to ORed Abort Output 0. */
<>	144:ef7eb2e8f9f7	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
<>	144:ef7eb2e8f9f7	1433	input source caused abort output 0. */
<>	144:ef7eb2e8f9f7	1434	__I uint32_t RESERVED3[6];
<>	144:ef7eb2e8f9f7	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	144:ef7eb2e8f9f7	1436	to ORed Abort Output 0. */
<>	144:ef7eb2e8f9f7	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
<>	144:ef7eb2e8f9f7	1438	input source caused abort output 0. */
<>	144:ef7eb2e8f9f7	1439	} LPC_SCTIPU_Type;
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441
<>	144:ef7eb2e8f9f7	1442	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1443	/* ================ FLASHCTRL ================ */
<>	144:ef7eb2e8f9f7	1444	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1445
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/**
<>	144:ef7eb2e8f9f7	1448	* @brief Flash controller (FLASHCTRL)
<>	144:ef7eb2e8f9f7	1449	*/
<>	144:ef7eb2e8f9f7	1450
<>	144:ef7eb2e8f9f7	1451	typedef struct { /!< FLASHCTRL Structure /
<>	144:ef7eb2e8f9f7	1452	__I uint32_t RESERVED0[8];
<>	144:ef7eb2e8f9f7	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
<>	144:ef7eb2e8f9f7	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
<>	144:ef7eb2e8f9f7	1455	__I uint32_t RESERVED1;
<>	144:ef7eb2e8f9f7	1456	__I uint32_t FMSW0; /!< Signature word /
<>	144:ef7eb2e8f9f7	1457	} LPC_FLASHCTRL_Type;
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459
<>	144:ef7eb2e8f9f7	1460	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1461	/* ================ C_CAN0 ================ */
<>	144:ef7eb2e8f9f7	1462	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	/**
<>	144:ef7eb2e8f9f7	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
<>	144:ef7eb2e8f9f7	1467	*/
<>	144:ef7eb2e8f9f7	1468
<>	144:ef7eb2e8f9f7	1469	typedef struct { /!< C_CAN0 Structure /
<>	144:ef7eb2e8f9f7	1470	__IO uint32_t CANCNTL; /!< CAN control /
<>	144:ef7eb2e8f9f7	1471	__IO uint32_t CANSTAT; /!< Status register /
<>	144:ef7eb2e8f9f7	1472	__I uint32_t CANEC; /!< Error counter /
<>	144:ef7eb2e8f9f7	1473	__IO uint32_t CANBT; /!< Bit timing register /
<>	144:ef7eb2e8f9f7	1474	__I uint32_t CANINT; /!< Interrupt register /
<>	144:ef7eb2e8f9f7	1475	__IO uint32_t CANTEST; /!< Test register /
<>	144:ef7eb2e8f9f7	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
<>	144:ef7eb2e8f9f7	1477	__I uint32_t RESERVED0;
<>	144:ef7eb2e8f9f7	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
<>	144:ef7eb2e8f9f7	1479
<>	144:ef7eb2e8f9f7	1480	union {
<>	144:ef7eb2e8f9f7	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
<>	144:ef7eb2e8f9f7	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
<>	144:ef7eb2e8f9f7	1483	};
<>	144:ef7eb2e8f9f7	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
<>	144:ef7eb2e8f9f7	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
<>	144:ef7eb2e8f9f7	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
<>	144:ef7eb2e8f9f7	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
<>	144:ef7eb2e8f9f7	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
<>	144:ef7eb2e8f9f7	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
<>	144:ef7eb2e8f9f7	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
<>	144:ef7eb2e8f9f7	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
<>	144:ef7eb2e8f9f7	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
<>	144:ef7eb2e8f9f7	1493	__I uint32_t RESERVED1[13];
<>	144:ef7eb2e8f9f7	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
<>	144:ef7eb2e8f9f7	1495
<>	144:ef7eb2e8f9f7	1496	union {
<>	144:ef7eb2e8f9f7	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
<>	144:ef7eb2e8f9f7	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
<>	144:ef7eb2e8f9f7	1499	};
<>	144:ef7eb2e8f9f7	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
<>	144:ef7eb2e8f9f7	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
<>	144:ef7eb2e8f9f7	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
<>	144:ef7eb2e8f9f7	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
<>	144:ef7eb2e8f9f7	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
<>	144:ef7eb2e8f9f7	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
<>	144:ef7eb2e8f9f7	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
<>	144:ef7eb2e8f9f7	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
<>	144:ef7eb2e8f9f7	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
<>	144:ef7eb2e8f9f7	1509	__I uint32_t RESERVED2[21];
<>	144:ef7eb2e8f9f7	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
<>	144:ef7eb2e8f9f7	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
<>	144:ef7eb2e8f9f7	1512	__I uint32_t RESERVED3[6];
<>	144:ef7eb2e8f9f7	1513	__I uint32_t CANND1; /!< New data 1 /
<>	144:ef7eb2e8f9f7	1514	__I uint32_t CANND2; /!< New data 2 /
<>	144:ef7eb2e8f9f7	1515	__I uint32_t RESERVED4[6];
<>	144:ef7eb2e8f9f7	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
<>	144:ef7eb2e8f9f7	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
<>	144:ef7eb2e8f9f7	1518	__I uint32_t RESERVED5[6];
<>	144:ef7eb2e8f9f7	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
<>	144:ef7eb2e8f9f7	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
<>	144:ef7eb2e8f9f7	1521	__I uint32_t RESERVED6[6];
<>	144:ef7eb2e8f9f7	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
<>	144:ef7eb2e8f9f7	1523	} LPC_C_CAN0_Type;
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525
<>	144:ef7eb2e8f9f7	1526	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1527	/* ================ IOCON ================ */
<>	144:ef7eb2e8f9f7	1528	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	/**
<>	144:ef7eb2e8f9f7	1532	* @brief I/O pin configuration (IOCON) (IOCON)
<>	144:ef7eb2e8f9f7	1533	*/
<>	144:ef7eb2e8f9f7	1534
<>	144:ef7eb2e8f9f7	1535	typedef struct { /!< IOCON Structure /
<>	144:ef7eb2e8f9f7	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	144:ef7eb2e8f9f7	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
<>	144:ef7eb2e8f9f7	1559	the I2C-bus SCL function. */
<>	144:ef7eb2e8f9f7	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
<>	144:ef7eb2e8f9f7	1561	the I2C-bus SCL function. */
<>	144:ef7eb2e8f9f7	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	144:ef7eb2e8f9f7	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	144:ef7eb2e8f9f7	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	144:ef7eb2e8f9f7	1614	} LPC_IOCON_Type;
<>	144:ef7eb2e8f9f7	1615
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	/* -------------------- End of section using anonymous unions ------------------- */
<>	144:ef7eb2e8f9f7	1618	#if defined(__CC_ARM)
<>	144:ef7eb2e8f9f7	1619	#pragma pop
<>	144:ef7eb2e8f9f7	1620	#elif defined(__ICCARM__)
<>	144:ef7eb2e8f9f7	1621	/* leave anonymous unions enabled */
<>	144:ef7eb2e8f9f7	1622	#elif defined(__GNUC__)
<>	144:ef7eb2e8f9f7	1623	/* anonymous unions are enabled by default */
<>	144:ef7eb2e8f9f7	1624	#elif defined(__TMS470__)
<>	144:ef7eb2e8f9f7	1625	/* anonymous unions are enabled by default */
<>	144:ef7eb2e8f9f7	1626	#elif defined(__TASKING__)
<>	144:ef7eb2e8f9f7	1627	#pragma warning restore
<>	144:ef7eb2e8f9f7	1628	#else
<>	144:ef7eb2e8f9f7	1629	#warning Not supported compiler type
<>	144:ef7eb2e8f9f7	1630	#endif
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1636	/* ================ Peripheral memory map ================ */
<>	144:ef7eb2e8f9f7	1637	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
<>	144:ef7eb2e8f9f7	1640	#define LPC_DMA_BASE 0x1C004000UL
<>	144:ef7eb2e8f9f7	1641	#define LPC_USB_BASE 0x1C00C000UL
<>	144:ef7eb2e8f9f7	1642	#define LPC_CRC_BASE 0x1C010000UL
<>	144:ef7eb2e8f9f7	1643	#define LPC_SCT0_BASE 0x1C018000UL
<>	144:ef7eb2e8f9f7	1644	#define LPC_SCT1_BASE 0x1C01C000UL
<>	144:ef7eb2e8f9f7	1645	#define LPC_SCT2_BASE 0x1C020000UL
<>	144:ef7eb2e8f9f7	1646	#define LPC_SCT3_BASE 0x1C024000UL
<>	144:ef7eb2e8f9f7	1647	#define LPC_ADC0_BASE 0x40000000UL
<>	144:ef7eb2e8f9f7	1648	#define LPC_DAC_BASE 0x40004000UL
<>	144:ef7eb2e8f9f7	1649	#define LPC_ACMP_BASE 0x40008000UL
<>	144:ef7eb2e8f9f7	1650	#define LPC_INMUX_BASE 0x40014000UL
<>	144:ef7eb2e8f9f7	1651	#define LPC_RTC_BASE 0x40028000UL
<>	144:ef7eb2e8f9f7	1652	#define LPC_WWDT_BASE 0x4002C000UL
<>	144:ef7eb2e8f9f7	1653	#define LPC_SWM_BASE 0x40038000UL
<>	144:ef7eb2e8f9f7	1654	#define LPC_PMU_BASE 0x4003C000UL
<>	144:ef7eb2e8f9f7	1655	#define LPC_USART0_BASE 0x40040000UL
<>	144:ef7eb2e8f9f7	1656	#define LPC_USART1_BASE 0x40044000UL
<>	144:ef7eb2e8f9f7	1657	#define LPC_SPI0_BASE 0x40048000UL
<>	144:ef7eb2e8f9f7	1658	#define LPC_SPI1_BASE 0x4004C000UL
<>	144:ef7eb2e8f9f7	1659	#define LPC_I2C0_BASE 0x40050000UL
<>	144:ef7eb2e8f9f7	1660	#define LPC_QEI_BASE 0x40058000UL
<>	144:ef7eb2e8f9f7	1661	#define LPC_SYSCON_BASE 0x40074000UL
<>	144:ef7eb2e8f9f7	1662	#define LPC_ADC1_BASE 0x40080000UL
<>	144:ef7eb2e8f9f7	1663	#define LPC_MRT_BASE 0x400A0000UL
<>	144:ef7eb2e8f9f7	1664	#define LPC_PINT_BASE 0x400A4000UL
<>	144:ef7eb2e8f9f7	1665	#define LPC_GINT0_BASE 0x400A8000UL
<>	144:ef7eb2e8f9f7	1666	#define LPC_GINT1_BASE 0x400AC000UL
<>	144:ef7eb2e8f9f7	1667	#define LPC_RIT_BASE 0x400B4000UL
<>	144:ef7eb2e8f9f7	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
<>	144:ef7eb2e8f9f7	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
<>	144:ef7eb2e8f9f7	1670	#define LPC_USART2_BASE 0x400C0000UL
<>	144:ef7eb2e8f9f7	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
<>	144:ef7eb2e8f9f7	1672	#define LPC_IOCON_BASE 0x400F8000UL
<>	144:ef7eb2e8f9f7	1673
<>	144:ef7eb2e8f9f7	1674
<>	144:ef7eb2e8f9f7	1675	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1676	/* ================ Peripheral declaration ================ */
<>	144:ef7eb2e8f9f7	1677	/* ================================================================================ */
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
<>	144:ef7eb2e8f9f7	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
<>	144:ef7eb2e8f9f7	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
<>	144:ef7eb2e8f9f7	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
<>	144:ef7eb2e8f9f7	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
<>	144:ef7eb2e8f9f7	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
<>	144:ef7eb2e8f9f7	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
<>	144:ef7eb2e8f9f7	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
<>	144:ef7eb2e8f9f7	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
<>	144:ef7eb2e8f9f7	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
<>	144:ef7eb2e8f9f7	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
<>	144:ef7eb2e8f9f7	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
<>	144:ef7eb2e8f9f7	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
<>	144:ef7eb2e8f9f7	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
<>	144:ef7eb2e8f9f7	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
<>	144:ef7eb2e8f9f7	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
<>	144:ef7eb2e8f9f7	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
<>	144:ef7eb2e8f9f7	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
<>	144:ef7eb2e8f9f7	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
<>	144:ef7eb2e8f9f7	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
<>	144:ef7eb2e8f9f7	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
<>	144:ef7eb2e8f9f7	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
<>	144:ef7eb2e8f9f7	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
<>	144:ef7eb2e8f9f7	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
<>	144:ef7eb2e8f9f7	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
<>	144:ef7eb2e8f9f7	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
<>	144:ef7eb2e8f9f7	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
<>	144:ef7eb2e8f9f7	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
<>	144:ef7eb2e8f9f7	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
<>	144:ef7eb2e8f9f7	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
<>	144:ef7eb2e8f9f7	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<>	144:ef7eb2e8f9f7	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
<>	144:ef7eb2e8f9f7	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
<>	144:ef7eb2e8f9f7	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
<>	144:ef7eb2e8f9f7	1713
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	/** @} / / End of group Device_Peripheral_Registers */
<>	144:ef7eb2e8f9f7	1716	/** @} / / End of group LPC15xx */
<>	144:ef7eb2e8f9f7	1717	/** @} / / End of group (null) */
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1720	}
<>	144:ef7eb2e8f9f7	1721	#endif
<>	144:ef7eb2e8f9f7	1722
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	#endif /* LPC15XX_H */
<>	144:ef7eb2e8f9f7	1725

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

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