Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /****************************************************************************
<> 144:ef7eb2e8f9f7 2 * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
<> 144:ef7eb2e8f9f7 3 * Project: NXP LPC11xx software example
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Description:
<> 144:ef7eb2e8f9f7 6 * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 7 * NXP LPC11xx Device Series
<> 144:ef7eb2e8f9f7 8
<> 144:ef7eb2e8f9f7 9 ****************************************************************************
<> 144:ef7eb2e8f9f7 10 * Software that is described herein is for illustrative purposes only
<> 144:ef7eb2e8f9f7 11 * which provides customers with programming information regarding the
<> 144:ef7eb2e8f9f7 12 * products. This software is supplied "AS IS" without any warranties.
<> 144:ef7eb2e8f9f7 13 * NXP Semiconductors assumes no responsibility or liability for the
<> 144:ef7eb2e8f9f7 14 * use of the software, conveys no license or title under any patent,
<> 144:ef7eb2e8f9f7 15 * copyright, or mask work right to the product. NXP Semiconductors
<> 144:ef7eb2e8f9f7 16 * reserves the right to make changes in the software without
<> 144:ef7eb2e8f9f7 17 * notification. NXP Semiconductors also make no representation or
<> 144:ef7eb2e8f9f7 18 * warranty that such application will be suitable for the specified
<> 144:ef7eb2e8f9f7 19 * use without further testing or modification.
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 * Permission to use, copy, modify, and distribute this software and its
<> 144:ef7eb2e8f9f7 22 * documentation is hereby granted, under NXP Semiconductors'
<> 144:ef7eb2e8f9f7 23 * relevant copyright in the software, without fee, provided that it
<> 144:ef7eb2e8f9f7 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
<> 144:ef7eb2e8f9f7 25 * copyright, permission, and disclaimer notice must appear in all copies of
<> 144:ef7eb2e8f9f7 26 * this code.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 ****************************************************************************/
<> 144:ef7eb2e8f9f7 29 #ifndef __LPC11xx_H__
<> 144:ef7eb2e8f9f7 30 #define __LPC11xx_H__
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 33 extern "C" {
<> 144:ef7eb2e8f9f7 34 #endif
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /** @addtogroup LPC11xx_Definitions LPC11xx Definitions
<> 144:ef7eb2e8f9f7 37 This file defines all structures and symbols for LPC11xx:
<> 144:ef7eb2e8f9f7 38 - Registers and bitfields
<> 144:ef7eb2e8f9f7 39 - peripheral base address
<> 144:ef7eb2e8f9f7 40 - peripheral ID
<> 144:ef7eb2e8f9f7 41 - PIO definitions
<> 144:ef7eb2e8f9f7 42 @{
<> 144:ef7eb2e8f9f7 43 */
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /******************************************************************************/
<> 144:ef7eb2e8f9f7 47 /* Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 48 /******************************************************************************/
<> 144:ef7eb2e8f9f7 49 /** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
<> 144:ef7eb2e8f9f7 50 Configuration of the Cortex-M0 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 51 @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /*
<> 144:ef7eb2e8f9f7 55 * ==========================================================================
<> 144:ef7eb2e8f9f7 56 * ---------- Interrupt Number Definition -----------------------------------
<> 144:ef7eb2e8f9f7 57 * ==========================================================================
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59 typedef enum IRQn
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
<> 144:ef7eb2e8f9f7 62 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
<> 144:ef7eb2e8f9f7 69 WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
<> 144:ef7eb2e8f9f7 70 WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
<> 144:ef7eb2e8f9f7 71 WAKEUP2_IRQn = 2,
<> 144:ef7eb2e8f9f7 72 WAKEUP3_IRQn = 3,
<> 144:ef7eb2e8f9f7 73 WAKEUP4_IRQn = 4,
<> 144:ef7eb2e8f9f7 74 WAKEUP5_IRQn = 5,
<> 144:ef7eb2e8f9f7 75 WAKEUP6_IRQn = 6,
<> 144:ef7eb2e8f9f7 76 WAKEUP7_IRQn = 7,
<> 144:ef7eb2e8f9f7 77 WAKEUP8_IRQn = 8,
<> 144:ef7eb2e8f9f7 78 WAKEUP9_IRQn = 9,
<> 144:ef7eb2e8f9f7 79 WAKEUP10_IRQn = 10,
<> 144:ef7eb2e8f9f7 80 WAKEUP11_IRQn = 11,
<> 144:ef7eb2e8f9f7 81 WAKEUP12_IRQn = 12,
<> 144:ef7eb2e8f9f7 82 CAN_IRQn = 13, /*!< CAN Interrupt */
<> 144:ef7eb2e8f9f7 83 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
<> 144:ef7eb2e8f9f7 84 I2C_IRQn = 15, /*!< I2C Interrupt */
<> 144:ef7eb2e8f9f7 85 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
<> 144:ef7eb2e8f9f7 86 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
<> 144:ef7eb2e8f9f7 87 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
<> 144:ef7eb2e8f9f7 88 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
<> 144:ef7eb2e8f9f7 89 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
<> 144:ef7eb2e8f9f7 90 UART_IRQn = 21, /*!< UART Interrupt */
<> 144:ef7eb2e8f9f7 91 Reserved0_IRQn = 22, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 92 Reserved1_IRQn = 23,
<> 144:ef7eb2e8f9f7 93 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
<> 144:ef7eb2e8f9f7 94 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
<> 144:ef7eb2e8f9f7 95 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
<> 144:ef7eb2e8f9f7 96 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
<> 144:ef7eb2e8f9f7 97 EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
<> 144:ef7eb2e8f9f7 98 EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
<> 144:ef7eb2e8f9f7 99 EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
<> 144:ef7eb2e8f9f7 100 EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
<> 144:ef7eb2e8f9f7 101 } IRQn_Type;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /*
<> 144:ef7eb2e8f9f7 104 * ==========================================================================
<> 144:ef7eb2e8f9f7 105 * ----------- Processor and Core Peripheral Section ------------------------
<> 144:ef7eb2e8f9f7 106 * ==========================================================================
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 110 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /*@}*/ /* end of group LPC11xx_CMSIS */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
<> 144:ef7eb2e8f9f7 118 #include "system_LPC11xx.h" /* System Header */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /******************************************************************************/
<> 144:ef7eb2e8f9f7 122 /* Device Specific Peripheral Registers structures */
<> 144:ef7eb2e8f9f7 123 /******************************************************************************/
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 126 #pragma anon_unions
<> 144:ef7eb2e8f9f7 127 #endif
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /*------------- System Control (SYSCON) --------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
<> 144:ef7eb2e8f9f7 131 @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 typedef struct
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
<> 144:ef7eb2e8f9f7 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
<> 144:ef7eb2e8f9f7 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
<> 144:ef7eb2e8f9f7 138 __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
<> 144:ef7eb2e8f9f7 139 uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
<> 144:ef7eb2e8f9f7 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
<> 144:ef7eb2e8f9f7 143 __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
<> 144:ef7eb2e8f9f7 144 uint32_t RESERVED1[1];
<> 144:ef7eb2e8f9f7 145 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
<> 144:ef7eb2e8f9f7 146 uint32_t RESERVED2[3];
<> 144:ef7eb2e8f9f7 147 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
<> 144:ef7eb2e8f9f7 148 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 149 uint32_t RESERVED3[10];
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
<> 144:ef7eb2e8f9f7 152 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 153 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
<> 144:ef7eb2e8f9f7 154 uint32_t RESERVED4[1];
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
<> 144:ef7eb2e8f9f7 157 uint32_t RESERVED5[4];
<> 144:ef7eb2e8f9f7 158 __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
<> 144:ef7eb2e8f9f7 159 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
<> 144:ef7eb2e8f9f7 160 __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
<> 144:ef7eb2e8f9f7 161 uint32_t RESERVED6[12];
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
<> 144:ef7eb2e8f9f7 164 __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 165 __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
<> 144:ef7eb2e8f9f7 166 uint32_t RESERVED8[1];
<> 144:ef7eb2e8f9f7 167 __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
<> 144:ef7eb2e8f9f7 168 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
<> 144:ef7eb2e8f9f7 169 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
<> 144:ef7eb2e8f9f7 170 uint32_t RESERVED9[5];
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
<> 144:ef7eb2e8f9f7 173 __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
<> 144:ef7eb2e8f9f7 174 uint32_t RESERVED10[18];
<> 144:ef7eb2e8f9f7 175 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
<> 144:ef7eb2e8f9f7 176 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 uint32_t RESERVED13[7];
<> 144:ef7eb2e8f9f7 179 __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
<> 144:ef7eb2e8f9f7 180 uint32_t RESERVED14[34];
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 183 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 184 __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
<> 144:ef7eb2e8f9f7 185 __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
<> 144:ef7eb2e8f9f7 186 __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
<> 144:ef7eb2e8f9f7 187 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
<> 144:ef7eb2e8f9f7 188 __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
<> 144:ef7eb2e8f9f7 189 __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
<> 144:ef7eb2e8f9f7 190 uint32_t RESERVED17[4];
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
<> 144:ef7eb2e8f9f7 193 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
<> 144:ef7eb2e8f9f7 194 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
<> 144:ef7eb2e8f9f7 195 uint32_t RESERVED15[110];
<> 144:ef7eb2e8f9f7 196 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
<> 144:ef7eb2e8f9f7 197 } LPC_SYSCON_TypeDef;
<> 144:ef7eb2e8f9f7 198 /*@}*/ /* end of group LPC11xx_SYSCON */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /*------------- Pin Connect Block (IOCON) --------------------------------*/
<> 144:ef7eb2e8f9f7 202 /** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
<> 144:ef7eb2e8f9f7 203 @{
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 typedef struct
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
<> 144:ef7eb2e8f9f7 208 uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 209 __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
<> 144:ef7eb2e8f9f7 213 __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
<> 144:ef7eb2e8f9f7 214 __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
<> 144:ef7eb2e8f9f7 217 __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
<> 144:ef7eb2e8f9f7 218 __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
<> 144:ef7eb2e8f9f7 219 __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
<> 144:ef7eb2e8f9f7 222 __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
<> 144:ef7eb2e8f9f7 223 __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
<> 144:ef7eb2e8f9f7 228 __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
<> 144:ef7eb2e8f9f7 229 __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
<> 144:ef7eb2e8f9f7 230 __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
<> 144:ef7eb2e8f9f7 232 __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
<> 144:ef7eb2e8f9f7 235 __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
<> 144:ef7eb2e8f9f7 236 __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
<> 144:ef7eb2e8f9f7 237 __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
<> 144:ef7eb2e8f9f7 238 __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
<> 144:ef7eb2e8f9f7 239 __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
<> 144:ef7eb2e8f9f7 240 __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
<> 144:ef7eb2e8f9f7 241 __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
<> 144:ef7eb2e8f9f7 244 __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
<> 144:ef7eb2e8f9f7 245 __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
<> 144:ef7eb2e8f9f7 246 __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
<> 144:ef7eb2e8f9f7 247 __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
<> 144:ef7eb2e8f9f7 248 __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
<> 144:ef7eb2e8f9f7 249 __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
<> 144:ef7eb2e8f9f7 250 __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
<> 144:ef7eb2e8f9f7 253 __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
<> 144:ef7eb2e8f9f7 254 __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
<> 144:ef7eb2e8f9f7 255 __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
<> 144:ef7eb2e8f9f7 256 __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
<> 144:ef7eb2e8f9f7 257 __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
<> 144:ef7eb2e8f9f7 258 __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
<> 144:ef7eb2e8f9f7 259 __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
<> 144:ef7eb2e8f9f7 262 __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
<> 144:ef7eb2e8f9f7 263 __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
<> 144:ef7eb2e8f9f7 264 __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
<> 144:ef7eb2e8f9f7 265 __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
<> 144:ef7eb2e8f9f7 266 __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
<> 144:ef7eb2e8f9f7 267 } LPC_IOCON_TypeDef;
<> 144:ef7eb2e8f9f7 268 /*@}*/ /* end of group LPC11xx_IOCON */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /*------------- Power Management Unit (PMU) --------------------------*/
<> 144:ef7eb2e8f9f7 272 /** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
<> 144:ef7eb2e8f9f7 273 @{
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 typedef struct
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
<> 144:ef7eb2e8f9f7 278 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 279 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
<> 144:ef7eb2e8f9f7 280 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
<> 144:ef7eb2e8f9f7 282 __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
<> 144:ef7eb2e8f9f7 283 } LPC_PMU_TypeDef;
<> 144:ef7eb2e8f9f7 284 /*@}*/ /* end of group LPC11xx_PMU */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 289 // ----- FLASHCTRL -----
<> 144:ef7eb2e8f9f7 290 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
<> 144:ef7eb2e8f9f7 293 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 294 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
<> 144:ef7eb2e8f9f7 295 __I uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 296 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
<> 144:ef7eb2e8f9f7 297 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
<> 144:ef7eb2e8f9f7 298 __I uint32_t RESERVED2[1];
<> 144:ef7eb2e8f9f7 299 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
<> 144:ef7eb2e8f9f7 300 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
<> 144:ef7eb2e8f9f7 301 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
<> 144:ef7eb2e8f9f7 302 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
<> 144:ef7eb2e8f9f7 303 __I uint32_t RESERVED3[1001];
<> 144:ef7eb2e8f9f7 304 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
<> 144:ef7eb2e8f9f7 305 __I uint32_t RESERVED4[1];
<> 144:ef7eb2e8f9f7 306 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
<> 144:ef7eb2e8f9f7 307 } LPC_FLASHCTRL_Type;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
<> 144:ef7eb2e8f9f7 311 /** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
<> 144:ef7eb2e8f9f7 312 @{
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 typedef struct
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 union {
<> 144:ef7eb2e8f9f7 317 __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
<> 144:ef7eb2e8f9f7 318 struct {
<> 144:ef7eb2e8f9f7 319 uint32_t RESERVED0[4095];
<> 144:ef7eb2e8f9f7 320 __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
<> 144:ef7eb2e8f9f7 321 };
<> 144:ef7eb2e8f9f7 322 };
<> 144:ef7eb2e8f9f7 323 uint32_t RESERVED1[4096];
<> 144:ef7eb2e8f9f7 324 __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
<> 144:ef7eb2e8f9f7 325 __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
<> 144:ef7eb2e8f9f7 326 __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
<> 144:ef7eb2e8f9f7 327 __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
<> 144:ef7eb2e8f9f7 328 __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
<> 144:ef7eb2e8f9f7 329 __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
<> 144:ef7eb2e8f9f7 330 __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
<> 144:ef7eb2e8f9f7 331 __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */
<> 144:ef7eb2e8f9f7 332 } LPC_GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 333 /*@}*/ /* end of group LPC11xx_GPIO */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /*------------- Timer (TMR) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 336 /** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
<> 144:ef7eb2e8f9f7 337 @{
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 typedef struct
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
<> 144:ef7eb2e8f9f7 342 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
<> 144:ef7eb2e8f9f7 343 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
<> 144:ef7eb2e8f9f7 344 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
<> 144:ef7eb2e8f9f7 345 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
<> 144:ef7eb2e8f9f7 346 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
<> 144:ef7eb2e8f9f7 347 union {
<> 144:ef7eb2e8f9f7 348 __IO uint32_t MR[4]; /*!< Offset: Match Register base */
<> 144:ef7eb2e8f9f7 349 struct{
<> 144:ef7eb2e8f9f7 350 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
<> 144:ef7eb2e8f9f7 353 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
<> 144:ef7eb2e8f9f7 354 };
<> 144:ef7eb2e8f9f7 355 };
<> 144:ef7eb2e8f9f7 356 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
<> 144:ef7eb2e8f9f7 357 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
<> 144:ef7eb2e8f9f7 358 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
<> 144:ef7eb2e8f9f7 359 uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 360 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
<> 144:ef7eb2e8f9f7 361 uint32_t RESERVED2[12];
<> 144:ef7eb2e8f9f7 362 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
<> 144:ef7eb2e8f9f7 364 } LPC_TMR_TypeDef;
<> 144:ef7eb2e8f9f7 365 /*@}*/ /* end of group LPC11xx_TMR */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
<> 144:ef7eb2e8f9f7 369 /** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
<> 144:ef7eb2e8f9f7 370 @{
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 typedef struct
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 union {
<> 144:ef7eb2e8f9f7 375 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
<> 144:ef7eb2e8f9f7 376 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
<> 144:ef7eb2e8f9f7 378 };
<> 144:ef7eb2e8f9f7 379 union {
<> 144:ef7eb2e8f9f7 380 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
<> 144:ef7eb2e8f9f7 381 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
<> 144:ef7eb2e8f9f7 382 };
<> 144:ef7eb2e8f9f7 383 union {
<> 144:ef7eb2e8f9f7 384 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
<> 144:ef7eb2e8f9f7 385 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
<> 144:ef7eb2e8f9f7 386 };
<> 144:ef7eb2e8f9f7 387 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
<> 144:ef7eb2e8f9f7 389 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 390 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
<> 144:ef7eb2e8f9f7 391 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
<> 144:ef7eb2e8f9f7 392 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
<> 144:ef7eb2e8f9f7 393 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 394 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
<> 144:ef7eb2e8f9f7 395 uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 396 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
<> 144:ef7eb2e8f9f7 397 uint32_t RESERVED2[6];
<> 144:ef7eb2e8f9f7 398 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
<> 144:ef7eb2e8f9f7 399 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
<> 144:ef7eb2e8f9f7 400 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
<> 144:ef7eb2e8f9f7 401 __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */
<> 144:ef7eb2e8f9f7 402 } LPC_UART_TypeDef;
<> 144:ef7eb2e8f9f7 403 /*@}*/ /* end of group LPC11xx_UART */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
<> 144:ef7eb2e8f9f7 407 /** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
<> 144:ef7eb2e8f9f7 408 @{
<> 144:ef7eb2e8f9f7 409 */
<> 144:ef7eb2e8f9f7 410 typedef struct
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
<> 144:ef7eb2e8f9f7 414 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
<> 144:ef7eb2e8f9f7 415 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
<> 144:ef7eb2e8f9f7 416 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
<> 144:ef7eb2e8f9f7 417 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
<> 144:ef7eb2e8f9f7 418 __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
<> 144:ef7eb2e8f9f7 419 __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
<> 144:ef7eb2e8f9f7 420 __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
<> 144:ef7eb2e8f9f7 421 } LPC_SSP_TypeDef;
<> 144:ef7eb2e8f9f7 422 /*@}*/ /* end of group LPC11xx_SSP */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
<> 144:ef7eb2e8f9f7 426 /** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
<> 144:ef7eb2e8f9f7 427 @{
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 typedef struct
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
<> 144:ef7eb2e8f9f7 432 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 433 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
<> 144:ef7eb2e8f9f7 434 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
<> 144:ef7eb2e8f9f7 435 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
<> 144:ef7eb2e8f9f7 436 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
<> 144:ef7eb2e8f9f7 437 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
<> 144:ef7eb2e8f9f7 438 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
<> 144:ef7eb2e8f9f7 439 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
<> 144:ef7eb2e8f9f7 440 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
<> 144:ef7eb2e8f9f7 441 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
<> 144:ef7eb2e8f9f7 442 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
<> 144:ef7eb2e8f9f7 443 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
<> 144:ef7eb2e8f9f7 444 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
<> 144:ef7eb2e8f9f7 445 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
<> 144:ef7eb2e8f9f7 446 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
<> 144:ef7eb2e8f9f7 447 } LPC_I2C_TypeDef;
<> 144:ef7eb2e8f9f7 448 /*@}*/ /* end of group LPC11xx_I2C */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
<> 144:ef7eb2e8f9f7 452 /** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
<> 144:ef7eb2e8f9f7 453 @{
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 typedef struct
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
<> 144:ef7eb2e8f9f7 458 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
<> 144:ef7eb2e8f9f7 459 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
<> 144:ef7eb2e8f9f7 460 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
<> 144:ef7eb2e8f9f7 461 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 462 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
<> 144:ef7eb2e8f9f7 464 } LPC_WDT_TypeDef;
<> 144:ef7eb2e8f9f7 465 /*@}*/ /* end of group LPC11xx_WDT */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
<> 144:ef7eb2e8f9f7 469 /** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
<> 144:ef7eb2e8f9f7 470 @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 typedef struct
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
<> 144:ef7eb2e8f9f7 476 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 477 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
<> 144:ef7eb2e8f9f7 478 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
<> 144:ef7eb2e8f9f7 479 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 480 } LPC_ADC_TypeDef;
<> 144:ef7eb2e8f9f7 481 /*@}*/ /* end of group LPC11xx_ADC */
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /*------------- CAN Controller (CAN) ----------------------------*/
<> 144:ef7eb2e8f9f7 485 /** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
<> 144:ef7eb2e8f9f7 486 @{
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 typedef struct
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 __IO uint32_t CNTL; /* 0x000 */
<> 144:ef7eb2e8f9f7 491 __IO uint32_t STAT;
<> 144:ef7eb2e8f9f7 492 __IO uint32_t EC;
<> 144:ef7eb2e8f9f7 493 __IO uint32_t BT;
<> 144:ef7eb2e8f9f7 494 __IO uint32_t INT;
<> 144:ef7eb2e8f9f7 495 __IO uint32_t TEST;
<> 144:ef7eb2e8f9f7 496 __IO uint32_t BRPE;
<> 144:ef7eb2e8f9f7 497 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 498 __IO uint32_t IF1_CMDREQ; /* 0x020 */
<> 144:ef7eb2e8f9f7 499 __IO uint32_t IF1_CMDMSK;
<> 144:ef7eb2e8f9f7 500 __IO uint32_t IF1_MSK1;
<> 144:ef7eb2e8f9f7 501 __IO uint32_t IF1_MSK2;
<> 144:ef7eb2e8f9f7 502 __IO uint32_t IF1_ARB1;
<> 144:ef7eb2e8f9f7 503 __IO uint32_t IF1_ARB2;
<> 144:ef7eb2e8f9f7 504 __IO uint32_t IF1_MCTRL;
<> 144:ef7eb2e8f9f7 505 __IO uint32_t IF1_DA1;
<> 144:ef7eb2e8f9f7 506 __IO uint32_t IF1_DA2;
<> 144:ef7eb2e8f9f7 507 __IO uint32_t IF1_DB1;
<> 144:ef7eb2e8f9f7 508 __IO uint32_t IF1_DB2;
<> 144:ef7eb2e8f9f7 509 uint32_t RESERVED1[13];
<> 144:ef7eb2e8f9f7 510 __IO uint32_t IF2_CMDREQ; /* 0x080 */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t IF2_CMDMSK;
<> 144:ef7eb2e8f9f7 512 __IO uint32_t IF2_MSK1;
<> 144:ef7eb2e8f9f7 513 __IO uint32_t IF2_MSK2;
<> 144:ef7eb2e8f9f7 514 __IO uint32_t IF2_ARB1;
<> 144:ef7eb2e8f9f7 515 __IO uint32_t IF2_ARB2;
<> 144:ef7eb2e8f9f7 516 __IO uint32_t IF2_MCTRL;
<> 144:ef7eb2e8f9f7 517 __IO uint32_t IF2_DA1;
<> 144:ef7eb2e8f9f7 518 __IO uint32_t IF2_DA2;
<> 144:ef7eb2e8f9f7 519 __IO uint32_t IF2_DB1;
<> 144:ef7eb2e8f9f7 520 __IO uint32_t IF2_DB2;
<> 144:ef7eb2e8f9f7 521 uint32_t RESERVED2[21];
<> 144:ef7eb2e8f9f7 522 __I uint32_t TXREQ1; /* 0x100 */
<> 144:ef7eb2e8f9f7 523 __I uint32_t TXREQ2;
<> 144:ef7eb2e8f9f7 524 uint32_t RESERVED3[6];
<> 144:ef7eb2e8f9f7 525 __I uint32_t ND1; /* 0x120 */
<> 144:ef7eb2e8f9f7 526 __I uint32_t ND2;
<> 144:ef7eb2e8f9f7 527 uint32_t RESERVED4[6];
<> 144:ef7eb2e8f9f7 528 __I uint32_t IR1; /* 0x140 */
<> 144:ef7eb2e8f9f7 529 __I uint32_t IR2;
<> 144:ef7eb2e8f9f7 530 uint32_t RESERVED5[6];
<> 144:ef7eb2e8f9f7 531 __I uint32_t MSGV1; /* 0x160 */
<> 144:ef7eb2e8f9f7 532 __I uint32_t MSGV2;
<> 144:ef7eb2e8f9f7 533 uint32_t RESERVED6[6];
<> 144:ef7eb2e8f9f7 534 __IO uint32_t CLKDIV; /* 0x180 */
<> 144:ef7eb2e8f9f7 535 } LPC_CAN_TypeDef;
<> 144:ef7eb2e8f9f7 536 /*@}*/ /* end of group LPC11xx_CAN */
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 539 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 540 #endif
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /******************************************************************************/
<> 144:ef7eb2e8f9f7 543 /* Peripheral memory map */
<> 144:ef7eb2e8f9f7 544 /******************************************************************************/
<> 144:ef7eb2e8f9f7 545 /* Base addresses */
<> 144:ef7eb2e8f9f7 546 #define LPC_FLASH_BASE (0x00000000UL)
<> 144:ef7eb2e8f9f7 547 #define LPC_RAM_BASE (0x10000000UL)
<> 144:ef7eb2e8f9f7 548 #define LPC_APB0_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 549 #define LPC_AHB_BASE (0x50000000UL)
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* APB0 peripherals */
<> 144:ef7eb2e8f9f7 552 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 553 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
<> 144:ef7eb2e8f9f7 554 #define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
<> 144:ef7eb2e8f9f7 555 #define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
<> 144:ef7eb2e8f9f7 556 #define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
<> 144:ef7eb2e8f9f7 557 #define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
<> 144:ef7eb2e8f9f7 558 #define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
<> 144:ef7eb2e8f9f7 559 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
<> 144:ef7eb2e8f9f7 560 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
<> 144:ef7eb2e8f9f7 561 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000)
<> 144:ef7eb2e8f9f7 562 #define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
<> 144:ef7eb2e8f9f7 563 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
<> 144:ef7eb2e8f9f7 564 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
<> 144:ef7eb2e8f9f7 565 #define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
<> 144:ef7eb2e8f9f7 566 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* AHB peripherals */
<> 144:ef7eb2e8f9f7 569 #define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 570 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 571 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
<> 144:ef7eb2e8f9f7 572 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
<> 144:ef7eb2e8f9f7 573 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /******************************************************************************/
<> 144:ef7eb2e8f9f7 576 /* Peripheral declaration */
<> 144:ef7eb2e8f9f7 577 /******************************************************************************/
<> 144:ef7eb2e8f9f7 578 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
<> 144:ef7eb2e8f9f7 579 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
<> 144:ef7eb2e8f9f7 580 #define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
<> 144:ef7eb2e8f9f7 581 #define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
<> 144:ef7eb2e8f9f7 582 #define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
<> 144:ef7eb2e8f9f7 583 #define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
<> 144:ef7eb2e8f9f7 584 #define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
<> 144:ef7eb2e8f9f7 585 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
<> 144:ef7eb2e8f9f7 586 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
<> 144:ef7eb2e8f9f7 587 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<> 144:ef7eb2e8f9f7 588 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
<> 144:ef7eb2e8f9f7 589 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
<> 144:ef7eb2e8f9f7 590 #define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
<> 144:ef7eb2e8f9f7 591 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
<> 144:ef7eb2e8f9f7 592 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
<> 144:ef7eb2e8f9f7 593 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
<> 144:ef7eb2e8f9f7 594 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
<> 144:ef7eb2e8f9f7 595 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
<> 144:ef7eb2e8f9f7 596 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600 #endif
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #endif /* __LPC11xx_H__ */