Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1
<> 144:ef7eb2e8f9f7 2 /****************************************************************************************************//**
<> 144:ef7eb2e8f9f7 3 * @file LPC11Uxx.h
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 7 * default LPC11Uxx Device Series
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * @version V0.1
<> 144:ef7eb2e8f9f7 10 * @date 21. March 2011
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
<> 144:ef7eb2e8f9f7 15 * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 *******************************************************************************************************/
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 // ################################################################################
<> 144:ef7eb2e8f9f7 20 // Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
<> 144:ef7eb2e8f9f7 21 // ################################################################################
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /** @addtogroup NXP
<> 144:ef7eb2e8f9f7 24 * @{
<> 144:ef7eb2e8f9f7 25 */
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 /** @addtogroup LPC11Uxx
<> 144:ef7eb2e8f9f7 28 * @{
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef __LPC11UXX_H__
<> 144:ef7eb2e8f9f7 32 #define __LPC11UXX_H__
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 35 extern "C" {
<> 144:ef7eb2e8f9f7 36 #endif
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 40 #pragma anon_unions
<> 144:ef7eb2e8f9f7 41 #endif
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Interrupt Number Definition */
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 typedef enum {
<> 144:ef7eb2e8f9f7 46 // ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
<> 144:ef7eb2e8f9f7 47 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
<> 144:ef7eb2e8f9f7 48 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
<> 144:ef7eb2e8f9f7 49 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
<> 144:ef7eb2e8f9f7 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
<> 144:ef7eb2e8f9f7 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
<> 144:ef7eb2e8f9f7 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
<> 144:ef7eb2e8f9f7 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
<> 144:ef7eb2e8f9f7 54 // --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
<> 144:ef7eb2e8f9f7 55 FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
<> 144:ef7eb2e8f9f7 56 FLEX_INT1_IRQn = 1,
<> 144:ef7eb2e8f9f7 57 FLEX_INT2_IRQn = 2,
<> 144:ef7eb2e8f9f7 58 FLEX_INT3_IRQn = 3,
<> 144:ef7eb2e8f9f7 59 FLEX_INT4_IRQn = 4,
<> 144:ef7eb2e8f9f7 60 FLEX_INT5_IRQn = 5,
<> 144:ef7eb2e8f9f7 61 FLEX_INT6_IRQn = 6,
<> 144:ef7eb2e8f9f7 62 FLEX_INT7_IRQn = 7,
<> 144:ef7eb2e8f9f7 63 GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
<> 144:ef7eb2e8f9f7 64 GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
<> 144:ef7eb2e8f9f7 65 Reserved0_IRQn = 10, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 66 Reserved1_IRQn = 11,
<> 144:ef7eb2e8f9f7 67 Reserved2_IRQn = 12,
<> 144:ef7eb2e8f9f7 68 Reserved3_IRQn = 13,
<> 144:ef7eb2e8f9f7 69 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
<> 144:ef7eb2e8f9f7 70 I2C_IRQn = 15, /*!< I2C Interrupt */
<> 144:ef7eb2e8f9f7 71 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
<> 144:ef7eb2e8f9f7 72 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
<> 144:ef7eb2e8f9f7 73 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
<> 144:ef7eb2e8f9f7 74 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
<> 144:ef7eb2e8f9f7 75 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
<> 144:ef7eb2e8f9f7 76 UART_IRQn = 21, /*!< UART Interrupt */
<> 144:ef7eb2e8f9f7 77 USB_IRQn = 22, /*!< USB IRQ Interrupt */
<> 144:ef7eb2e8f9f7 78 USB_FIQn = 23, /*!< USB FIQ Interrupt */
<> 144:ef7eb2e8f9f7 79 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
<> 144:ef7eb2e8f9f7 80 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
<> 144:ef7eb2e8f9f7 81 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
<> 144:ef7eb2e8f9f7 82 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
<> 144:ef7eb2e8f9f7 83 Reserved4_IRQn = 28, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 84 Reserved5_IRQn = 29, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 85 USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
<> 144:ef7eb2e8f9f7 86 Reserved6_IRQn = 31, /*!< Reserved Interrupt */
<> 144:ef7eb2e8f9f7 87 } IRQn_Type;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @addtogroup Configuration_of_CMSIS
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 97 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 99 /** @} */ /* End of group Configuration_of_CMSIS */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
<> 144:ef7eb2e8f9f7 102 #include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @addtogroup Device_Peripheral_Registers
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 110 // ----- I2C -----
<> 144:ef7eb2e8f9f7 111 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /**
<> 144:ef7eb2e8f9f7 115 * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 typedef struct { /*!< (@ 0x40000000) I2C Structure */
<> 144:ef7eb2e8f9f7 119 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
<> 144:ef7eb2e8f9f7 120 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
<> 144:ef7eb2e8f9f7 121 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
<> 144:ef7eb2e8f9f7 122 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
<> 144:ef7eb2e8f9f7 123 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
<> 144:ef7eb2e8f9f7 124 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
<> 144:ef7eb2e8f9f7 125 __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
<> 144:ef7eb2e8f9f7 126 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
<> 144:ef7eb2e8f9f7 127 __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
<> 144:ef7eb2e8f9f7 128 __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
<> 144:ef7eb2e8f9f7 129 __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
<> 144:ef7eb2e8f9f7 130 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
<> 144:ef7eb2e8f9f7 131 union{
<> 144:ef7eb2e8f9f7 132 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
<> 144:ef7eb2e8f9f7 133 struct{
<> 144:ef7eb2e8f9f7 134 __IO uint32_t MASK0;
<> 144:ef7eb2e8f9f7 135 __IO uint32_t MASK1;
<> 144:ef7eb2e8f9f7 136 __IO uint32_t MASK2;
<> 144:ef7eb2e8f9f7 137 __IO uint32_t MASK3;
<> 144:ef7eb2e8f9f7 138 };
<> 144:ef7eb2e8f9f7 139 };
<> 144:ef7eb2e8f9f7 140 } LPC_I2C_Type;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 144 // ----- WWDT -----
<> 144:ef7eb2e8f9f7 145 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
<> 144:ef7eb2e8f9f7 153 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
<> 144:ef7eb2e8f9f7 154 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
<> 144:ef7eb2e8f9f7 155 __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
<> 144:ef7eb2e8f9f7 156 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
<> 144:ef7eb2e8f9f7 157 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
<> 144:ef7eb2e8f9f7 158 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
<> 144:ef7eb2e8f9f7 159 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
<> 144:ef7eb2e8f9f7 160 } LPC_WWDT_Type;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 164 // ----- USART -----
<> 144:ef7eb2e8f9f7 165 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 typedef struct { /*!< (@ 0x40008000) USART Structure */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 union {
<> 144:ef7eb2e8f9f7 175 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
<> 144:ef7eb2e8f9f7 176 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
<> 144:ef7eb2e8f9f7 177 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
<> 144:ef7eb2e8f9f7 178 };
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 union {
<> 144:ef7eb2e8f9f7 181 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
<> 144:ef7eb2e8f9f7 182 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
<> 144:ef7eb2e8f9f7 183 };
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 union {
<> 144:ef7eb2e8f9f7 186 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
<> 144:ef7eb2e8f9f7 187 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
<> 144:ef7eb2e8f9f7 188 };
<> 144:ef7eb2e8f9f7 189 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
<> 144:ef7eb2e8f9f7 190 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
<> 144:ef7eb2e8f9f7 191 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
<> 144:ef7eb2e8f9f7 192 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
<> 144:ef7eb2e8f9f7 193 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
<> 144:ef7eb2e8f9f7 194 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
<> 144:ef7eb2e8f9f7 195 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
<> 144:ef7eb2e8f9f7 196 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
<> 144:ef7eb2e8f9f7 197 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
<> 144:ef7eb2e8f9f7 198 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
<> 144:ef7eb2e8f9f7 199 __I uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 200 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
<> 144:ef7eb2e8f9f7 201 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 202 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
<> 144:ef7eb2e8f9f7 203 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
<> 144:ef7eb2e8f9f7 204 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
<> 144:ef7eb2e8f9f7 205 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
<> 144:ef7eb2e8f9f7 206 __IO uint32_t SYNCCTRL;
<> 144:ef7eb2e8f9f7 207 } LPC_USART_Type;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 211 // ----- Timer -----
<> 144:ef7eb2e8f9f7 212 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
<> 144:ef7eb2e8f9f7 222 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
<> 144:ef7eb2e8f9f7 223 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
<> 144:ef7eb2e8f9f7 224 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
<> 144:ef7eb2e8f9f7 226 union {
<> 144:ef7eb2e8f9f7 227 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
<> 144:ef7eb2e8f9f7 228 struct{
<> 144:ef7eb2e8f9f7 229 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
<> 144:ef7eb2e8f9f7 230 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
<> 144:ef7eb2e8f9f7 232 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
<> 144:ef7eb2e8f9f7 233 };
<> 144:ef7eb2e8f9f7 234 };
<> 144:ef7eb2e8f9f7 235 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
<> 144:ef7eb2e8f9f7 236 union{
<> 144:ef7eb2e8f9f7 237 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
<> 144:ef7eb2e8f9f7 238 struct{
<> 144:ef7eb2e8f9f7 239 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
<> 144:ef7eb2e8f9f7 240 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
<> 144:ef7eb2e8f9f7 241 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
<> 144:ef7eb2e8f9f7 242 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
<> 144:ef7eb2e8f9f7 243 };
<> 144:ef7eb2e8f9f7 244 };
<> 144:ef7eb2e8f9f7 245 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
<> 144:ef7eb2e8f9f7 246 __I uint32_t RESERVED0[12];
<> 144:ef7eb2e8f9f7 247 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
<> 144:ef7eb2e8f9f7 248 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
<> 144:ef7eb2e8f9f7 249 } LPC_CTxxBx_Type;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 254 // ----- ADC -----
<> 144:ef7eb2e8f9f7 255 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
<> 144:ef7eb2e8f9f7 263 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
<> 144:ef7eb2e8f9f7 264 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
<> 144:ef7eb2e8f9f7 265 __I uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 266 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 267 union{
<> 144:ef7eb2e8f9f7 268 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
<> 144:ef7eb2e8f9f7 269 struct{
<> 144:ef7eb2e8f9f7 270 __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
<> 144:ef7eb2e8f9f7 271 __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
<> 144:ef7eb2e8f9f7 272 __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
<> 144:ef7eb2e8f9f7 273 __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
<> 144:ef7eb2e8f9f7 274 __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
<> 144:ef7eb2e8f9f7 275 __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
<> 144:ef7eb2e8f9f7 276 __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
<> 144:ef7eb2e8f9f7 277 __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
<> 144:ef7eb2e8f9f7 278 };
<> 144:ef7eb2e8f9f7 279 };
<> 144:ef7eb2e8f9f7 280 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
<> 144:ef7eb2e8f9f7 281 } LPC_ADC_Type;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 285 // ----- PMU -----
<> 144:ef7eb2e8f9f7 286 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 typedef struct { /*!< (@ 0x40038000) PMU Structure */
<> 144:ef7eb2e8f9f7 294 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
<> 144:ef7eb2e8f9f7 295 union{
<> 144:ef7eb2e8f9f7 296 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
<> 144:ef7eb2e8f9f7 297 struct{
<> 144:ef7eb2e8f9f7 298 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
<> 144:ef7eb2e8f9f7 299 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
<> 144:ef7eb2e8f9f7 300 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
<> 144:ef7eb2e8f9f7 301 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
<> 144:ef7eb2e8f9f7 302 };
<> 144:ef7eb2e8f9f7 303 };
<> 144:ef7eb2e8f9f7 304 } LPC_PMU_Type;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 308 // ----- FLASHCTRL -----
<> 144:ef7eb2e8f9f7 309 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
<> 144:ef7eb2e8f9f7 317 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 318 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
<> 144:ef7eb2e8f9f7 319 __I uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 320 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
<> 144:ef7eb2e8f9f7 321 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
<> 144:ef7eb2e8f9f7 322 __I uint32_t RESERVED2[1];
<> 144:ef7eb2e8f9f7 323 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
<> 144:ef7eb2e8f9f7 324 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
<> 144:ef7eb2e8f9f7 325 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
<> 144:ef7eb2e8f9f7 326 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
<> 144:ef7eb2e8f9f7 327 __I uint32_t RESERVED3[1001];
<> 144:ef7eb2e8f9f7 328 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
<> 144:ef7eb2e8f9f7 329 __I uint32_t RESERVED4[1];
<> 144:ef7eb2e8f9f7 330 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
<> 144:ef7eb2e8f9f7 331 } LPC_FLASHCTRL_Type;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 335 // ----- SSP0/1 -----
<> 144:ef7eb2e8f9f7 336 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /**
<> 144:ef7eb2e8f9f7 340 * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
<> 144:ef7eb2e8f9f7 344 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
<> 144:ef7eb2e8f9f7 345 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
<> 144:ef7eb2e8f9f7 346 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
<> 144:ef7eb2e8f9f7 347 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
<> 144:ef7eb2e8f9f7 348 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
<> 144:ef7eb2e8f9f7 349 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
<> 144:ef7eb2e8f9f7 350 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
<> 144:ef7eb2e8f9f7 351 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 353 } LPC_SSPx_Type;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 358 // ----- IOCONFIG -----
<> 144:ef7eb2e8f9f7 359 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
<> 144:ef7eb2e8f9f7 367 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
<> 144:ef7eb2e8f9f7 368 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
<> 144:ef7eb2e8f9f7 369 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
<> 144:ef7eb2e8f9f7 370 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
<> 144:ef7eb2e8f9f7 371 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
<> 144:ef7eb2e8f9f7 372 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
<> 144:ef7eb2e8f9f7 373 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
<> 144:ef7eb2e8f9f7 374 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
<> 144:ef7eb2e8f9f7 375 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
<> 144:ef7eb2e8f9f7 376 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
<> 144:ef7eb2e8f9f7 378 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
<> 144:ef7eb2e8f9f7 379 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
<> 144:ef7eb2e8f9f7 381 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
<> 144:ef7eb2e8f9f7 382 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
<> 144:ef7eb2e8f9f7 383 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
<> 144:ef7eb2e8f9f7 384 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
<> 144:ef7eb2e8f9f7 385 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
<> 144:ef7eb2e8f9f7 386 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
<> 144:ef7eb2e8f9f7 387 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
<> 144:ef7eb2e8f9f7 389 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
<> 144:ef7eb2e8f9f7 390 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
<> 144:ef7eb2e8f9f7 391 __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
<> 144:ef7eb2e8f9f7 392 __IO uint32_t PIO1_1;
<> 144:ef7eb2e8f9f7 393 __IO uint32_t PIO1_2;
<> 144:ef7eb2e8f9f7 394 __IO uint32_t PIO1_3;
<> 144:ef7eb2e8f9f7 395 __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
<> 144:ef7eb2e8f9f7 396 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
<> 144:ef7eb2e8f9f7 397 __IO uint32_t PIO1_6;
<> 144:ef7eb2e8f9f7 398 __IO uint32_t PIO1_7;
<> 144:ef7eb2e8f9f7 399 __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
<> 144:ef7eb2e8f9f7 400 __IO uint32_t PIO1_9;
<> 144:ef7eb2e8f9f7 401 __IO uint32_t PIO1_10;
<> 144:ef7eb2e8f9f7 402 __IO uint32_t PIO1_11;
<> 144:ef7eb2e8f9f7 403 __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
<> 144:ef7eb2e8f9f7 404 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
<> 144:ef7eb2e8f9f7 405 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
<> 144:ef7eb2e8f9f7 406 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
<> 144:ef7eb2e8f9f7 407 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
<> 144:ef7eb2e8f9f7 408 __IO uint32_t PIO1_17;
<> 144:ef7eb2e8f9f7 409 __IO uint32_t PIO1_18;
<> 144:ef7eb2e8f9f7 410 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
<> 144:ef7eb2e8f9f7 411 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
<> 144:ef7eb2e8f9f7 412 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
<> 144:ef7eb2e8f9f7 414 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
<> 144:ef7eb2e8f9f7 415 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
<> 144:ef7eb2e8f9f7 416 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
<> 144:ef7eb2e8f9f7 417 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
<> 144:ef7eb2e8f9f7 418 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
<> 144:ef7eb2e8f9f7 419 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
<> 144:ef7eb2e8f9f7 420 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
<> 144:ef7eb2e8f9f7 421 __IO uint32_t PIO1_30;
<> 144:ef7eb2e8f9f7 422 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
<> 144:ef7eb2e8f9f7 423 } LPC_IOCON_Type;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 427 // ----- SYSCON -----
<> 144:ef7eb2e8f9f7 428 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
<> 144:ef7eb2e8f9f7 436 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
<> 144:ef7eb2e8f9f7 437 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
<> 144:ef7eb2e8f9f7 438 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
<> 144:ef7eb2e8f9f7 439 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
<> 144:ef7eb2e8f9f7 440 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
<> 144:ef7eb2e8f9f7 441 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
<> 144:ef7eb2e8f9f7 442 __I uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 443 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
<> 144:ef7eb2e8f9f7 444 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
<> 144:ef7eb2e8f9f7 445 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 446 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
<> 144:ef7eb2e8f9f7 447 __I uint32_t RESERVED2[3];
<> 144:ef7eb2e8f9f7 448 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
<> 144:ef7eb2e8f9f7 449 __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
<> 144:ef7eb2e8f9f7 450 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
<> 144:ef7eb2e8f9f7 451 __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
<> 144:ef7eb2e8f9f7 452 __I uint32_t RESERVED3[8];
<> 144:ef7eb2e8f9f7 453 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
<> 144:ef7eb2e8f9f7 454 __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
<> 144:ef7eb2e8f9f7 455 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
<> 144:ef7eb2e8f9f7 456 __I uint32_t RESERVED4[1];
<> 144:ef7eb2e8f9f7 457 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
<> 144:ef7eb2e8f9f7 458 __I uint32_t RESERVED5[4];
<> 144:ef7eb2e8f9f7 459 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
<> 144:ef7eb2e8f9f7 460 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
<> 144:ef7eb2e8f9f7 462 __I uint32_t RESERVED6[8];
<> 144:ef7eb2e8f9f7 463 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
<> 144:ef7eb2e8f9f7 464 __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
<> 144:ef7eb2e8f9f7 465 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
<> 144:ef7eb2e8f9f7 466 __I uint32_t RESERVED7[5];
<> 144:ef7eb2e8f9f7 467 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
<> 144:ef7eb2e8f9f7 468 __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
<> 144:ef7eb2e8f9f7 469 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
<> 144:ef7eb2e8f9f7 470 __I uint32_t RESERVED8[5];
<> 144:ef7eb2e8f9f7 471 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
<> 144:ef7eb2e8f9f7 472 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
<> 144:ef7eb2e8f9f7 473 __I uint32_t RESERVED9[18];
<> 144:ef7eb2e8f9f7 474 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
<> 144:ef7eb2e8f9f7 476 __I uint32_t RESERVED10[6];
<> 144:ef7eb2e8f9f7 477 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
<> 144:ef7eb2e8f9f7 478 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
<> 144:ef7eb2e8f9f7 479 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 480 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
<> 144:ef7eb2e8f9f7 481 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
<> 144:ef7eb2e8f9f7 482 __I uint32_t RESERVED11[25];
<> 144:ef7eb2e8f9f7 483 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
<> 144:ef7eb2e8f9f7 484 __I uint32_t RESERVED12[3];
<> 144:ef7eb2e8f9f7 485 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
<> 144:ef7eb2e8f9f7 486 __I uint32_t RESERVED13[6];
<> 144:ef7eb2e8f9f7 487 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
<> 144:ef7eb2e8f9f7 488 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
<> 144:ef7eb2e8f9f7 489 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
<> 144:ef7eb2e8f9f7 490 __I uint32_t RESERVED14[110];
<> 144:ef7eb2e8f9f7 491 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
<> 144:ef7eb2e8f9f7 492 } LPC_SYSCON_Type;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 496 // ----- GPIO_PIN_INT -----
<> 144:ef7eb2e8f9f7 497 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /**
<> 144:ef7eb2e8f9f7 501 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
<> 144:ef7eb2e8f9f7 510 __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
<> 144:ef7eb2e8f9f7 512 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
<> 144:ef7eb2e8f9f7 513 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
<> 144:ef7eb2e8f9f7 514 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
<> 144:ef7eb2e8f9f7 515 } LPC_GPIO_PIN_INT_Type;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 519 // ----- GPIO_GROUP_INT0/1 -----
<> 144:ef7eb2e8f9f7 520 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /**
<> 144:ef7eb2e8f9f7 524 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
<> 144:ef7eb2e8f9f7 528 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
<> 144:ef7eb2e8f9f7 529 __I uint32_t RESERVED0[7];
<> 144:ef7eb2e8f9f7 530 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
<> 144:ef7eb2e8f9f7 531 __I uint32_t RESERVED1[6];
<> 144:ef7eb2e8f9f7 532 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
<> 144:ef7eb2e8f9f7 533 } LPC_GPIO_GROUP_INTx_Type;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 538 // ----- USB -----
<> 144:ef7eb2e8f9f7 539 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 typedef struct { /*!< (@ 0x40080000) USB Structure */
<> 144:ef7eb2e8f9f7 547 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
<> 144:ef7eb2e8f9f7 548 __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
<> 144:ef7eb2e8f9f7 549 __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
<> 144:ef7eb2e8f9f7 550 __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
<> 144:ef7eb2e8f9f7 551 __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
<> 144:ef7eb2e8f9f7 552 __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
<> 144:ef7eb2e8f9f7 553 __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
<> 144:ef7eb2e8f9f7 554 __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
<> 144:ef7eb2e8f9f7 555 __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
<> 144:ef7eb2e8f9f7 556 __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
<> 144:ef7eb2e8f9f7 557 __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
<> 144:ef7eb2e8f9f7 558 __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
<> 144:ef7eb2e8f9f7 559 __I uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 560 __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
<> 144:ef7eb2e8f9f7 561 } LPC_USB_Type;
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 565 // ----- GPIO_PORT -----
<> 144:ef7eb2e8f9f7 566 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 typedef struct {
<> 144:ef7eb2e8f9f7 574 union {
<> 144:ef7eb2e8f9f7 575 struct {
<> 144:ef7eb2e8f9f7 576 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
<> 144:ef7eb2e8f9f7 577 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
<> 144:ef7eb2e8f9f7 578 };
<> 144:ef7eb2e8f9f7 579 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
<> 144:ef7eb2e8f9f7 580 };
<> 144:ef7eb2e8f9f7 581 __I uint32_t RESERVED0[1008];
<> 144:ef7eb2e8f9f7 582 union {
<> 144:ef7eb2e8f9f7 583 struct {
<> 144:ef7eb2e8f9f7 584 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 585 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
<> 144:ef7eb2e8f9f7 586 };
<> 144:ef7eb2e8f9f7 587 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
<> 144:ef7eb2e8f9f7 588 };
<> 144:ef7eb2e8f9f7 589 uint32_t RESERVED1[960];
<> 144:ef7eb2e8f9f7 590 __IO uint32_t DIR[2]; /* 0x2000 */
<> 144:ef7eb2e8f9f7 591 uint32_t RESERVED2[30];
<> 144:ef7eb2e8f9f7 592 __IO uint32_t MASK[2]; /* 0x2080 */
<> 144:ef7eb2e8f9f7 593 uint32_t RESERVED3[30];
<> 144:ef7eb2e8f9f7 594 __IO uint32_t PIN[2]; /* 0x2100 */
<> 144:ef7eb2e8f9f7 595 uint32_t RESERVED4[30];
<> 144:ef7eb2e8f9f7 596 __IO uint32_t MPIN[2]; /* 0x2180 */
<> 144:ef7eb2e8f9f7 597 uint32_t RESERVED5[30];
<> 144:ef7eb2e8f9f7 598 __IO uint32_t SET[2]; /* 0x2200 */
<> 144:ef7eb2e8f9f7 599 uint32_t RESERVED6[30];
<> 144:ef7eb2e8f9f7 600 __O uint32_t CLR[2]; /* 0x2280 */
<> 144:ef7eb2e8f9f7 601 uint32_t RESERVED7[30];
<> 144:ef7eb2e8f9f7 602 __O uint32_t NOT[2]; /* 0x2300 */
<> 144:ef7eb2e8f9f7 603 } LPC_GPIO_Type;
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 607 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 608 #endif
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 612 // ----- Peripheral memory map -----
<> 144:ef7eb2e8f9f7 613 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 #define LPC_I2C_BASE (0x40000000)
<> 144:ef7eb2e8f9f7 616 #define LPC_WWDT_BASE (0x40004000)
<> 144:ef7eb2e8f9f7 617 #define LPC_USART_BASE (0x40008000)
<> 144:ef7eb2e8f9f7 618 #define LPC_CT16B0_BASE (0x4000C000)
<> 144:ef7eb2e8f9f7 619 #define LPC_CT16B1_BASE (0x40010000)
<> 144:ef7eb2e8f9f7 620 #define LPC_CT32B0_BASE (0x40014000)
<> 144:ef7eb2e8f9f7 621 #define LPC_CT32B1_BASE (0x40018000)
<> 144:ef7eb2e8f9f7 622 #define LPC_ADC_BASE (0x4001C000)
<> 144:ef7eb2e8f9f7 623 #define LPC_PMU_BASE (0x40038000)
<> 144:ef7eb2e8f9f7 624 #define LPC_FLASHCTRL_BASE (0x4003C000)
<> 144:ef7eb2e8f9f7 625 #define LPC_SSP0_BASE (0x40040000)
<> 144:ef7eb2e8f9f7 626 #define LPC_SSP1_BASE (0x40058000)
<> 144:ef7eb2e8f9f7 627 #define LPC_IOCON_BASE (0x40044000)
<> 144:ef7eb2e8f9f7 628 #define LPC_SYSCON_BASE (0x40048000)
<> 144:ef7eb2e8f9f7 629 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
<> 144:ef7eb2e8f9f7 630 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
<> 144:ef7eb2e8f9f7 631 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
<> 144:ef7eb2e8f9f7 632 #define LPC_USB_BASE (0x40080000)
<> 144:ef7eb2e8f9f7 633 #define LPC_GPIO_BASE (0x50000000)
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 637 // ----- Peripheral declaration -----
<> 144:ef7eb2e8f9f7 638 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
<> 144:ef7eb2e8f9f7 641 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
<> 144:ef7eb2e8f9f7 642 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
<> 144:ef7eb2e8f9f7 643 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
<> 144:ef7eb2e8f9f7 644 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
<> 144:ef7eb2e8f9f7 645 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
<> 144:ef7eb2e8f9f7 646 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
<> 144:ef7eb2e8f9f7 647 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
<> 144:ef7eb2e8f9f7 648 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
<> 144:ef7eb2e8f9f7 649 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<> 144:ef7eb2e8f9f7 650 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
<> 144:ef7eb2e8f9f7 651 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
<> 144:ef7eb2e8f9f7 652 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
<> 144:ef7eb2e8f9f7 653 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
<> 144:ef7eb2e8f9f7 654 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
<> 144:ef7eb2e8f9f7 655 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
<> 144:ef7eb2e8f9f7 656 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
<> 144:ef7eb2e8f9f7 657 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
<> 144:ef7eb2e8f9f7 658 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /** @} */ /* End of group Device_Peripheral_Registers */
<> 144:ef7eb2e8f9f7 662 /** @} */ /* End of group (null) */
<> 144:ef7eb2e8f9f7 663 /** @} */ /* End of group LPC11Uxx */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 #endif
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 #endif // __LPC11UXX_H__