added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | ; * --------------------------------------------------------------------------------------- |
<> | 144:ef7eb2e8f9f7 | 2 | ; * @file: startup_MK64F12.s |
<> | 144:ef7eb2e8f9f7 | 3 | ; * @purpose: CMSIS Cortex-M4 Core Device Startup File |
<> | 144:ef7eb2e8f9f7 | 4 | ; * MK64F12 |
<> | 144:ef7eb2e8f9f7 | 5 | ; * @version: 2.8 |
<> | 144:ef7eb2e8f9f7 | 6 | ; * @date: 2015-2-19 |
<> | 144:ef7eb2e8f9f7 | 7 | ; * @build: b151210 |
<> | 144:ef7eb2e8f9f7 | 8 | ; * --------------------------------------------------------------------------------------- |
<> | 144:ef7eb2e8f9f7 | 9 | ; * |
<> | 144:ef7eb2e8f9f7 | 10 | ; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 11 | ; * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 12 | ; * |
<> | 144:ef7eb2e8f9f7 | 13 | ; * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | ; * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | ; * |
<> | 144:ef7eb2e8f9f7 | 16 | ; * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 17 | ; * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 18 | ; * |
<> | 144:ef7eb2e8f9f7 | 19 | ; * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 20 | ; * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 21 | ; * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 22 | ; * |
<> | 144:ef7eb2e8f9f7 | 23 | ; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 24 | ; * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 25 | ; * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 26 | ; * |
<> | 144:ef7eb2e8f9f7 | 27 | ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 28 | ; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 29 | ; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 30 | ; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 31 | ; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 32 | ; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 33 | ; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 34 | ; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 35 | ; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 36 | ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 37 | ; * |
<> | 144:ef7eb2e8f9f7 | 38 | ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
<> | 144:ef7eb2e8f9f7 | 39 | ; * |
<> | 144:ef7eb2e8f9f7 | 40 | ; *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | __initial_sp EQU 0x20030000 ; Top of RAM |
<> | 144:ef7eb2e8f9f7 | 43 | PRESERVE8 |
<> | 144:ef7eb2e8f9f7 | 44 | THUMB |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | ; Vector Table Mapped to Address 0 at Reset |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | AREA RESET, DATA, READONLY |
<> | 144:ef7eb2e8f9f7 | 50 | EXPORT __Vectors |
<> | 144:ef7eb2e8f9f7 | 51 | EXPORT __Vectors_End |
<> | 144:ef7eb2e8f9f7 | 52 | EXPORT __Vectors_Size |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | __Vectors DCD __initial_sp ; Top of Stack |
<> | 144:ef7eb2e8f9f7 | 55 | DCD Reset_Handler ; Reset Handler |
<> | 144:ef7eb2e8f9f7 | 56 | DCD NMI_Handler ;NMI Handler |
<> | 144:ef7eb2e8f9f7 | 57 | DCD HardFault_Handler ;Hard Fault Handler |
<> | 144:ef7eb2e8f9f7 | 58 | DCD MemManage_Handler ;MPU Fault Handler |
<> | 144:ef7eb2e8f9f7 | 59 | DCD BusFault_Handler ;Bus Fault Handler |
<> | 144:ef7eb2e8f9f7 | 60 | DCD UsageFault_Handler ;Usage Fault Handler |
<> | 144:ef7eb2e8f9f7 | 61 | DCD 0 ;Reserved |
<> | 144:ef7eb2e8f9f7 | 62 | DCD 0 ;Reserved |
<> | 144:ef7eb2e8f9f7 | 63 | DCD 0 ;Reserved |
<> | 144:ef7eb2e8f9f7 | 64 | DCD 0 ;Reserved |
<> | 144:ef7eb2e8f9f7 | 65 | DCD SVC_Handler ;SVCall Handler |
<> | 144:ef7eb2e8f9f7 | 66 | DCD DebugMon_Handler ;Debug Monitor Handler |
<> | 144:ef7eb2e8f9f7 | 67 | DCD 0 ;Reserved |
<> | 144:ef7eb2e8f9f7 | 68 | DCD PendSV_Handler ;PendSV Handler |
<> | 144:ef7eb2e8f9f7 | 69 | DCD SysTick_Handler ;SysTick Handler |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | ;External Interrupts |
<> | 144:ef7eb2e8f9f7 | 72 | DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 73 | DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 74 | DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 75 | DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 76 | DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 77 | DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 78 | DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 79 | DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 80 | DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 81 | DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 82 | DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 83 | DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 84 | DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 85 | DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 86 | DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 87 | DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete |
<> | 144:ef7eb2e8f9f7 | 88 | DCD DMA_Error_IRQHandler ;DMA Error Interrupt |
<> | 144:ef7eb2e8f9f7 | 89 | DCD MCM_IRQHandler ;Normal Interrupt |
<> | 144:ef7eb2e8f9f7 | 90 | DCD FTFE_IRQHandler ;FTFE Command complete interrupt |
<> | 144:ef7eb2e8f9f7 | 91 | DCD Read_Collision_IRQHandler ;Read Collision Interrupt |
<> | 144:ef7eb2e8f9f7 | 92 | DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning |
<> | 144:ef7eb2e8f9f7 | 93 | DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit |
<> | 144:ef7eb2e8f9f7 | 94 | DCD WDOG_EWM_IRQHandler ;WDOG Interrupt |
<> | 144:ef7eb2e8f9f7 | 95 | DCD RNG_IRQHandler ;RNG Interrupt |
<> | 144:ef7eb2e8f9f7 | 96 | DCD I2C0_IRQHandler ;I2C0 interrupt |
<> | 144:ef7eb2e8f9f7 | 97 | DCD I2C1_IRQHandler ;I2C1 interrupt |
<> | 144:ef7eb2e8f9f7 | 98 | DCD SPI0_IRQHandler ;SPI0 Interrupt |
<> | 144:ef7eb2e8f9f7 | 99 | DCD SPI1_IRQHandler ;SPI1 Interrupt |
<> | 144:ef7eb2e8f9f7 | 100 | DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 101 | DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt |
<> | 144:ef7eb2e8f9f7 | 102 | DCD UART0_LON_IRQHandler ;UART0 LON interrupt |
<> | 144:ef7eb2e8f9f7 | 103 | DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 104 | DCD UART0_ERR_IRQHandler ;UART0 Error interrupt |
<> | 144:ef7eb2e8f9f7 | 105 | DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 106 | DCD UART1_ERR_IRQHandler ;UART1 Error interrupt |
<> | 144:ef7eb2e8f9f7 | 107 | DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 108 | DCD UART2_ERR_IRQHandler ;UART2 Error interrupt |
<> | 144:ef7eb2e8f9f7 | 109 | DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 110 | DCD UART3_ERR_IRQHandler ;UART3 Error interrupt |
<> | 144:ef7eb2e8f9f7 | 111 | DCD ADC0_IRQHandler ;ADC0 interrupt |
<> | 144:ef7eb2e8f9f7 | 112 | DCD CMP0_IRQHandler ;CMP0 interrupt |
<> | 144:ef7eb2e8f9f7 | 113 | DCD CMP1_IRQHandler ;CMP1 interrupt |
<> | 144:ef7eb2e8f9f7 | 114 | DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 115 | DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 116 | DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 117 | DCD CMT_IRQHandler ;CMT interrupt |
<> | 144:ef7eb2e8f9f7 | 118 | DCD RTC_IRQHandler ;RTC interrupt |
<> | 144:ef7eb2e8f9f7 | 119 | DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt |
<> | 144:ef7eb2e8f9f7 | 120 | DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt |
<> | 144:ef7eb2e8f9f7 | 121 | DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt |
<> | 144:ef7eb2e8f9f7 | 122 | DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt |
<> | 144:ef7eb2e8f9f7 | 123 | DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt |
<> | 144:ef7eb2e8f9f7 | 124 | DCD PDB0_IRQHandler ;PDB0 Interrupt |
<> | 144:ef7eb2e8f9f7 | 125 | DCD USB0_IRQHandler ;USB0 interrupt |
<> | 144:ef7eb2e8f9f7 | 126 | DCD USBDCD_IRQHandler ;USBDCD Interrupt |
<> | 144:ef7eb2e8f9f7 | 127 | DCD Reserved71_IRQHandler ;Reserved interrupt 71 |
<> | 144:ef7eb2e8f9f7 | 128 | DCD DAC0_IRQHandler ;DAC0 interrupt |
<> | 144:ef7eb2e8f9f7 | 129 | DCD MCG_IRQHandler ;MCG Interrupt |
<> | 144:ef7eb2e8f9f7 | 130 | DCD LPTMR0_IRQHandler ;LPTimer interrupt |
<> | 144:ef7eb2e8f9f7 | 131 | DCD PORTA_IRQHandler ;Port A interrupt |
<> | 144:ef7eb2e8f9f7 | 132 | DCD PORTB_IRQHandler ;Port B interrupt |
<> | 144:ef7eb2e8f9f7 | 133 | DCD PORTC_IRQHandler ;Port C interrupt |
<> | 144:ef7eb2e8f9f7 | 134 | DCD PORTD_IRQHandler ;Port D interrupt |
<> | 144:ef7eb2e8f9f7 | 135 | DCD PORTE_IRQHandler ;Port E interrupt |
<> | 144:ef7eb2e8f9f7 | 136 | DCD SWI_IRQHandler ;Software interrupt |
<> | 144:ef7eb2e8f9f7 | 137 | DCD SPI2_IRQHandler ;SPI2 Interrupt |
<> | 144:ef7eb2e8f9f7 | 138 | DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 139 | DCD UART4_ERR_IRQHandler ;UART4 Error interrupt |
<> | 144:ef7eb2e8f9f7 | 140 | DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 141 | DCD UART5_ERR_IRQHandler ;UART5 Error interrupt |
<> | 144:ef7eb2e8f9f7 | 142 | DCD CMP2_IRQHandler ;CMP2 interrupt |
<> | 144:ef7eb2e8f9f7 | 143 | DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 144 | DCD DAC1_IRQHandler ;DAC1 interrupt |
<> | 144:ef7eb2e8f9f7 | 145 | DCD ADC1_IRQHandler ;ADC1 interrupt |
<> | 144:ef7eb2e8f9f7 | 146 | DCD I2C2_IRQHandler ;I2C2 interrupt |
<> | 144:ef7eb2e8f9f7 | 147 | DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt |
<> | 144:ef7eb2e8f9f7 | 148 | DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt |
<> | 144:ef7eb2e8f9f7 | 149 | DCD CAN0_Error_IRQHandler ;CAN0 error interrupt |
<> | 144:ef7eb2e8f9f7 | 150 | DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt |
<> | 144:ef7eb2e8f9f7 | 151 | DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt |
<> | 144:ef7eb2e8f9f7 | 152 | DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt |
<> | 144:ef7eb2e8f9f7 | 153 | DCD SDHC_IRQHandler ;SDHC interrupt |
<> | 144:ef7eb2e8f9f7 | 154 | DCD ENET_1588_Timer_IRQHandler ;Ethernet MAC IEEE 1588 Timer Interrupt |
<> | 144:ef7eb2e8f9f7 | 155 | DCD ENET_Transmit_IRQHandler ;Ethernet MAC Transmit Interrupt |
<> | 144:ef7eb2e8f9f7 | 156 | DCD ENET_Receive_IRQHandler ;Ethernet MAC Receive Interrupt |
<> | 144:ef7eb2e8f9f7 | 157 | DCD ENET_Error_IRQHandler ;Ethernet MAC Error and miscelaneous Interrupt |
<> | 144:ef7eb2e8f9f7 | 158 | DCD DefaultISR ;102 |
<> | 144:ef7eb2e8f9f7 | 159 | DCD DefaultISR ;103 |
<> | 144:ef7eb2e8f9f7 | 160 | DCD DefaultISR ;104 |
<> | 144:ef7eb2e8f9f7 | 161 | DCD DefaultISR ;105 |
<> | 144:ef7eb2e8f9f7 | 162 | DCD DefaultISR ;106 |
<> | 144:ef7eb2e8f9f7 | 163 | DCD DefaultISR ;107 |
<> | 144:ef7eb2e8f9f7 | 164 | DCD DefaultISR ;108 |
<> | 144:ef7eb2e8f9f7 | 165 | DCD DefaultISR ;109 |
<> | 144:ef7eb2e8f9f7 | 166 | DCD DefaultISR ;110 |
<> | 144:ef7eb2e8f9f7 | 167 | DCD DefaultISR ;111 |
<> | 144:ef7eb2e8f9f7 | 168 | DCD DefaultISR ;112 |
<> | 144:ef7eb2e8f9f7 | 169 | DCD DefaultISR ;113 |
<> | 144:ef7eb2e8f9f7 | 170 | DCD DefaultISR ;114 |
<> | 144:ef7eb2e8f9f7 | 171 | DCD DefaultISR ;115 |
<> | 144:ef7eb2e8f9f7 | 172 | DCD DefaultISR ;116 |
<> | 144:ef7eb2e8f9f7 | 173 | DCD DefaultISR ;117 |
<> | 144:ef7eb2e8f9f7 | 174 | DCD DefaultISR ;118 |
<> | 144:ef7eb2e8f9f7 | 175 | DCD DefaultISR ;119 |
<> | 144:ef7eb2e8f9f7 | 176 | DCD DefaultISR ;120 |
<> | 144:ef7eb2e8f9f7 | 177 | DCD DefaultISR ;121 |
<> | 144:ef7eb2e8f9f7 | 178 | DCD DefaultISR ;122 |
<> | 144:ef7eb2e8f9f7 | 179 | DCD DefaultISR ;123 |
<> | 144:ef7eb2e8f9f7 | 180 | DCD DefaultISR ;124 |
<> | 144:ef7eb2e8f9f7 | 181 | DCD DefaultISR ;125 |
<> | 144:ef7eb2e8f9f7 | 182 | DCD DefaultISR ;126 |
<> | 144:ef7eb2e8f9f7 | 183 | DCD DefaultISR ;127 |
<> | 144:ef7eb2e8f9f7 | 184 | DCD DefaultISR ;128 |
<> | 144:ef7eb2e8f9f7 | 185 | DCD DefaultISR ;129 |
<> | 144:ef7eb2e8f9f7 | 186 | DCD DefaultISR ;130 |
<> | 144:ef7eb2e8f9f7 | 187 | DCD DefaultISR ;131 |
<> | 144:ef7eb2e8f9f7 | 188 | DCD DefaultISR ;132 |
<> | 144:ef7eb2e8f9f7 | 189 | DCD DefaultISR ;133 |
<> | 144:ef7eb2e8f9f7 | 190 | DCD DefaultISR ;134 |
<> | 144:ef7eb2e8f9f7 | 191 | DCD DefaultISR ;135 |
<> | 144:ef7eb2e8f9f7 | 192 | DCD DefaultISR ;136 |
<> | 144:ef7eb2e8f9f7 | 193 | DCD DefaultISR ;137 |
<> | 144:ef7eb2e8f9f7 | 194 | DCD DefaultISR ;138 |
<> | 144:ef7eb2e8f9f7 | 195 | DCD DefaultISR ;139 |
<> | 144:ef7eb2e8f9f7 | 196 | DCD DefaultISR ;140 |
<> | 144:ef7eb2e8f9f7 | 197 | DCD DefaultISR ;141 |
<> | 144:ef7eb2e8f9f7 | 198 | DCD DefaultISR ;142 |
<> | 144:ef7eb2e8f9f7 | 199 | DCD DefaultISR ;143 |
<> | 144:ef7eb2e8f9f7 | 200 | DCD DefaultISR ;144 |
<> | 144:ef7eb2e8f9f7 | 201 | DCD DefaultISR ;145 |
<> | 144:ef7eb2e8f9f7 | 202 | DCD DefaultISR ;146 |
<> | 144:ef7eb2e8f9f7 | 203 | DCD DefaultISR ;147 |
<> | 144:ef7eb2e8f9f7 | 204 | DCD DefaultISR ;148 |
<> | 144:ef7eb2e8f9f7 | 205 | DCD DefaultISR ;149 |
<> | 144:ef7eb2e8f9f7 | 206 | DCD DefaultISR ;150 |
<> | 144:ef7eb2e8f9f7 | 207 | DCD DefaultISR ;151 |
<> | 144:ef7eb2e8f9f7 | 208 | DCD DefaultISR ;152 |
<> | 144:ef7eb2e8f9f7 | 209 | DCD DefaultISR ;153 |
<> | 144:ef7eb2e8f9f7 | 210 | DCD DefaultISR ;154 |
<> | 144:ef7eb2e8f9f7 | 211 | DCD DefaultISR ;155 |
<> | 144:ef7eb2e8f9f7 | 212 | DCD DefaultISR ;156 |
<> | 144:ef7eb2e8f9f7 | 213 | DCD DefaultISR ;157 |
<> | 144:ef7eb2e8f9f7 | 214 | DCD DefaultISR ;158 |
<> | 144:ef7eb2e8f9f7 | 215 | DCD DefaultISR ;159 |
<> | 144:ef7eb2e8f9f7 | 216 | DCD DefaultISR ;160 |
<> | 144:ef7eb2e8f9f7 | 217 | DCD DefaultISR ;161 |
<> | 144:ef7eb2e8f9f7 | 218 | DCD DefaultISR ;162 |
<> | 144:ef7eb2e8f9f7 | 219 | DCD DefaultISR ;163 |
<> | 144:ef7eb2e8f9f7 | 220 | DCD DefaultISR ;164 |
<> | 144:ef7eb2e8f9f7 | 221 | DCD DefaultISR ;165 |
<> | 144:ef7eb2e8f9f7 | 222 | DCD DefaultISR ;166 |
<> | 144:ef7eb2e8f9f7 | 223 | DCD DefaultISR ;167 |
<> | 144:ef7eb2e8f9f7 | 224 | DCD DefaultISR ;168 |
<> | 144:ef7eb2e8f9f7 | 225 | DCD DefaultISR ;169 |
<> | 144:ef7eb2e8f9f7 | 226 | DCD DefaultISR ;170 |
<> | 144:ef7eb2e8f9f7 | 227 | DCD DefaultISR ;171 |
<> | 144:ef7eb2e8f9f7 | 228 | DCD DefaultISR ;172 |
<> | 144:ef7eb2e8f9f7 | 229 | DCD DefaultISR ;173 |
<> | 144:ef7eb2e8f9f7 | 230 | DCD DefaultISR ;174 |
<> | 144:ef7eb2e8f9f7 | 231 | DCD DefaultISR ;175 |
<> | 144:ef7eb2e8f9f7 | 232 | DCD DefaultISR ;176 |
<> | 144:ef7eb2e8f9f7 | 233 | DCD DefaultISR ;177 |
<> | 144:ef7eb2e8f9f7 | 234 | DCD DefaultISR ;178 |
<> | 144:ef7eb2e8f9f7 | 235 | DCD DefaultISR ;179 |
<> | 144:ef7eb2e8f9f7 | 236 | DCD DefaultISR ;180 |
<> | 144:ef7eb2e8f9f7 | 237 | DCD DefaultISR ;181 |
<> | 144:ef7eb2e8f9f7 | 238 | DCD DefaultISR ;182 |
<> | 144:ef7eb2e8f9f7 | 239 | DCD DefaultISR ;183 |
<> | 144:ef7eb2e8f9f7 | 240 | DCD DefaultISR ;184 |
<> | 144:ef7eb2e8f9f7 | 241 | DCD DefaultISR ;185 |
<> | 144:ef7eb2e8f9f7 | 242 | DCD DefaultISR ;186 |
<> | 144:ef7eb2e8f9f7 | 243 | DCD DefaultISR ;187 |
<> | 144:ef7eb2e8f9f7 | 244 | DCD DefaultISR ;188 |
<> | 144:ef7eb2e8f9f7 | 245 | DCD DefaultISR ;189 |
<> | 144:ef7eb2e8f9f7 | 246 | DCD DefaultISR ;190 |
<> | 144:ef7eb2e8f9f7 | 247 | DCD DefaultISR ;191 |
<> | 144:ef7eb2e8f9f7 | 248 | DCD DefaultISR ;192 |
<> | 144:ef7eb2e8f9f7 | 249 | DCD DefaultISR ;193 |
<> | 144:ef7eb2e8f9f7 | 250 | DCD DefaultISR ;194 |
<> | 144:ef7eb2e8f9f7 | 251 | DCD DefaultISR ;195 |
<> | 144:ef7eb2e8f9f7 | 252 | DCD DefaultISR ;196 |
<> | 144:ef7eb2e8f9f7 | 253 | DCD DefaultISR ;197 |
<> | 144:ef7eb2e8f9f7 | 254 | DCD DefaultISR ;198 |
<> | 144:ef7eb2e8f9f7 | 255 | DCD DefaultISR ;199 |
<> | 144:ef7eb2e8f9f7 | 256 | DCD DefaultISR ;200 |
<> | 144:ef7eb2e8f9f7 | 257 | DCD DefaultISR ;201 |
<> | 144:ef7eb2e8f9f7 | 258 | DCD DefaultISR ;202 |
<> | 144:ef7eb2e8f9f7 | 259 | DCD DefaultISR ;203 |
<> | 144:ef7eb2e8f9f7 | 260 | DCD DefaultISR ;204 |
<> | 144:ef7eb2e8f9f7 | 261 | DCD DefaultISR ;205 |
<> | 144:ef7eb2e8f9f7 | 262 | DCD DefaultISR ;206 |
<> | 144:ef7eb2e8f9f7 | 263 | DCD DefaultISR ;207 |
<> | 144:ef7eb2e8f9f7 | 264 | DCD DefaultISR ;208 |
<> | 144:ef7eb2e8f9f7 | 265 | DCD DefaultISR ;209 |
<> | 144:ef7eb2e8f9f7 | 266 | DCD DefaultISR ;210 |
<> | 144:ef7eb2e8f9f7 | 267 | DCD DefaultISR ;211 |
<> | 144:ef7eb2e8f9f7 | 268 | DCD DefaultISR ;212 |
<> | 144:ef7eb2e8f9f7 | 269 | DCD DefaultISR ;213 |
<> | 144:ef7eb2e8f9f7 | 270 | DCD DefaultISR ;214 |
<> | 144:ef7eb2e8f9f7 | 271 | DCD DefaultISR ;215 |
<> | 144:ef7eb2e8f9f7 | 272 | DCD DefaultISR ;216 |
<> | 144:ef7eb2e8f9f7 | 273 | DCD DefaultISR ;217 |
<> | 144:ef7eb2e8f9f7 | 274 | DCD DefaultISR ;218 |
<> | 144:ef7eb2e8f9f7 | 275 | DCD DefaultISR ;219 |
<> | 144:ef7eb2e8f9f7 | 276 | DCD DefaultISR ;220 |
<> | 144:ef7eb2e8f9f7 | 277 | DCD DefaultISR ;221 |
<> | 144:ef7eb2e8f9f7 | 278 | DCD DefaultISR ;222 |
<> | 144:ef7eb2e8f9f7 | 279 | DCD DefaultISR ;223 |
<> | 144:ef7eb2e8f9f7 | 280 | DCD DefaultISR ;224 |
<> | 144:ef7eb2e8f9f7 | 281 | DCD DefaultISR ;225 |
<> | 144:ef7eb2e8f9f7 | 282 | DCD DefaultISR ;226 |
<> | 144:ef7eb2e8f9f7 | 283 | DCD DefaultISR ;227 |
<> | 144:ef7eb2e8f9f7 | 284 | DCD DefaultISR ;228 |
<> | 144:ef7eb2e8f9f7 | 285 | DCD DefaultISR ;229 |
<> | 144:ef7eb2e8f9f7 | 286 | DCD DefaultISR ;230 |
<> | 144:ef7eb2e8f9f7 | 287 | DCD DefaultISR ;231 |
<> | 144:ef7eb2e8f9f7 | 288 | DCD DefaultISR ;232 |
<> | 144:ef7eb2e8f9f7 | 289 | DCD DefaultISR ;233 |
<> | 144:ef7eb2e8f9f7 | 290 | DCD DefaultISR ;234 |
<> | 144:ef7eb2e8f9f7 | 291 | DCD DefaultISR ;235 |
<> | 144:ef7eb2e8f9f7 | 292 | DCD DefaultISR ;236 |
<> | 144:ef7eb2e8f9f7 | 293 | DCD DefaultISR ;237 |
<> | 144:ef7eb2e8f9f7 | 294 | DCD DefaultISR ;238 |
<> | 144:ef7eb2e8f9f7 | 295 | DCD DefaultISR ;239 |
<> | 144:ef7eb2e8f9f7 | 296 | DCD DefaultISR ;240 |
<> | 144:ef7eb2e8f9f7 | 297 | DCD DefaultISR ;241 |
<> | 144:ef7eb2e8f9f7 | 298 | DCD DefaultISR ;242 |
<> | 144:ef7eb2e8f9f7 | 299 | DCD DefaultISR ;243 |
<> | 144:ef7eb2e8f9f7 | 300 | DCD DefaultISR ;244 |
<> | 144:ef7eb2e8f9f7 | 301 | DCD DefaultISR ;245 |
<> | 144:ef7eb2e8f9f7 | 302 | DCD DefaultISR ;246 |
<> | 144:ef7eb2e8f9f7 | 303 | DCD DefaultISR ;247 |
<> | 144:ef7eb2e8f9f7 | 304 | DCD DefaultISR ;248 |
<> | 144:ef7eb2e8f9f7 | 305 | DCD DefaultISR ;249 |
<> | 144:ef7eb2e8f9f7 | 306 | DCD DefaultISR ;250 |
<> | 144:ef7eb2e8f9f7 | 307 | DCD DefaultISR ;251 |
<> | 144:ef7eb2e8f9f7 | 308 | DCD DefaultISR ;252 |
<> | 144:ef7eb2e8f9f7 | 309 | DCD DefaultISR ;253 |
<> | 144:ef7eb2e8f9f7 | 310 | DCD DefaultISR ;254 |
<> | 144:ef7eb2e8f9f7 | 311 | DCD 0xFFFFFFFF ; Reserved for user TRIM value |
<> | 144:ef7eb2e8f9f7 | 312 | __Vectors_End |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | __Vectors_Size EQU __Vectors_End - __Vectors |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | ; <h> Flash Configuration |
<> | 144:ef7eb2e8f9f7 | 317 | ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) |
<> | 144:ef7eb2e8f9f7 | 318 | ; <i> and security information that allows the MCU to restrict access to the FTFL module. |
<> | 144:ef7eb2e8f9f7 | 319 | ; <h> Backdoor Comparison Key |
<> | 144:ef7eb2e8f9f7 | 320 | ; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 321 | ; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 322 | ; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 323 | ; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 324 | ; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 325 | ; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 326 | ; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 327 | ; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 328 | BackDoorK0 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 329 | BackDoorK1 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 330 | BackDoorK2 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 331 | BackDoorK3 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 332 | BackDoorK4 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 333 | BackDoorK5 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 334 | BackDoorK6 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 335 | BackDoorK7 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 336 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 337 | ; <h> Program flash protection bytes (FPROT) |
<> | 144:ef7eb2e8f9f7 | 338 | ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. |
<> | 144:ef7eb2e8f9f7 | 339 | ; <i> Each bit protects a 1/32 region of the program flash memory. |
<> | 144:ef7eb2e8f9f7 | 340 | ; <h> FPROT0 |
<> | 144:ef7eb2e8f9f7 | 341 | ; <i> Program Flash Region Protect Register 0 |
<> | 144:ef7eb2e8f9f7 | 342 | ; <i> 1/32 - 8/32 region |
<> | 144:ef7eb2e8f9f7 | 343 | ; <o.0> FPROT0.0 |
<> | 144:ef7eb2e8f9f7 | 344 | ; <o.1> FPROT0.1 |
<> | 144:ef7eb2e8f9f7 | 345 | ; <o.2> FPROT0.2 |
<> | 144:ef7eb2e8f9f7 | 346 | ; <o.3> FPROT0.3 |
<> | 144:ef7eb2e8f9f7 | 347 | ; <o.4> FPROT0.4 |
<> | 144:ef7eb2e8f9f7 | 348 | ; <o.5> FPROT0.5 |
<> | 144:ef7eb2e8f9f7 | 349 | ; <o.6> FPROT0.6 |
<> | 144:ef7eb2e8f9f7 | 350 | ; <o.7> FPROT0.7 |
<> | 144:ef7eb2e8f9f7 | 351 | nFPROT0 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 352 | FPROT0 EQU nFPROT0:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 353 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 354 | ; <h> FPROT1 |
<> | 144:ef7eb2e8f9f7 | 355 | ; <i> Program Flash Region Protect Register 1 |
<> | 144:ef7eb2e8f9f7 | 356 | ; <i> 9/32 - 16/32 region |
<> | 144:ef7eb2e8f9f7 | 357 | ; <o.0> FPROT1.0 |
<> | 144:ef7eb2e8f9f7 | 358 | ; <o.1> FPROT1.1 |
<> | 144:ef7eb2e8f9f7 | 359 | ; <o.2> FPROT1.2 |
<> | 144:ef7eb2e8f9f7 | 360 | ; <o.3> FPROT1.3 |
<> | 144:ef7eb2e8f9f7 | 361 | ; <o.4> FPROT1.4 |
<> | 144:ef7eb2e8f9f7 | 362 | ; <o.5> FPROT1.5 |
<> | 144:ef7eb2e8f9f7 | 363 | ; <o.6> FPROT1.6 |
<> | 144:ef7eb2e8f9f7 | 364 | ; <o.7> FPROT1.7 |
<> | 144:ef7eb2e8f9f7 | 365 | nFPROT1 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 366 | FPROT1 EQU nFPROT1:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 367 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 368 | ; <h> FPROT2 |
<> | 144:ef7eb2e8f9f7 | 369 | ; <i> Program Flash Region Protect Register 2 |
<> | 144:ef7eb2e8f9f7 | 370 | ; <i> 17/32 - 24/32 region |
<> | 144:ef7eb2e8f9f7 | 371 | ; <o.0> FPROT2.0 |
<> | 144:ef7eb2e8f9f7 | 372 | ; <o.1> FPROT2.1 |
<> | 144:ef7eb2e8f9f7 | 373 | ; <o.2> FPROT2.2 |
<> | 144:ef7eb2e8f9f7 | 374 | ; <o.3> FPROT2.3 |
<> | 144:ef7eb2e8f9f7 | 375 | ; <o.4> FPROT2.4 |
<> | 144:ef7eb2e8f9f7 | 376 | ; <o.5> FPROT2.5 |
<> | 144:ef7eb2e8f9f7 | 377 | ; <o.6> FPROT2.6 |
<> | 144:ef7eb2e8f9f7 | 378 | ; <o.7> FPROT2.7 |
<> | 144:ef7eb2e8f9f7 | 379 | nFPROT2 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 380 | FPROT2 EQU nFPROT2:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 381 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 382 | ; <h> FPROT3 |
<> | 144:ef7eb2e8f9f7 | 383 | ; <i> Program Flash Region Protect Register 3 |
<> | 144:ef7eb2e8f9f7 | 384 | ; <i> 25/32 - 32/32 region |
<> | 144:ef7eb2e8f9f7 | 385 | ; <o.0> FPROT3.0 |
<> | 144:ef7eb2e8f9f7 | 386 | ; <o.1> FPROT3.1 |
<> | 144:ef7eb2e8f9f7 | 387 | ; <o.2> FPROT3.2 |
<> | 144:ef7eb2e8f9f7 | 388 | ; <o.3> FPROT3.3 |
<> | 144:ef7eb2e8f9f7 | 389 | ; <o.4> FPROT3.4 |
<> | 144:ef7eb2e8f9f7 | 390 | ; <o.5> FPROT3.5 |
<> | 144:ef7eb2e8f9f7 | 391 | ; <o.6> FPROT3.6 |
<> | 144:ef7eb2e8f9f7 | 392 | ; <o.7> FPROT3.7 |
<> | 144:ef7eb2e8f9f7 | 393 | nFPROT3 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 394 | FPROT3 EQU nFPROT3:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 395 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 396 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 397 | ; <h> Data flash protection byte (FDPROT) |
<> | 144:ef7eb2e8f9f7 | 398 | ; <i> Each bit protects a 1/8 region of the data flash memory. |
<> | 144:ef7eb2e8f9f7 | 399 | ; <i> (Program flash only devices: Reserved) |
<> | 144:ef7eb2e8f9f7 | 400 | ; <o.0> FDPROT.0 |
<> | 144:ef7eb2e8f9f7 | 401 | ; <o.1> FDPROT.1 |
<> | 144:ef7eb2e8f9f7 | 402 | ; <o.2> FDPROT.2 |
<> | 144:ef7eb2e8f9f7 | 403 | ; <o.3> FDPROT.3 |
<> | 144:ef7eb2e8f9f7 | 404 | ; <o.4> FDPROT.4 |
<> | 144:ef7eb2e8f9f7 | 405 | ; <o.5> FDPROT.5 |
<> | 144:ef7eb2e8f9f7 | 406 | ; <o.6> FDPROT.6 |
<> | 144:ef7eb2e8f9f7 | 407 | ; <o.7> FDPROT.7 |
<> | 144:ef7eb2e8f9f7 | 408 | nFDPROT EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 409 | FDPROT EQU nFDPROT:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 410 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 411 | ; <h> EEPROM protection byte (FEPROT) |
<> | 144:ef7eb2e8f9f7 | 412 | ; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. |
<> | 144:ef7eb2e8f9f7 | 413 | ; <i> (Program flash only devices: Reserved) |
<> | 144:ef7eb2e8f9f7 | 414 | ; <o.0> FEPROT.0 |
<> | 144:ef7eb2e8f9f7 | 415 | ; <o.1> FEPROT.1 |
<> | 144:ef7eb2e8f9f7 | 416 | ; <o.2> FEPROT.2 |
<> | 144:ef7eb2e8f9f7 | 417 | ; <o.3> FEPROT.3 |
<> | 144:ef7eb2e8f9f7 | 418 | ; <o.4> FEPROT.4 |
<> | 144:ef7eb2e8f9f7 | 419 | ; <o.5> FEPROT.5 |
<> | 144:ef7eb2e8f9f7 | 420 | ; <o.6> FEPROT.6 |
<> | 144:ef7eb2e8f9f7 | 421 | ; <o.7> FEPROT.7 |
<> | 144:ef7eb2e8f9f7 | 422 | nFEPROT EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 423 | FEPROT EQU nFEPROT:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 424 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 425 | ; <h> Flash nonvolatile option byte (FOPT) |
<> | 144:ef7eb2e8f9f7 | 426 | ; <i> Allows the user to customize the operation of the MCU at boot time. |
<> | 144:ef7eb2e8f9f7 | 427 | ; <o.0> LPBOOT |
<> | 144:ef7eb2e8f9f7 | 428 | ; <0=> Low-power boot |
<> | 144:ef7eb2e8f9f7 | 429 | ; <1=> Normal boot |
<> | 144:ef7eb2e8f9f7 | 430 | ; <o.1> EZPORT_DIS |
<> | 144:ef7eb2e8f9f7 | 431 | ; <0=> EzPort operation is disabled |
<> | 144:ef7eb2e8f9f7 | 432 | ; <1=> EzPort operation is enabled |
<> | 144:ef7eb2e8f9f7 | 433 | FOPT EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 434 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 435 | ; <h> Flash security byte (FSEC) |
<> | 144:ef7eb2e8f9f7 | 436 | ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", |
<> | 144:ef7eb2e8f9f7 | 437 | ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! |
<> | 144:ef7eb2e8f9f7 | 438 | ; <o.0..1> SEC |
<> | 144:ef7eb2e8f9f7 | 439 | ; <2=> MCU security status is unsecure |
<> | 144:ef7eb2e8f9f7 | 440 | ; <3=> MCU security status is secure |
<> | 144:ef7eb2e8f9f7 | 441 | ; <i> Flash Security |
<> | 144:ef7eb2e8f9f7 | 442 | ; <o.2..3> FSLACC |
<> | 144:ef7eb2e8f9f7 | 443 | ; <2=> Freescale factory access denied |
<> | 144:ef7eb2e8f9f7 | 444 | ; <3=> Freescale factory access granted |
<> | 144:ef7eb2e8f9f7 | 445 | ; <i> Freescale Failure Analysis Access Code |
<> | 144:ef7eb2e8f9f7 | 446 | ; <o.4..5> MEEN |
<> | 144:ef7eb2e8f9f7 | 447 | ; <2=> Mass erase is disabled |
<> | 144:ef7eb2e8f9f7 | 448 | ; <3=> Mass erase is enabled |
<> | 144:ef7eb2e8f9f7 | 449 | ; <o.6..7> KEYEN |
<> | 144:ef7eb2e8f9f7 | 450 | ; <2=> Backdoor key access enabled |
<> | 144:ef7eb2e8f9f7 | 451 | ; <3=> Backdoor key access disabled |
<> | 144:ef7eb2e8f9f7 | 452 | ; <i> Backdoor Key Security Enable |
<> | 144:ef7eb2e8f9f7 | 453 | FSEC EQU 0xFE |
<> | 144:ef7eb2e8f9f7 | 454 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 455 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 456 | IF :LNOT::DEF:RAM_TARGET |
<> | 144:ef7eb2e8f9f7 | 457 | AREA FlashConfig, DATA, READONLY |
<> | 144:ef7eb2e8f9f7 | 458 | __FlashConfig |
<> | 144:ef7eb2e8f9f7 | 459 | DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 |
<> | 144:ef7eb2e8f9f7 | 460 | DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 |
<> | 144:ef7eb2e8f9f7 | 461 | DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 |
<> | 144:ef7eb2e8f9f7 | 462 | DCB FSEC , FOPT , FEPROT , FDPROT |
<> | 144:ef7eb2e8f9f7 | 463 | ENDIF |
<> | 144:ef7eb2e8f9f7 | 464 | |
<> | 144:ef7eb2e8f9f7 | 465 | |
<> | 144:ef7eb2e8f9f7 | 466 | AREA |.text|, CODE, READONLY |
<> | 144:ef7eb2e8f9f7 | 467 | |
<> | 144:ef7eb2e8f9f7 | 468 | ; Reset Handler |
<> | 144:ef7eb2e8f9f7 | 469 | |
<> | 144:ef7eb2e8f9f7 | 470 | Reset_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 471 | EXPORT Reset_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 472 | IMPORT SystemInit |
<> | 144:ef7eb2e8f9f7 | 473 | IMPORT __main |
<> | 144:ef7eb2e8f9f7 | 474 | |
<> | 144:ef7eb2e8f9f7 | 475 | IF :LNOT::DEF:RAM_TARGET |
<> | 144:ef7eb2e8f9f7 | 476 | REQUIRE FlashConfig |
<> | 144:ef7eb2e8f9f7 | 477 | ENDIF |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | CPSID I ; Mask interrupts |
<> | 144:ef7eb2e8f9f7 | 480 | LDR R0, =0xE000ED08 |
<> | 144:ef7eb2e8f9f7 | 481 | LDR R1, =__Vectors |
<> | 144:ef7eb2e8f9f7 | 482 | STR R1, [R0] |
<> | 144:ef7eb2e8f9f7 | 483 | LDR R0, =SystemInit |
<> | 144:ef7eb2e8f9f7 | 484 | BLX R0 |
<> | 144:ef7eb2e8f9f7 | 485 | CPSIE i ; Unmask interrupts |
<> | 144:ef7eb2e8f9f7 | 486 | LDR R0, =__main |
<> | 144:ef7eb2e8f9f7 | 487 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 488 | ENDP |
<> | 144:ef7eb2e8f9f7 | 489 | |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | ; Dummy Exception Handlers (infinite loops which can be modified) |
<> | 144:ef7eb2e8f9f7 | 492 | NMI_Handler\ |
<> | 144:ef7eb2e8f9f7 | 493 | PROC |
<> | 144:ef7eb2e8f9f7 | 494 | EXPORT NMI_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 495 | B . |
<> | 144:ef7eb2e8f9f7 | 496 | ENDP |
<> | 144:ef7eb2e8f9f7 | 497 | HardFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 498 | PROC |
<> | 144:ef7eb2e8f9f7 | 499 | EXPORT HardFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 500 | B . |
<> | 144:ef7eb2e8f9f7 | 501 | ENDP |
<> | 144:ef7eb2e8f9f7 | 502 | MemManage_Handler\ |
<> | 144:ef7eb2e8f9f7 | 503 | PROC |
<> | 144:ef7eb2e8f9f7 | 504 | EXPORT MemManage_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 505 | B . |
<> | 144:ef7eb2e8f9f7 | 506 | ENDP |
<> | 144:ef7eb2e8f9f7 | 507 | BusFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 508 | PROC |
<> | 144:ef7eb2e8f9f7 | 509 | EXPORT BusFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 510 | B . |
<> | 144:ef7eb2e8f9f7 | 511 | ENDP |
<> | 144:ef7eb2e8f9f7 | 512 | UsageFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 513 | PROC |
<> | 144:ef7eb2e8f9f7 | 514 | EXPORT UsageFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 515 | B . |
<> | 144:ef7eb2e8f9f7 | 516 | ENDP |
<> | 144:ef7eb2e8f9f7 | 517 | SVC_Handler\ |
<> | 144:ef7eb2e8f9f7 | 518 | PROC |
<> | 144:ef7eb2e8f9f7 | 519 | EXPORT SVC_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 520 | B . |
<> | 144:ef7eb2e8f9f7 | 521 | ENDP |
<> | 144:ef7eb2e8f9f7 | 522 | DebugMon_Handler\ |
<> | 144:ef7eb2e8f9f7 | 523 | PROC |
<> | 144:ef7eb2e8f9f7 | 524 | EXPORT DebugMon_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 525 | B . |
<> | 144:ef7eb2e8f9f7 | 526 | ENDP |
<> | 144:ef7eb2e8f9f7 | 527 | PendSV_Handler\ |
<> | 144:ef7eb2e8f9f7 | 528 | PROC |
<> | 144:ef7eb2e8f9f7 | 529 | EXPORT PendSV_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 530 | B . |
<> | 144:ef7eb2e8f9f7 | 531 | ENDP |
<> | 144:ef7eb2e8f9f7 | 532 | SysTick_Handler\ |
<> | 144:ef7eb2e8f9f7 | 533 | PROC |
<> | 144:ef7eb2e8f9f7 | 534 | EXPORT SysTick_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 535 | B . |
<> | 144:ef7eb2e8f9f7 | 536 | ENDP |
<> | 144:ef7eb2e8f9f7 | 537 | DMA0_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 538 | PROC |
<> | 144:ef7eb2e8f9f7 | 539 | EXPORT DMA0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 540 | LDR R0, =DMA0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 541 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 542 | ENDP |
<> | 144:ef7eb2e8f9f7 | 543 | |
<> | 144:ef7eb2e8f9f7 | 544 | DMA1_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 545 | PROC |
<> | 144:ef7eb2e8f9f7 | 546 | EXPORT DMA1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 547 | LDR R0, =DMA1_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 548 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 549 | ENDP |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | DMA2_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 552 | PROC |
<> | 144:ef7eb2e8f9f7 | 553 | EXPORT DMA2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 554 | LDR R0, =DMA2_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 555 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 556 | ENDP |
<> | 144:ef7eb2e8f9f7 | 557 | |
<> | 144:ef7eb2e8f9f7 | 558 | DMA3_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 559 | PROC |
<> | 144:ef7eb2e8f9f7 | 560 | EXPORT DMA3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 561 | LDR R0, =DMA3_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 562 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 563 | ENDP |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | DMA4_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 566 | PROC |
<> | 144:ef7eb2e8f9f7 | 567 | EXPORT DMA4_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 568 | LDR R0, =DMA4_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 569 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 570 | ENDP |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | DMA5_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 573 | PROC |
<> | 144:ef7eb2e8f9f7 | 574 | EXPORT DMA5_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 575 | LDR R0, =DMA5_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 576 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 577 | ENDP |
<> | 144:ef7eb2e8f9f7 | 578 | |
<> | 144:ef7eb2e8f9f7 | 579 | DMA6_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 580 | PROC |
<> | 144:ef7eb2e8f9f7 | 581 | EXPORT DMA6_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 582 | LDR R0, =DMA6_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 583 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 584 | ENDP |
<> | 144:ef7eb2e8f9f7 | 585 | |
<> | 144:ef7eb2e8f9f7 | 586 | DMA7_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 587 | PROC |
<> | 144:ef7eb2e8f9f7 | 588 | EXPORT DMA7_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 589 | LDR R0, =DMA7_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 590 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 591 | ENDP |
<> | 144:ef7eb2e8f9f7 | 592 | |
<> | 144:ef7eb2e8f9f7 | 593 | DMA8_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 594 | PROC |
<> | 144:ef7eb2e8f9f7 | 595 | EXPORT DMA8_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 596 | LDR R0, =DMA8_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 597 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 598 | ENDP |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | DMA9_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 601 | PROC |
<> | 144:ef7eb2e8f9f7 | 602 | EXPORT DMA9_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 603 | LDR R0, =DMA9_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 604 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 605 | ENDP |
<> | 144:ef7eb2e8f9f7 | 606 | |
<> | 144:ef7eb2e8f9f7 | 607 | DMA10_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 608 | PROC |
<> | 144:ef7eb2e8f9f7 | 609 | EXPORT DMA10_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 610 | LDR R0, =DMA10_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 611 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 612 | ENDP |
<> | 144:ef7eb2e8f9f7 | 613 | |
<> | 144:ef7eb2e8f9f7 | 614 | DMA11_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 615 | PROC |
<> | 144:ef7eb2e8f9f7 | 616 | EXPORT DMA11_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 617 | LDR R0, =DMA11_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 618 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 619 | ENDP |
<> | 144:ef7eb2e8f9f7 | 620 | |
<> | 144:ef7eb2e8f9f7 | 621 | DMA12_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 622 | PROC |
<> | 144:ef7eb2e8f9f7 | 623 | EXPORT DMA12_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 624 | LDR R0, =DMA12_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 625 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 626 | ENDP |
<> | 144:ef7eb2e8f9f7 | 627 | |
<> | 144:ef7eb2e8f9f7 | 628 | DMA13_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 629 | PROC |
<> | 144:ef7eb2e8f9f7 | 630 | EXPORT DMA13_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 631 | LDR R0, =DMA13_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 632 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 633 | ENDP |
<> | 144:ef7eb2e8f9f7 | 634 | |
<> | 144:ef7eb2e8f9f7 | 635 | DMA14_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 636 | PROC |
<> | 144:ef7eb2e8f9f7 | 637 | EXPORT DMA14_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 638 | LDR R0, =DMA14_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 639 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 640 | ENDP |
<> | 144:ef7eb2e8f9f7 | 641 | |
<> | 144:ef7eb2e8f9f7 | 642 | DMA15_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 643 | PROC |
<> | 144:ef7eb2e8f9f7 | 644 | EXPORT DMA15_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 645 | LDR R0, =DMA15_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 646 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 647 | ENDP |
<> | 144:ef7eb2e8f9f7 | 648 | |
<> | 144:ef7eb2e8f9f7 | 649 | DMA_Error_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 650 | PROC |
<> | 144:ef7eb2e8f9f7 | 651 | EXPORT DMA_Error_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 652 | LDR R0, =DMA_Error_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 653 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 654 | ENDP |
<> | 144:ef7eb2e8f9f7 | 655 | |
<> | 144:ef7eb2e8f9f7 | 656 | I2C0_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 657 | PROC |
<> | 144:ef7eb2e8f9f7 | 658 | EXPORT I2C0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 659 | LDR R0, =I2C0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 660 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 661 | ENDP |
<> | 144:ef7eb2e8f9f7 | 662 | |
<> | 144:ef7eb2e8f9f7 | 663 | I2C1_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 664 | PROC |
<> | 144:ef7eb2e8f9f7 | 665 | EXPORT I2C1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 666 | LDR R0, =I2C1_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 667 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 668 | ENDP |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | SPI0_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 671 | PROC |
<> | 144:ef7eb2e8f9f7 | 672 | EXPORT SPI0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 673 | LDR R0, =SPI0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 674 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 675 | ENDP |
<> | 144:ef7eb2e8f9f7 | 676 | |
<> | 144:ef7eb2e8f9f7 | 677 | SPI1_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 678 | PROC |
<> | 144:ef7eb2e8f9f7 | 679 | EXPORT SPI1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 680 | LDR R0, =SPI1_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 681 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 682 | ENDP |
<> | 144:ef7eb2e8f9f7 | 683 | |
<> | 144:ef7eb2e8f9f7 | 684 | I2S0_Tx_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 685 | PROC |
<> | 144:ef7eb2e8f9f7 | 686 | EXPORT I2S0_Tx_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 687 | LDR R0, =I2S0_Tx_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 688 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 689 | ENDP |
<> | 144:ef7eb2e8f9f7 | 690 | |
<> | 144:ef7eb2e8f9f7 | 691 | I2S0_Rx_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 692 | PROC |
<> | 144:ef7eb2e8f9f7 | 693 | EXPORT I2S0_Rx_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 694 | LDR R0, =I2S0_Rx_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 695 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 696 | ENDP |
<> | 144:ef7eb2e8f9f7 | 697 | |
<> | 144:ef7eb2e8f9f7 | 698 | UART0_LON_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 699 | PROC |
<> | 144:ef7eb2e8f9f7 | 700 | EXPORT UART0_LON_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 701 | LDR R0, =UART0_LON_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 702 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 703 | ENDP |
<> | 144:ef7eb2e8f9f7 | 704 | |
<> | 144:ef7eb2e8f9f7 | 705 | UART0_RX_TX_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 706 | PROC |
<> | 144:ef7eb2e8f9f7 | 707 | EXPORT UART0_RX_TX_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 708 | LDR R0, =UART0_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 709 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 710 | ENDP |
<> | 144:ef7eb2e8f9f7 | 711 | |
<> | 144:ef7eb2e8f9f7 | 712 | UART0_ERR_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 713 | PROC |
<> | 144:ef7eb2e8f9f7 | 714 | EXPORT UART0_ERR_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 715 | LDR R0, =UART0_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 716 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 717 | ENDP |
<> | 144:ef7eb2e8f9f7 | 718 | |
<> | 144:ef7eb2e8f9f7 | 719 | UART1_RX_TX_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 720 | PROC |
<> | 144:ef7eb2e8f9f7 | 721 | EXPORT UART1_RX_TX_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 722 | LDR R0, =UART1_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 723 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 724 | ENDP |
<> | 144:ef7eb2e8f9f7 | 725 | |
<> | 144:ef7eb2e8f9f7 | 726 | UART1_ERR_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 727 | PROC |
<> | 144:ef7eb2e8f9f7 | 728 | EXPORT UART1_ERR_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 729 | LDR R0, =UART1_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 730 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 731 | ENDP |
<> | 144:ef7eb2e8f9f7 | 732 | |
<> | 144:ef7eb2e8f9f7 | 733 | UART2_RX_TX_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 734 | PROC |
<> | 144:ef7eb2e8f9f7 | 735 | EXPORT UART2_RX_TX_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 736 | LDR R0, =UART2_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 737 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 738 | ENDP |
<> | 144:ef7eb2e8f9f7 | 739 | |
<> | 144:ef7eb2e8f9f7 | 740 | UART2_ERR_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 741 | PROC |
<> | 144:ef7eb2e8f9f7 | 742 | EXPORT UART2_ERR_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 743 | LDR R0, =UART2_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 744 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 745 | ENDP |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | UART3_RX_TX_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 748 | PROC |
<> | 144:ef7eb2e8f9f7 | 749 | EXPORT UART3_RX_TX_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 750 | LDR R0, =UART3_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 751 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 752 | ENDP |
<> | 144:ef7eb2e8f9f7 | 753 | |
<> | 144:ef7eb2e8f9f7 | 754 | UART3_ERR_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 755 | PROC |
<> | 144:ef7eb2e8f9f7 | 756 | EXPORT UART3_ERR_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 757 | LDR R0, =UART3_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 758 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 759 | ENDP |
<> | 144:ef7eb2e8f9f7 | 760 | |
<> | 144:ef7eb2e8f9f7 | 761 | SPI2_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 762 | PROC |
<> | 144:ef7eb2e8f9f7 | 763 | EXPORT SPI2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 764 | LDR R0, =SPI2_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 765 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 766 | ENDP |
<> | 144:ef7eb2e8f9f7 | 767 | |
<> | 144:ef7eb2e8f9f7 | 768 | UART4_RX_TX_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 769 | PROC |
<> | 144:ef7eb2e8f9f7 | 770 | EXPORT UART4_RX_TX_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 771 | LDR R0, =UART4_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 772 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 773 | ENDP |
<> | 144:ef7eb2e8f9f7 | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | UART4_ERR_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 776 | PROC |
<> | 144:ef7eb2e8f9f7 | 777 | EXPORT UART4_ERR_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 778 | LDR R0, =UART4_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 779 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 780 | ENDP |
<> | 144:ef7eb2e8f9f7 | 781 | |
<> | 144:ef7eb2e8f9f7 | 782 | UART5_RX_TX_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 783 | PROC |
<> | 144:ef7eb2e8f9f7 | 784 | EXPORT UART5_RX_TX_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 785 | LDR R0, =UART5_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 786 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 787 | ENDP |
<> | 144:ef7eb2e8f9f7 | 788 | |
<> | 144:ef7eb2e8f9f7 | 789 | UART5_ERR_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 790 | PROC |
<> | 144:ef7eb2e8f9f7 | 791 | EXPORT UART5_ERR_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 792 | LDR R0, =UART5_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 793 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 794 | ENDP |
<> | 144:ef7eb2e8f9f7 | 795 | |
<> | 144:ef7eb2e8f9f7 | 796 | I2C2_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 797 | PROC |
<> | 144:ef7eb2e8f9f7 | 798 | EXPORT I2C2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 799 | LDR R0, =I2C2_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 800 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 801 | ENDP |
<> | 144:ef7eb2e8f9f7 | 802 | |
<> | 144:ef7eb2e8f9f7 | 803 | CAN0_ORed_Message_buffer_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 804 | PROC |
<> | 144:ef7eb2e8f9f7 | 805 | EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 806 | LDR R0, =CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 807 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 808 | ENDP |
<> | 144:ef7eb2e8f9f7 | 809 | |
<> | 144:ef7eb2e8f9f7 | 810 | CAN0_Bus_Off_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 811 | PROC |
<> | 144:ef7eb2e8f9f7 | 812 | EXPORT CAN0_Bus_Off_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 813 | LDR R0, =CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 814 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 815 | ENDP |
<> | 144:ef7eb2e8f9f7 | 816 | |
<> | 144:ef7eb2e8f9f7 | 817 | CAN0_Error_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 818 | PROC |
<> | 144:ef7eb2e8f9f7 | 819 | EXPORT CAN0_Error_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 820 | LDR R0, =CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 821 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 822 | ENDP |
<> | 144:ef7eb2e8f9f7 | 823 | |
<> | 144:ef7eb2e8f9f7 | 824 | CAN0_Tx_Warning_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 825 | PROC |
<> | 144:ef7eb2e8f9f7 | 826 | EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 827 | LDR R0, =CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 828 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 829 | ENDP |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | CAN0_Rx_Warning_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 832 | PROC |
<> | 144:ef7eb2e8f9f7 | 833 | EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 834 | LDR R0, =CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 835 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 836 | ENDP |
<> | 144:ef7eb2e8f9f7 | 837 | |
<> | 144:ef7eb2e8f9f7 | 838 | CAN0_Wake_Up_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 839 | PROC |
<> | 144:ef7eb2e8f9f7 | 840 | EXPORT CAN0_Wake_Up_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 841 | LDR R0, =CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 842 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 843 | ENDP |
<> | 144:ef7eb2e8f9f7 | 844 | |
<> | 144:ef7eb2e8f9f7 | 845 | SDHC_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 846 | PROC |
<> | 144:ef7eb2e8f9f7 | 847 | EXPORT SDHC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 848 | LDR R0, =SDHC_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 849 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 850 | ENDP |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | ENET_1588_Timer_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 853 | PROC |
<> | 144:ef7eb2e8f9f7 | 854 | EXPORT ENET_1588_Timer_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 855 | LDR R0, =ENET_1588_Timer_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 856 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 857 | ENDP |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | ENET_Transmit_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 860 | PROC |
<> | 144:ef7eb2e8f9f7 | 861 | EXPORT ENET_Transmit_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 862 | LDR R0, =ENET_Transmit_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 863 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 864 | ENDP |
<> | 144:ef7eb2e8f9f7 | 865 | |
<> | 144:ef7eb2e8f9f7 | 866 | ENET_Receive_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 867 | PROC |
<> | 144:ef7eb2e8f9f7 | 868 | EXPORT ENET_Receive_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 869 | LDR R0, =ENET_Receive_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 870 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 871 | ENDP |
<> | 144:ef7eb2e8f9f7 | 872 | |
<> | 144:ef7eb2e8f9f7 | 873 | ENET_Error_IRQHandler\ |
<> | 144:ef7eb2e8f9f7 | 874 | PROC |
<> | 144:ef7eb2e8f9f7 | 875 | EXPORT ENET_Error_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 876 | LDR R0, =ENET_Error_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 877 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 878 | ENDP |
<> | 144:ef7eb2e8f9f7 | 879 | |
<> | 144:ef7eb2e8f9f7 | 880 | Default_Handler\ |
<> | 144:ef7eb2e8f9f7 | 881 | PROC |
<> | 144:ef7eb2e8f9f7 | 882 | EXPORT DMA0_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 883 | EXPORT DMA1_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 884 | EXPORT DMA2_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 885 | EXPORT DMA3_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 886 | EXPORT DMA4_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 887 | EXPORT DMA5_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 888 | EXPORT DMA6_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 889 | EXPORT DMA7_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 890 | EXPORT DMA8_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 891 | EXPORT DMA9_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 892 | EXPORT DMA10_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 893 | EXPORT DMA11_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 894 | EXPORT DMA12_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 895 | EXPORT DMA13_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 896 | EXPORT DMA14_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 897 | EXPORT DMA15_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 898 | EXPORT DMA_Error_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 899 | EXPORT MCM_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 900 | EXPORT FTFE_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 901 | EXPORT Read_Collision_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 902 | EXPORT LVD_LVW_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 903 | EXPORT LLWU_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 904 | EXPORT WDOG_EWM_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 905 | EXPORT RNG_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 906 | EXPORT I2C0_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 907 | EXPORT I2C1_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 908 | EXPORT SPI0_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 909 | EXPORT SPI1_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 910 | EXPORT I2S0_Tx_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 911 | EXPORT I2S0_Rx_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 912 | EXPORT UART0_LON_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 913 | EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 914 | EXPORT UART0_ERR_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 915 | EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 916 | EXPORT UART1_ERR_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 917 | EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 918 | EXPORT UART2_ERR_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 919 | EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 920 | EXPORT UART3_ERR_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 921 | EXPORT ADC0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 922 | EXPORT CMP0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 923 | EXPORT CMP1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 924 | EXPORT FTM0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 925 | EXPORT FTM1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 926 | EXPORT FTM2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 927 | EXPORT CMT_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 928 | EXPORT RTC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 929 | EXPORT RTC_Seconds_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 930 | EXPORT PIT0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 931 | EXPORT PIT1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 932 | EXPORT PIT2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 933 | EXPORT PIT3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 934 | EXPORT PDB0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 935 | EXPORT USB0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 936 | EXPORT USBDCD_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 937 | EXPORT Reserved71_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 938 | EXPORT DAC0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 939 | EXPORT MCG_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 940 | EXPORT LPTMR0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 941 | EXPORT PORTA_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 942 | EXPORT PORTB_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 943 | EXPORT PORTC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 944 | EXPORT PORTD_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 945 | EXPORT PORTE_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 946 | EXPORT SWI_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 947 | EXPORT SPI2_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 948 | EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 949 | EXPORT UART4_ERR_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 950 | EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 951 | EXPORT UART5_ERR_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 952 | EXPORT CMP2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 953 | EXPORT FTM3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 954 | EXPORT DAC1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 955 | EXPORT ADC1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 956 | EXPORT I2C2_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 957 | EXPORT CAN0_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 958 | EXPORT SDHC_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 959 | EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 960 | EXPORT ENET_Transmit_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 961 | EXPORT ENET_Receive_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 962 | EXPORT ENET_Error_DriverIRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 963 | EXPORT DefaultISR [WEAK] |
<> | 144:ef7eb2e8f9f7 | 964 | DMA0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 965 | DMA1_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 966 | DMA2_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 967 | DMA3_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 968 | DMA4_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 969 | DMA5_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 970 | DMA6_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 971 | DMA7_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 972 | DMA8_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 973 | DMA9_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 974 | DMA10_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 975 | DMA11_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 976 | DMA12_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 977 | DMA13_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 978 | DMA14_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 979 | DMA15_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 980 | DMA_Error_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 981 | MCM_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 982 | FTFE_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 983 | Read_Collision_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 984 | LVD_LVW_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 985 | LLWU_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 986 | WDOG_EWM_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 987 | RNG_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 988 | I2C0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 989 | I2C1_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 990 | SPI0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 991 | SPI1_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 992 | I2S0_Tx_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 993 | I2S0_Rx_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 994 | UART0_LON_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 995 | UART0_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 996 | UART0_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 997 | UART1_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 998 | UART1_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 999 | UART2_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1000 | UART2_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1001 | UART3_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1002 | UART3_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1003 | ADC0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1004 | CMP0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1005 | CMP1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1006 | FTM0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1007 | FTM1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1008 | FTM2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1009 | CMT_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1010 | RTC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1011 | RTC_Seconds_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1012 | PIT0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1013 | PIT1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1014 | PIT2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1015 | PIT3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1016 | PDB0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1017 | USB0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1018 | USBDCD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1019 | Reserved71_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1020 | DAC0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1021 | MCG_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1022 | LPTMR0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1023 | PORTA_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1024 | PORTB_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1025 | PORTC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1026 | PORTD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1027 | PORTE_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1028 | SWI_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1029 | SPI2_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1030 | UART4_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1031 | UART4_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1032 | UART5_RX_TX_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1033 | UART5_ERR_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1034 | CMP2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1035 | FTM3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1036 | DAC1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1037 | ADC1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 1038 | I2C2_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1039 | CAN0_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1040 | SDHC_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1041 | ENET_1588_Timer_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1042 | ENET_Transmit_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1043 | ENET_Receive_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1044 | ENET_Error_DriverIRQHandler |
<> | 144:ef7eb2e8f9f7 | 1045 | DefaultISR |
<> | 144:ef7eb2e8f9f7 | 1046 | B DefaultISR |
<> | 144:ef7eb2e8f9f7 | 1047 | ENDP |
<> | 144:ef7eb2e8f9f7 | 1048 | ALIGN |
<> | 144:ef7eb2e8f9f7 | 1049 | |
<> | 144:ef7eb2e8f9f7 | 1050 | |
<> | 144:ef7eb2e8f9f7 | 1051 | END |