Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12_features.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Version: rev. 2.14, 2015-06-08
<> 144:ef7eb2e8f9f7 4 ** Build: b151217
<> 144:ef7eb2e8f9f7 5 **
<> 144:ef7eb2e8f9f7 6 ** Abstract:
<> 144:ef7eb2e8f9f7 7 ** Chip specific module features.
<> 144:ef7eb2e8f9f7 8 **
<> 144:ef7eb2e8f9f7 9 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 10 ** All rights reserved.
<> 144:ef7eb2e8f9f7 11 **
<> 144:ef7eb2e8f9f7 12 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 13 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 14 **
<> 144:ef7eb2e8f9f7 15 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 16 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 **
<> 144:ef7eb2e8f9f7 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 19 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 20 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 **
<> 144:ef7eb2e8f9f7 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 23 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 24 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 36 **
<> 144:ef7eb2e8f9f7 37 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 38 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 39 **
<> 144:ef7eb2e8f9f7 40 ** Revisions:
<> 144:ef7eb2e8f9f7 41 ** - rev. 1.0 (2013-08-12)
<> 144:ef7eb2e8f9f7 42 ** Initial version.
<> 144:ef7eb2e8f9f7 43 ** - rev. 2.0 (2013-10-29)
<> 144:ef7eb2e8f9f7 44 ** Register accessor macros added to the memory map.
<> 144:ef7eb2e8f9f7 45 ** Symbols for Processor Expert memory map compatibility added to the memory map.
<> 144:ef7eb2e8f9f7 46 ** Startup file for gcc has been updated according to CMSIS 3.2.
<> 144:ef7eb2e8f9f7 47 ** System initialization updated.
<> 144:ef7eb2e8f9f7 48 ** MCG - registers updated.
<> 144:ef7eb2e8f9f7 49 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
<> 144:ef7eb2e8f9f7 50 ** - rev. 2.1 (2013-10-30)
<> 144:ef7eb2e8f9f7 51 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
<> 144:ef7eb2e8f9f7 52 ** - rev. 2.2 (2013-12-09)
<> 144:ef7eb2e8f9f7 53 ** DMA - EARS register removed.
<> 144:ef7eb2e8f9f7 54 ** AIPS0, AIPS1 - MPRA register updated.
<> 144:ef7eb2e8f9f7 55 ** - rev. 2.3 (2014-01-24)
<> 144:ef7eb2e8f9f7 56 ** Update according to reference manual rev. 2
<> 144:ef7eb2e8f9f7 57 ** ENET, MCG, MCM, SIM, USB - registers updated
<> 144:ef7eb2e8f9f7 58 ** - rev. 2.4 (2014-01-30)
<> 144:ef7eb2e8f9f7 59 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
<> 144:ef7eb2e8f9f7 60 ** - rev. 2.5 (2014-02-10)
<> 144:ef7eb2e8f9f7 61 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
<> 144:ef7eb2e8f9f7 62 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
<> 144:ef7eb2e8f9f7 63 ** - rev. 2.6 (2014-02-10)
<> 144:ef7eb2e8f9f7 64 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
<> 144:ef7eb2e8f9f7 65 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
<> 144:ef7eb2e8f9f7 66 ** Module access macro module_BASES replaced by module_BASE_PTRS.
<> 144:ef7eb2e8f9f7 67 ** - rev. 2.7 (2014-08-28)
<> 144:ef7eb2e8f9f7 68 ** Update of system files - default clock configuration changed.
<> 144:ef7eb2e8f9f7 69 ** Update of startup files - possibility to override DefaultISR added.
<> 144:ef7eb2e8f9f7 70 ** - rev. 2.8 (2014-10-14)
<> 144:ef7eb2e8f9f7 71 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
<> 144:ef7eb2e8f9f7 72 ** - rev. 2.9 (2015-01-21)
<> 144:ef7eb2e8f9f7 73 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
<> 144:ef7eb2e8f9f7 74 ** - rev. 2.10 (2015-02-19)
<> 144:ef7eb2e8f9f7 75 ** Renamed interrupt vector LLW to LLWU.
<> 144:ef7eb2e8f9f7 76 ** - rev. 2.11 (2015-05-19)
<> 144:ef7eb2e8f9f7 77 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
<> 144:ef7eb2e8f9f7 78 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
<> 144:ef7eb2e8f9f7 79 ** Added features for PDB and PORT.
<> 144:ef7eb2e8f9f7 80 ** - rev. 2.12 (2015-05-25)
<> 144:ef7eb2e8f9f7 81 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
<> 144:ef7eb2e8f9f7 82 ** - rev. 2.13 (2015-05-27)
<> 144:ef7eb2e8f9f7 83 ** Several USB features added.
<> 144:ef7eb2e8f9f7 84 ** - rev. 2.14 (2015-06-08)
<> 144:ef7eb2e8f9f7 85 ** FTM features BUS_CLOCK and FAST_CLOCK removed.
<> 144:ef7eb2e8f9f7 86 **
<> 144:ef7eb2e8f9f7 87 ** ###################################################################
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #ifndef _MK64F12_FEATURES_H_
<> 144:ef7eb2e8f9f7 91 #define _MK64F12_FEATURES_H_
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* SOC module features */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #if defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \
<> 144:ef7eb2e8f9f7 96 defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
<> 144:ef7eb2e8f9f7 97 /* @brief ACMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 98 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
<> 144:ef7eb2e8f9f7 99 /* @brief ADC16 availability on the SoC. */
<> 144:ef7eb2e8f9f7 100 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
<> 144:ef7eb2e8f9f7 101 /* @brief ADC12 availability on the SoC. */
<> 144:ef7eb2e8f9f7 102 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
<> 144:ef7eb2e8f9f7 103 /* @brief AFE availability on the SoC. */
<> 144:ef7eb2e8f9f7 104 #define FSL_FEATURE_SOC_AFE_COUNT (0)
<> 144:ef7eb2e8f9f7 105 /* @brief AIPS availability on the SoC. */
<> 144:ef7eb2e8f9f7 106 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
<> 144:ef7eb2e8f9f7 107 /* @brief AOI availability on the SoC. */
<> 144:ef7eb2e8f9f7 108 #define FSL_FEATURE_SOC_AOI_COUNT (0)
<> 144:ef7eb2e8f9f7 109 /* @brief AXBS availability on the SoC. */
<> 144:ef7eb2e8f9f7 110 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
<> 144:ef7eb2e8f9f7 111 /* @brief ASMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 112 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
<> 144:ef7eb2e8f9f7 113 /* @brief CADC availability on the SoC. */
<> 144:ef7eb2e8f9f7 114 #define FSL_FEATURE_SOC_CADC_COUNT (0)
<> 144:ef7eb2e8f9f7 115 /* @brief FLEXCAN availability on the SoC. */
<> 144:ef7eb2e8f9f7 116 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
<> 144:ef7eb2e8f9f7 117 /* @brief MMCAU availability on the SoC. */
<> 144:ef7eb2e8f9f7 118 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
<> 144:ef7eb2e8f9f7 119 /* @brief CMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 120 #define FSL_FEATURE_SOC_CMP_COUNT (3)
<> 144:ef7eb2e8f9f7 121 /* @brief CMT availability on the SoC. */
<> 144:ef7eb2e8f9f7 122 #define FSL_FEATURE_SOC_CMT_COUNT (1)
<> 144:ef7eb2e8f9f7 123 /* @brief CNC availability on the SoC. */
<> 144:ef7eb2e8f9f7 124 #define FSL_FEATURE_SOC_CNC_COUNT (0)
<> 144:ef7eb2e8f9f7 125 /* @brief CRC availability on the SoC. */
<> 144:ef7eb2e8f9f7 126 #define FSL_FEATURE_SOC_CRC_COUNT (1)
<> 144:ef7eb2e8f9f7 127 /* @brief DAC availability on the SoC. */
<> 144:ef7eb2e8f9f7 128 #define FSL_FEATURE_SOC_DAC_COUNT (2)
<> 144:ef7eb2e8f9f7 129 /* @brief DAC32 availability on the SoC. */
<> 144:ef7eb2e8f9f7 130 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
<> 144:ef7eb2e8f9f7 131 /* @brief DCDC availability on the SoC. */
<> 144:ef7eb2e8f9f7 132 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
<> 144:ef7eb2e8f9f7 133 /* @brief DDR availability on the SoC. */
<> 144:ef7eb2e8f9f7 134 #define FSL_FEATURE_SOC_DDR_COUNT (0)
<> 144:ef7eb2e8f9f7 135 /* @brief DMA availability on the SoC. */
<> 144:ef7eb2e8f9f7 136 #define FSL_FEATURE_SOC_DMA_COUNT (0)
<> 144:ef7eb2e8f9f7 137 /* @brief EDMA availability on the SoC. */
<> 144:ef7eb2e8f9f7 138 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
<> 144:ef7eb2e8f9f7 139 /* @brief DMAMUX availability on the SoC. */
<> 144:ef7eb2e8f9f7 140 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
<> 144:ef7eb2e8f9f7 141 /* @brief DRY availability on the SoC. */
<> 144:ef7eb2e8f9f7 142 #define FSL_FEATURE_SOC_DRY_COUNT (0)
<> 144:ef7eb2e8f9f7 143 /* @brief DSPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 144 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
<> 144:ef7eb2e8f9f7 145 /* @brief EMVSIM availability on the SoC. */
<> 144:ef7eb2e8f9f7 146 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
<> 144:ef7eb2e8f9f7 147 /* @brief ENC availability on the SoC. */
<> 144:ef7eb2e8f9f7 148 #define FSL_FEATURE_SOC_ENC_COUNT (0)
<> 144:ef7eb2e8f9f7 149 /* @brief ENET availability on the SoC. */
<> 144:ef7eb2e8f9f7 150 #define FSL_FEATURE_SOC_ENET_COUNT (1)
<> 144:ef7eb2e8f9f7 151 /* @brief EWM availability on the SoC. */
<> 144:ef7eb2e8f9f7 152 #define FSL_FEATURE_SOC_EWM_COUNT (1)
<> 144:ef7eb2e8f9f7 153 /* @brief FB availability on the SoC. */
<> 144:ef7eb2e8f9f7 154 #define FSL_FEATURE_SOC_FB_COUNT (1)
<> 144:ef7eb2e8f9f7 155 /* @brief FGPIO availability on the SoC. */
<> 144:ef7eb2e8f9f7 156 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
<> 144:ef7eb2e8f9f7 157 /* @brief FLEXIO availability on the SoC. */
<> 144:ef7eb2e8f9f7 158 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
<> 144:ef7eb2e8f9f7 159 /* @brief FMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 160 #define FSL_FEATURE_SOC_FMC_COUNT (1)
<> 144:ef7eb2e8f9f7 161 /* @brief FSKDT availability on the SoC. */
<> 144:ef7eb2e8f9f7 162 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
<> 144:ef7eb2e8f9f7 163 /* @brief FTFA availability on the SoC. */
<> 144:ef7eb2e8f9f7 164 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
<> 144:ef7eb2e8f9f7 165 /* @brief FTFE availability on the SoC. */
<> 144:ef7eb2e8f9f7 166 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
<> 144:ef7eb2e8f9f7 167 /* @brief FTFL availability on the SoC. */
<> 144:ef7eb2e8f9f7 168 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
<> 144:ef7eb2e8f9f7 169 /* @brief FTM availability on the SoC. */
<> 144:ef7eb2e8f9f7 170 #define FSL_FEATURE_SOC_FTM_COUNT (4)
<> 144:ef7eb2e8f9f7 171 /* @brief FTMRA availability on the SoC. */
<> 144:ef7eb2e8f9f7 172 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
<> 144:ef7eb2e8f9f7 173 /* @brief FTMRE availability on the SoC. */
<> 144:ef7eb2e8f9f7 174 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
<> 144:ef7eb2e8f9f7 175 /* @brief FTMRH availability on the SoC. */
<> 144:ef7eb2e8f9f7 176 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
<> 144:ef7eb2e8f9f7 177 /* @brief GPIO availability on the SoC. */
<> 144:ef7eb2e8f9f7 178 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
<> 144:ef7eb2e8f9f7 179 /* @brief HSADC availability on the SoC. */
<> 144:ef7eb2e8f9f7 180 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
<> 144:ef7eb2e8f9f7 181 /* @brief I2C availability on the SoC. */
<> 144:ef7eb2e8f9f7 182 #define FSL_FEATURE_SOC_I2C_COUNT (3)
<> 144:ef7eb2e8f9f7 183 /* @brief I2S availability on the SoC. */
<> 144:ef7eb2e8f9f7 184 #define FSL_FEATURE_SOC_I2S_COUNT (1)
<> 144:ef7eb2e8f9f7 185 /* @brief ICS availability on the SoC. */
<> 144:ef7eb2e8f9f7 186 #define FSL_FEATURE_SOC_ICS_COUNT (0)
<> 144:ef7eb2e8f9f7 187 /* @brief INTMUX availability on the SoC. */
<> 144:ef7eb2e8f9f7 188 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
<> 144:ef7eb2e8f9f7 189 /* @brief IRQ availability on the SoC. */
<> 144:ef7eb2e8f9f7 190 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
<> 144:ef7eb2e8f9f7 191 /* @brief KBI availability on the SoC. */
<> 144:ef7eb2e8f9f7 192 #define FSL_FEATURE_SOC_KBI_COUNT (0)
<> 144:ef7eb2e8f9f7 193 /* @brief SLCD availability on the SoC. */
<> 144:ef7eb2e8f9f7 194 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
<> 144:ef7eb2e8f9f7 195 /* @brief LCDC availability on the SoC. */
<> 144:ef7eb2e8f9f7 196 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
<> 144:ef7eb2e8f9f7 197 /* @brief LDO availability on the SoC. */
<> 144:ef7eb2e8f9f7 198 #define FSL_FEATURE_SOC_LDO_COUNT (0)
<> 144:ef7eb2e8f9f7 199 /* @brief LLWU availability on the SoC. */
<> 144:ef7eb2e8f9f7 200 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
<> 144:ef7eb2e8f9f7 201 /* @brief LMEM availability on the SoC. */
<> 144:ef7eb2e8f9f7 202 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
<> 144:ef7eb2e8f9f7 203 /* @brief LPI2C availability on the SoC. */
<> 144:ef7eb2e8f9f7 204 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
<> 144:ef7eb2e8f9f7 205 /* @brief LPIT availability on the SoC. */
<> 144:ef7eb2e8f9f7 206 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
<> 144:ef7eb2e8f9f7 207 /* @brief LPSCI availability on the SoC. */
<> 144:ef7eb2e8f9f7 208 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
<> 144:ef7eb2e8f9f7 209 /* @brief LPSPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 210 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
<> 144:ef7eb2e8f9f7 211 /* @brief LPTMR availability on the SoC. */
<> 144:ef7eb2e8f9f7 212 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
<> 144:ef7eb2e8f9f7 213 /* @brief LPTPM availability on the SoC. */
<> 144:ef7eb2e8f9f7 214 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
<> 144:ef7eb2e8f9f7 215 /* @brief LPUART availability on the SoC. */
<> 144:ef7eb2e8f9f7 216 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
<> 144:ef7eb2e8f9f7 217 /* @brief LTC availability on the SoC. */
<> 144:ef7eb2e8f9f7 218 #define FSL_FEATURE_SOC_LTC_COUNT (0)
<> 144:ef7eb2e8f9f7 219 /* @brief MC availability on the SoC. */
<> 144:ef7eb2e8f9f7 220 #define FSL_FEATURE_SOC_MC_COUNT (0)
<> 144:ef7eb2e8f9f7 221 /* @brief MCG availability on the SoC. */
<> 144:ef7eb2e8f9f7 222 #define FSL_FEATURE_SOC_MCG_COUNT (1)
<> 144:ef7eb2e8f9f7 223 /* @brief MCGLITE availability on the SoC. */
<> 144:ef7eb2e8f9f7 224 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
<> 144:ef7eb2e8f9f7 225 /* @brief MCM availability on the SoC. */
<> 144:ef7eb2e8f9f7 226 #define FSL_FEATURE_SOC_MCM_COUNT (1)
<> 144:ef7eb2e8f9f7 227 /* @brief MMAU availability on the SoC. */
<> 144:ef7eb2e8f9f7 228 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
<> 144:ef7eb2e8f9f7 229 /* @brief MMDVSQ availability on the SoC. */
<> 144:ef7eb2e8f9f7 230 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
<> 144:ef7eb2e8f9f7 231 /* @brief MPU availability on the SoC. */
<> 144:ef7eb2e8f9f7 232 #define FSL_FEATURE_SOC_MPU_COUNT (1)
<> 144:ef7eb2e8f9f7 233 /* @brief MSCAN availability on the SoC. */
<> 144:ef7eb2e8f9f7 234 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
<> 144:ef7eb2e8f9f7 235 /* @brief MSCM availability on the SoC. */
<> 144:ef7eb2e8f9f7 236 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
<> 144:ef7eb2e8f9f7 237 /* @brief MTB availability on the SoC. */
<> 144:ef7eb2e8f9f7 238 #define FSL_FEATURE_SOC_MTB_COUNT (0)
<> 144:ef7eb2e8f9f7 239 /* @brief MTBDWT availability on the SoC. */
<> 144:ef7eb2e8f9f7 240 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
<> 144:ef7eb2e8f9f7 241 /* @brief MU availability on the SoC. */
<> 144:ef7eb2e8f9f7 242 #define FSL_FEATURE_SOC_MU_COUNT (0)
<> 144:ef7eb2e8f9f7 243 /* @brief NFC availability on the SoC. */
<> 144:ef7eb2e8f9f7 244 #define FSL_FEATURE_SOC_NFC_COUNT (0)
<> 144:ef7eb2e8f9f7 245 /* @brief OPAMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 246 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
<> 144:ef7eb2e8f9f7 247 /* @brief OSC availability on the SoC. */
<> 144:ef7eb2e8f9f7 248 #define FSL_FEATURE_SOC_OSC_COUNT (1)
<> 144:ef7eb2e8f9f7 249 /* @brief OSC32 availability on the SoC. */
<> 144:ef7eb2e8f9f7 250 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
<> 144:ef7eb2e8f9f7 251 /* @brief OTFAD availability on the SoC. */
<> 144:ef7eb2e8f9f7 252 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
<> 144:ef7eb2e8f9f7 253 /* @brief PDB availability on the SoC. */
<> 144:ef7eb2e8f9f7 254 #define FSL_FEATURE_SOC_PDB_COUNT (1)
<> 144:ef7eb2e8f9f7 255 /* @brief PCC availability on the SoC. */
<> 144:ef7eb2e8f9f7 256 #define FSL_FEATURE_SOC_PCC_COUNT (0)
<> 144:ef7eb2e8f9f7 257 /* @brief PGA availability on the SoC. */
<> 144:ef7eb2e8f9f7 258 #define FSL_FEATURE_SOC_PGA_COUNT (0)
<> 144:ef7eb2e8f9f7 259 /* @brief PIT availability on the SoC. */
<> 144:ef7eb2e8f9f7 260 #define FSL_FEATURE_SOC_PIT_COUNT (1)
<> 144:ef7eb2e8f9f7 261 /* @brief PMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 262 #define FSL_FEATURE_SOC_PMC_COUNT (1)
<> 144:ef7eb2e8f9f7 263 /* @brief PORT availability on the SoC. */
<> 144:ef7eb2e8f9f7 264 #define FSL_FEATURE_SOC_PORT_COUNT (5)
<> 144:ef7eb2e8f9f7 265 /* @brief PWM availability on the SoC. */
<> 144:ef7eb2e8f9f7 266 #define FSL_FEATURE_SOC_PWM_COUNT (0)
<> 144:ef7eb2e8f9f7 267 /* @brief PWT availability on the SoC. */
<> 144:ef7eb2e8f9f7 268 #define FSL_FEATURE_SOC_PWT_COUNT (0)
<> 144:ef7eb2e8f9f7 269 /* @brief QuadSPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 270 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
<> 144:ef7eb2e8f9f7 271 /* @brief RCM availability on the SoC. */
<> 144:ef7eb2e8f9f7 272 #define FSL_FEATURE_SOC_RCM_COUNT (1)
<> 144:ef7eb2e8f9f7 273 /* @brief RFSYS availability on the SoC. */
<> 144:ef7eb2e8f9f7 274 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
<> 144:ef7eb2e8f9f7 275 /* @brief RFVBAT availability on the SoC. */
<> 144:ef7eb2e8f9f7 276 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
<> 144:ef7eb2e8f9f7 277 /* @brief RNG availability on the SoC. */
<> 144:ef7eb2e8f9f7 278 #define FSL_FEATURE_SOC_RNG_COUNT (1)
<> 144:ef7eb2e8f9f7 279 /* @brief RNGB availability on the SoC. */
<> 144:ef7eb2e8f9f7 280 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
<> 144:ef7eb2e8f9f7 281 /* @brief ROM availability on the SoC. */
<> 144:ef7eb2e8f9f7 282 #define FSL_FEATURE_SOC_ROM_COUNT (0)
<> 144:ef7eb2e8f9f7 283 /* @brief RSIM availability on the SoC. */
<> 144:ef7eb2e8f9f7 284 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
<> 144:ef7eb2e8f9f7 285 /* @brief RTC availability on the SoC. */
<> 144:ef7eb2e8f9f7 286 #define FSL_FEATURE_SOC_RTC_COUNT (1)
<> 144:ef7eb2e8f9f7 287 /* @brief SCG availability on the SoC. */
<> 144:ef7eb2e8f9f7 288 #define FSL_FEATURE_SOC_SCG_COUNT (0)
<> 144:ef7eb2e8f9f7 289 /* @brief SCI availability on the SoC. */
<> 144:ef7eb2e8f9f7 290 #define FSL_FEATURE_SOC_SCI_COUNT (0)
<> 144:ef7eb2e8f9f7 291 /* @brief SDHC availability on the SoC. */
<> 144:ef7eb2e8f9f7 292 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
<> 144:ef7eb2e8f9f7 293 /* @brief SDRAM availability on the SoC. */
<> 144:ef7eb2e8f9f7 294 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
<> 144:ef7eb2e8f9f7 295 /* @brief SEMA42 availability on the SoC. */
<> 144:ef7eb2e8f9f7 296 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
<> 144:ef7eb2e8f9f7 297 /* @brief SIM availability on the SoC. */
<> 144:ef7eb2e8f9f7 298 #define FSL_FEATURE_SOC_SIM_COUNT (1)
<> 144:ef7eb2e8f9f7 299 /* @brief SMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 300 #define FSL_FEATURE_SOC_SMC_COUNT (1)
<> 144:ef7eb2e8f9f7 301 /* @brief SPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 302 #define FSL_FEATURE_SOC_SPI_COUNT (0)
<> 144:ef7eb2e8f9f7 303 /* @brief TMR availability on the SoC. */
<> 144:ef7eb2e8f9f7 304 #define FSL_FEATURE_SOC_TMR_COUNT (0)
<> 144:ef7eb2e8f9f7 305 /* @brief TPM availability on the SoC. */
<> 144:ef7eb2e8f9f7 306 #define FSL_FEATURE_SOC_TPM_COUNT (0)
<> 144:ef7eb2e8f9f7 307 /* @brief TRGMUX availability on the SoC. */
<> 144:ef7eb2e8f9f7 308 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
<> 144:ef7eb2e8f9f7 309 /* @brief TRIAMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 310 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
<> 144:ef7eb2e8f9f7 311 /* @brief TRNG availability on the SoC. */
<> 144:ef7eb2e8f9f7 312 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
<> 144:ef7eb2e8f9f7 313 /* @brief TSI availability on the SoC. */
<> 144:ef7eb2e8f9f7 314 #define FSL_FEATURE_SOC_TSI_COUNT (0)
<> 144:ef7eb2e8f9f7 315 /* @brief TSTMR availability on the SoC. */
<> 144:ef7eb2e8f9f7 316 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
<> 144:ef7eb2e8f9f7 317 /* @brief UART availability on the SoC. */
<> 144:ef7eb2e8f9f7 318 #define FSL_FEATURE_SOC_UART_COUNT (6)
<> 144:ef7eb2e8f9f7 319 /* @brief USB availability on the SoC. */
<> 144:ef7eb2e8f9f7 320 #define FSL_FEATURE_SOC_USB_COUNT (1)
<> 144:ef7eb2e8f9f7 321 /* @brief USBDCD availability on the SoC. */
<> 144:ef7eb2e8f9f7 322 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
<> 144:ef7eb2e8f9f7 323 /* @brief USBHSDCD availability on the SoC. */
<> 144:ef7eb2e8f9f7 324 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
<> 144:ef7eb2e8f9f7 325 /* @brief USBPHY availability on the SoC. */
<> 144:ef7eb2e8f9f7 326 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
<> 144:ef7eb2e8f9f7 327 /* @brief VREF availability on the SoC. */
<> 144:ef7eb2e8f9f7 328 #define FSL_FEATURE_SOC_VREF_COUNT (1)
<> 144:ef7eb2e8f9f7 329 /* @brief WDOG availability on the SoC. */
<> 144:ef7eb2e8f9f7 330 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
<> 144:ef7eb2e8f9f7 331 /* @brief XBAR availability on the SoC. */
<> 144:ef7eb2e8f9f7 332 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
<> 144:ef7eb2e8f9f7 333 /* @brief XBARA availability on the SoC. */
<> 144:ef7eb2e8f9f7 334 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
<> 144:ef7eb2e8f9f7 335 /* @brief XBARB availability on the SoC. */
<> 144:ef7eb2e8f9f7 336 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
<> 144:ef7eb2e8f9f7 337 /* @brief XCVR availability on the SoC. */
<> 144:ef7eb2e8f9f7 338 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
<> 144:ef7eb2e8f9f7 339 /* @brief XRDC availability on the SoC. */
<> 144:ef7eb2e8f9f7 340 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
<> 144:ef7eb2e8f9f7 341 /* @brief ZLL availability on the SoC. */
<> 144:ef7eb2e8f9f7 342 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
<> 144:ef7eb2e8f9f7 343 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12)
<> 144:ef7eb2e8f9f7 344 /* @brief ACMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 345 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
<> 144:ef7eb2e8f9f7 346 /* @brief ADC16 availability on the SoC. */
<> 144:ef7eb2e8f9f7 347 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
<> 144:ef7eb2e8f9f7 348 /* @brief ADC12 availability on the SoC. */
<> 144:ef7eb2e8f9f7 349 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
<> 144:ef7eb2e8f9f7 350 /* @brief AFE availability on the SoC. */
<> 144:ef7eb2e8f9f7 351 #define FSL_FEATURE_SOC_AFE_COUNT (0)
<> 144:ef7eb2e8f9f7 352 /* @brief AIPS availability on the SoC. */
<> 144:ef7eb2e8f9f7 353 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
<> 144:ef7eb2e8f9f7 354 /* @brief AOI availability on the SoC. */
<> 144:ef7eb2e8f9f7 355 #define FSL_FEATURE_SOC_AOI_COUNT (0)
<> 144:ef7eb2e8f9f7 356 /* @brief AXBS availability on the SoC. */
<> 144:ef7eb2e8f9f7 357 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
<> 144:ef7eb2e8f9f7 358 /* @brief ASMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 359 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
<> 144:ef7eb2e8f9f7 360 /* @brief CADC availability on the SoC. */
<> 144:ef7eb2e8f9f7 361 #define FSL_FEATURE_SOC_CADC_COUNT (0)
<> 144:ef7eb2e8f9f7 362 /* @brief FLEXCAN availability on the SoC. */
<> 144:ef7eb2e8f9f7 363 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
<> 144:ef7eb2e8f9f7 364 /* @brief MMCAU availability on the SoC. */
<> 144:ef7eb2e8f9f7 365 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
<> 144:ef7eb2e8f9f7 366 /* @brief CMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 367 #define FSL_FEATURE_SOC_CMP_COUNT (3)
<> 144:ef7eb2e8f9f7 368 /* @brief CMT availability on the SoC. */
<> 144:ef7eb2e8f9f7 369 #define FSL_FEATURE_SOC_CMT_COUNT (1)
<> 144:ef7eb2e8f9f7 370 /* @brief CNC availability on the SoC. */
<> 144:ef7eb2e8f9f7 371 #define FSL_FEATURE_SOC_CNC_COUNT (0)
<> 144:ef7eb2e8f9f7 372 /* @brief CRC availability on the SoC. */
<> 144:ef7eb2e8f9f7 373 #define FSL_FEATURE_SOC_CRC_COUNT (1)
<> 144:ef7eb2e8f9f7 374 /* @brief DAC availability on the SoC. */
<> 144:ef7eb2e8f9f7 375 #define FSL_FEATURE_SOC_DAC_COUNT (1)
<> 144:ef7eb2e8f9f7 376 /* @brief DAC32 availability on the SoC. */
<> 144:ef7eb2e8f9f7 377 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
<> 144:ef7eb2e8f9f7 378 /* @brief DCDC availability on the SoC. */
<> 144:ef7eb2e8f9f7 379 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
<> 144:ef7eb2e8f9f7 380 /* @brief DDR availability on the SoC. */
<> 144:ef7eb2e8f9f7 381 #define FSL_FEATURE_SOC_DDR_COUNT (0)
<> 144:ef7eb2e8f9f7 382 /* @brief DMA availability on the SoC. */
<> 144:ef7eb2e8f9f7 383 #define FSL_FEATURE_SOC_DMA_COUNT (0)
<> 144:ef7eb2e8f9f7 384 /* @brief EDMA availability on the SoC. */
<> 144:ef7eb2e8f9f7 385 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
<> 144:ef7eb2e8f9f7 386 /* @brief DMAMUX availability on the SoC. */
<> 144:ef7eb2e8f9f7 387 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
<> 144:ef7eb2e8f9f7 388 /* @brief DRY availability on the SoC. */
<> 144:ef7eb2e8f9f7 389 #define FSL_FEATURE_SOC_DRY_COUNT (0)
<> 144:ef7eb2e8f9f7 390 /* @brief DSPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 391 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
<> 144:ef7eb2e8f9f7 392 /* @brief EMVSIM availability on the SoC. */
<> 144:ef7eb2e8f9f7 393 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
<> 144:ef7eb2e8f9f7 394 /* @brief ENC availability on the SoC. */
<> 144:ef7eb2e8f9f7 395 #define FSL_FEATURE_SOC_ENC_COUNT (0)
<> 144:ef7eb2e8f9f7 396 /* @brief ENET availability on the SoC. */
<> 144:ef7eb2e8f9f7 397 #define FSL_FEATURE_SOC_ENET_COUNT (1)
<> 144:ef7eb2e8f9f7 398 /* @brief EWM availability on the SoC. */
<> 144:ef7eb2e8f9f7 399 #define FSL_FEATURE_SOC_EWM_COUNT (1)
<> 144:ef7eb2e8f9f7 400 /* @brief FB availability on the SoC. */
<> 144:ef7eb2e8f9f7 401 #define FSL_FEATURE_SOC_FB_COUNT (1)
<> 144:ef7eb2e8f9f7 402 /* @brief FGPIO availability on the SoC. */
<> 144:ef7eb2e8f9f7 403 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
<> 144:ef7eb2e8f9f7 404 /* @brief FLEXIO availability on the SoC. */
<> 144:ef7eb2e8f9f7 405 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
<> 144:ef7eb2e8f9f7 406 /* @brief FMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 407 #define FSL_FEATURE_SOC_FMC_COUNT (1)
<> 144:ef7eb2e8f9f7 408 /* @brief FSKDT availability on the SoC. */
<> 144:ef7eb2e8f9f7 409 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
<> 144:ef7eb2e8f9f7 410 /* @brief FTFA availability on the SoC. */
<> 144:ef7eb2e8f9f7 411 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
<> 144:ef7eb2e8f9f7 412 /* @brief FTFE availability on the SoC. */
<> 144:ef7eb2e8f9f7 413 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
<> 144:ef7eb2e8f9f7 414 /* @brief FTFL availability on the SoC. */
<> 144:ef7eb2e8f9f7 415 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
<> 144:ef7eb2e8f9f7 416 /* @brief FTM availability on the SoC. */
<> 144:ef7eb2e8f9f7 417 #define FSL_FEATURE_SOC_FTM_COUNT (4)
<> 144:ef7eb2e8f9f7 418 /* @brief FTMRA availability on the SoC. */
<> 144:ef7eb2e8f9f7 419 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
<> 144:ef7eb2e8f9f7 420 /* @brief FTMRE availability on the SoC. */
<> 144:ef7eb2e8f9f7 421 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
<> 144:ef7eb2e8f9f7 422 /* @brief FTMRH availability on the SoC. */
<> 144:ef7eb2e8f9f7 423 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
<> 144:ef7eb2e8f9f7 424 /* @brief GPIO availability on the SoC. */
<> 144:ef7eb2e8f9f7 425 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
<> 144:ef7eb2e8f9f7 426 /* @brief HSADC availability on the SoC. */
<> 144:ef7eb2e8f9f7 427 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
<> 144:ef7eb2e8f9f7 428 /* @brief I2C availability on the SoC. */
<> 144:ef7eb2e8f9f7 429 #define FSL_FEATURE_SOC_I2C_COUNT (3)
<> 144:ef7eb2e8f9f7 430 /* @brief I2S availability on the SoC. */
<> 144:ef7eb2e8f9f7 431 #define FSL_FEATURE_SOC_I2S_COUNT (1)
<> 144:ef7eb2e8f9f7 432 /* @brief ICS availability on the SoC. */
<> 144:ef7eb2e8f9f7 433 #define FSL_FEATURE_SOC_ICS_COUNT (0)
<> 144:ef7eb2e8f9f7 434 /* @brief INTMUX availability on the SoC. */
<> 144:ef7eb2e8f9f7 435 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
<> 144:ef7eb2e8f9f7 436 /* @brief IRQ availability on the SoC. */
<> 144:ef7eb2e8f9f7 437 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
<> 144:ef7eb2e8f9f7 438 /* @brief KBI availability on the SoC. */
<> 144:ef7eb2e8f9f7 439 #define FSL_FEATURE_SOC_KBI_COUNT (0)
<> 144:ef7eb2e8f9f7 440 /* @brief SLCD availability on the SoC. */
<> 144:ef7eb2e8f9f7 441 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
<> 144:ef7eb2e8f9f7 442 /* @brief LCDC availability on the SoC. */
<> 144:ef7eb2e8f9f7 443 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
<> 144:ef7eb2e8f9f7 444 /* @brief LDO availability on the SoC. */
<> 144:ef7eb2e8f9f7 445 #define FSL_FEATURE_SOC_LDO_COUNT (0)
<> 144:ef7eb2e8f9f7 446 /* @brief LLWU availability on the SoC. */
<> 144:ef7eb2e8f9f7 447 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
<> 144:ef7eb2e8f9f7 448 /* @brief LMEM availability on the SoC. */
<> 144:ef7eb2e8f9f7 449 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
<> 144:ef7eb2e8f9f7 450 /* @brief LPI2C availability on the SoC. */
<> 144:ef7eb2e8f9f7 451 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
<> 144:ef7eb2e8f9f7 452 /* @brief LPIT availability on the SoC. */
<> 144:ef7eb2e8f9f7 453 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
<> 144:ef7eb2e8f9f7 454 /* @brief LPSCI availability on the SoC. */
<> 144:ef7eb2e8f9f7 455 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
<> 144:ef7eb2e8f9f7 456 /* @brief LPSPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 457 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
<> 144:ef7eb2e8f9f7 458 /* @brief LPTMR availability on the SoC. */
<> 144:ef7eb2e8f9f7 459 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
<> 144:ef7eb2e8f9f7 460 /* @brief LPTPM availability on the SoC. */
<> 144:ef7eb2e8f9f7 461 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
<> 144:ef7eb2e8f9f7 462 /* @brief LPUART availability on the SoC. */
<> 144:ef7eb2e8f9f7 463 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
<> 144:ef7eb2e8f9f7 464 /* @brief LTC availability on the SoC. */
<> 144:ef7eb2e8f9f7 465 #define FSL_FEATURE_SOC_LTC_COUNT (0)
<> 144:ef7eb2e8f9f7 466 /* @brief MC availability on the SoC. */
<> 144:ef7eb2e8f9f7 467 #define FSL_FEATURE_SOC_MC_COUNT (0)
<> 144:ef7eb2e8f9f7 468 /* @brief MCG availability on the SoC. */
<> 144:ef7eb2e8f9f7 469 #define FSL_FEATURE_SOC_MCG_COUNT (1)
<> 144:ef7eb2e8f9f7 470 /* @brief MCGLITE availability on the SoC. */
<> 144:ef7eb2e8f9f7 471 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
<> 144:ef7eb2e8f9f7 472 /* @brief MCM availability on the SoC. */
<> 144:ef7eb2e8f9f7 473 #define FSL_FEATURE_SOC_MCM_COUNT (1)
<> 144:ef7eb2e8f9f7 474 /* @brief MMAU availability on the SoC. */
<> 144:ef7eb2e8f9f7 475 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
<> 144:ef7eb2e8f9f7 476 /* @brief MMDVSQ availability on the SoC. */
<> 144:ef7eb2e8f9f7 477 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
<> 144:ef7eb2e8f9f7 478 /* @brief MPU availability on the SoC. */
<> 144:ef7eb2e8f9f7 479 #define FSL_FEATURE_SOC_MPU_COUNT (1)
<> 144:ef7eb2e8f9f7 480 /* @brief MSCAN availability on the SoC. */
<> 144:ef7eb2e8f9f7 481 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
<> 144:ef7eb2e8f9f7 482 /* @brief MSCM availability on the SoC. */
<> 144:ef7eb2e8f9f7 483 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
<> 144:ef7eb2e8f9f7 484 /* @brief MTB availability on the SoC. */
<> 144:ef7eb2e8f9f7 485 #define FSL_FEATURE_SOC_MTB_COUNT (0)
<> 144:ef7eb2e8f9f7 486 /* @brief MTBDWT availability on the SoC. */
<> 144:ef7eb2e8f9f7 487 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
<> 144:ef7eb2e8f9f7 488 /* @brief MU availability on the SoC. */
<> 144:ef7eb2e8f9f7 489 #define FSL_FEATURE_SOC_MU_COUNT (0)
<> 144:ef7eb2e8f9f7 490 /* @brief NFC availability on the SoC. */
<> 144:ef7eb2e8f9f7 491 #define FSL_FEATURE_SOC_NFC_COUNT (0)
<> 144:ef7eb2e8f9f7 492 /* @brief OPAMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 493 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
<> 144:ef7eb2e8f9f7 494 /* @brief OSC availability on the SoC. */
<> 144:ef7eb2e8f9f7 495 #define FSL_FEATURE_SOC_OSC_COUNT (1)
<> 144:ef7eb2e8f9f7 496 /* @brief OSC32 availability on the SoC. */
<> 144:ef7eb2e8f9f7 497 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
<> 144:ef7eb2e8f9f7 498 /* @brief OTFAD availability on the SoC. */
<> 144:ef7eb2e8f9f7 499 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
<> 144:ef7eb2e8f9f7 500 /* @brief PDB availability on the SoC. */
<> 144:ef7eb2e8f9f7 501 #define FSL_FEATURE_SOC_PDB_COUNT (1)
<> 144:ef7eb2e8f9f7 502 /* @brief PCC availability on the SoC. */
<> 144:ef7eb2e8f9f7 503 #define FSL_FEATURE_SOC_PCC_COUNT (0)
<> 144:ef7eb2e8f9f7 504 /* @brief PGA availability on the SoC. */
<> 144:ef7eb2e8f9f7 505 #define FSL_FEATURE_SOC_PGA_COUNT (0)
<> 144:ef7eb2e8f9f7 506 /* @brief PIT availability on the SoC. */
<> 144:ef7eb2e8f9f7 507 #define FSL_FEATURE_SOC_PIT_COUNT (1)
<> 144:ef7eb2e8f9f7 508 /* @brief PMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 509 #define FSL_FEATURE_SOC_PMC_COUNT (1)
<> 144:ef7eb2e8f9f7 510 /* @brief PORT availability on the SoC. */
<> 144:ef7eb2e8f9f7 511 #define FSL_FEATURE_SOC_PORT_COUNT (5)
<> 144:ef7eb2e8f9f7 512 /* @brief PWM availability on the SoC. */
<> 144:ef7eb2e8f9f7 513 #define FSL_FEATURE_SOC_PWM_COUNT (0)
<> 144:ef7eb2e8f9f7 514 /* @brief PWT availability on the SoC. */
<> 144:ef7eb2e8f9f7 515 #define FSL_FEATURE_SOC_PWT_COUNT (0)
<> 144:ef7eb2e8f9f7 516 /* @brief QuadSPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 517 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
<> 144:ef7eb2e8f9f7 518 /* @brief RCM availability on the SoC. */
<> 144:ef7eb2e8f9f7 519 #define FSL_FEATURE_SOC_RCM_COUNT (1)
<> 144:ef7eb2e8f9f7 520 /* @brief RFSYS availability on the SoC. */
<> 144:ef7eb2e8f9f7 521 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
<> 144:ef7eb2e8f9f7 522 /* @brief RFVBAT availability on the SoC. */
<> 144:ef7eb2e8f9f7 523 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
<> 144:ef7eb2e8f9f7 524 /* @brief RNG availability on the SoC. */
<> 144:ef7eb2e8f9f7 525 #define FSL_FEATURE_SOC_RNG_COUNT (1)
<> 144:ef7eb2e8f9f7 526 /* @brief RNGB availability on the SoC. */
<> 144:ef7eb2e8f9f7 527 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
<> 144:ef7eb2e8f9f7 528 /* @brief ROM availability on the SoC. */
<> 144:ef7eb2e8f9f7 529 #define FSL_FEATURE_SOC_ROM_COUNT (0)
<> 144:ef7eb2e8f9f7 530 /* @brief RSIM availability on the SoC. */
<> 144:ef7eb2e8f9f7 531 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
<> 144:ef7eb2e8f9f7 532 /* @brief RTC availability on the SoC. */
<> 144:ef7eb2e8f9f7 533 #define FSL_FEATURE_SOC_RTC_COUNT (1)
<> 144:ef7eb2e8f9f7 534 /* @brief SCG availability on the SoC. */
<> 144:ef7eb2e8f9f7 535 #define FSL_FEATURE_SOC_SCG_COUNT (0)
<> 144:ef7eb2e8f9f7 536 /* @brief SCI availability on the SoC. */
<> 144:ef7eb2e8f9f7 537 #define FSL_FEATURE_SOC_SCI_COUNT (0)
<> 144:ef7eb2e8f9f7 538 /* @brief SDHC availability on the SoC. */
<> 144:ef7eb2e8f9f7 539 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
<> 144:ef7eb2e8f9f7 540 /* @brief SDRAM availability on the SoC. */
<> 144:ef7eb2e8f9f7 541 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
<> 144:ef7eb2e8f9f7 542 /* @brief SEMA42 availability on the SoC. */
<> 144:ef7eb2e8f9f7 543 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
<> 144:ef7eb2e8f9f7 544 /* @brief SIM availability on the SoC. */
<> 144:ef7eb2e8f9f7 545 #define FSL_FEATURE_SOC_SIM_COUNT (1)
<> 144:ef7eb2e8f9f7 546 /* @brief SMC availability on the SoC. */
<> 144:ef7eb2e8f9f7 547 #define FSL_FEATURE_SOC_SMC_COUNT (1)
<> 144:ef7eb2e8f9f7 548 /* @brief SPI availability on the SoC. */
<> 144:ef7eb2e8f9f7 549 #define FSL_FEATURE_SOC_SPI_COUNT (0)
<> 144:ef7eb2e8f9f7 550 /* @brief TMR availability on the SoC. */
<> 144:ef7eb2e8f9f7 551 #define FSL_FEATURE_SOC_TMR_COUNT (0)
<> 144:ef7eb2e8f9f7 552 /* @brief TPM availability on the SoC. */
<> 144:ef7eb2e8f9f7 553 #define FSL_FEATURE_SOC_TPM_COUNT (0)
<> 144:ef7eb2e8f9f7 554 /* @brief TRGMUX availability on the SoC. */
<> 144:ef7eb2e8f9f7 555 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
<> 144:ef7eb2e8f9f7 556 /* @brief TRIAMP availability on the SoC. */
<> 144:ef7eb2e8f9f7 557 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
<> 144:ef7eb2e8f9f7 558 /* @brief TRNG availability on the SoC. */
<> 144:ef7eb2e8f9f7 559 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
<> 144:ef7eb2e8f9f7 560 /* @brief TSI availability on the SoC. */
<> 144:ef7eb2e8f9f7 561 #define FSL_FEATURE_SOC_TSI_COUNT (0)
<> 144:ef7eb2e8f9f7 562 /* @brief TSTMR availability on the SoC. */
<> 144:ef7eb2e8f9f7 563 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
<> 144:ef7eb2e8f9f7 564 /* @brief UART availability on the SoC. */
<> 144:ef7eb2e8f9f7 565 #define FSL_FEATURE_SOC_UART_COUNT (6)
<> 144:ef7eb2e8f9f7 566 /* @brief USB availability on the SoC. */
<> 144:ef7eb2e8f9f7 567 #define FSL_FEATURE_SOC_USB_COUNT (1)
<> 144:ef7eb2e8f9f7 568 /* @brief USBDCD availability on the SoC. */
<> 144:ef7eb2e8f9f7 569 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
<> 144:ef7eb2e8f9f7 570 /* @brief USBHSDCD availability on the SoC. */
<> 144:ef7eb2e8f9f7 571 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
<> 144:ef7eb2e8f9f7 572 /* @brief USBPHY availability on the SoC. */
<> 144:ef7eb2e8f9f7 573 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
<> 144:ef7eb2e8f9f7 574 /* @brief VREF availability on the SoC. */
<> 144:ef7eb2e8f9f7 575 #define FSL_FEATURE_SOC_VREF_COUNT (1)
<> 144:ef7eb2e8f9f7 576 /* @brief WDOG availability on the SoC. */
<> 144:ef7eb2e8f9f7 577 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
<> 144:ef7eb2e8f9f7 578 /* @brief XBAR availability on the SoC. */
<> 144:ef7eb2e8f9f7 579 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
<> 144:ef7eb2e8f9f7 580 /* @brief XBARA availability on the SoC. */
<> 144:ef7eb2e8f9f7 581 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
<> 144:ef7eb2e8f9f7 582 /* @brief XBARB availability on the SoC. */
<> 144:ef7eb2e8f9f7 583 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
<> 144:ef7eb2e8f9f7 584 /* @brief XCVR availability on the SoC. */
<> 144:ef7eb2e8f9f7 585 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
<> 144:ef7eb2e8f9f7 586 /* @brief XRDC availability on the SoC. */
<> 144:ef7eb2e8f9f7 587 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
<> 144:ef7eb2e8f9f7 588 /* @brief ZLL availability on the SoC. */
<> 144:ef7eb2e8f9f7 589 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
<> 144:ef7eb2e8f9f7 590 #endif
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* ADC16 module features */
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
<> 144:ef7eb2e8f9f7 595 #define FSL_FEATURE_ADC16_HAS_PGA (0)
<> 144:ef7eb2e8f9f7 596 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
<> 144:ef7eb2e8f9f7 597 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
<> 144:ef7eb2e8f9f7 598 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
<> 144:ef7eb2e8f9f7 599 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
<> 144:ef7eb2e8f9f7 600 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
<> 144:ef7eb2e8f9f7 601 #define FSL_FEATURE_ADC16_HAS_DMA (1)
<> 144:ef7eb2e8f9f7 602 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
<> 144:ef7eb2e8f9f7 603 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
<> 144:ef7eb2e8f9f7 604 /* @brief Has FIFO (bit SC4[AFDEP]). */
<> 144:ef7eb2e8f9f7 605 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
<> 144:ef7eb2e8f9f7 606 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
<> 144:ef7eb2e8f9f7 607 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
<> 144:ef7eb2e8f9f7 608 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
<> 144:ef7eb2e8f9f7 609 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
<> 144:ef7eb2e8f9f7 610 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
<> 144:ef7eb2e8f9f7 611 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
<> 144:ef7eb2e8f9f7 612 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
<> 144:ef7eb2e8f9f7 613 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
<> 144:ef7eb2e8f9f7 614 /* @brief Has HW averaging (bit SC3[AVGE]). */
<> 144:ef7eb2e8f9f7 615 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
<> 144:ef7eb2e8f9f7 616 /* @brief Has offset correction (register OFS). */
<> 144:ef7eb2e8f9f7 617 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
<> 144:ef7eb2e8f9f7 618 /* @brief Maximum ADC resolution. */
<> 144:ef7eb2e8f9f7 619 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
<> 144:ef7eb2e8f9f7 620 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
<> 144:ef7eb2e8f9f7 621 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* FLEXCAN module features */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* @brief Message buffer size */
<> 144:ef7eb2e8f9f7 626 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
<> 144:ef7eb2e8f9f7 627 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
<> 144:ef7eb2e8f9f7 628 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
<> 144:ef7eb2e8f9f7 629 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
<> 144:ef7eb2e8f9f7 630 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
<> 144:ef7eb2e8f9f7 631 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
<> 144:ef7eb2e8f9f7 632 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
<> 144:ef7eb2e8f9f7 633 /* @brief Has extended bit timing register (register CBT). */
<> 144:ef7eb2e8f9f7 634 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
<> 144:ef7eb2e8f9f7 635 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
<> 144:ef7eb2e8f9f7 636 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
<> 144:ef7eb2e8f9f7 637 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
<> 144:ef7eb2e8f9f7 638 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
<> 144:ef7eb2e8f9f7 639 /* @brief Has bitfield name BUF31TO0M. */
<> 144:ef7eb2e8f9f7 640 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
<> 144:ef7eb2e8f9f7 641 /* @brief Number of interrupt vectors. */
<> 144:ef7eb2e8f9f7 642 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* CMP module features */
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
<> 144:ef7eb2e8f9f7 647 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
<> 144:ef7eb2e8f9f7 648 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
<> 144:ef7eb2e8f9f7 649 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
<> 144:ef7eb2e8f9f7 650 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
<> 144:ef7eb2e8f9f7 651 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
<> 144:ef7eb2e8f9f7 652 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
<> 144:ef7eb2e8f9f7 653 #define FSL_FEATURE_CMP_HAS_DMA (1)
<> 144:ef7eb2e8f9f7 654 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
<> 144:ef7eb2e8f9f7 655 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
<> 144:ef7eb2e8f9f7 656 /* @brief Has DAC Test function in CMP (register DACTEST). */
<> 144:ef7eb2e8f9f7 657 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* CRC module features */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* @brief Has data register with name CRC */
<> 144:ef7eb2e8f9f7 662 #define FSL_FEATURE_CRC_HAS_CRC_REG (0)
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* DAC module features */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* @brief Define the size of hardware buffer */
<> 144:ef7eb2e8f9f7 667 #define FSL_FEATURE_DAC_BUFFER_SIZE (16)
<> 144:ef7eb2e8f9f7 668 /* @brief Define whether the buffer supports watermark event detection or not. */
<> 144:ef7eb2e8f9f7 669 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
<> 144:ef7eb2e8f9f7 670 /* @brief Define whether the buffer supports watermark selection detection or not. */
<> 144:ef7eb2e8f9f7 671 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
<> 144:ef7eb2e8f9f7 672 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
<> 144:ef7eb2e8f9f7 673 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
<> 144:ef7eb2e8f9f7 674 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
<> 144:ef7eb2e8f9f7 675 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
<> 144:ef7eb2e8f9f7 676 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
<> 144:ef7eb2e8f9f7 677 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
<> 144:ef7eb2e8f9f7 678 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
<> 144:ef7eb2e8f9f7 679 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
<> 144:ef7eb2e8f9f7 680 /* @brief Define whether FIFO buffer mode is available or not. */
<> 144:ef7eb2e8f9f7 681 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
<> 144:ef7eb2e8f9f7 682 /* @brief Define whether swing buffer mode is available or not.. */
<> 144:ef7eb2e8f9f7 683 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* EDMA module features */
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
<> 144:ef7eb2e8f9f7 688 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
<> 144:ef7eb2e8f9f7 689 /* @brief Total number of DMA channels on all modules. */
<> 144:ef7eb2e8f9f7 690 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16)
<> 144:ef7eb2e8f9f7 691 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
<> 144:ef7eb2e8f9f7 692 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
<> 144:ef7eb2e8f9f7 693 /* @brief Has DMA_Error interrupt vector. */
<> 144:ef7eb2e8f9f7 694 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
<> 144:ef7eb2e8f9f7 695 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
<> 144:ef7eb2e8f9f7 696 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* DMAMUX module features */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* @brief Number of DMA channels (related to number of register CHCFGn). */
<> 144:ef7eb2e8f9f7 701 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
<> 144:ef7eb2e8f9f7 702 /* @brief Total number of DMA channels on all modules. */
<> 144:ef7eb2e8f9f7 703 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
<> 144:ef7eb2e8f9f7 704 /* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
<> 144:ef7eb2e8f9f7 705 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /* ENET module features */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
<> 144:ef7eb2e8f9f7 710 #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
<> 144:ef7eb2e8f9f7 711 /* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
<> 144:ef7eb2e8f9f7 712 #define FSL_FEATURE_ENET_SUPPORT_PTP (1)
<> 144:ef7eb2e8f9f7 713 /* @brief Number of associated interrupt vectors. */
<> 144:ef7eb2e8f9f7 714 #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
<> 144:ef7eb2e8f9f7 715 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
<> 144:ef7eb2e8f9f7 716 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* EWM module features */
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* @brief Has clock select (register CLKCTRL). */
<> 144:ef7eb2e8f9f7 721 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
<> 144:ef7eb2e8f9f7 722 /* @brief Has clock prescaler (register CLKPRESCALER). */
<> 144:ef7eb2e8f9f7 723 #define FSL_FEATURE_EWM_HAS_PRESCALER (0)
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* FLEXBUS module features */
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* No feature definitions */
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* FLASH module features */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #if defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
<> 144:ef7eb2e8f9f7 732 /* @brief Is of type FTFA. */
<> 144:ef7eb2e8f9f7 733 #define FSL_FEATURE_FLASH_IS_FTFA (0)
<> 144:ef7eb2e8f9f7 734 /* @brief Is of type FTFE. */
<> 144:ef7eb2e8f9f7 735 #define FSL_FEATURE_FLASH_IS_FTFE (1)
<> 144:ef7eb2e8f9f7 736 /* @brief Is of type FTFL. */
<> 144:ef7eb2e8f9f7 737 #define FSL_FEATURE_FLASH_IS_FTFL (0)
<> 144:ef7eb2e8f9f7 738 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
<> 144:ef7eb2e8f9f7 739 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
<> 144:ef7eb2e8f9f7 740 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
<> 144:ef7eb2e8f9f7 741 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
<> 144:ef7eb2e8f9f7 742 /* @brief Has EEPROM region protection (register FEPROT). */
<> 144:ef7eb2e8f9f7 743 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
<> 144:ef7eb2e8f9f7 744 /* @brief Has data flash region protection (register FDPROT). */
<> 144:ef7eb2e8f9f7 745 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
<> 144:ef7eb2e8f9f7 746 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
<> 144:ef7eb2e8f9f7 747 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
<> 144:ef7eb2e8f9f7 748 /* @brief Has flash cache control in FMC module. */
<> 144:ef7eb2e8f9f7 749 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
<> 144:ef7eb2e8f9f7 750 /* @brief Has flash cache control in MCM module. */
<> 144:ef7eb2e8f9f7 751 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
<> 144:ef7eb2e8f9f7 752 /* @brief P-Flash start address. */
<> 144:ef7eb2e8f9f7 753 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
<> 144:ef7eb2e8f9f7 754 /* @brief P-Flash block count. */
<> 144:ef7eb2e8f9f7 755 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
<> 144:ef7eb2e8f9f7 756 /* @brief P-Flash block size. */
<> 144:ef7eb2e8f9f7 757 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
<> 144:ef7eb2e8f9f7 758 /* @brief P-Flash sector size. */
<> 144:ef7eb2e8f9f7 759 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
<> 144:ef7eb2e8f9f7 760 /* @brief P-Flash write unit size. */
<> 144:ef7eb2e8f9f7 761 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
<> 144:ef7eb2e8f9f7 762 /* @brief P-Flash data path width. */
<> 144:ef7eb2e8f9f7 763 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
<> 144:ef7eb2e8f9f7 764 /* @brief P-Flash block swap feature. */
<> 144:ef7eb2e8f9f7 765 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
<> 144:ef7eb2e8f9f7 766 /* @brief Has FlexNVM memory. */
<> 144:ef7eb2e8f9f7 767 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
<> 144:ef7eb2e8f9f7 768 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
<> 144:ef7eb2e8f9f7 769 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
<> 144:ef7eb2e8f9f7 770 /* @brief FlexNVM block count. */
<> 144:ef7eb2e8f9f7 771 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
<> 144:ef7eb2e8f9f7 772 /* @brief FlexNVM block size. */
<> 144:ef7eb2e8f9f7 773 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
<> 144:ef7eb2e8f9f7 774 /* @brief FlexNVM sector size. */
<> 144:ef7eb2e8f9f7 775 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
<> 144:ef7eb2e8f9f7 776 /* @brief FlexNVM write unit size. */
<> 144:ef7eb2e8f9f7 777 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
<> 144:ef7eb2e8f9f7 778 /* @brief FlexNVM data path width. */
<> 144:ef7eb2e8f9f7 779 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
<> 144:ef7eb2e8f9f7 780 /* @brief Has FlexRAM memory. */
<> 144:ef7eb2e8f9f7 781 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
<> 144:ef7eb2e8f9f7 782 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
<> 144:ef7eb2e8f9f7 783 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
<> 144:ef7eb2e8f9f7 784 /* @brief FlexRAM size. */
<> 144:ef7eb2e8f9f7 785 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
<> 144:ef7eb2e8f9f7 786 /* @brief Has 0x00 Read 1s Block command. */
<> 144:ef7eb2e8f9f7 787 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
<> 144:ef7eb2e8f9f7 788 /* @brief Has 0x01 Read 1s Section command. */
<> 144:ef7eb2e8f9f7 789 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
<> 144:ef7eb2e8f9f7 790 /* @brief Has 0x02 Program Check command. */
<> 144:ef7eb2e8f9f7 791 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
<> 144:ef7eb2e8f9f7 792 /* @brief Has 0x03 Read Resource command. */
<> 144:ef7eb2e8f9f7 793 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
<> 144:ef7eb2e8f9f7 794 /* @brief Has 0x06 Program Longword command. */
<> 144:ef7eb2e8f9f7 795 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
<> 144:ef7eb2e8f9f7 796 /* @brief Has 0x07 Program Phrase command. */
<> 144:ef7eb2e8f9f7 797 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
<> 144:ef7eb2e8f9f7 798 /* @brief Has 0x08 Erase Flash Block command. */
<> 144:ef7eb2e8f9f7 799 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
<> 144:ef7eb2e8f9f7 800 /* @brief Has 0x09 Erase Flash Sector command. */
<> 144:ef7eb2e8f9f7 801 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
<> 144:ef7eb2e8f9f7 802 /* @brief Has 0x0B Program Section command. */
<> 144:ef7eb2e8f9f7 803 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
<> 144:ef7eb2e8f9f7 804 /* @brief Has 0x40 Read 1s All Blocks command. */
<> 144:ef7eb2e8f9f7 805 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
<> 144:ef7eb2e8f9f7 806 /* @brief Has 0x41 Read Once command. */
<> 144:ef7eb2e8f9f7 807 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
<> 144:ef7eb2e8f9f7 808 /* @brief Has 0x43 Program Once command. */
<> 144:ef7eb2e8f9f7 809 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
<> 144:ef7eb2e8f9f7 810 /* @brief Has 0x44 Erase All Blocks command. */
<> 144:ef7eb2e8f9f7 811 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
<> 144:ef7eb2e8f9f7 812 /* @brief Has 0x45 Verify Backdoor Access Key command. */
<> 144:ef7eb2e8f9f7 813 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
<> 144:ef7eb2e8f9f7 814 /* @brief Has 0x46 Swap Control command. */
<> 144:ef7eb2e8f9f7 815 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
<> 144:ef7eb2e8f9f7 816 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
<> 144:ef7eb2e8f9f7 817 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
<> 144:ef7eb2e8f9f7 818 /* @brief Has 0x80 Program Partition command. */
<> 144:ef7eb2e8f9f7 819 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
<> 144:ef7eb2e8f9f7 820 /* @brief Has 0x81 Set FlexRAM Function command. */
<> 144:ef7eb2e8f9f7 821 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
<> 144:ef7eb2e8f9f7 822 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
<> 144:ef7eb2e8f9f7 823 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 824 /* @brief P-Flash Erase sector command address alignment. */
<> 144:ef7eb2e8f9f7 825 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 826 /* @brief P-Flash Rrogram/Verify section command address alignment. */
<> 144:ef7eb2e8f9f7 827 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 828 /* @brief P-Flash Read resource command address alignment. */
<> 144:ef7eb2e8f9f7 829 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
<> 144:ef7eb2e8f9f7 830 /* @brief P-Flash Program check command address alignment. */
<> 144:ef7eb2e8f9f7 831 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
<> 144:ef7eb2e8f9f7 832 /* @brief P-Flash Program check command address alignment. */
<> 144:ef7eb2e8f9f7 833 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 834 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
<> 144:ef7eb2e8f9f7 835 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
<> 144:ef7eb2e8f9f7 836 /* @brief FlexNVM Erase sector command address alignment. */
<> 144:ef7eb2e8f9f7 837 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
<> 144:ef7eb2e8f9f7 838 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
<> 144:ef7eb2e8f9f7 839 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
<> 144:ef7eb2e8f9f7 840 /* @brief FlexNVM Read resource command address alignment. */
<> 144:ef7eb2e8f9f7 841 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
<> 144:ef7eb2e8f9f7 842 /* @brief FlexNVM Program check command address alignment. */
<> 144:ef7eb2e8f9f7 843 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
<> 144:ef7eb2e8f9f7 844 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 845 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 846 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 847 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 848 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 849 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 850 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 851 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 852 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 853 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 854 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 855 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 856 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 857 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 858 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 859 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 860 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 861 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 862 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 863 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 864 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 865 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 866 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 867 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 868 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 869 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 870 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 871 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 872 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 873 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 874 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 875 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 876 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 877 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
<> 144:ef7eb2e8f9f7 878 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 879 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
<> 144:ef7eb2e8f9f7 880 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 881 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
<> 144:ef7eb2e8f9f7 882 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 883 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
<> 144:ef7eb2e8f9f7 884 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 885 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
<> 144:ef7eb2e8f9f7 886 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 887 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
<> 144:ef7eb2e8f9f7 888 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 889 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
<> 144:ef7eb2e8f9f7 890 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 891 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
<> 144:ef7eb2e8f9f7 892 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 893 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
<> 144:ef7eb2e8f9f7 894 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 895 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
<> 144:ef7eb2e8f9f7 896 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 897 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
<> 144:ef7eb2e8f9f7 898 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 899 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
<> 144:ef7eb2e8f9f7 900 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 901 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
<> 144:ef7eb2e8f9f7 902 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 903 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
<> 144:ef7eb2e8f9f7 904 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 905 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
<> 144:ef7eb2e8f9f7 906 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 907 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
<> 144:ef7eb2e8f9f7 908 #elif defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
<> 144:ef7eb2e8f9f7 909 /* @brief Is of type FTFA. */
<> 144:ef7eb2e8f9f7 910 #define FSL_FEATURE_FLASH_IS_FTFA (0)
<> 144:ef7eb2e8f9f7 911 /* @brief Is of type FTFE. */
<> 144:ef7eb2e8f9f7 912 #define FSL_FEATURE_FLASH_IS_FTFE (1)
<> 144:ef7eb2e8f9f7 913 /* @brief Is of type FTFL. */
<> 144:ef7eb2e8f9f7 914 #define FSL_FEATURE_FLASH_IS_FTFL (0)
<> 144:ef7eb2e8f9f7 915 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
<> 144:ef7eb2e8f9f7 916 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
<> 144:ef7eb2e8f9f7 917 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
<> 144:ef7eb2e8f9f7 918 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
<> 144:ef7eb2e8f9f7 919 /* @brief Has EEPROM region protection (register FEPROT). */
<> 144:ef7eb2e8f9f7 920 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
<> 144:ef7eb2e8f9f7 921 /* @brief Has data flash region protection (register FDPROT). */
<> 144:ef7eb2e8f9f7 922 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
<> 144:ef7eb2e8f9f7 923 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
<> 144:ef7eb2e8f9f7 924 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
<> 144:ef7eb2e8f9f7 925 /* @brief Has flash cache control in FMC module. */
<> 144:ef7eb2e8f9f7 926 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
<> 144:ef7eb2e8f9f7 927 /* @brief Has flash cache control in MCM module. */
<> 144:ef7eb2e8f9f7 928 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
<> 144:ef7eb2e8f9f7 929 /* @brief P-Flash start address. */
<> 144:ef7eb2e8f9f7 930 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
<> 144:ef7eb2e8f9f7 931 /* @brief P-Flash block count. */
<> 144:ef7eb2e8f9f7 932 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
<> 144:ef7eb2e8f9f7 933 /* @brief P-Flash block size. */
<> 144:ef7eb2e8f9f7 934 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
<> 144:ef7eb2e8f9f7 935 /* @brief P-Flash sector size. */
<> 144:ef7eb2e8f9f7 936 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
<> 144:ef7eb2e8f9f7 937 /* @brief P-Flash write unit size. */
<> 144:ef7eb2e8f9f7 938 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
<> 144:ef7eb2e8f9f7 939 /* @brief P-Flash data path width. */
<> 144:ef7eb2e8f9f7 940 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
<> 144:ef7eb2e8f9f7 941 /* @brief P-Flash block swap feature. */
<> 144:ef7eb2e8f9f7 942 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
<> 144:ef7eb2e8f9f7 943 /* @brief Has FlexNVM memory. */
<> 144:ef7eb2e8f9f7 944 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
<> 144:ef7eb2e8f9f7 945 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
<> 144:ef7eb2e8f9f7 946 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
<> 144:ef7eb2e8f9f7 947 /* @brief FlexNVM block count. */
<> 144:ef7eb2e8f9f7 948 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
<> 144:ef7eb2e8f9f7 949 /* @brief FlexNVM block size. */
<> 144:ef7eb2e8f9f7 950 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
<> 144:ef7eb2e8f9f7 951 /* @brief FlexNVM sector size. */
<> 144:ef7eb2e8f9f7 952 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
<> 144:ef7eb2e8f9f7 953 /* @brief FlexNVM write unit size. */
<> 144:ef7eb2e8f9f7 954 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
<> 144:ef7eb2e8f9f7 955 /* @brief FlexNVM data path width. */
<> 144:ef7eb2e8f9f7 956 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
<> 144:ef7eb2e8f9f7 957 /* @brief Has FlexRAM memory. */
<> 144:ef7eb2e8f9f7 958 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
<> 144:ef7eb2e8f9f7 959 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
<> 144:ef7eb2e8f9f7 960 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
<> 144:ef7eb2e8f9f7 961 /* @brief FlexRAM size. */
<> 144:ef7eb2e8f9f7 962 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
<> 144:ef7eb2e8f9f7 963 /* @brief Has 0x00 Read 1s Block command. */
<> 144:ef7eb2e8f9f7 964 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
<> 144:ef7eb2e8f9f7 965 /* @brief Has 0x01 Read 1s Section command. */
<> 144:ef7eb2e8f9f7 966 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
<> 144:ef7eb2e8f9f7 967 /* @brief Has 0x02 Program Check command. */
<> 144:ef7eb2e8f9f7 968 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
<> 144:ef7eb2e8f9f7 969 /* @brief Has 0x03 Read Resource command. */
<> 144:ef7eb2e8f9f7 970 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
<> 144:ef7eb2e8f9f7 971 /* @brief Has 0x06 Program Longword command. */
<> 144:ef7eb2e8f9f7 972 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
<> 144:ef7eb2e8f9f7 973 /* @brief Has 0x07 Program Phrase command. */
<> 144:ef7eb2e8f9f7 974 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
<> 144:ef7eb2e8f9f7 975 /* @brief Has 0x08 Erase Flash Block command. */
<> 144:ef7eb2e8f9f7 976 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
<> 144:ef7eb2e8f9f7 977 /* @brief Has 0x09 Erase Flash Sector command. */
<> 144:ef7eb2e8f9f7 978 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
<> 144:ef7eb2e8f9f7 979 /* @brief Has 0x0B Program Section command. */
<> 144:ef7eb2e8f9f7 980 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
<> 144:ef7eb2e8f9f7 981 /* @brief Has 0x40 Read 1s All Blocks command. */
<> 144:ef7eb2e8f9f7 982 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
<> 144:ef7eb2e8f9f7 983 /* @brief Has 0x41 Read Once command. */
<> 144:ef7eb2e8f9f7 984 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
<> 144:ef7eb2e8f9f7 985 /* @brief Has 0x43 Program Once command. */
<> 144:ef7eb2e8f9f7 986 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
<> 144:ef7eb2e8f9f7 987 /* @brief Has 0x44 Erase All Blocks command. */
<> 144:ef7eb2e8f9f7 988 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
<> 144:ef7eb2e8f9f7 989 /* @brief Has 0x45 Verify Backdoor Access Key command. */
<> 144:ef7eb2e8f9f7 990 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
<> 144:ef7eb2e8f9f7 991 /* @brief Has 0x46 Swap Control command. */
<> 144:ef7eb2e8f9f7 992 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
<> 144:ef7eb2e8f9f7 993 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
<> 144:ef7eb2e8f9f7 994 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
<> 144:ef7eb2e8f9f7 995 /* @brief Has 0x80 Program Partition command. */
<> 144:ef7eb2e8f9f7 996 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
<> 144:ef7eb2e8f9f7 997 /* @brief Has 0x81 Set FlexRAM Function command. */
<> 144:ef7eb2e8f9f7 998 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
<> 144:ef7eb2e8f9f7 999 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
<> 144:ef7eb2e8f9f7 1000 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 1001 /* @brief P-Flash Erase sector command address alignment. */
<> 144:ef7eb2e8f9f7 1002 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 1003 /* @brief P-Flash Rrogram/Verify section command address alignment. */
<> 144:ef7eb2e8f9f7 1004 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 1005 /* @brief P-Flash Read resource command address alignment. */
<> 144:ef7eb2e8f9f7 1006 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
<> 144:ef7eb2e8f9f7 1007 /* @brief P-Flash Program check command address alignment. */
<> 144:ef7eb2e8f9f7 1008 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
<> 144:ef7eb2e8f9f7 1009 /* @brief P-Flash Program check command address alignment. */
<> 144:ef7eb2e8f9f7 1010 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
<> 144:ef7eb2e8f9f7 1011 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
<> 144:ef7eb2e8f9f7 1012 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 1013 /* @brief FlexNVM Erase sector command address alignment. */
<> 144:ef7eb2e8f9f7 1014 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 1015 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
<> 144:ef7eb2e8f9f7 1016 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
<> 144:ef7eb2e8f9f7 1017 /* @brief FlexNVM Read resource command address alignment. */
<> 144:ef7eb2e8f9f7 1018 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
<> 144:ef7eb2e8f9f7 1019 /* @brief FlexNVM Program check command address alignment. */
<> 144:ef7eb2e8f9f7 1020 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
<> 144:ef7eb2e8f9f7 1021 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1022 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
<> 144:ef7eb2e8f9f7 1023 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1024 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 1025 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1026 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
<> 144:ef7eb2e8f9f7 1027 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1028 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
<> 144:ef7eb2e8f9f7 1029 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1030 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
<> 144:ef7eb2e8f9f7 1031 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1032 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
<> 144:ef7eb2e8f9f7 1033 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1034 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 1035 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1036 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 1037 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1038 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
<> 144:ef7eb2e8f9f7 1039 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1040 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 1041 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1042 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
<> 144:ef7eb2e8f9f7 1043 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1044 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
<> 144:ef7eb2e8f9f7 1045 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1046 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
<> 144:ef7eb2e8f9f7 1047 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1048 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
<> 144:ef7eb2e8f9f7 1049 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1050 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
<> 144:ef7eb2e8f9f7 1051 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1052 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
<> 144:ef7eb2e8f9f7 1053 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1054 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
<> 144:ef7eb2e8f9f7 1055 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1056 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
<> 144:ef7eb2e8f9f7 1057 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1058 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
<> 144:ef7eb2e8f9f7 1059 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1060 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
<> 144:ef7eb2e8f9f7 1061 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1062 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
<> 144:ef7eb2e8f9f7 1063 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1064 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
<> 144:ef7eb2e8f9f7 1065 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1066 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
<> 144:ef7eb2e8f9f7 1067 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1068 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
<> 144:ef7eb2e8f9f7 1069 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1070 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
<> 144:ef7eb2e8f9f7 1071 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1072 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
<> 144:ef7eb2e8f9f7 1073 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1074 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
<> 144:ef7eb2e8f9f7 1075 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1076 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
<> 144:ef7eb2e8f9f7 1077 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1078 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
<> 144:ef7eb2e8f9f7 1079 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1080 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
<> 144:ef7eb2e8f9f7 1081 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1082 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
<> 144:ef7eb2e8f9f7 1083 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 144:ef7eb2e8f9f7 1084 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
<> 144:ef7eb2e8f9f7 1085 #endif /* defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) */
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* FTM module features */
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* @brief Number of channels. */
<> 144:ef7eb2e8f9f7 1090 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
<> 144:ef7eb2e8f9f7 1091 ((x) == FTM0 ? (8) : \
<> 144:ef7eb2e8f9f7 1092 ((x) == FTM1 ? (2) : \
<> 144:ef7eb2e8f9f7 1093 ((x) == FTM2 ? (2) : \
<> 144:ef7eb2e8f9f7 1094 ((x) == FTM3 ? (8) : (-1)))))
<> 144:ef7eb2e8f9f7 1095 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
<> 144:ef7eb2e8f9f7 1096 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
<> 144:ef7eb2e8f9f7 1097 /* @brief Enable pwm output for the module. */
<> 144:ef7eb2e8f9f7 1098 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
<> 144:ef7eb2e8f9f7 1099 /* @brief Has half-cycle reload for the module. */
<> 144:ef7eb2e8f9f7 1100 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
<> 144:ef7eb2e8f9f7 1101 /* @brief Has reload interrupt. */
<> 144:ef7eb2e8f9f7 1102 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
<> 144:ef7eb2e8f9f7 1103 /* @brief Has reload initialization trigger. */
<> 144:ef7eb2e8f9f7 1104 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* I2C module features */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
<> 144:ef7eb2e8f9f7 1109 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
<> 144:ef7eb2e8f9f7 1110 /* @brief Maximum supported baud rate in kilobit per second. */
<> 144:ef7eb2e8f9f7 1111 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
<> 144:ef7eb2e8f9f7 1112 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
<> 144:ef7eb2e8f9f7 1113 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
<> 144:ef7eb2e8f9f7 1114 /* @brief Has DMA support (register bit C1[DMAEN]). */
<> 144:ef7eb2e8f9f7 1115 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
<> 144:ef7eb2e8f9f7 1116 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
<> 144:ef7eb2e8f9f7 1117 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
<> 144:ef7eb2e8f9f7 1118 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
<> 144:ef7eb2e8f9f7 1119 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
<> 144:ef7eb2e8f9f7 1120 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
<> 144:ef7eb2e8f9f7 1121 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
<> 144:ef7eb2e8f9f7 1122 /* @brief Maximum width of the glitch filter in number of bus clocks. */
<> 144:ef7eb2e8f9f7 1123 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
<> 144:ef7eb2e8f9f7 1124 /* @brief Has control of the drive capability of the I2C pins. */
<> 144:ef7eb2e8f9f7 1125 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
<> 144:ef7eb2e8f9f7 1126 /* @brief Has double buffering support (register S2). */
<> 144:ef7eb2e8f9f7 1127 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /* SAI module features */
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
<> 144:ef7eb2e8f9f7 1132 #define FSL_FEATURE_SAI_FIFO_COUNT (8)
<> 144:ef7eb2e8f9f7 1133 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
<> 144:ef7eb2e8f9f7 1134 #define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
<> 144:ef7eb2e8f9f7 1135 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
<> 144:ef7eb2e8f9f7 1136 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
<> 144:ef7eb2e8f9f7 1137 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
<> 144:ef7eb2e8f9f7 1138 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
<> 144:ef7eb2e8f9f7 1139 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
<> 144:ef7eb2e8f9f7 1140 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
<> 144:ef7eb2e8f9f7 1141 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
<> 144:ef7eb2e8f9f7 1142 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
<> 144:ef7eb2e8f9f7 1143 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
<> 144:ef7eb2e8f9f7 1144 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
<> 144:ef7eb2e8f9f7 1145 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
<> 144:ef7eb2e8f9f7 1146 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
<> 144:ef7eb2e8f9f7 1147 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
<> 144:ef7eb2e8f9f7 1148 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
<> 144:ef7eb2e8f9f7 1149 /* @brief Ihe interrupt source number */
<> 144:ef7eb2e8f9f7 1150 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
<> 144:ef7eb2e8f9f7 1151 /* @brief Has register of MCR. */
<> 144:ef7eb2e8f9f7 1152 #define FSL_FEATURE_SAI_HAS_MCR (1)
<> 144:ef7eb2e8f9f7 1153 /* @brief Has register of MDR */
<> 144:ef7eb2e8f9f7 1154 #define FSL_FEATURE_SAI_HAS_MDR (1)
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* LLWU module features */
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1159 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
<> 144:ef7eb2e8f9f7 1160 /* @brief Has pins 8-15 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1161 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
<> 144:ef7eb2e8f9f7 1162 /* @brief Maximum number of internal modules connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1163 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
<> 144:ef7eb2e8f9f7 1164 /* @brief Number of digital filters. */
<> 144:ef7eb2e8f9f7 1165 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
<> 144:ef7eb2e8f9f7 1166 /* @brief Has MF5 register. */
<> 144:ef7eb2e8f9f7 1167 #define FSL_FEATURE_LLWU_HAS_MF (0)
<> 144:ef7eb2e8f9f7 1168 /* @brief Has PF register. */
<> 144:ef7eb2e8f9f7 1169 #define FSL_FEATURE_LLWU_HAS_PF (0)
<> 144:ef7eb2e8f9f7 1170 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
<> 144:ef7eb2e8f9f7 1171 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
<> 144:ef7eb2e8f9f7 1172 /* @brief Has external pin 0 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1173 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
<> 144:ef7eb2e8f9f7 1174 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1175 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
<> 144:ef7eb2e8f9f7 1176 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1177 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
<> 144:ef7eb2e8f9f7 1178 /* @brief Has external pin 1 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1179 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
<> 144:ef7eb2e8f9f7 1180 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1181 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
<> 144:ef7eb2e8f9f7 1182 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1183 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
<> 144:ef7eb2e8f9f7 1184 /* @brief Has external pin 2 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1185 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
<> 144:ef7eb2e8f9f7 1186 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1187 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
<> 144:ef7eb2e8f9f7 1188 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1189 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
<> 144:ef7eb2e8f9f7 1190 /* @brief Has external pin 3 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1191 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
<> 144:ef7eb2e8f9f7 1192 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1193 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
<> 144:ef7eb2e8f9f7 1194 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1195 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
<> 144:ef7eb2e8f9f7 1196 /* @brief Has external pin 4 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1197 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
<> 144:ef7eb2e8f9f7 1198 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1199 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
<> 144:ef7eb2e8f9f7 1200 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1201 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
<> 144:ef7eb2e8f9f7 1202 /* @brief Has external pin 5 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1203 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
<> 144:ef7eb2e8f9f7 1204 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1205 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
<> 144:ef7eb2e8f9f7 1206 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1207 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1208 /* @brief Has external pin 6 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1209 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
<> 144:ef7eb2e8f9f7 1210 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1211 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
<> 144:ef7eb2e8f9f7 1212 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1213 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
<> 144:ef7eb2e8f9f7 1214 /* @brief Has external pin 7 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1215 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
<> 144:ef7eb2e8f9f7 1216 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1217 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
<> 144:ef7eb2e8f9f7 1218 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1219 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
<> 144:ef7eb2e8f9f7 1220 /* @brief Has external pin 8 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1221 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
<> 144:ef7eb2e8f9f7 1222 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1223 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
<> 144:ef7eb2e8f9f7 1224 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1225 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
<> 144:ef7eb2e8f9f7 1226 /* @brief Has external pin 9 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1227 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
<> 144:ef7eb2e8f9f7 1228 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1229 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
<> 144:ef7eb2e8f9f7 1230 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1231 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
<> 144:ef7eb2e8f9f7 1232 /* @brief Has external pin 10 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1233 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
<> 144:ef7eb2e8f9f7 1234 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1235 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
<> 144:ef7eb2e8f9f7 1236 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1237 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
<> 144:ef7eb2e8f9f7 1238 /* @brief Has external pin 11 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1239 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
<> 144:ef7eb2e8f9f7 1240 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1241 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
<> 144:ef7eb2e8f9f7 1242 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1243 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
<> 144:ef7eb2e8f9f7 1244 /* @brief Has external pin 12 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1245 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
<> 144:ef7eb2e8f9f7 1246 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1247 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
<> 144:ef7eb2e8f9f7 1248 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1249 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1250 /* @brief Has external pin 13 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1251 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
<> 144:ef7eb2e8f9f7 1252 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1253 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
<> 144:ef7eb2e8f9f7 1254 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1255 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
<> 144:ef7eb2e8f9f7 1256 /* @brief Has external pin 14 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1257 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
<> 144:ef7eb2e8f9f7 1258 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1259 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
<> 144:ef7eb2e8f9f7 1260 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1261 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
<> 144:ef7eb2e8f9f7 1262 /* @brief Has external pin 15 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1263 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
<> 144:ef7eb2e8f9f7 1264 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1265 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
<> 144:ef7eb2e8f9f7 1266 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1267 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
<> 144:ef7eb2e8f9f7 1268 /* @brief Has external pin 16 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1269 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
<> 144:ef7eb2e8f9f7 1270 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1271 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1272 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1273 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1274 /* @brief Has external pin 17 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1275 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
<> 144:ef7eb2e8f9f7 1276 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1277 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1278 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1279 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1280 /* @brief Has external pin 18 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1281 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
<> 144:ef7eb2e8f9f7 1282 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1283 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1284 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1285 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1286 /* @brief Has external pin 19 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1287 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
<> 144:ef7eb2e8f9f7 1288 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1289 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1290 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1291 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1292 /* @brief Has external pin 20 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1293 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
<> 144:ef7eb2e8f9f7 1294 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1295 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1296 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1297 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1298 /* @brief Has external pin 21 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1299 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
<> 144:ef7eb2e8f9f7 1300 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1301 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1302 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1303 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1304 /* @brief Has external pin 22 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1305 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
<> 144:ef7eb2e8f9f7 1306 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1307 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1308 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1309 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1310 /* @brief Has external pin 23 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1311 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
<> 144:ef7eb2e8f9f7 1312 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1313 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1314 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1315 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1316 /* @brief Has external pin 24 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1317 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
<> 144:ef7eb2e8f9f7 1318 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1319 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1320 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1321 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1322 /* @brief Has external pin 25 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1323 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
<> 144:ef7eb2e8f9f7 1324 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1325 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1326 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1327 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1328 /* @brief Has external pin 26 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1329 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
<> 144:ef7eb2e8f9f7 1330 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1331 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1332 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1333 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1334 /* @brief Has external pin 27 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1335 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
<> 144:ef7eb2e8f9f7 1336 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1337 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1338 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1339 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1340 /* @brief Has external pin 28 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1341 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
<> 144:ef7eb2e8f9f7 1342 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1343 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1344 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1345 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1346 /* @brief Has external pin 29 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1347 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
<> 144:ef7eb2e8f9f7 1348 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1349 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1350 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1351 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1352 /* @brief Has external pin 30 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1353 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
<> 144:ef7eb2e8f9f7 1354 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1355 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1356 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1357 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1358 /* @brief Has external pin 31 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1359 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
<> 144:ef7eb2e8f9f7 1360 /* @brief Index of port of external pin. */
<> 144:ef7eb2e8f9f7 1361 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
<> 144:ef7eb2e8f9f7 1362 /* @brief Number of external pin port on specified port. */
<> 144:ef7eb2e8f9f7 1363 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
<> 144:ef7eb2e8f9f7 1364 /* @brief Has internal module 0 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1365 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
<> 144:ef7eb2e8f9f7 1366 /* @brief Has internal module 1 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1367 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
<> 144:ef7eb2e8f9f7 1368 /* @brief Has internal module 2 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1369 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
<> 144:ef7eb2e8f9f7 1370 /* @brief Has internal module 3 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1371 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
<> 144:ef7eb2e8f9f7 1372 /* @brief Has internal module 4 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1373 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
<> 144:ef7eb2e8f9f7 1374 /* @brief Has internal module 5 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1375 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
<> 144:ef7eb2e8f9f7 1376 /* @brief Has internal module 6 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1377 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
<> 144:ef7eb2e8f9f7 1378 /* @brief Has internal module 7 connected to LLWU device. */
<> 144:ef7eb2e8f9f7 1379 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
<> 144:ef7eb2e8f9f7 1380 /* @brief Has Version ID Register (LLWU_VERID). */
<> 144:ef7eb2e8f9f7 1381 #define FSL_FEATURE_LLWU_HAS_VERID (0)
<> 144:ef7eb2e8f9f7 1382 /* @brief Has Parameter Register (LLWU_PARAM). */
<> 144:ef7eb2e8f9f7 1383 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
<> 144:ef7eb2e8f9f7 1384 /* @brief Width of registers of the LLWU. */
<> 144:ef7eb2e8f9f7 1385 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
<> 144:ef7eb2e8f9f7 1386 /* @brief Has DMA Enable register (LLWU_DE). */
<> 144:ef7eb2e8f9f7 1387 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /* LPTMR module features */
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* @brief Has shared interrupt handler with another LPTMR module. */
<> 144:ef7eb2e8f9f7 1392 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* MCG module features */
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
<> 144:ef7eb2e8f9f7 1397 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
<> 144:ef7eb2e8f9f7 1398 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
<> 144:ef7eb2e8f9f7 1399 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
<> 144:ef7eb2e8f9f7 1400 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
<> 144:ef7eb2e8f9f7 1401 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
<> 144:ef7eb2e8f9f7 1402 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
<> 144:ef7eb2e8f9f7 1403 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
<> 144:ef7eb2e8f9f7 1404 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
<> 144:ef7eb2e8f9f7 1405 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
<> 144:ef7eb2e8f9f7 1406 /* @brief The PLL clock is divided by 2 before VCO divider. */
<> 144:ef7eb2e8f9f7 1407 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
<> 144:ef7eb2e8f9f7 1408 /* @brief FRDIV supports 1280. */
<> 144:ef7eb2e8f9f7 1409 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
<> 144:ef7eb2e8f9f7 1410 /* @brief FRDIV supports 1536. */
<> 144:ef7eb2e8f9f7 1411 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
<> 144:ef7eb2e8f9f7 1412 /* @brief MCGFFCLK divider. */
<> 144:ef7eb2e8f9f7 1413 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
<> 144:ef7eb2e8f9f7 1414 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
<> 144:ef7eb2e8f9f7 1415 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
<> 144:ef7eb2e8f9f7 1416 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
<> 144:ef7eb2e8f9f7 1417 #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
<> 144:ef7eb2e8f9f7 1418 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
<> 144:ef7eb2e8f9f7 1419 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
<> 144:ef7eb2e8f9f7 1420 /* @brief Has 48MHz internal oscillator. */
<> 144:ef7eb2e8f9f7 1421 #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
<> 144:ef7eb2e8f9f7 1422 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
<> 144:ef7eb2e8f9f7 1423 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
<> 144:ef7eb2e8f9f7 1424 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
<> 144:ef7eb2e8f9f7 1425 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
<> 144:ef7eb2e8f9f7 1426 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
<> 144:ef7eb2e8f9f7 1427 #define FSL_FEATURE_MCG_HAS_LOLRE (1)
<> 144:ef7eb2e8f9f7 1428 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
<> 144:ef7eb2e8f9f7 1429 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
<> 144:ef7eb2e8f9f7 1430 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
<> 144:ef7eb2e8f9f7 1431 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
<> 144:ef7eb2e8f9f7 1432 /* @brief TBD */
<> 144:ef7eb2e8f9f7 1433 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
<> 144:ef7eb2e8f9f7 1434 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
<> 144:ef7eb2e8f9f7 1435 #define FSL_FEATURE_MCG_HAS_PLL (1)
<> 144:ef7eb2e8f9f7 1436 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
<> 144:ef7eb2e8f9f7 1437 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
<> 144:ef7eb2e8f9f7 1438 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
<> 144:ef7eb2e8f9f7 1439 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
<> 144:ef7eb2e8f9f7 1440 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
<> 144:ef7eb2e8f9f7 1441 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
<> 144:ef7eb2e8f9f7 1442 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
<> 144:ef7eb2e8f9f7 1443 #define FSL_FEATURE_MCG_HAS_FLL (1)
<> 144:ef7eb2e8f9f7 1444 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
<> 144:ef7eb2e8f9f7 1445 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
<> 144:ef7eb2e8f9f7 1446 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
<> 144:ef7eb2e8f9f7 1447 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
<> 144:ef7eb2e8f9f7 1448 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
<> 144:ef7eb2e8f9f7 1449 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
<> 144:ef7eb2e8f9f7 1450 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
<> 144:ef7eb2e8f9f7 1451 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
<> 144:ef7eb2e8f9f7 1452 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
<> 144:ef7eb2e8f9f7 1453 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
<> 144:ef7eb2e8f9f7 1454 /* @brief Has external clock monitor (register bit C6[CME]). */
<> 144:ef7eb2e8f9f7 1455 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
<> 144:ef7eb2e8f9f7 1456 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
<> 144:ef7eb2e8f9f7 1457 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
<> 144:ef7eb2e8f9f7 1458 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
<> 144:ef7eb2e8f9f7 1459 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
<> 144:ef7eb2e8f9f7 1460 /* @brief Has PEI mode or PBI mode. */
<> 144:ef7eb2e8f9f7 1461 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
<> 144:ef7eb2e8f9f7 1462 /* @brief Reset clock mode is BLPI. */
<> 144:ef7eb2e8f9f7 1463 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /* MPU module features */
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /* @brief Specifies number of descriptors available. */
<> 144:ef7eb2e8f9f7 1468 #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
<> 144:ef7eb2e8f9f7 1469 /* @brief Has process identifier support. */
<> 144:ef7eb2e8f9f7 1470 #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
<> 144:ef7eb2e8f9f7 1471 /* @brief Has master 0. */
<> 144:ef7eb2e8f9f7 1472 #define FSL_FEATURE_MPU_HAS_MASTER0 (1)
<> 144:ef7eb2e8f9f7 1473 /* @brief Has master 1. */
<> 144:ef7eb2e8f9f7 1474 #define FSL_FEATURE_MPU_HAS_MASTER1 (1)
<> 144:ef7eb2e8f9f7 1475 /* @brief Has master 2. */
<> 144:ef7eb2e8f9f7 1476 #define FSL_FEATURE_MPU_HAS_MASTER2 (1)
<> 144:ef7eb2e8f9f7 1477 /* @brief Has master 3. */
<> 144:ef7eb2e8f9f7 1478 #define FSL_FEATURE_MPU_HAS_MASTER3 (1)
<> 144:ef7eb2e8f9f7 1479 /* @brief Has master 4. */
<> 144:ef7eb2e8f9f7 1480 #define FSL_FEATURE_MPU_HAS_MASTER4 (1)
<> 144:ef7eb2e8f9f7 1481 /* @brief Has master 5. */
<> 144:ef7eb2e8f9f7 1482 #define FSL_FEATURE_MPU_HAS_MASTER5 (1)
<> 144:ef7eb2e8f9f7 1483 /* @brief Has master 6. */
<> 144:ef7eb2e8f9f7 1484 #define FSL_FEATURE_MPU_HAS_MASTER6 (0)
<> 144:ef7eb2e8f9f7 1485 /* @brief Has master 7. */
<> 144:ef7eb2e8f9f7 1486 #define FSL_FEATURE_MPU_HAS_MASTER7 (0)
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* interrupt module features */
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 /* @brief Lowest interrupt request number. */
<> 144:ef7eb2e8f9f7 1491 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
<> 144:ef7eb2e8f9f7 1492 /* @brief Highest interrupt request number. */
<> 144:ef7eb2e8f9f7 1493 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* OSC module features */
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /* @brief Has OSC1 external oscillator. */
<> 144:ef7eb2e8f9f7 1498 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
<> 144:ef7eb2e8f9f7 1499 /* @brief Has OSC0 external oscillator. */
<> 144:ef7eb2e8f9f7 1500 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
<> 144:ef7eb2e8f9f7 1501 /* @brief Has OSC external oscillator (without index). */
<> 144:ef7eb2e8f9f7 1502 #define FSL_FEATURE_OSC_HAS_OSC (1)
<> 144:ef7eb2e8f9f7 1503 /* @brief Number of OSC external oscillators. */
<> 144:ef7eb2e8f9f7 1504 #define FSL_FEATURE_OSC_OSC_COUNT (1)
<> 144:ef7eb2e8f9f7 1505 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
<> 144:ef7eb2e8f9f7 1506 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /* PDB module features */
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
<> 144:ef7eb2e8f9f7 1511 #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
<> 144:ef7eb2e8f9f7 1512 /* @brief Has DAC support. */
<> 144:ef7eb2e8f9f7 1513 #define FSL_FEATURE_PDB_HAS_DAC (1)
<> 144:ef7eb2e8f9f7 1514 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
<> 144:ef7eb2e8f9f7 1515 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /* PIT module features */
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
<> 144:ef7eb2e8f9f7 1520 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
<> 144:ef7eb2e8f9f7 1521 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
<> 144:ef7eb2e8f9f7 1522 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
<> 144:ef7eb2e8f9f7 1523 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
<> 144:ef7eb2e8f9f7 1524 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
<> 144:ef7eb2e8f9f7 1525 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
<> 144:ef7eb2e8f9f7 1526 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /* PMC module features */
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* @brief Has Bandgap Enable In VLPx Operation support. */
<> 144:ef7eb2e8f9f7 1531 #define FSL_FEATURE_PMC_HAS_BGEN (1)
<> 144:ef7eb2e8f9f7 1532 /* @brief Has Bandgap Buffer Enable. */
<> 144:ef7eb2e8f9f7 1533 #define FSL_FEATURE_PMC_HAS_BGBE (1)
<> 144:ef7eb2e8f9f7 1534 /* @brief Has Bandgap Buffer Drive Select. */
<> 144:ef7eb2e8f9f7 1535 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
<> 144:ef7eb2e8f9f7 1536 /* @brief Has Low-Voltage Detect Voltage Select support. */
<> 144:ef7eb2e8f9f7 1537 #define FSL_FEATURE_PMC_HAS_LVDV (1)
<> 144:ef7eb2e8f9f7 1538 /* @brief Has Low-Voltage Warning Voltage Select support. */
<> 144:ef7eb2e8f9f7 1539 #define FSL_FEATURE_PMC_HAS_LVWV (1)
<> 144:ef7eb2e8f9f7 1540 /* @brief Has LPO. */
<> 144:ef7eb2e8f9f7 1541 #define FSL_FEATURE_PMC_HAS_LPO (0)
<> 144:ef7eb2e8f9f7 1542 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
<> 144:ef7eb2e8f9f7 1543 #define FSL_FEATURE_PMC_HAS_VLPO (0)
<> 144:ef7eb2e8f9f7 1544 /* @brief Has acknowledge isolation support. */
<> 144:ef7eb2e8f9f7 1545 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
<> 144:ef7eb2e8f9f7 1546 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
<> 144:ef7eb2e8f9f7 1547 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
<> 144:ef7eb2e8f9f7 1548 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
<> 144:ef7eb2e8f9f7 1549 #define FSL_FEATURE_PMC_HAS_REGONS (1)
<> 144:ef7eb2e8f9f7 1550 /* @brief Has PMC_HVDSC1. */
<> 144:ef7eb2e8f9f7 1551 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
<> 144:ef7eb2e8f9f7 1552 /* @brief Has PMC_PARAM. */
<> 144:ef7eb2e8f9f7 1553 #define FSL_FEATURE_PMC_HAS_PARAM (0)
<> 144:ef7eb2e8f9f7 1554 /* @brief Has PMC_VERID. */
<> 144:ef7eb2e8f9f7 1555 #define FSL_FEATURE_PMC_HAS_VERID (0)
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 /* PORT module features */
<> 144:ef7eb2e8f9f7 1558
<> 144:ef7eb2e8f9f7 1559 /* @brief Has control lock (register bit PCR[LK]). */
<> 144:ef7eb2e8f9f7 1560 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
<> 144:ef7eb2e8f9f7 1561 /* @brief Has open drain control (register bit PCR[ODE]). */
<> 144:ef7eb2e8f9f7 1562 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
<> 144:ef7eb2e8f9f7 1563 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
<> 144:ef7eb2e8f9f7 1564 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
<> 144:ef7eb2e8f9f7 1565 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
<> 144:ef7eb2e8f9f7 1566 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
<> 144:ef7eb2e8f9f7 1567 /* @brief Has pull resistor selection available. */
<> 144:ef7eb2e8f9f7 1568 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
<> 144:ef7eb2e8f9f7 1569 /* @brief Has pull resistor enable (register bit PCR[PE]). */
<> 144:ef7eb2e8f9f7 1570 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
<> 144:ef7eb2e8f9f7 1571 /* @brief Has slew rate control (register bit PCR[SRE]). */
<> 144:ef7eb2e8f9f7 1572 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
<> 144:ef7eb2e8f9f7 1573 /* @brief Has passive filter (register bit field PCR[PFE]). */
<> 144:ef7eb2e8f9f7 1574 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
<> 144:ef7eb2e8f9f7 1575 /* @brief Has drive strength control (register bit PCR[DSE]). */
<> 144:ef7eb2e8f9f7 1576 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
<> 144:ef7eb2e8f9f7 1577 /* @brief Has separate drive strength register (HDRVE). */
<> 144:ef7eb2e8f9f7 1578 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
<> 144:ef7eb2e8f9f7 1579 /* @brief Has glitch filter (register IOFLT). */
<> 144:ef7eb2e8f9f7 1580 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
<> 144:ef7eb2e8f9f7 1581 /* @brief Defines width of PCR[MUX] field. */
<> 144:ef7eb2e8f9f7 1582 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
<> 144:ef7eb2e8f9f7 1583 /* @brief Has dedicated interrupt vector. */
<> 144:ef7eb2e8f9f7 1584 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
<> 144:ef7eb2e8f9f7 1585 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
<> 144:ef7eb2e8f9f7 1586 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
<> 144:ef7eb2e8f9f7 1587 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
<> 144:ef7eb2e8f9f7 1588 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* GPIO module features */
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
<> 144:ef7eb2e8f9f7 1593 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
<> 144:ef7eb2e8f9f7 1594 /* @brief Has port input disable register (PIDR). */
<> 144:ef7eb2e8f9f7 1595 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
<> 144:ef7eb2e8f9f7 1596 /* @brief Has dedicated interrupt vector. */
<> 144:ef7eb2e8f9f7 1597 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 /* RCM module features */
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 /* @brief Has Loss-of-Lock Reset support. */
<> 144:ef7eb2e8f9f7 1602 #define FSL_FEATURE_RCM_HAS_LOL (1)
<> 144:ef7eb2e8f9f7 1603 /* @brief Has Loss-of-Clock Reset support. */
<> 144:ef7eb2e8f9f7 1604 #define FSL_FEATURE_RCM_HAS_LOC (1)
<> 144:ef7eb2e8f9f7 1605 /* @brief Has JTAG generated Reset support. */
<> 144:ef7eb2e8f9f7 1606 #define FSL_FEATURE_RCM_HAS_JTAG (1)
<> 144:ef7eb2e8f9f7 1607 /* @brief Has EzPort generated Reset support. */
<> 144:ef7eb2e8f9f7 1608 #define FSL_FEATURE_RCM_HAS_EZPORT (1)
<> 144:ef7eb2e8f9f7 1609 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
<> 144:ef7eb2e8f9f7 1610 #define FSL_FEATURE_RCM_HAS_EZPMS (1)
<> 144:ef7eb2e8f9f7 1611 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
<> 144:ef7eb2e8f9f7 1612 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
<> 144:ef7eb2e8f9f7 1613 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
<> 144:ef7eb2e8f9f7 1614 #define FSL_FEATURE_RCM_HAS_SSRS (0)
<> 144:ef7eb2e8f9f7 1615 /* @brief Has Version ID Register (RCM_VERID). */
<> 144:ef7eb2e8f9f7 1616 #define FSL_FEATURE_RCM_HAS_VERID (0)
<> 144:ef7eb2e8f9f7 1617 /* @brief Has Parameter Register (RCM_PARAM). */
<> 144:ef7eb2e8f9f7 1618 #define FSL_FEATURE_RCM_HAS_PARAM (0)
<> 144:ef7eb2e8f9f7 1619 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
<> 144:ef7eb2e8f9f7 1620 #define FSL_FEATURE_RCM_HAS_SRIE (0)
<> 144:ef7eb2e8f9f7 1621 /* @brief Width of registers of the RCM. */
<> 144:ef7eb2e8f9f7 1622 #define FSL_FEATURE_RCM_REG_WIDTH (8)
<> 144:ef7eb2e8f9f7 1623 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
<> 144:ef7eb2e8f9f7 1624 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
<> 144:ef7eb2e8f9f7 1625 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
<> 144:ef7eb2e8f9f7 1626 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
<> 144:ef7eb2e8f9f7 1627 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
<> 144:ef7eb2e8f9f7 1628 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /* RTC module features */
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 #if defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VDC12) || \
<> 144:ef7eb2e8f9f7 1633 defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12)
<> 144:ef7eb2e8f9f7 1634 /* @brief Has wakeup pin. */
<> 144:ef7eb2e8f9f7 1635 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
<> 144:ef7eb2e8f9f7 1636 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
<> 144:ef7eb2e8f9f7 1637 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
<> 144:ef7eb2e8f9f7 1638 /* @brief Has low power features (registers MER, MCLR and MCHR). */
<> 144:ef7eb2e8f9f7 1639 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
<> 144:ef7eb2e8f9f7 1640 /* @brief Has read/write access control (registers WAR and RAR). */
<> 144:ef7eb2e8f9f7 1641 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
<> 144:ef7eb2e8f9f7 1642 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
<> 144:ef7eb2e8f9f7 1643 #define FSL_FEATURE_RTC_HAS_SECURITY (1)
<> 144:ef7eb2e8f9f7 1644 /* @brief Has RTC_CLKIN available. */
<> 144:ef7eb2e8f9f7 1645 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
<> 144:ef7eb2e8f9f7 1646 /* @brief Has prescaler adjust for LPO. */
<> 144:ef7eb2e8f9f7 1647 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
<> 144:ef7eb2e8f9f7 1648 /* @brief Has Clock Pin Enable field. */
<> 144:ef7eb2e8f9f7 1649 #define FSL_FEATURE_RTC_HAS_CPE (0)
<> 144:ef7eb2e8f9f7 1650 /* @brief Has Timer Seconds Interrupt Configuration field. */
<> 144:ef7eb2e8f9f7 1651 #define FSL_FEATURE_RTC_HAS_TSIC (0)
<> 144:ef7eb2e8f9f7 1652 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
<> 144:ef7eb2e8f9f7 1653 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
<> 144:ef7eb2e8f9f7 1654 #elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
<> 144:ef7eb2e8f9f7 1655 /* @brief Has wakeup pin. */
<> 144:ef7eb2e8f9f7 1656 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
<> 144:ef7eb2e8f9f7 1657 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
<> 144:ef7eb2e8f9f7 1658 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
<> 144:ef7eb2e8f9f7 1659 /* @brief Has low power features (registers MER, MCLR and MCHR). */
<> 144:ef7eb2e8f9f7 1660 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
<> 144:ef7eb2e8f9f7 1661 /* @brief Has read/write access control (registers WAR and RAR). */
<> 144:ef7eb2e8f9f7 1662 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
<> 144:ef7eb2e8f9f7 1663 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
<> 144:ef7eb2e8f9f7 1664 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
<> 144:ef7eb2e8f9f7 1665 /* @brief Has RTC_CLKIN available. */
<> 144:ef7eb2e8f9f7 1666 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
<> 144:ef7eb2e8f9f7 1667 /* @brief Has prescaler adjust for LPO. */
<> 144:ef7eb2e8f9f7 1668 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
<> 144:ef7eb2e8f9f7 1669 /* @brief Has Clock Pin Enable field. */
<> 144:ef7eb2e8f9f7 1670 #define FSL_FEATURE_RTC_HAS_CPE (0)
<> 144:ef7eb2e8f9f7 1671 /* @brief Has Timer Seconds Interrupt Configuration field. */
<> 144:ef7eb2e8f9f7 1672 #define FSL_FEATURE_RTC_HAS_TSIC (0)
<> 144:ef7eb2e8f9f7 1673 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
<> 144:ef7eb2e8f9f7 1674 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
<> 144:ef7eb2e8f9f7 1675 #endif /* defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VDC12) || \
<> 144:ef7eb2e8f9f7 1676 defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */
<> 144:ef7eb2e8f9f7 1677
<> 144:ef7eb2e8f9f7 1678 /* SDHC module features */
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
<> 144:ef7eb2e8f9f7 1681 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
<> 144:ef7eb2e8f9f7 1682 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
<> 144:ef7eb2e8f9f7 1683 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
<> 144:ef7eb2e8f9f7 1684 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
<> 144:ef7eb2e8f9f7 1685 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /* SIM module features */
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* @brief Has USB FS divider. */
<> 144:ef7eb2e8f9f7 1690 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
<> 144:ef7eb2e8f9f7 1691 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
<> 144:ef7eb2e8f9f7 1692 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
<> 144:ef7eb2e8f9f7 1693 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
<> 144:ef7eb2e8f9f7 1694 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
<> 144:ef7eb2e8f9f7 1695 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
<> 144:ef7eb2e8f9f7 1696 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
<> 144:ef7eb2e8f9f7 1697 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
<> 144:ef7eb2e8f9f7 1698 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
<> 144:ef7eb2e8f9f7 1699 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
<> 144:ef7eb2e8f9f7 1700 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
<> 144:ef7eb2e8f9f7 1701 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
<> 144:ef7eb2e8f9f7 1702 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
<> 144:ef7eb2e8f9f7 1703 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
<> 144:ef7eb2e8f9f7 1704 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
<> 144:ef7eb2e8f9f7 1705 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
<> 144:ef7eb2e8f9f7 1706 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
<> 144:ef7eb2e8f9f7 1707 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
<> 144:ef7eb2e8f9f7 1708 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
<> 144:ef7eb2e8f9f7 1709 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
<> 144:ef7eb2e8f9f7 1710 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
<> 144:ef7eb2e8f9f7 1711 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
<> 144:ef7eb2e8f9f7 1712 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
<> 144:ef7eb2e8f9f7 1713 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
<> 144:ef7eb2e8f9f7 1714 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
<> 144:ef7eb2e8f9f7 1715 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
<> 144:ef7eb2e8f9f7 1716 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
<> 144:ef7eb2e8f9f7 1717 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
<> 144:ef7eb2e8f9f7 1718 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
<> 144:ef7eb2e8f9f7 1719 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
<> 144:ef7eb2e8f9f7 1720 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
<> 144:ef7eb2e8f9f7 1721 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
<> 144:ef7eb2e8f9f7 1722 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
<> 144:ef7eb2e8f9f7 1723 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
<> 144:ef7eb2e8f9f7 1724 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
<> 144:ef7eb2e8f9f7 1725 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
<> 144:ef7eb2e8f9f7 1726 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
<> 144:ef7eb2e8f9f7 1727 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
<> 144:ef7eb2e8f9f7 1728 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
<> 144:ef7eb2e8f9f7 1729 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
<> 144:ef7eb2e8f9f7 1730 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
<> 144:ef7eb2e8f9f7 1731 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
<> 144:ef7eb2e8f9f7 1732 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
<> 144:ef7eb2e8f9f7 1733 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
<> 144:ef7eb2e8f9f7 1734 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
<> 144:ef7eb2e8f9f7 1735 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
<> 144:ef7eb2e8f9f7 1736 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
<> 144:ef7eb2e8f9f7 1737 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
<> 144:ef7eb2e8f9f7 1738 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
<> 144:ef7eb2e8f9f7 1739 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
<> 144:ef7eb2e8f9f7 1740 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
<> 144:ef7eb2e8f9f7 1741 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
<> 144:ef7eb2e8f9f7 1742 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
<> 144:ef7eb2e8f9f7 1743 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
<> 144:ef7eb2e8f9f7 1744 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
<> 144:ef7eb2e8f9f7 1745 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
<> 144:ef7eb2e8f9f7 1746 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
<> 144:ef7eb2e8f9f7 1747 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
<> 144:ef7eb2e8f9f7 1748 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
<> 144:ef7eb2e8f9f7 1749 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
<> 144:ef7eb2e8f9f7 1750 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
<> 144:ef7eb2e8f9f7 1751 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
<> 144:ef7eb2e8f9f7 1752 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
<> 144:ef7eb2e8f9f7 1753 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
<> 144:ef7eb2e8f9f7 1754 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
<> 144:ef7eb2e8f9f7 1755 /* @brief Has FTM module(s) configuration. */
<> 144:ef7eb2e8f9f7 1756 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
<> 144:ef7eb2e8f9f7 1757 /* @brief Number of FTM modules. */
<> 144:ef7eb2e8f9f7 1758 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
<> 144:ef7eb2e8f9f7 1759 /* @brief Number of FTM triggers with selectable source. */
<> 144:ef7eb2e8f9f7 1760 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
<> 144:ef7eb2e8f9f7 1761 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
<> 144:ef7eb2e8f9f7 1762 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
<> 144:ef7eb2e8f9f7 1763 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
<> 144:ef7eb2e8f9f7 1764 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
<> 144:ef7eb2e8f9f7 1765 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
<> 144:ef7eb2e8f9f7 1766 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
<> 144:ef7eb2e8f9f7 1767 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
<> 144:ef7eb2e8f9f7 1768 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
<> 144:ef7eb2e8f9f7 1769 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
<> 144:ef7eb2e8f9f7 1770 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
<> 144:ef7eb2e8f9f7 1771 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
<> 144:ef7eb2e8f9f7 1772 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
<> 144:ef7eb2e8f9f7 1773 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
<> 144:ef7eb2e8f9f7 1774 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
<> 144:ef7eb2e8f9f7 1775 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
<> 144:ef7eb2e8f9f7 1776 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
<> 144:ef7eb2e8f9f7 1777 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
<> 144:ef7eb2e8f9f7 1778 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
<> 144:ef7eb2e8f9f7 1779 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
<> 144:ef7eb2e8f9f7 1780 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
<> 144:ef7eb2e8f9f7 1781 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
<> 144:ef7eb2e8f9f7 1782 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
<> 144:ef7eb2e8f9f7 1783 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
<> 144:ef7eb2e8f9f7 1784 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
<> 144:ef7eb2e8f9f7 1785 /* @brief Has TPM module(s) configuration. */
<> 144:ef7eb2e8f9f7 1786 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
<> 144:ef7eb2e8f9f7 1787 /* @brief The highest TPM module index. */
<> 144:ef7eb2e8f9f7 1788 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
<> 144:ef7eb2e8f9f7 1789 /* @brief Has TPM module with index 0. */
<> 144:ef7eb2e8f9f7 1790 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
<> 144:ef7eb2e8f9f7 1791 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
<> 144:ef7eb2e8f9f7 1792 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
<> 144:ef7eb2e8f9f7 1793 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
<> 144:ef7eb2e8f9f7 1794 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
<> 144:ef7eb2e8f9f7 1795 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
<> 144:ef7eb2e8f9f7 1796 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
<> 144:ef7eb2e8f9f7 1797 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
<> 144:ef7eb2e8f9f7 1798 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
<> 144:ef7eb2e8f9f7 1799 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
<> 144:ef7eb2e8f9f7 1800 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
<> 144:ef7eb2e8f9f7 1801 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
<> 144:ef7eb2e8f9f7 1802 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
<> 144:ef7eb2e8f9f7 1803 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
<> 144:ef7eb2e8f9f7 1804 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
<> 144:ef7eb2e8f9f7 1805 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
<> 144:ef7eb2e8f9f7 1806 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
<> 144:ef7eb2e8f9f7 1807 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
<> 144:ef7eb2e8f9f7 1808 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
<> 144:ef7eb2e8f9f7 1809 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
<> 144:ef7eb2e8f9f7 1810 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
<> 144:ef7eb2e8f9f7 1811 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
<> 144:ef7eb2e8f9f7 1812 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
<> 144:ef7eb2e8f9f7 1813 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
<> 144:ef7eb2e8f9f7 1814 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
<> 144:ef7eb2e8f9f7 1815 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
<> 144:ef7eb2e8f9f7 1816 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
<> 144:ef7eb2e8f9f7 1817 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
<> 144:ef7eb2e8f9f7 1818 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
<> 144:ef7eb2e8f9f7 1819 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
<> 144:ef7eb2e8f9f7 1820 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
<> 144:ef7eb2e8f9f7 1821 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
<> 144:ef7eb2e8f9f7 1822 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
<> 144:ef7eb2e8f9f7 1823 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
<> 144:ef7eb2e8f9f7 1824 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
<> 144:ef7eb2e8f9f7 1825 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
<> 144:ef7eb2e8f9f7 1826 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
<> 144:ef7eb2e8f9f7 1827 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
<> 144:ef7eb2e8f9f7 1828 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
<> 144:ef7eb2e8f9f7 1829 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
<> 144:ef7eb2e8f9f7 1830 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
<> 144:ef7eb2e8f9f7 1831 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
<> 144:ef7eb2e8f9f7 1832 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
<> 144:ef7eb2e8f9f7 1833 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
<> 144:ef7eb2e8f9f7 1834 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
<> 144:ef7eb2e8f9f7 1835 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
<> 144:ef7eb2e8f9f7 1836 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
<> 144:ef7eb2e8f9f7 1837 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
<> 144:ef7eb2e8f9f7 1838 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
<> 144:ef7eb2e8f9f7 1839 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
<> 144:ef7eb2e8f9f7 1840 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
<> 144:ef7eb2e8f9f7 1841 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
<> 144:ef7eb2e8f9f7 1842 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
<> 144:ef7eb2e8f9f7 1843 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1844 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
<> 144:ef7eb2e8f9f7 1845 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1846 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
<> 144:ef7eb2e8f9f7 1847 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1848 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1849 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1850 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1851 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1852 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1853 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1854 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1855 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1856 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1857 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1858 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1859 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1860 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1861 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
<> 144:ef7eb2e8f9f7 1862 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
<> 144:ef7eb2e8f9f7 1863 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
<> 144:ef7eb2e8f9f7 1864 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
<> 144:ef7eb2e8f9f7 1865 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
<> 144:ef7eb2e8f9f7 1866 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
<> 144:ef7eb2e8f9f7 1867 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
<> 144:ef7eb2e8f9f7 1868 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
<> 144:ef7eb2e8f9f7 1869 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
<> 144:ef7eb2e8f9f7 1870 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
<> 144:ef7eb2e8f9f7 1871 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
<> 144:ef7eb2e8f9f7 1872 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
<> 144:ef7eb2e8f9f7 1873 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
<> 144:ef7eb2e8f9f7 1874 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
<> 144:ef7eb2e8f9f7 1875 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
<> 144:ef7eb2e8f9f7 1876 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
<> 144:ef7eb2e8f9f7 1877 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
<> 144:ef7eb2e8f9f7 1878 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
<> 144:ef7eb2e8f9f7 1879 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
<> 144:ef7eb2e8f9f7 1880 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
<> 144:ef7eb2e8f9f7 1881 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
<> 144:ef7eb2e8f9f7 1882 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
<> 144:ef7eb2e8f9f7 1883 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
<> 144:ef7eb2e8f9f7 1884 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
<> 144:ef7eb2e8f9f7 1885 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
<> 144:ef7eb2e8f9f7 1886 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
<> 144:ef7eb2e8f9f7 1887 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
<> 144:ef7eb2e8f9f7 1888 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
<> 144:ef7eb2e8f9f7 1889 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
<> 144:ef7eb2e8f9f7 1890 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
<> 144:ef7eb2e8f9f7 1891 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
<> 144:ef7eb2e8f9f7 1892 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
<> 144:ef7eb2e8f9f7 1893 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
<> 144:ef7eb2e8f9f7 1894 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
<> 144:ef7eb2e8f9f7 1895 /* @brief Has device die ID (register bit field SDID[DIEID]). */
<> 144:ef7eb2e8f9f7 1896 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
<> 144:ef7eb2e8f9f7 1897 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
<> 144:ef7eb2e8f9f7 1898 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
<> 144:ef7eb2e8f9f7 1899 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
<> 144:ef7eb2e8f9f7 1900 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
<> 144:ef7eb2e8f9f7 1901 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
<> 144:ef7eb2e8f9f7 1902 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
<> 144:ef7eb2e8f9f7 1903 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
<> 144:ef7eb2e8f9f7 1904 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
<> 144:ef7eb2e8f9f7 1905 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
<> 144:ef7eb2e8f9f7 1906 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
<> 144:ef7eb2e8f9f7 1907 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
<> 144:ef7eb2e8f9f7 1908 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
<> 144:ef7eb2e8f9f7 1909 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
<> 144:ef7eb2e8f9f7 1910 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
<> 144:ef7eb2e8f9f7 1911 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
<> 144:ef7eb2e8f9f7 1912 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
<> 144:ef7eb2e8f9f7 1913 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
<> 144:ef7eb2e8f9f7 1914 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
<> 144:ef7eb2e8f9f7 1915 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
<> 144:ef7eb2e8f9f7 1916 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
<> 144:ef7eb2e8f9f7 1917 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
<> 144:ef7eb2e8f9f7 1918 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
<> 144:ef7eb2e8f9f7 1919 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
<> 144:ef7eb2e8f9f7 1920 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
<> 144:ef7eb2e8f9f7 1921 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
<> 144:ef7eb2e8f9f7 1922 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
<> 144:ef7eb2e8f9f7 1923 /* @brief Has miscellanious control register (register MCR). */
<> 144:ef7eb2e8f9f7 1924 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
<> 144:ef7eb2e8f9f7 1925 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
<> 144:ef7eb2e8f9f7 1926 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
<> 144:ef7eb2e8f9f7 1927 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
<> 144:ef7eb2e8f9f7 1928 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
<> 144:ef7eb2e8f9f7 1929 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
<> 144:ef7eb2e8f9f7 1930 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 /* SMC module features */
<> 144:ef7eb2e8f9f7 1933
<> 144:ef7eb2e8f9f7 1934 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
<> 144:ef7eb2e8f9f7 1935 #define FSL_FEATURE_SMC_HAS_PSTOPO (0)
<> 144:ef7eb2e8f9f7 1936 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
<> 144:ef7eb2e8f9f7 1937 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
<> 144:ef7eb2e8f9f7 1938 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
<> 144:ef7eb2e8f9f7 1939 #define FSL_FEATURE_SMC_HAS_PORPO (1)
<> 144:ef7eb2e8f9f7 1940 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
<> 144:ef7eb2e8f9f7 1941 #define FSL_FEATURE_SMC_HAS_LPWUI (1)
<> 144:ef7eb2e8f9f7 1942 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
<> 144:ef7eb2e8f9f7 1943 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
<> 144:ef7eb2e8f9f7 1944 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
<> 144:ef7eb2e8f9f7 1945 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
<> 144:ef7eb2e8f9f7 1946 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
<> 144:ef7eb2e8f9f7 1947 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
<> 144:ef7eb2e8f9f7 1948 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
<> 144:ef7eb2e8f9f7 1949 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
<> 144:ef7eb2e8f9f7 1950 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
<> 144:ef7eb2e8f9f7 1951 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
<> 144:ef7eb2e8f9f7 1952 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
<> 144:ef7eb2e8f9f7 1953 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
<> 144:ef7eb2e8f9f7 1954 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
<> 144:ef7eb2e8f9f7 1955 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
<> 144:ef7eb2e8f9f7 1956 /* @brief Has stop submode. */
<> 144:ef7eb2e8f9f7 1957 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
<> 144:ef7eb2e8f9f7 1958 /* @brief Has stop submode 0(VLLS0). */
<> 144:ef7eb2e8f9f7 1959 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
<> 144:ef7eb2e8f9f7 1960 /* @brief Has stop submode 2(VLLS2). */
<> 144:ef7eb2e8f9f7 1961 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
<> 144:ef7eb2e8f9f7 1962 /* @brief Has SMC_PARAM. */
<> 144:ef7eb2e8f9f7 1963 #define FSL_FEATURE_SMC_HAS_PARAM (0)
<> 144:ef7eb2e8f9f7 1964 /* @brief Has SMC_VERID. */
<> 144:ef7eb2e8f9f7 1965 #define FSL_FEATURE_SMC_HAS_VERID (0)
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /* DSPI module features */
<> 144:ef7eb2e8f9f7 1968
<> 144:ef7eb2e8f9f7 1969 /* @brief Receive/transmit FIFO size in number of items. */
<> 144:ef7eb2e8f9f7 1970 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
<> 144:ef7eb2e8f9f7 1971 ((x) == DSPI0 ? (4) : \
<> 144:ef7eb2e8f9f7 1972 ((x) == DSPI1 ? (1) : \
<> 144:ef7eb2e8f9f7 1973 ((x) == DSPI2 ? (1) : (-1))))
<> 144:ef7eb2e8f9f7 1974 /* @brief Maximum transfer data width in bits. */
<> 144:ef7eb2e8f9f7 1975 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
<> 144:ef7eb2e8f9f7 1976 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
<> 144:ef7eb2e8f9f7 1977 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
<> 144:ef7eb2e8f9f7 1978 /* @brief Number of chip select pins. */
<> 144:ef7eb2e8f9f7 1979 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
<> 144:ef7eb2e8f9f7 1980 /* @brief Has chip select strobe capability on the PCS5 pin. */
<> 144:ef7eb2e8f9f7 1981 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
<> 144:ef7eb2e8f9f7 1982 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
<> 144:ef7eb2e8f9f7 1983 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
<> 144:ef7eb2e8f9f7 1984 /* @brief Has 16-bit data transfer support. */
<> 144:ef7eb2e8f9f7 1985 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
<> 144:ef7eb2e8f9f7 1986 /* @brief Has separate DMA RX and TX requests. */
<> 144:ef7eb2e8f9f7 1987 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
<> 144:ef7eb2e8f9f7 1988 ((x) == DSPI0 ? (1) : \
<> 144:ef7eb2e8f9f7 1989 ((x) == DSPI1 ? (0) : \
<> 144:ef7eb2e8f9f7 1990 ((x) == DSPI2 ? (0) : (-1))))
<> 144:ef7eb2e8f9f7 1991
<> 144:ef7eb2e8f9f7 1992 /* SysTick module features */
<> 144:ef7eb2e8f9f7 1993
<> 144:ef7eb2e8f9f7 1994 /* @brief Systick has external reference clock. */
<> 144:ef7eb2e8f9f7 1995 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
<> 144:ef7eb2e8f9f7 1996 /* @brief Systick external reference clock is core clock divided by this value. */
<> 144:ef7eb2e8f9f7 1997 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /* UART module features */
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
<> 144:ef7eb2e8f9f7 2002 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
<> 144:ef7eb2e8f9f7 2003 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
<> 144:ef7eb2e8f9f7 2004 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2005 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
<> 144:ef7eb2e8f9f7 2006 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
<> 144:ef7eb2e8f9f7 2007 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
<> 144:ef7eb2e8f9f7 2008 #define FSL_FEATURE_UART_HAS_FIFO (1)
<> 144:ef7eb2e8f9f7 2009 /* @brief Hardware flow control (RTS, CTS) is supported. */
<> 144:ef7eb2e8f9f7 2010 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
<> 144:ef7eb2e8f9f7 2011 /* @brief Infrared (modulation) is supported. */
<> 144:ef7eb2e8f9f7 2012 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
<> 144:ef7eb2e8f9f7 2013 /* @brief 2 bits long stop bit is available. */
<> 144:ef7eb2e8f9f7 2014 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
<> 144:ef7eb2e8f9f7 2015 /* @brief Maximal data width without parity bit. */
<> 144:ef7eb2e8f9f7 2016 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2017 /* @brief Baud rate fine adjustment is available. */
<> 144:ef7eb2e8f9f7 2018 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
<> 144:ef7eb2e8f9f7 2019 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
<> 144:ef7eb2e8f9f7 2020 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2021 /* @brief Baud rate oversampling is available. */
<> 144:ef7eb2e8f9f7 2022 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2023 /* @brief Baud rate oversampling is available. */
<> 144:ef7eb2e8f9f7 2024 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2025 /* @brief Peripheral type. */
<> 144:ef7eb2e8f9f7 2026 #define FSL_FEATURE_UART_IS_SCI (0)
<> 144:ef7eb2e8f9f7 2027 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
<> 144:ef7eb2e8f9f7 2028 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
<> 144:ef7eb2e8f9f7 2029 ((x) == UART0 ? (8) : \
<> 144:ef7eb2e8f9f7 2030 ((x) == UART1 ? (8) : \
<> 144:ef7eb2e8f9f7 2031 ((x) == UART2 ? (1) : \
<> 144:ef7eb2e8f9f7 2032 ((x) == UART3 ? (1) : \
<> 144:ef7eb2e8f9f7 2033 ((x) == UART4 ? (1) : \
<> 144:ef7eb2e8f9f7 2034 ((x) == UART5 ? (1) : (-1)))))))
<> 144:ef7eb2e8f9f7 2035 /* @brief Maximal data width without parity bit. */
<> 144:ef7eb2e8f9f7 2036 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
<> 144:ef7eb2e8f9f7 2037 /* @brief Maximal data width with parity bit. */
<> 144:ef7eb2e8f9f7 2038 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
<> 144:ef7eb2e8f9f7 2039 /* @brief Supports two match addresses to filter incoming frames. */
<> 144:ef7eb2e8f9f7 2040 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
<> 144:ef7eb2e8f9f7 2041 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
<> 144:ef7eb2e8f9f7 2042 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
<> 144:ef7eb2e8f9f7 2043 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
<> 144:ef7eb2e8f9f7 2044 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
<> 144:ef7eb2e8f9f7 2045 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
<> 144:ef7eb2e8f9f7 2046 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
<> 144:ef7eb2e8f9f7 2047 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
<> 144:ef7eb2e8f9f7 2048 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
<> 144:ef7eb2e8f9f7 2049 /* @brief Has improved smart card (ISO7816 protocol) support. */
<> 144:ef7eb2e8f9f7 2050 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2051 /* @brief Has local operation network (CEA709.1-B protocol) support. */
<> 144:ef7eb2e8f9f7 2052 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
<> 144:ef7eb2e8f9f7 2053 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
<> 144:ef7eb2e8f9f7 2054 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
<> 144:ef7eb2e8f9f7 2055 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
<> 144:ef7eb2e8f9f7 2056 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
<> 144:ef7eb2e8f9f7 2057 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
<> 144:ef7eb2e8f9f7 2058 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
<> 144:ef7eb2e8f9f7 2059 /* @brief Has separate DMA RX and TX requests. */
<> 144:ef7eb2e8f9f7 2060 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
<> 144:ef7eb2e8f9f7 2061 ((x) == UART0 ? (1) : \
<> 144:ef7eb2e8f9f7 2062 ((x) == UART1 ? (1) : \
<> 144:ef7eb2e8f9f7 2063 ((x) == UART2 ? (1) : \
<> 144:ef7eb2e8f9f7 2064 ((x) == UART3 ? (1) : \
<> 144:ef7eb2e8f9f7 2065 ((x) == UART4 ? (0) : \
<> 144:ef7eb2e8f9f7 2066 ((x) == UART5 ? (0) : (-1)))))))
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 /* USB module features */
<> 144:ef7eb2e8f9f7 2069
<> 144:ef7eb2e8f9f7 2070 /* @brief HOST mode enabled */
<> 144:ef7eb2e8f9f7 2071 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
<> 144:ef7eb2e8f9f7 2072 /* @brief OTG mode enabled */
<> 144:ef7eb2e8f9f7 2073 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
<> 144:ef7eb2e8f9f7 2074 /* @brief Size of the USB dedicated RAM */
<> 144:ef7eb2e8f9f7 2075 #define FSL_FEATURE_USB_KHCI_USB_RAM (0)
<> 144:ef7eb2e8f9f7 2076 /* @brief Has KEEP_ALIVE_CTRL register */
<> 144:ef7eb2e8f9f7 2077 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
<> 144:ef7eb2e8f9f7 2078 /* @brief Has the Dynamic SOF threshold compare support */
<> 144:ef7eb2e8f9f7 2079 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
<> 144:ef7eb2e8f9f7 2080 /* @brief Has the VBUS detect support */
<> 144:ef7eb2e8f9f7 2081 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
<> 144:ef7eb2e8f9f7 2082 /* @brief Has the IRC48M module clock support */
<> 144:ef7eb2e8f9f7 2083 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
<> 144:ef7eb2e8f9f7 2084 /* @brief Number of endpoints supported */
<> 144:ef7eb2e8f9f7 2085 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 /* VREF module features */
<> 144:ef7eb2e8f9f7 2088
<> 144:ef7eb2e8f9f7 2089 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
<> 144:ef7eb2e8f9f7 2090 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
<> 144:ef7eb2e8f9f7 2091 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
<> 144:ef7eb2e8f9f7 2092 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
<> 144:ef7eb2e8f9f7 2093 /* @brief Describes the set of SC[MODE_LV] bitfield values */
<> 144:ef7eb2e8f9f7 2094 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
<> 144:ef7eb2e8f9f7 2095 /* @brief Module has also low reference (registers VREFL/VREFH) */
<> 144:ef7eb2e8f9f7 2096 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
<> 144:ef7eb2e8f9f7 2097 /* @brief Has VREF_TRM4. */
<> 144:ef7eb2e8f9f7 2098 #define FSL_FEATURE_VREF_HAS_TRM4 (0)
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /* WDOG module features */
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 /* @brief Watchdog is available. */
<> 144:ef7eb2e8f9f7 2103 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
<> 144:ef7eb2e8f9f7 2104 /* @brief Has Wait mode support. */
<> 144:ef7eb2e8f9f7 2105 #define FSL_FEATURE_WDOG_HAS_WAITEN (1)
<> 144:ef7eb2e8f9f7 2106
<> 144:ef7eb2e8f9f7 2107 #endif /* _MK64F12_FEATURES_H_ */
<> 144:ef7eb2e8f9f7 2108