Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KL43Z/system_MKL43Z4.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MKL43Z128VLH4
<> 144:ef7eb2e8f9f7 4 ** MKL43Z128VMP4
<> 144:ef7eb2e8f9f7 5 ** MKL43Z256VLH4
<> 144:ef7eb2e8f9f7 6 ** MKL43Z256VMP4
<> 144:ef7eb2e8f9f7 7 **
<> 144:ef7eb2e8f9f7 8 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 9 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 10 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 11 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 12 **
<> 144:ef7eb2e8f9f7 13 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
<> 144:ef7eb2e8f9f7 14 ** Version: rev. 1.6, 2015-07-29
<> 144:ef7eb2e8f9f7 15 ** Build: b151217
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Abstract:
<> 144:ef7eb2e8f9f7 18 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 19 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 20 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 21 **
<> 144:ef7eb2e8f9f7 22 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 23 ** All rights reserved.
<> 144:ef7eb2e8f9f7 24 **
<> 144:ef7eb2e8f9f7 25 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 26 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 27 **
<> 144:ef7eb2e8f9f7 28 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 29 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 30 **
<> 144:ef7eb2e8f9f7 31 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 32 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 33 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 34 **
<> 144:ef7eb2e8f9f7 35 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 36 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 37 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 38 **
<> 144:ef7eb2e8f9f7 39 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 40 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 41 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 42 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 43 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 44 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 45 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 46 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 47 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 48 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 49 **
<> 144:ef7eb2e8f9f7 50 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 51 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 52 **
<> 144:ef7eb2e8f9f7 53 ** Revisions:
<> 144:ef7eb2e8f9f7 54 ** - rev. 1.0 (2014-03-27)
<> 144:ef7eb2e8f9f7 55 ** Initial version.
<> 144:ef7eb2e8f9f7 56 ** - rev. 1.1 (2014-05-26)
<> 144:ef7eb2e8f9f7 57 ** I2S registers TCR2/RCR2 and others were changed.
<> 144:ef7eb2e8f9f7 58 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
<> 144:ef7eb2e8f9f7 59 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
<> 144:ef7eb2e8f9f7 60 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
<> 144:ef7eb2e8f9f7 61 ** Clock configuration for high range external oscillator has been added.
<> 144:ef7eb2e8f9f7 62 ** RFSYS module access has been added.
<> 144:ef7eb2e8f9f7 63 ** - rev. 1.2 (2014-07-10)
<> 144:ef7eb2e8f9f7 64 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
<> 144:ef7eb2e8f9f7 65 ** UART0 - UART0 module renamed to UART2.
<> 144:ef7eb2e8f9f7 66 ** I2S - removed MDR register.
<> 144:ef7eb2e8f9f7 67 ** - rev. 1.3 (2014-08-21)
<> 144:ef7eb2e8f9f7 68 ** UART2 - Removed ED register.
<> 144:ef7eb2e8f9f7 69 ** UART2 - Removed MODEM register.
<> 144:ef7eb2e8f9f7 70 ** UART2 - Removed IR register.
<> 144:ef7eb2e8f9f7 71 ** UART2 - Removed PFIFO register.
<> 144:ef7eb2e8f9f7 72 ** UART2 - Removed CFIFO register.
<> 144:ef7eb2e8f9f7 73 ** UART2 - Removed SFIFO register.
<> 144:ef7eb2e8f9f7 74 ** UART2 - Removed TWFIFO register.
<> 144:ef7eb2e8f9f7 75 ** UART2 - Removed TCFIFO register.
<> 144:ef7eb2e8f9f7 76 ** UART2 - Removed RWFIFO register.
<> 144:ef7eb2e8f9f7 77 ** UART2 - Removed RCFIFO register.
<> 144:ef7eb2e8f9f7 78 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
<> 144:ef7eb2e8f9f7 79 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
<> 144:ef7eb2e8f9f7 80 ** SIM - Removed bitfield DIEID in SDID register.
<> 144:ef7eb2e8f9f7 81 ** - rev. 1.4 (2014-09-01)
<> 144:ef7eb2e8f9f7 82 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
<> 144:ef7eb2e8f9f7 83 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
<> 144:ef7eb2e8f9f7 84 ** - rev. 1.5 (2014-09-05)
<> 144:ef7eb2e8f9f7 85 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
<> 144:ef7eb2e8f9f7 86 ** - rev. 1.6 (2015-07-29)
<> 144:ef7eb2e8f9f7 87 ** Correction of backward compatibility.
<> 144:ef7eb2e8f9f7 88 **
<> 144:ef7eb2e8f9f7 89 ** ###################################################################
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*!
<> 144:ef7eb2e8f9f7 93 * @file MKL43Z4
<> 144:ef7eb2e8f9f7 94 * @version 1.6
<> 144:ef7eb2e8f9f7 95 * @date 2015-07-29
<> 144:ef7eb2e8f9f7 96 * @brief Device specific configuration file for MKL43Z4 (implementation file)
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 99 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 100 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #include <stdint.h>
<> 144:ef7eb2e8f9f7 104 #include "fsl_device_registers.h"
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 109 -- Core clock
<> 144:ef7eb2e8f9f7 110 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 115 -- SystemInit()
<> 144:ef7eb2e8f9f7 116 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #if (ACK_ISOLATION)
<> 144:ef7eb2e8f9f7 121 if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
<> 144:ef7eb2e8f9f7 122 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
<> 144:ef7eb2e8f9f7 123 }
<> 144:ef7eb2e8f9f7 124 #endif
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 127 /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
<> 144:ef7eb2e8f9f7 128 SIM->COPC = (uint32_t)0x00u;
<> 144:ef7eb2e8f9f7 129 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 134 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 135 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 140 uint16_t Divider;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 143 /* High internal reference clock is selected */
<> 144:ef7eb2e8f9f7 144 MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 145 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
<> 144:ef7eb2e8f9f7 146 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 147 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 148 MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
<> 144:ef7eb2e8f9f7 149 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
<> 144:ef7eb2e8f9f7 150 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 151 MCGOUTClock = CPU_XTAL_CLK_HZ;
<> 144:ef7eb2e8f9f7 152 } else {
<> 144:ef7eb2e8f9f7 153 /* Reserved value */
<> 144:ef7eb2e8f9f7 154 return;
<> 144:ef7eb2e8f9f7 155 } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
<> 144:ef7eb2e8f9f7 156 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 }