Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* ---------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2 /* @file: startup_MKL43Z4.s */
<> 144:ef7eb2e8f9f7 3 /* @purpose: CMSIS Cortex-M0P Core Device Startup File */
<> 144:ef7eb2e8f9f7 4 /* MKL43Z4 */
<> 144:ef7eb2e8f9f7 5 /* @version: 1.8 */
<> 144:ef7eb2e8f9f7 6 /* @date: 2016-6-24 */
<> 144:ef7eb2e8f9f7 7 /* @build: b160627 */
<> 144:ef7eb2e8f9f7 8 /* ---------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 9 /* */
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
<> 144:ef7eb2e8f9f7 11 /* All rights reserved. */
<> 144:ef7eb2e8f9f7 12 /* */
<> 144:ef7eb2e8f9f7 13 /* Redistribution and use in source and binary forms, with or without modification, */
<> 144:ef7eb2e8f9f7 14 /* are permitted provided that the following conditions are met: */
<> 144:ef7eb2e8f9f7 15 /* */
<> 144:ef7eb2e8f9f7 16 /* o Redistributions of source code must retain the above copyright notice, this list */
<> 144:ef7eb2e8f9f7 17 /* of conditions and the following disclaimer. */
<> 144:ef7eb2e8f9f7 18 /* */
<> 144:ef7eb2e8f9f7 19 /* o Redistributions in binary form must reproduce the above copyright notice, this */
<> 144:ef7eb2e8f9f7 20 /* list of conditions and the following disclaimer in the documentation and/or */
<> 144:ef7eb2e8f9f7 21 /* other materials provided with the distribution. */
<> 144:ef7eb2e8f9f7 22 /* */
<> 144:ef7eb2e8f9f7 23 /* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
<> 144:ef7eb2e8f9f7 24 /* contributors may be used to endorse or promote products derived from this */
<> 144:ef7eb2e8f9f7 25 /* software without specific prior written permission. */
<> 144:ef7eb2e8f9f7 26 /* */
<> 144:ef7eb2e8f9f7 27 /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
<> 144:ef7eb2e8f9f7 28 /* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
<> 144:ef7eb2e8f9f7 29 /* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
<> 144:ef7eb2e8f9f7 30 /* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
<> 144:ef7eb2e8f9f7 31 /* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
<> 144:ef7eb2e8f9f7 32 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
<> 144:ef7eb2e8f9f7 33 /* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
<> 144:ef7eb2e8f9f7 34 /* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
<> 144:ef7eb2e8f9f7 35 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
<> 144:ef7eb2e8f9f7 36 /* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
<> 144:ef7eb2e8f9f7 37 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 38 /* Version: GCC for ARM Embedded Processors */
<> 144:ef7eb2e8f9f7 39 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 40 .syntax unified
<> 144:ef7eb2e8f9f7 41 .arch armv6-m
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 .section .isr_vector, "a"
<> 144:ef7eb2e8f9f7 44 .align 2
<> 144:ef7eb2e8f9f7 45 .globl __isr_vector
<> 144:ef7eb2e8f9f7 46 __isr_vector:
<> 144:ef7eb2e8f9f7 47 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 48 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 49 .long NMI_Handler /* NMI Handler*/
<> 144:ef7eb2e8f9f7 50 .long HardFault_Handler /* Hard Fault Handler*/
<> 144:ef7eb2e8f9f7 51 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 52 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 53 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 54 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 55 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 56 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 57 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 58 .long SVC_Handler /* SVCall Handler*/
<> 144:ef7eb2e8f9f7 59 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 60 .long 0 /* Reserved*/
<> 144:ef7eb2e8f9f7 61 .long PendSV_Handler /* PendSV Handler*/
<> 144:ef7eb2e8f9f7 62 .long SysTick_Handler /* SysTick Handler*/
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* External Interrupts*/
<> 144:ef7eb2e8f9f7 65 .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
<> 144:ef7eb2e8f9f7 66 .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
<> 144:ef7eb2e8f9f7 67 .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
<> 144:ef7eb2e8f9f7 68 .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
<> 144:ef7eb2e8f9f7 69 .long Reserved20_IRQHandler /* Reserved interrupt*/
<> 144:ef7eb2e8f9f7 70 .long FTFA_IRQHandler /* Command complete and read collision*/
<> 144:ef7eb2e8f9f7 71 .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/
<> 144:ef7eb2e8f9f7 72 .long LLWU_IRQHandler /* Low leakage wakeup*/
<> 144:ef7eb2e8f9f7 73 .long I2C0_IRQHandler /* I2C0 interrupt*/
<> 144:ef7eb2e8f9f7 74 .long I2C1_IRQHandler /* I2C1 interrupt*/
<> 144:ef7eb2e8f9f7 75 .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
<> 144:ef7eb2e8f9f7 76 .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
<> 144:ef7eb2e8f9f7 77 .long LPUART0_IRQHandler /* LPUART0 status and error*/
<> 144:ef7eb2e8f9f7 78 .long LPUART1_IRQHandler /* LPUART1 status and error*/
<> 144:ef7eb2e8f9f7 79 .long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/
<> 144:ef7eb2e8f9f7 80 .long ADC0_IRQHandler /* ADC0 interrupt*/
<> 144:ef7eb2e8f9f7 81 .long CMP0_IRQHandler /* CMP0 interrupt*/
<> 144:ef7eb2e8f9f7 82 .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
<> 144:ef7eb2e8f9f7 83 .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
<> 144:ef7eb2e8f9f7 84 .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
<> 144:ef7eb2e8f9f7 85 .long RTC_IRQHandler /* RTC alarm*/
<> 144:ef7eb2e8f9f7 86 .long RTC_Seconds_IRQHandler /* RTC seconds*/
<> 144:ef7eb2e8f9f7 87 .long PIT_IRQHandler /* PIT interrupt*/
<> 144:ef7eb2e8f9f7 88 .long I2S0_IRQHandler /* I2S0 interrupt*/
<> 144:ef7eb2e8f9f7 89 .long USB0_IRQHandler /* USB0 interrupt*/
<> 144:ef7eb2e8f9f7 90 .long DAC0_IRQHandler /* DAC0 interrupt*/
<> 144:ef7eb2e8f9f7 91 .long Reserved42_IRQHandler /* Reserved interrupt*/
<> 144:ef7eb2e8f9f7 92 .long Reserved43_IRQHandler /* Reserved interrupt*/
<> 144:ef7eb2e8f9f7 93 .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
<> 144:ef7eb2e8f9f7 94 .long LCD_IRQHandler /* LCD interrupt*/
<> 144:ef7eb2e8f9f7 95 .long PORTA_IRQHandler /* PORTA Pin detect*/
<> 144:ef7eb2e8f9f7 96 .long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Flash Configuration */
<> 144:ef7eb2e8f9f7 101 .section .FlashConfig, "a"
<> 144:ef7eb2e8f9f7 102 .long 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 103 .long 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 104 .long 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 105 .long 0xFFFF3FFE
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 .text
<> 144:ef7eb2e8f9f7 108 .thumb
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* Reset Handler */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 .thumb_func
<> 144:ef7eb2e8f9f7 113 .align 2
<> 144:ef7eb2e8f9f7 114 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 115 .weak Reset_Handler
<> 144:ef7eb2e8f9f7 116 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 117 Reset_Handler:
<> 144:ef7eb2e8f9f7 118 cpsid i /* Mask interrupts */
<> 144:ef7eb2e8f9f7 119 .equ VTOR, 0xE000ED08
<> 144:ef7eb2e8f9f7 120 ldr r0, =VTOR
<> 144:ef7eb2e8f9f7 121 ldr r1, =__isr_vector
<> 144:ef7eb2e8f9f7 122 str r1, [r0]
<> 144:ef7eb2e8f9f7 123 #ifndef __NO_SYSTEM_INIT
<> 144:ef7eb2e8f9f7 124 ldr r0,=SystemInit
<> 144:ef7eb2e8f9f7 125 blx r0
<> 144:ef7eb2e8f9f7 126 #endif
<> 144:ef7eb2e8f9f7 127 /* Loop to copy data from read only memory to RAM. The ranges
<> 144:ef7eb2e8f9f7 128 * of copy from/to are specified by following symbols evaluated in
<> 144:ef7eb2e8f9f7 129 * linker script.
<> 144:ef7eb2e8f9f7 130 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 144:ef7eb2e8f9f7 131 * __data_start__/__data_end__: RAM address range that data should be
<> 144:ef7eb2e8f9f7 132 * copied to. Both must be aligned to 4 bytes boundary. */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 135 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 136 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 subs r3, r2
<> 144:ef7eb2e8f9f7 139 ble .LC0
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 .LC1:
<> 144:ef7eb2e8f9f7 142 subs r3, 4
<> 144:ef7eb2e8f9f7 143 ldr r0, [r1,r3]
<> 144:ef7eb2e8f9f7 144 str r0, [r2,r3]
<> 144:ef7eb2e8f9f7 145 bgt .LC1
<> 144:ef7eb2e8f9f7 146 .LC0:
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #ifdef __STARTUP_CLEAR_BSS
<> 144:ef7eb2e8f9f7 149 /* This part of work usually is done in C library startup code. Otherwise,
<> 144:ef7eb2e8f9f7 150 * define this macro to enable it in this startup.
<> 144:ef7eb2e8f9f7 151 *
<> 144:ef7eb2e8f9f7 152 * Loop to zero out BSS section, which uses following symbols
<> 144:ef7eb2e8f9f7 153 * in linker script:
<> 144:ef7eb2e8f9f7 154 * __bss_start__: start of BSS section. Must align to 4
<> 144:ef7eb2e8f9f7 155 * __bss_end__: end of BSS section. Must align to 4
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 ldr r1, =__bss_start__
<> 144:ef7eb2e8f9f7 158 ldr r2, =__bss_end__
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 subs r2, r1
<> 144:ef7eb2e8f9f7 161 ble .LC3
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 movs r0, 0
<> 144:ef7eb2e8f9f7 164 .LC2:
<> 144:ef7eb2e8f9f7 165 str r0, [r1, r2]
<> 144:ef7eb2e8f9f7 166 subs r2, 4
<> 144:ef7eb2e8f9f7 167 bge .LC2
<> 144:ef7eb2e8f9f7 168 .LC3:
<> 144:ef7eb2e8f9f7 169 #endif
<> 144:ef7eb2e8f9f7 170 cpsie i /* Unmask interrupts */
<> 144:ef7eb2e8f9f7 171 #ifndef __START
<> 144:ef7eb2e8f9f7 172 #define __START _start
<> 144:ef7eb2e8f9f7 173 #endif
<> 144:ef7eb2e8f9f7 174 #ifndef __ATOLLIC__
<> 144:ef7eb2e8f9f7 175 ldr r0,=__START
<> 144:ef7eb2e8f9f7 176 blx r0
<> 144:ef7eb2e8f9f7 177 #else
<> 144:ef7eb2e8f9f7 178 ldr r0,=__libc_init_array
<> 144:ef7eb2e8f9f7 179 blx r0
<> 144:ef7eb2e8f9f7 180 ldr r0,=main
<> 144:ef7eb2e8f9f7 181 bx r0
<> 144:ef7eb2e8f9f7 182 #endif
<> 144:ef7eb2e8f9f7 183 .pool
<> 144:ef7eb2e8f9f7 184 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 .align 1
<> 144:ef7eb2e8f9f7 187 .thumb_func
<> 144:ef7eb2e8f9f7 188 .weak DefaultISR
<> 144:ef7eb2e8f9f7 189 .type DefaultISR, %function
<> 144:ef7eb2e8f9f7 190 DefaultISR:
<> 144:ef7eb2e8f9f7 191 ldr r0, =DefaultISR
<> 144:ef7eb2e8f9f7 192 bx r0
<> 144:ef7eb2e8f9f7 193 .size DefaultISR, . - DefaultISR
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 .align 1
<> 144:ef7eb2e8f9f7 196 .thumb_func
<> 144:ef7eb2e8f9f7 197 .weak NMI_Handler
<> 144:ef7eb2e8f9f7 198 .type NMI_Handler, %function
<> 144:ef7eb2e8f9f7 199 NMI_Handler:
<> 144:ef7eb2e8f9f7 200 ldr r0,=NMI_Handler
<> 144:ef7eb2e8f9f7 201 bx r0
<> 144:ef7eb2e8f9f7 202 .size NMI_Handler, . - NMI_Handler
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 .align 1
<> 144:ef7eb2e8f9f7 205 .thumb_func
<> 144:ef7eb2e8f9f7 206 .weak HardFault_Handler
<> 144:ef7eb2e8f9f7 207 .type HardFault_Handler, %function
<> 144:ef7eb2e8f9f7 208 HardFault_Handler:
<> 144:ef7eb2e8f9f7 209 ldr r0,=HardFault_Handler
<> 144:ef7eb2e8f9f7 210 bx r0
<> 144:ef7eb2e8f9f7 211 .size HardFault_Handler, . - HardFault_Handler
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 .align 1
<> 144:ef7eb2e8f9f7 214 .thumb_func
<> 144:ef7eb2e8f9f7 215 .weak SVC_Handler
<> 144:ef7eb2e8f9f7 216 .type SVC_Handler, %function
<> 144:ef7eb2e8f9f7 217 SVC_Handler:
<> 144:ef7eb2e8f9f7 218 ldr r0,=SVC_Handler
<> 144:ef7eb2e8f9f7 219 bx r0
<> 144:ef7eb2e8f9f7 220 .size SVC_Handler, . - SVC_Handler
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 .align 1
<> 144:ef7eb2e8f9f7 223 .thumb_func
<> 144:ef7eb2e8f9f7 224 .weak PendSV_Handler
<> 144:ef7eb2e8f9f7 225 .type PendSV_Handler, %function
<> 144:ef7eb2e8f9f7 226 PendSV_Handler:
<> 144:ef7eb2e8f9f7 227 ldr r0,=PendSV_Handler
<> 144:ef7eb2e8f9f7 228 bx r0
<> 144:ef7eb2e8f9f7 229 .size PendSV_Handler, . - PendSV_Handler
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 .align 1
<> 144:ef7eb2e8f9f7 232 .thumb_func
<> 144:ef7eb2e8f9f7 233 .weak SysTick_Handler
<> 144:ef7eb2e8f9f7 234 .type SysTick_Handler, %function
<> 144:ef7eb2e8f9f7 235 SysTick_Handler:
<> 144:ef7eb2e8f9f7 236 ldr r0,=SysTick_Handler
<> 144:ef7eb2e8f9f7 237 bx r0
<> 144:ef7eb2e8f9f7 238 .size SysTick_Handler, . - SysTick_Handler
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 .align 1
<> 144:ef7eb2e8f9f7 241 .thumb_func
<> 144:ef7eb2e8f9f7 242 .weak DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 243 .type DMA0_IRQHandler, %function
<> 144:ef7eb2e8f9f7 244 DMA0_IRQHandler:
<> 144:ef7eb2e8f9f7 245 ldr r0,=DMA0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 246 bx r0
<> 144:ef7eb2e8f9f7 247 .size DMA0_IRQHandler, . - DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 .align 1
<> 144:ef7eb2e8f9f7 250 .thumb_func
<> 144:ef7eb2e8f9f7 251 .weak DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 252 .type DMA1_IRQHandler, %function
<> 144:ef7eb2e8f9f7 253 DMA1_IRQHandler:
<> 144:ef7eb2e8f9f7 254 ldr r0,=DMA1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 255 bx r0
<> 144:ef7eb2e8f9f7 256 .size DMA1_IRQHandler, . - DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 .align 1
<> 144:ef7eb2e8f9f7 259 .thumb_func
<> 144:ef7eb2e8f9f7 260 .weak DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 261 .type DMA2_IRQHandler, %function
<> 144:ef7eb2e8f9f7 262 DMA2_IRQHandler:
<> 144:ef7eb2e8f9f7 263 ldr r0,=DMA2_DriverIRQHandler
<> 144:ef7eb2e8f9f7 264 bx r0
<> 144:ef7eb2e8f9f7 265 .size DMA2_IRQHandler, . - DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 .align 1
<> 144:ef7eb2e8f9f7 268 .thumb_func
<> 144:ef7eb2e8f9f7 269 .weak DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 270 .type DMA3_IRQHandler, %function
<> 144:ef7eb2e8f9f7 271 DMA3_IRQHandler:
<> 144:ef7eb2e8f9f7 272 ldr r0,=DMA3_DriverIRQHandler
<> 144:ef7eb2e8f9f7 273 bx r0
<> 144:ef7eb2e8f9f7 274 .size DMA3_IRQHandler, . - DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 .align 1
<> 144:ef7eb2e8f9f7 277 .thumb_func
<> 144:ef7eb2e8f9f7 278 .weak I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 279 .type I2C0_IRQHandler, %function
<> 144:ef7eb2e8f9f7 280 I2C0_IRQHandler:
<> 144:ef7eb2e8f9f7 281 ldr r0,=I2C0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 282 bx r0
<> 144:ef7eb2e8f9f7 283 .size I2C0_IRQHandler, . - I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 .align 1
<> 144:ef7eb2e8f9f7 286 .thumb_func
<> 144:ef7eb2e8f9f7 287 .weak I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 288 .type I2C1_IRQHandler, %function
<> 144:ef7eb2e8f9f7 289 I2C1_IRQHandler:
<> 144:ef7eb2e8f9f7 290 ldr r0,=I2C1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 291 bx r0
<> 144:ef7eb2e8f9f7 292 .size I2C1_IRQHandler, . - I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 .align 1
<> 144:ef7eb2e8f9f7 295 .thumb_func
<> 144:ef7eb2e8f9f7 296 .weak SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 297 .type SPI0_IRQHandler, %function
<> 144:ef7eb2e8f9f7 298 SPI0_IRQHandler:
<> 144:ef7eb2e8f9f7 299 ldr r0,=SPI0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 300 bx r0
<> 144:ef7eb2e8f9f7 301 .size SPI0_IRQHandler, . - SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 .align 1
<> 144:ef7eb2e8f9f7 304 .thumb_func
<> 144:ef7eb2e8f9f7 305 .weak SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 306 .type SPI1_IRQHandler, %function
<> 144:ef7eb2e8f9f7 307 SPI1_IRQHandler:
<> 144:ef7eb2e8f9f7 308 ldr r0,=SPI1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 309 bx r0
<> 144:ef7eb2e8f9f7 310 .size SPI1_IRQHandler, . - SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 .align 1
<> 144:ef7eb2e8f9f7 313 .thumb_func
<> 144:ef7eb2e8f9f7 314 .weak LPUART0_IRQHandler
<> 144:ef7eb2e8f9f7 315 .type LPUART0_IRQHandler, %function
<> 144:ef7eb2e8f9f7 316 LPUART0_IRQHandler:
<> 144:ef7eb2e8f9f7 317 ldr r0,=LPUART0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 318 bx r0
<> 144:ef7eb2e8f9f7 319 .size LPUART0_IRQHandler, . - LPUART0_IRQHandler
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 .align 1
<> 144:ef7eb2e8f9f7 322 .thumb_func
<> 144:ef7eb2e8f9f7 323 .weak LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 324 .type LPUART1_IRQHandler, %function
<> 144:ef7eb2e8f9f7 325 LPUART1_IRQHandler:
<> 144:ef7eb2e8f9f7 326 ldr r0,=LPUART1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 327 bx r0
<> 144:ef7eb2e8f9f7 328 .size LPUART1_IRQHandler, . - LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 .align 1
<> 144:ef7eb2e8f9f7 331 .thumb_func
<> 144:ef7eb2e8f9f7 332 .weak UART2_FLEXIO_IRQHandler
<> 144:ef7eb2e8f9f7 333 .type UART2_FLEXIO_IRQHandler, %function
<> 144:ef7eb2e8f9f7 334 UART2_FLEXIO_IRQHandler:
<> 144:ef7eb2e8f9f7 335 ldr r0,=UART2_FLEXIO_DriverIRQHandler
<> 144:ef7eb2e8f9f7 336 bx r0
<> 144:ef7eb2e8f9f7 337 .size UART2_FLEXIO_IRQHandler, . - UART2_FLEXIO_IRQHandler
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 .align 1
<> 144:ef7eb2e8f9f7 340 .thumb_func
<> 144:ef7eb2e8f9f7 341 .weak I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 342 .type I2S0_IRQHandler, %function
<> 144:ef7eb2e8f9f7 343 I2S0_IRQHandler:
<> 144:ef7eb2e8f9f7 344 ldr r0,=I2S0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 345 bx r0
<> 144:ef7eb2e8f9f7 346 .size I2S0_IRQHandler, . - I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 350 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 351 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 352 .macro def_irq_handler handler_name
<> 144:ef7eb2e8f9f7 353 .weak \handler_name
<> 144:ef7eb2e8f9f7 354 .set \handler_name, DefaultISR
<> 144:ef7eb2e8f9f7 355 .endm
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Exception Handlers */
<> 144:ef7eb2e8f9f7 358 def_irq_handler DMA0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 359 def_irq_handler DMA1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 360 def_irq_handler DMA2_DriverIRQHandler
<> 144:ef7eb2e8f9f7 361 def_irq_handler DMA3_DriverIRQHandler
<> 144:ef7eb2e8f9f7 362 def_irq_handler Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 363 def_irq_handler FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 364 def_irq_handler PMC_IRQHandler
<> 144:ef7eb2e8f9f7 365 def_irq_handler LLWU_IRQHandler
<> 144:ef7eb2e8f9f7 366 def_irq_handler I2C0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 367 def_irq_handler I2C1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 368 def_irq_handler SPI0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 369 def_irq_handler SPI1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 370 def_irq_handler LPUART0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 371 def_irq_handler LPUART1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 372 def_irq_handler UART2_FLEXIO_DriverIRQHandler
<> 144:ef7eb2e8f9f7 373 def_irq_handler ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 374 def_irq_handler CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 375 def_irq_handler TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 376 def_irq_handler TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 377 def_irq_handler TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 378 def_irq_handler RTC_IRQHandler
<> 144:ef7eb2e8f9f7 379 def_irq_handler RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 380 def_irq_handler PIT_IRQHandler
<> 144:ef7eb2e8f9f7 381 def_irq_handler I2S0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 382 def_irq_handler USB0_IRQHandler
<> 144:ef7eb2e8f9f7 383 def_irq_handler DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 384 def_irq_handler Reserved42_IRQHandler
<> 144:ef7eb2e8f9f7 385 def_irq_handler Reserved43_IRQHandler
<> 144:ef7eb2e8f9f7 386 def_irq_handler LPTMR0_IRQHandler
<> 144:ef7eb2e8f9f7 387 def_irq_handler LCD_IRQHandler
<> 144:ef7eb2e8f9f7 388 def_irq_handler PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 389 def_irq_handler PORTC_PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 .end