Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ; * ---------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2 ; * @file: startup_MKL43Z4.s
<> 144:ef7eb2e8f9f7 3 ; * @purpose: CMSIS Cortex-M0P Core Device Startup File
<> 144:ef7eb2e8f9f7 4 ; * MKL43Z4
<> 144:ef7eb2e8f9f7 5 ; * @version: 1.8
<> 144:ef7eb2e8f9f7 6 ; * @date: 2016-6-24
<> 144:ef7eb2e8f9f7 7 ; * @build: b160627
<> 144:ef7eb2e8f9f7 8 ; * ---------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9 ; *
<> 144:ef7eb2e8f9f7 10 ; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 11 ; * All rights reserved.
<> 144:ef7eb2e8f9f7 12 ; *
<> 144:ef7eb2e8f9f7 13 ; * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 ; * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 ; *
<> 144:ef7eb2e8f9f7 16 ; * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 17 ; * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 ; *
<> 144:ef7eb2e8f9f7 19 ; * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 20 ; * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 21 ; * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 22 ; *
<> 144:ef7eb2e8f9f7 23 ; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 24 ; * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 25 ; * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 ; *
<> 144:ef7eb2e8f9f7 27 ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 28 ; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 29 ; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 ; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 31 ; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 32 ; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 33 ; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 34 ; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 35 ; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 36 ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 ; *
<> 144:ef7eb2e8f9f7 38 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 39 ; *
<> 144:ef7eb2e8f9f7 40 ; *****************************************************************************/
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 __initial_sp EQU 0x20006000 ; Top of RAM
<> 144:ef7eb2e8f9f7 43 PRESERVE8
<> 144:ef7eb2e8f9f7 44 THUMB
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 50 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 51 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 52 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 55 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 56 DCD NMI_Handler ;NMI Handler
<> 144:ef7eb2e8f9f7 57 DCD HardFault_Handler ;Hard Fault Handler
<> 144:ef7eb2e8f9f7 58 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 59 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 60 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 61 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 62 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 63 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 64 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 65 DCD SVC_Handler ;SVCall Handler
<> 144:ef7eb2e8f9f7 66 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 67 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 68 DCD PendSV_Handler ;PendSV Handler
<> 144:ef7eb2e8f9f7 69 DCD SysTick_Handler ;SysTick Handler
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 ;External Interrupts
<> 144:ef7eb2e8f9f7 72 DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
<> 144:ef7eb2e8f9f7 73 DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
<> 144:ef7eb2e8f9f7 74 DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
<> 144:ef7eb2e8f9f7 75 DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
<> 144:ef7eb2e8f9f7 76 DCD Reserved20_IRQHandler ;Reserved interrupt
<> 144:ef7eb2e8f9f7 77 DCD FTFA_IRQHandler ;Command complete and read collision
<> 144:ef7eb2e8f9f7 78 DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
<> 144:ef7eb2e8f9f7 79 DCD LLWU_IRQHandler ;Low leakage wakeup
<> 144:ef7eb2e8f9f7 80 DCD I2C0_IRQHandler ;I2C0 interrupt
<> 144:ef7eb2e8f9f7 81 DCD I2C1_IRQHandler ;I2C1 interrupt
<> 144:ef7eb2e8f9f7 82 DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 83 DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 84 DCD LPUART0_IRQHandler ;LPUART0 status and error
<> 144:ef7eb2e8f9f7 85 DCD LPUART1_IRQHandler ;LPUART1 status and error
<> 144:ef7eb2e8f9f7 86 DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
<> 144:ef7eb2e8f9f7 87 DCD ADC0_IRQHandler ;ADC0 interrupt
<> 144:ef7eb2e8f9f7 88 DCD CMP0_IRQHandler ;CMP0 interrupt
<> 144:ef7eb2e8f9f7 89 DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 90 DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 91 DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 92 DCD RTC_IRQHandler ;RTC alarm
<> 144:ef7eb2e8f9f7 93 DCD RTC_Seconds_IRQHandler ;RTC seconds
<> 144:ef7eb2e8f9f7 94 DCD PIT_IRQHandler ;PIT interrupt
<> 144:ef7eb2e8f9f7 95 DCD I2S0_IRQHandler ;I2S0 interrupt
<> 144:ef7eb2e8f9f7 96 DCD USB0_IRQHandler ;USB0 interrupt
<> 144:ef7eb2e8f9f7 97 DCD DAC0_IRQHandler ;DAC0 interrupt
<> 144:ef7eb2e8f9f7 98 DCD Reserved42_IRQHandler ;Reserved interrupt
<> 144:ef7eb2e8f9f7 99 DCD Reserved43_IRQHandler ;Reserved interrupt
<> 144:ef7eb2e8f9f7 100 DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
<> 144:ef7eb2e8f9f7 101 DCD LCD_IRQHandler ;LCD interrupt
<> 144:ef7eb2e8f9f7 102 DCD PORTA_IRQHandler ;PORTA Pin detect
<> 144:ef7eb2e8f9f7 103 DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
<> 144:ef7eb2e8f9f7 104 __Vectors_End
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 ; <h> Flash Configuration
<> 144:ef7eb2e8f9f7 109 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
<> 144:ef7eb2e8f9f7 110 ; <i> and security information that allows the MCU to restrict access to the FTFL module.
<> 144:ef7eb2e8f9f7 111 ; <h> Backdoor Comparison Key
<> 144:ef7eb2e8f9f7 112 ; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 113 ; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 114 ; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 115 ; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 116 ; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 117 ; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 118 ; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 119 ; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 120 BackDoorK0 EQU 0xFF
<> 144:ef7eb2e8f9f7 121 BackDoorK1 EQU 0xFF
<> 144:ef7eb2e8f9f7 122 BackDoorK2 EQU 0xFF
<> 144:ef7eb2e8f9f7 123 BackDoorK3 EQU 0xFF
<> 144:ef7eb2e8f9f7 124 BackDoorK4 EQU 0xFF
<> 144:ef7eb2e8f9f7 125 BackDoorK5 EQU 0xFF
<> 144:ef7eb2e8f9f7 126 BackDoorK6 EQU 0xFF
<> 144:ef7eb2e8f9f7 127 BackDoorK7 EQU 0xFF
<> 144:ef7eb2e8f9f7 128 ; </h>
<> 144:ef7eb2e8f9f7 129 ; <h> Program flash protection bytes (FPROT)
<> 144:ef7eb2e8f9f7 130 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
<> 144:ef7eb2e8f9f7 131 ; <i> Each bit protects a 1/32 region of the program flash memory.
<> 144:ef7eb2e8f9f7 132 ; <h> FPROT0
<> 144:ef7eb2e8f9f7 133 ; <i> Program Flash Region Protect Register 0
<> 144:ef7eb2e8f9f7 134 ; <i> 1/32 - 8/32 region
<> 144:ef7eb2e8f9f7 135 ; <o.0> FPROT0.0
<> 144:ef7eb2e8f9f7 136 ; <o.1> FPROT0.1
<> 144:ef7eb2e8f9f7 137 ; <o.2> FPROT0.2
<> 144:ef7eb2e8f9f7 138 ; <o.3> FPROT0.3
<> 144:ef7eb2e8f9f7 139 ; <o.4> FPROT0.4
<> 144:ef7eb2e8f9f7 140 ; <o.5> FPROT0.5
<> 144:ef7eb2e8f9f7 141 ; <o.6> FPROT0.6
<> 144:ef7eb2e8f9f7 142 ; <o.7> FPROT0.7
<> 144:ef7eb2e8f9f7 143 nFPROT0 EQU 0x00
<> 144:ef7eb2e8f9f7 144 FPROT0 EQU nFPROT0:EOR:0xFF
<> 144:ef7eb2e8f9f7 145 ; </h>
<> 144:ef7eb2e8f9f7 146 ; <h> FPROT1
<> 144:ef7eb2e8f9f7 147 ; <i> Program Flash Region Protect Register 1
<> 144:ef7eb2e8f9f7 148 ; <i> 9/32 - 16/32 region
<> 144:ef7eb2e8f9f7 149 ; <o.0> FPROT1.0
<> 144:ef7eb2e8f9f7 150 ; <o.1> FPROT1.1
<> 144:ef7eb2e8f9f7 151 ; <o.2> FPROT1.2
<> 144:ef7eb2e8f9f7 152 ; <o.3> FPROT1.3
<> 144:ef7eb2e8f9f7 153 ; <o.4> FPROT1.4
<> 144:ef7eb2e8f9f7 154 ; <o.5> FPROT1.5
<> 144:ef7eb2e8f9f7 155 ; <o.6> FPROT1.6
<> 144:ef7eb2e8f9f7 156 ; <o.7> FPROT1.7
<> 144:ef7eb2e8f9f7 157 nFPROT1 EQU 0x00
<> 144:ef7eb2e8f9f7 158 FPROT1 EQU nFPROT1:EOR:0xFF
<> 144:ef7eb2e8f9f7 159 ; </h>
<> 144:ef7eb2e8f9f7 160 ; <h> FPROT2
<> 144:ef7eb2e8f9f7 161 ; <i> Program Flash Region Protect Register 2
<> 144:ef7eb2e8f9f7 162 ; <i> 17/32 - 24/32 region
<> 144:ef7eb2e8f9f7 163 ; <o.0> FPROT2.0
<> 144:ef7eb2e8f9f7 164 ; <o.1> FPROT2.1
<> 144:ef7eb2e8f9f7 165 ; <o.2> FPROT2.2
<> 144:ef7eb2e8f9f7 166 ; <o.3> FPROT2.3
<> 144:ef7eb2e8f9f7 167 ; <o.4> FPROT2.4
<> 144:ef7eb2e8f9f7 168 ; <o.5> FPROT2.5
<> 144:ef7eb2e8f9f7 169 ; <o.6> FPROT2.6
<> 144:ef7eb2e8f9f7 170 ; <o.7> FPROT2.7
<> 144:ef7eb2e8f9f7 171 nFPROT2 EQU 0x00
<> 144:ef7eb2e8f9f7 172 FPROT2 EQU nFPROT2:EOR:0xFF
<> 144:ef7eb2e8f9f7 173 ; </h>
<> 144:ef7eb2e8f9f7 174 ; <h> FPROT3
<> 144:ef7eb2e8f9f7 175 ; <i> Program Flash Region Protect Register 3
<> 144:ef7eb2e8f9f7 176 ; <i> 25/32 - 32/32 region
<> 144:ef7eb2e8f9f7 177 ; <o.0> FPROT3.0
<> 144:ef7eb2e8f9f7 178 ; <o.1> FPROT3.1
<> 144:ef7eb2e8f9f7 179 ; <o.2> FPROT3.2
<> 144:ef7eb2e8f9f7 180 ; <o.3> FPROT3.3
<> 144:ef7eb2e8f9f7 181 ; <o.4> FPROT3.4
<> 144:ef7eb2e8f9f7 182 ; <o.5> FPROT3.5
<> 144:ef7eb2e8f9f7 183 ; <o.6> FPROT3.6
<> 144:ef7eb2e8f9f7 184 ; <o.7> FPROT3.7
<> 144:ef7eb2e8f9f7 185 nFPROT3 EQU 0x00
<> 144:ef7eb2e8f9f7 186 FPROT3 EQU nFPROT3:EOR:0xFF
<> 144:ef7eb2e8f9f7 187 ; </h>
<> 144:ef7eb2e8f9f7 188 ; </h>
<> 144:ef7eb2e8f9f7 189 ; <h> Flash nonvolatile option byte (FOPT)
<> 144:ef7eb2e8f9f7 190 ; <i> Allows the user to customize the operation of the MCU at boot time.
<> 144:ef7eb2e8f9f7 191 ; <o.0> LPBOOT0
<> 144:ef7eb2e8f9f7 192 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
<> 144:ef7eb2e8f9f7 193 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
<> 144:ef7eb2e8f9f7 194 ; <o.1> BOOTPIN_OPT
<> 144:ef7eb2e8f9f7 195 ; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
<> 144:ef7eb2e8f9f7 196 ; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
<> 144:ef7eb2e8f9f7 197 ; <o.2> NMI_DIS
<> 144:ef7eb2e8f9f7 198 ; <0=> NMI interrupts are always blocked
<> 144:ef7eb2e8f9f7 199 ; <1=> NMI_b pin/interrupts reset default to enabled
<> 144:ef7eb2e8f9f7 200 ; <o.3> RESET_PIN_CFG
<> 144:ef7eb2e8f9f7 201 ; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
<> 144:ef7eb2e8f9f7 202 ; <1=> RESET_b pin is dedicated
<> 144:ef7eb2e8f9f7 203 ; <o.4> LPBOOT1
<> 144:ef7eb2e8f9f7 204 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
<> 144:ef7eb2e8f9f7 205 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
<> 144:ef7eb2e8f9f7 206 ; <o.5> FAST_INIT
<> 144:ef7eb2e8f9f7 207 ; <0=> Slower initialization
<> 144:ef7eb2e8f9f7 208 ; <1=> Fast Initialization
<> 144:ef7eb2e8f9f7 209 ; <o.6..7> BOOTSRC_SEL
<> 144:ef7eb2e8f9f7 210 ; <0=> Boot from Flash
<> 144:ef7eb2e8f9f7 211 ; <2=> Boot from ROM
<> 144:ef7eb2e8f9f7 212 ; <3=> Boot from ROM
<> 144:ef7eb2e8f9f7 213 ; <i> Boot source selection
<> 144:ef7eb2e8f9f7 214 FOPT EQU 0x3F
<> 144:ef7eb2e8f9f7 215 ; </h>
<> 144:ef7eb2e8f9f7 216 ; <h> Flash security byte (FSEC)
<> 144:ef7eb2e8f9f7 217 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
<> 144:ef7eb2e8f9f7 218 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
<> 144:ef7eb2e8f9f7 219 ; <o.0..1> SEC
<> 144:ef7eb2e8f9f7 220 ; <2=> MCU security status is unsecure
<> 144:ef7eb2e8f9f7 221 ; <3=> MCU security status is secure
<> 144:ef7eb2e8f9f7 222 ; <i> Flash Security
<> 144:ef7eb2e8f9f7 223 ; <o.2..3> FSLACC
<> 144:ef7eb2e8f9f7 224 ; <2=> Freescale factory access denied
<> 144:ef7eb2e8f9f7 225 ; <3=> Freescale factory access granted
<> 144:ef7eb2e8f9f7 226 ; <i> Freescale Failure Analysis Access Code
<> 144:ef7eb2e8f9f7 227 ; <o.4..5> MEEN
<> 144:ef7eb2e8f9f7 228 ; <2=> Mass erase is disabled
<> 144:ef7eb2e8f9f7 229 ; <3=> Mass erase is enabled
<> 144:ef7eb2e8f9f7 230 ; <o.6..7> KEYEN
<> 144:ef7eb2e8f9f7 231 ; <2=> Backdoor key access enabled
<> 144:ef7eb2e8f9f7 232 ; <3=> Backdoor key access disabled
<> 144:ef7eb2e8f9f7 233 ; <i> Backdoor Key Security Enable
<> 144:ef7eb2e8f9f7 234 FSEC EQU 0xFE
<> 144:ef7eb2e8f9f7 235 ; </h>
<> 144:ef7eb2e8f9f7 236 ; </h>
<> 144:ef7eb2e8f9f7 237 IF :LNOT::DEF:RAM_TARGET
<> 144:ef7eb2e8f9f7 238 AREA FlashConfig, DATA, READONLY
<> 144:ef7eb2e8f9f7 239 __FlashConfig
<> 144:ef7eb2e8f9f7 240 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
<> 144:ef7eb2e8f9f7 241 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
<> 144:ef7eb2e8f9f7 242 DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
<> 144:ef7eb2e8f9f7 243 DCB FSEC , FOPT , 0xFF , 0xFF
<> 144:ef7eb2e8f9f7 244 ENDIF
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 ; Reset Handler
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 252 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 253 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 254 IMPORT __main
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 IF :LNOT::DEF:RAM_TARGET
<> 144:ef7eb2e8f9f7 257 REQUIRE FlashConfig
<> 144:ef7eb2e8f9f7 258 ENDIF
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 CPSID I ; Mask interrupts
<> 144:ef7eb2e8f9f7 261 LDR R0, =0xE000ED08
<> 144:ef7eb2e8f9f7 262 LDR R1, =__Vectors
<> 144:ef7eb2e8f9f7 263 STR R1, [R0]
<> 144:ef7eb2e8f9f7 264 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 265 BLX R0
<> 144:ef7eb2e8f9f7 266 CPSIE i ; Unmask interrupts
<> 144:ef7eb2e8f9f7 267 LDR R0, =__main
<> 144:ef7eb2e8f9f7 268 BX R0
<> 144:ef7eb2e8f9f7 269 ENDP
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 273 NMI_Handler\
<> 144:ef7eb2e8f9f7 274 PROC
<> 144:ef7eb2e8f9f7 275 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 276 B .
<> 144:ef7eb2e8f9f7 277 ENDP
<> 144:ef7eb2e8f9f7 278 HardFault_Handler\
<> 144:ef7eb2e8f9f7 279 PROC
<> 144:ef7eb2e8f9f7 280 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 281 B .
<> 144:ef7eb2e8f9f7 282 ENDP
<> 144:ef7eb2e8f9f7 283 SVC_Handler\
<> 144:ef7eb2e8f9f7 284 PROC
<> 144:ef7eb2e8f9f7 285 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 286 B .
<> 144:ef7eb2e8f9f7 287 ENDP
<> 144:ef7eb2e8f9f7 288 PendSV_Handler\
<> 144:ef7eb2e8f9f7 289 PROC
<> 144:ef7eb2e8f9f7 290 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 291 B .
<> 144:ef7eb2e8f9f7 292 ENDP
<> 144:ef7eb2e8f9f7 293 SysTick_Handler\
<> 144:ef7eb2e8f9f7 294 PROC
<> 144:ef7eb2e8f9f7 295 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 296 B .
<> 144:ef7eb2e8f9f7 297 ENDP
<> 144:ef7eb2e8f9f7 298 DMA0_IRQHandler\
<> 144:ef7eb2e8f9f7 299 PROC
<> 144:ef7eb2e8f9f7 300 EXPORT DMA0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 301 LDR R0, =DMA0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 302 BX R0
<> 144:ef7eb2e8f9f7 303 ENDP
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 DMA1_IRQHandler\
<> 144:ef7eb2e8f9f7 306 PROC
<> 144:ef7eb2e8f9f7 307 EXPORT DMA1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 308 LDR R0, =DMA1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 309 BX R0
<> 144:ef7eb2e8f9f7 310 ENDP
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 DMA2_IRQHandler\
<> 144:ef7eb2e8f9f7 313 PROC
<> 144:ef7eb2e8f9f7 314 EXPORT DMA2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 315 LDR R0, =DMA2_DriverIRQHandler
<> 144:ef7eb2e8f9f7 316 BX R0
<> 144:ef7eb2e8f9f7 317 ENDP
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 DMA3_IRQHandler\
<> 144:ef7eb2e8f9f7 320 PROC
<> 144:ef7eb2e8f9f7 321 EXPORT DMA3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 322 LDR R0, =DMA3_DriverIRQHandler
<> 144:ef7eb2e8f9f7 323 BX R0
<> 144:ef7eb2e8f9f7 324 ENDP
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 I2C0_IRQHandler\
<> 144:ef7eb2e8f9f7 327 PROC
<> 144:ef7eb2e8f9f7 328 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 329 LDR R0, =I2C0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 330 BX R0
<> 144:ef7eb2e8f9f7 331 ENDP
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 I2C1_IRQHandler\
<> 144:ef7eb2e8f9f7 334 PROC
<> 144:ef7eb2e8f9f7 335 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 336 LDR R0, =I2C1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 337 BX R0
<> 144:ef7eb2e8f9f7 338 ENDP
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 SPI0_IRQHandler\
<> 144:ef7eb2e8f9f7 341 PROC
<> 144:ef7eb2e8f9f7 342 EXPORT SPI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 343 LDR R0, =SPI0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 344 BX R0
<> 144:ef7eb2e8f9f7 345 ENDP
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 SPI1_IRQHandler\
<> 144:ef7eb2e8f9f7 348 PROC
<> 144:ef7eb2e8f9f7 349 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 350 LDR R0, =SPI1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 351 BX R0
<> 144:ef7eb2e8f9f7 352 ENDP
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 LPUART0_IRQHandler\
<> 144:ef7eb2e8f9f7 355 PROC
<> 144:ef7eb2e8f9f7 356 EXPORT LPUART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 357 LDR R0, =LPUART0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 358 BX R0
<> 144:ef7eb2e8f9f7 359 ENDP
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 LPUART1_IRQHandler\
<> 144:ef7eb2e8f9f7 362 PROC
<> 144:ef7eb2e8f9f7 363 EXPORT LPUART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 364 LDR R0, =LPUART1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 365 BX R0
<> 144:ef7eb2e8f9f7 366 ENDP
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 UART2_FLEXIO_IRQHandler\
<> 144:ef7eb2e8f9f7 369 PROC
<> 144:ef7eb2e8f9f7 370 EXPORT UART2_FLEXIO_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 371 LDR R0, =UART2_FLEXIO_DriverIRQHandler
<> 144:ef7eb2e8f9f7 372 BX R0
<> 144:ef7eb2e8f9f7 373 ENDP
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 I2S0_IRQHandler\
<> 144:ef7eb2e8f9f7 376 PROC
<> 144:ef7eb2e8f9f7 377 EXPORT I2S0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 378 LDR R0, =I2S0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 379 BX R0
<> 144:ef7eb2e8f9f7 380 ENDP
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 Default_Handler\
<> 144:ef7eb2e8f9f7 383 PROC
<> 144:ef7eb2e8f9f7 384 EXPORT DMA0_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 385 EXPORT DMA1_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 386 EXPORT DMA2_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 387 EXPORT DMA3_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 388 EXPORT Reserved20_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 389 EXPORT FTFA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 390 EXPORT PMC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 391 EXPORT LLWU_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 392 EXPORT I2C0_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 393 EXPORT I2C1_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 394 EXPORT SPI0_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 395 EXPORT SPI1_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 396 EXPORT LPUART0_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 397 EXPORT LPUART1_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 398 EXPORT UART2_FLEXIO_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 399 EXPORT ADC0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 400 EXPORT CMP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 401 EXPORT TPM0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 402 EXPORT TPM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 403 EXPORT TPM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 404 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 405 EXPORT RTC_Seconds_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 406 EXPORT PIT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 407 EXPORT I2S0_DriverIRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 408 EXPORT USB0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 409 EXPORT DAC0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 410 EXPORT Reserved42_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 411 EXPORT Reserved43_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 412 EXPORT LPTMR0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 413 EXPORT LCD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 414 EXPORT PORTA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 415 EXPORT PORTC_PORTD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 416 EXPORT DefaultISR [WEAK]
<> 144:ef7eb2e8f9f7 417 DMA0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 418 DMA1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 419 DMA2_DriverIRQHandler
<> 144:ef7eb2e8f9f7 420 DMA3_DriverIRQHandler
<> 144:ef7eb2e8f9f7 421 Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 422 FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 423 PMC_IRQHandler
<> 144:ef7eb2e8f9f7 424 LLWU_IRQHandler
<> 144:ef7eb2e8f9f7 425 I2C0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 426 I2C1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 427 SPI0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 428 SPI1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 429 LPUART0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 430 LPUART1_DriverIRQHandler
<> 144:ef7eb2e8f9f7 431 UART2_FLEXIO_DriverIRQHandler
<> 144:ef7eb2e8f9f7 432 ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 433 CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 434 TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 435 TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 436 TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 437 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 438 RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 439 PIT_IRQHandler
<> 144:ef7eb2e8f9f7 440 I2S0_DriverIRQHandler
<> 144:ef7eb2e8f9f7 441 USB0_IRQHandler
<> 144:ef7eb2e8f9f7 442 DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 443 Reserved42_IRQHandler
<> 144:ef7eb2e8f9f7 444 Reserved43_IRQHandler
<> 144:ef7eb2e8f9f7 445 LPTMR0_IRQHandler
<> 144:ef7eb2e8f9f7 446 LCD_IRQHandler
<> 144:ef7eb2e8f9f7 447 PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 448 PORTC_PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 449 DefaultISR
<> 144:ef7eb2e8f9f7 450 LDR R0, =DefaultISR
<> 144:ef7eb2e8f9f7 451 BX R0
<> 144:ef7eb2e8f9f7 452 ENDP
<> 144:ef7eb2e8f9f7 453 ALIGN
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 END