Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KL43Z/MKL43Z4.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MKL43Z128VLH4
<> 144:ef7eb2e8f9f7 4 ** MKL43Z128VMP4
<> 144:ef7eb2e8f9f7 5 ** MKL43Z256VLH4
<> 144:ef7eb2e8f9f7 6 ** MKL43Z256VMP4
<> 144:ef7eb2e8f9f7 7 **
<> 144:ef7eb2e8f9f7 8 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 9 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 10 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 11 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 12 **
<> 144:ef7eb2e8f9f7 13 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
<> 144:ef7eb2e8f9f7 14 ** Version: rev. 1.6, 2015-07-29
<> 144:ef7eb2e8f9f7 15 ** Build: b151221
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Abstract:
<> 144:ef7eb2e8f9f7 18 ** CMSIS Peripheral Access Layer for MKL43Z4
<> 144:ef7eb2e8f9f7 19 **
<> 144:ef7eb2e8f9f7 20 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 21 ** All rights reserved.
<> 144:ef7eb2e8f9f7 22 **
<> 144:ef7eb2e8f9f7 23 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 24 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 27 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 28 **
<> 144:ef7eb2e8f9f7 29 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 30 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 31 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 32 **
<> 144:ef7eb2e8f9f7 33 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 34 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 35 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 36 **
<> 144:ef7eb2e8f9f7 37 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 38 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 39 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 40 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 41 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 42 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 43 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 44 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 45 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 46 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 47 **
<> 144:ef7eb2e8f9f7 48 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 49 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 50 **
<> 144:ef7eb2e8f9f7 51 ** Revisions:
<> 144:ef7eb2e8f9f7 52 ** - rev. 1.0 (2014-03-27)
<> 144:ef7eb2e8f9f7 53 ** Initial version.
<> 144:ef7eb2e8f9f7 54 ** - rev. 1.1 (2014-05-26)
<> 144:ef7eb2e8f9f7 55 ** I2S registers TCR2/RCR2 and others were changed.
<> 144:ef7eb2e8f9f7 56 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
<> 144:ef7eb2e8f9f7 57 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
<> 144:ef7eb2e8f9f7 58 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
<> 144:ef7eb2e8f9f7 59 ** Clock configuration for high range external oscillator has been added.
<> 144:ef7eb2e8f9f7 60 ** RFSYS module access has been added.
<> 144:ef7eb2e8f9f7 61 ** - rev. 1.2 (2014-07-10)
<> 144:ef7eb2e8f9f7 62 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
<> 144:ef7eb2e8f9f7 63 ** UART0 - UART0 module renamed to UART2.
<> 144:ef7eb2e8f9f7 64 ** I2S - removed MDR register.
<> 144:ef7eb2e8f9f7 65 ** - rev. 1.3 (2014-08-21)
<> 144:ef7eb2e8f9f7 66 ** UART2 - Removed ED register.
<> 144:ef7eb2e8f9f7 67 ** UART2 - Removed MODEM register.
<> 144:ef7eb2e8f9f7 68 ** UART2 - Removed IR register.
<> 144:ef7eb2e8f9f7 69 ** UART2 - Removed PFIFO register.
<> 144:ef7eb2e8f9f7 70 ** UART2 - Removed CFIFO register.
<> 144:ef7eb2e8f9f7 71 ** UART2 - Removed SFIFO register.
<> 144:ef7eb2e8f9f7 72 ** UART2 - Removed TWFIFO register.
<> 144:ef7eb2e8f9f7 73 ** UART2 - Removed TCFIFO register.
<> 144:ef7eb2e8f9f7 74 ** UART2 - Removed RWFIFO register.
<> 144:ef7eb2e8f9f7 75 ** UART2 - Removed RCFIFO register.
<> 144:ef7eb2e8f9f7 76 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
<> 144:ef7eb2e8f9f7 77 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
<> 144:ef7eb2e8f9f7 78 ** SIM - Removed bitfield DIEID in SDID register.
<> 144:ef7eb2e8f9f7 79 ** - rev. 1.4 (2014-09-01)
<> 144:ef7eb2e8f9f7 80 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
<> 144:ef7eb2e8f9f7 81 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
<> 144:ef7eb2e8f9f7 82 ** - rev. 1.5 (2014-09-05)
<> 144:ef7eb2e8f9f7 83 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
<> 144:ef7eb2e8f9f7 84 ** - rev. 1.6 (2015-07-29)
<> 144:ef7eb2e8f9f7 85 ** Correction of backward compatibility.
<> 144:ef7eb2e8f9f7 86 **
<> 144:ef7eb2e8f9f7 87 ** ###################################################################
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /*!
<> 144:ef7eb2e8f9f7 91 * @file MKL43Z4.h
<> 144:ef7eb2e8f9f7 92 * @version 1.6
<> 144:ef7eb2e8f9f7 93 * @date 2015-07-29
<> 144:ef7eb2e8f9f7 94 * @brief CMSIS Peripheral Access Layer for MKL43Z4
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 * CMSIS Peripheral Access Layer for MKL43Z4
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #ifndef _MKL43Z4_H_
<> 144:ef7eb2e8f9f7 100 #define _MKL43Z4_H_ /**< Symbol preventing repeated inclusion */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** Memory map major version (memory maps with equal major version number are
<> 144:ef7eb2e8f9f7 103 * compatible) */
<> 144:ef7eb2e8f9f7 104 #define MCU_MEM_MAP_VERSION 0x0100U
<> 144:ef7eb2e8f9f7 105 /** Memory map minor version */
<> 144:ef7eb2e8f9f7 106 #define MCU_MEM_MAP_VERSION_MINOR 0x0006U
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 110 -- Interrupt vector numbers
<> 144:ef7eb2e8f9f7 111 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /*!
<> 144:ef7eb2e8f9f7 114 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** Interrupt Number Definitions */
<> 144:ef7eb2e8f9f7 119 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 typedef enum IRQn {
<> 144:ef7eb2e8f9f7 122 /* Auxiliary constants */
<> 144:ef7eb2e8f9f7 123 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Core interrupts */
<> 144:ef7eb2e8f9f7 126 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 127 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 128 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 129 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 130 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Device specific interrupts */
<> 144:ef7eb2e8f9f7 133 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
<> 144:ef7eb2e8f9f7 134 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
<> 144:ef7eb2e8f9f7 135 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
<> 144:ef7eb2e8f9f7 136 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
<> 144:ef7eb2e8f9f7 137 Reserved20_IRQn = 4, /**< Reserved interrupt */
<> 144:ef7eb2e8f9f7 138 FTFA_IRQn = 5, /**< Command complete and read collision */
<> 144:ef7eb2e8f9f7 139 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
<> 144:ef7eb2e8f9f7 140 LLWU_IRQn = 7, /**< Low leakage wakeup */
<> 144:ef7eb2e8f9f7 141 I2C0_IRQn = 8, /**< I2C0 interrupt */
<> 144:ef7eb2e8f9f7 142 I2C1_IRQn = 9, /**< I2C1 interrupt */
<> 144:ef7eb2e8f9f7 143 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
<> 144:ef7eb2e8f9f7 144 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
<> 144:ef7eb2e8f9f7 145 LPUART0_IRQn = 12, /**< LPUART0 status and error */
<> 144:ef7eb2e8f9f7 146 LPUART1_IRQn = 13, /**< LPUART1 status and error */
<> 144:ef7eb2e8f9f7 147 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
<> 144:ef7eb2e8f9f7 148 ADC0_IRQn = 15, /**< ADC0 interrupt */
<> 144:ef7eb2e8f9f7 149 CMP0_IRQn = 16, /**< CMP0 interrupt */
<> 144:ef7eb2e8f9f7 150 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
<> 144:ef7eb2e8f9f7 151 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
<> 144:ef7eb2e8f9f7 152 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
<> 144:ef7eb2e8f9f7 153 RTC_IRQn = 20, /**< RTC alarm */
<> 144:ef7eb2e8f9f7 154 RTC_Seconds_IRQn = 21, /**< RTC seconds */
<> 144:ef7eb2e8f9f7 155 PIT_IRQn = 22, /**< PIT interrupt */
<> 144:ef7eb2e8f9f7 156 I2S0_IRQn = 23, /**< I2S0 interrupt */
<> 144:ef7eb2e8f9f7 157 USB0_IRQn = 24, /**< USB0 interrupt */
<> 144:ef7eb2e8f9f7 158 DAC0_IRQn = 25, /**< DAC0 interrupt */
<> 144:ef7eb2e8f9f7 159 Reserved42_IRQn = 26, /**< Reserved interrupt */
<> 144:ef7eb2e8f9f7 160 Reserved43_IRQn = 27, /**< Reserved interrupt */
<> 144:ef7eb2e8f9f7 161 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
<> 144:ef7eb2e8f9f7 162 LCD_IRQn = 29, /**< LCD interrupt */
<> 144:ef7eb2e8f9f7 163 PORTA_IRQn = 30, /**< PORTA Pin detect */
<> 144:ef7eb2e8f9f7 164 PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
<> 144:ef7eb2e8f9f7 165 } IRQn_Type;
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /*!
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */ /* end of group Interrupt_vector_numbers */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 173 -- Cortex M0 Core Configuration
<> 144:ef7eb2e8f9f7 174 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /*!
<> 144:ef7eb2e8f9f7 177 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
<> 144:ef7eb2e8f9f7 182 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
<> 144:ef7eb2e8f9f7 183 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
<> 144:ef7eb2e8f9f7 184 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
<> 144:ef7eb2e8f9f7 185 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
<> 144:ef7eb2e8f9f7 188 #include "system_MKL43Z4.h" /* Device specific configuration file */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /*!
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */ /* end of group Cortex_Core_Configuration */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 196 -- Mapping Information
<> 144:ef7eb2e8f9f7 197 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /*!
<> 144:ef7eb2e8f9f7 200 * @addtogroup Mapping_Information Mapping Information
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /** Mapping Information */
<> 144:ef7eb2e8f9f7 205 /*!
<> 144:ef7eb2e8f9f7 206 * @addtogroup edma_request
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /*******************************************************************************
<> 144:ef7eb2e8f9f7 211 * Definitions
<> 144:ef7eb2e8f9f7 212 ******************************************************************************/
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /*!
<> 144:ef7eb2e8f9f7 215 * @brief Structure for the DMA hardware request
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 * Defines the structure for the DMA hardware request collections. The user can configure the
<> 144:ef7eb2e8f9f7 218 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
<> 144:ef7eb2e8f9f7 219 * of the hardware request varies according to the to SoC.
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 typedef enum _dma_request_source
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 kDmaRequestMux0Disable = 0|0x100U, /**< Disable */
<> 144:ef7eb2e8f9f7 224 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
<> 144:ef7eb2e8f9f7 225 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
<> 144:ef7eb2e8f9f7 226 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
<> 144:ef7eb2e8f9f7 227 kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */
<> 144:ef7eb2e8f9f7 228 kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */
<> 144:ef7eb2e8f9f7 229 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
<> 144:ef7eb2e8f9f7 230 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
<> 144:ef7eb2e8f9f7 231 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
<> 144:ef7eb2e8f9f7 232 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
<> 144:ef7eb2e8f9f7 233 kDmaRequestMux0FlexIOChannel0 = 10|0x100U, /**< FlexIO Channel 0. */
<> 144:ef7eb2e8f9f7 234 kDmaRequestMux0FlexIOChannel1 = 11|0x100U, /**< FlexIO Channel 0. */
<> 144:ef7eb2e8f9f7 235 kDmaRequestMux0FlexIOChannel2 = 12|0x100U, /**< FlexIO Channel 0. */
<> 144:ef7eb2e8f9f7 236 kDmaRequestMux0FlexIOChannel3 = 13|0x100U, /**< FlexIO Channel 0. */
<> 144:ef7eb2e8f9f7 237 kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 Receive. */
<> 144:ef7eb2e8f9f7 238 kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 Transmit. */
<> 144:ef7eb2e8f9f7 239 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */
<> 144:ef7eb2e8f9f7 240 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */
<> 144:ef7eb2e8f9f7 241 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */
<> 144:ef7eb2e8f9f7 242 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */
<> 144:ef7eb2e8f9f7 243 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
<> 144:ef7eb2e8f9f7 244 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
<> 144:ef7eb2e8f9f7 245 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */
<> 144:ef7eb2e8f9f7 246 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */
<> 144:ef7eb2e8f9f7 247 kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 channel 0. */
<> 144:ef7eb2e8f9f7 248 kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 channel 1. */
<> 144:ef7eb2e8f9f7 249 kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 channel 2. */
<> 144:ef7eb2e8f9f7 250 kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 channel 3. */
<> 144:ef7eb2e8f9f7 251 kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 channel 4. */
<> 144:ef7eb2e8f9f7 252 kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 channel 5. */
<> 144:ef7eb2e8f9f7 253 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */
<> 144:ef7eb2e8f9f7 254 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */
<> 144:ef7eb2e8f9f7 255 kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 channel 0. */
<> 144:ef7eb2e8f9f7 256 kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 channel 1. */
<> 144:ef7eb2e8f9f7 257 kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 channel 0. */
<> 144:ef7eb2e8f9f7 258 kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 channel 1. */
<> 144:ef7eb2e8f9f7 259 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
<> 144:ef7eb2e8f9f7 260 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
<> 144:ef7eb2e8f9f7 261 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
<> 144:ef7eb2e8f9f7 262 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
<> 144:ef7eb2e8f9f7 263 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
<> 144:ef7eb2e8f9f7 264 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
<> 144:ef7eb2e8f9f7 265 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
<> 144:ef7eb2e8f9f7 266 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */
<> 144:ef7eb2e8f9f7 267 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
<> 144:ef7eb2e8f9f7 268 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
<> 144:ef7eb2e8f9f7 269 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
<> 144:ef7eb2e8f9f7 270 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
<> 144:ef7eb2e8f9f7 271 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */
<> 144:ef7eb2e8f9f7 272 kDmaRequestMux0PortA = 49|0x100U, /**< GPIO Port A. */
<> 144:ef7eb2e8f9f7 273 kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */
<> 144:ef7eb2e8f9f7 274 kDmaRequestMux0PortC = 51|0x100U, /**< GPIO Port C. */
<> 144:ef7eb2e8f9f7 275 kDmaRequestMux0PortD = 52|0x100U, /**< GPIO Port D. */
<> 144:ef7eb2e8f9f7 276 kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */
<> 144:ef7eb2e8f9f7 277 kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0 overflow. */
<> 144:ef7eb2e8f9f7 278 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1 overflow. */
<> 144:ef7eb2e8f9f7 279 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2 overflow. */
<> 144:ef7eb2e8f9f7 280 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
<> 144:ef7eb2e8f9f7 281 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
<> 144:ef7eb2e8f9f7 282 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
<> 144:ef7eb2e8f9f7 283 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled. */
<> 144:ef7eb2e8f9f7 284 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled. */
<> 144:ef7eb2e8f9f7 285 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled. */
<> 144:ef7eb2e8f9f7 286 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled. */
<> 144:ef7eb2e8f9f7 287 } dma_request_source_t;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* @} */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /*!
<> 144:ef7eb2e8f9f7 293 * @}
<> 144:ef7eb2e8f9f7 294 */ /* end of group Mapping_Information */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 298 -- Device Peripheral Access Layer
<> 144:ef7eb2e8f9f7 299 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /*!
<> 144:ef7eb2e8f9f7 302 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
<> 144:ef7eb2e8f9f7 303 * @{
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /*
<> 144:ef7eb2e8f9f7 308 ** Start of section using anonymous unions
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 #if defined(__ARMCC_VERSION)
<> 144:ef7eb2e8f9f7 312 #pragma push
<> 144:ef7eb2e8f9f7 313 #pragma anon_unions
<> 144:ef7eb2e8f9f7 314 #elif defined(__CWCC__)
<> 144:ef7eb2e8f9f7 315 #pragma push
<> 144:ef7eb2e8f9f7 316 #pragma cpp_extensions on
<> 144:ef7eb2e8f9f7 317 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 318 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 319 #elif defined(__IAR_SYSTEMS_ICC__)
<> 144:ef7eb2e8f9f7 320 #pragma language=extended
<> 144:ef7eb2e8f9f7 321 #else
<> 144:ef7eb2e8f9f7 322 #error Not supported compiler type
<> 144:ef7eb2e8f9f7 323 #endif
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 326 -- ADC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 327 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /*!
<> 144:ef7eb2e8f9f7 330 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /** ADC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 335 typedef struct {
<> 144:ef7eb2e8f9f7 336 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 337 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
<> 144:ef7eb2e8f9f7 338 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
<> 144:ef7eb2e8f9f7 339 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
<> 144:ef7eb2e8f9f7 340 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
<> 144:ef7eb2e8f9f7 341 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
<> 144:ef7eb2e8f9f7 342 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
<> 144:ef7eb2e8f9f7 343 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
<> 144:ef7eb2e8f9f7 344 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 345 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 346 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 347 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
<> 144:ef7eb2e8f9f7 348 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
<> 144:ef7eb2e8f9f7 349 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
<> 144:ef7eb2e8f9f7 350 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
<> 144:ef7eb2e8f9f7 353 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
<> 144:ef7eb2e8f9f7 354 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 355 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
<> 144:ef7eb2e8f9f7 356 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
<> 144:ef7eb2e8f9f7 357 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
<> 144:ef7eb2e8f9f7 358 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
<> 144:ef7eb2e8f9f7 359 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
<> 144:ef7eb2e8f9f7 362 } ADC_Type;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 365 -- ADC Register Masks
<> 144:ef7eb2e8f9f7 366 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /*!
<> 144:ef7eb2e8f9f7 369 * @addtogroup ADC_Register_Masks ADC Register Masks
<> 144:ef7eb2e8f9f7 370 * @{
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /*! @name SC1 - ADC Status and Control Registers 1 */
<> 144:ef7eb2e8f9f7 374 #define ADC_SC1_ADCH_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 375 #define ADC_SC1_ADCH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 376 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
<> 144:ef7eb2e8f9f7 377 #define ADC_SC1_DIFF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 378 #define ADC_SC1_DIFF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 379 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
<> 144:ef7eb2e8f9f7 380 #define ADC_SC1_AIEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 381 #define ADC_SC1_AIEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 382 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
<> 144:ef7eb2e8f9f7 383 #define ADC_SC1_COCO_MASK (0x80U)
<> 144:ef7eb2e8f9f7 384 #define ADC_SC1_COCO_SHIFT (7U)
<> 144:ef7eb2e8f9f7 385 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /* The count of ADC_SC1 */
<> 144:ef7eb2e8f9f7 388 #define ADC_SC1_COUNT (2U)
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /*! @name CFG1 - ADC Configuration Register 1 */
<> 144:ef7eb2e8f9f7 391 #define ADC_CFG1_ADICLK_MASK (0x3U)
<> 144:ef7eb2e8f9f7 392 #define ADC_CFG1_ADICLK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 393 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
<> 144:ef7eb2e8f9f7 394 #define ADC_CFG1_MODE_MASK (0xCU)
<> 144:ef7eb2e8f9f7 395 #define ADC_CFG1_MODE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 396 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
<> 144:ef7eb2e8f9f7 397 #define ADC_CFG1_ADLSMP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 398 #define ADC_CFG1_ADLSMP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 399 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
<> 144:ef7eb2e8f9f7 400 #define ADC_CFG1_ADIV_MASK (0x60U)
<> 144:ef7eb2e8f9f7 401 #define ADC_CFG1_ADIV_SHIFT (5U)
<> 144:ef7eb2e8f9f7 402 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
<> 144:ef7eb2e8f9f7 403 #define ADC_CFG1_ADLPC_MASK (0x80U)
<> 144:ef7eb2e8f9f7 404 #define ADC_CFG1_ADLPC_SHIFT (7U)
<> 144:ef7eb2e8f9f7 405 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*! @name CFG2 - ADC Configuration Register 2 */
<> 144:ef7eb2e8f9f7 408 #define ADC_CFG2_ADLSTS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 409 #define ADC_CFG2_ADLSTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 410 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
<> 144:ef7eb2e8f9f7 411 #define ADC_CFG2_ADHSC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 412 #define ADC_CFG2_ADHSC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 413 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
<> 144:ef7eb2e8f9f7 414 #define ADC_CFG2_ADACKEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 415 #define ADC_CFG2_ADACKEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 416 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
<> 144:ef7eb2e8f9f7 417 #define ADC_CFG2_MUXSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 418 #define ADC_CFG2_MUXSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 419 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /*! @name R - ADC Data Result Register */
<> 144:ef7eb2e8f9f7 422 #define ADC_R_D_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 423 #define ADC_R_D_SHIFT (0U)
<> 144:ef7eb2e8f9f7 424 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* The count of ADC_R */
<> 144:ef7eb2e8f9f7 427 #define ADC_R_COUNT (2U)
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /*! @name CV1 - Compare Value Registers */
<> 144:ef7eb2e8f9f7 430 #define ADC_CV1_CV_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 431 #define ADC_CV1_CV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 432 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /*! @name CV2 - Compare Value Registers */
<> 144:ef7eb2e8f9f7 435 #define ADC_CV2_CV_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 436 #define ADC_CV2_CV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 437 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /*! @name SC2 - Status and Control Register 2 */
<> 144:ef7eb2e8f9f7 440 #define ADC_SC2_REFSEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 441 #define ADC_SC2_REFSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 442 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
<> 144:ef7eb2e8f9f7 443 #define ADC_SC2_DMAEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 444 #define ADC_SC2_DMAEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 445 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 446 #define ADC_SC2_ACREN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 447 #define ADC_SC2_ACREN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 448 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
<> 144:ef7eb2e8f9f7 449 #define ADC_SC2_ACFGT_MASK (0x10U)
<> 144:ef7eb2e8f9f7 450 #define ADC_SC2_ACFGT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 451 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
<> 144:ef7eb2e8f9f7 452 #define ADC_SC2_ACFE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 453 #define ADC_SC2_ACFE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 454 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
<> 144:ef7eb2e8f9f7 455 #define ADC_SC2_ADTRG_MASK (0x40U)
<> 144:ef7eb2e8f9f7 456 #define ADC_SC2_ADTRG_SHIFT (6U)
<> 144:ef7eb2e8f9f7 457 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
<> 144:ef7eb2e8f9f7 458 #define ADC_SC2_ADACT_MASK (0x80U)
<> 144:ef7eb2e8f9f7 459 #define ADC_SC2_ADACT_SHIFT (7U)
<> 144:ef7eb2e8f9f7 460 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /*! @name SC3 - Status and Control Register 3 */
<> 144:ef7eb2e8f9f7 463 #define ADC_SC3_AVGS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 464 #define ADC_SC3_AVGS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 465 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
<> 144:ef7eb2e8f9f7 466 #define ADC_SC3_AVGE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 467 #define ADC_SC3_AVGE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 468 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
<> 144:ef7eb2e8f9f7 469 #define ADC_SC3_ADCO_MASK (0x8U)
<> 144:ef7eb2e8f9f7 470 #define ADC_SC3_ADCO_SHIFT (3U)
<> 144:ef7eb2e8f9f7 471 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
<> 144:ef7eb2e8f9f7 472 #define ADC_SC3_CALF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 473 #define ADC_SC3_CALF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 474 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
<> 144:ef7eb2e8f9f7 475 #define ADC_SC3_CAL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 476 #define ADC_SC3_CAL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 477 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /*! @name OFS - ADC Offset Correction Register */
<> 144:ef7eb2e8f9f7 480 #define ADC_OFS_OFS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 481 #define ADC_OFS_OFS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 482 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /*! @name PG - ADC Plus-Side Gain Register */
<> 144:ef7eb2e8f9f7 485 #define ADC_PG_PG_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 486 #define ADC_PG_PG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 487 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /*! @name MG - ADC Minus-Side Gain Register */
<> 144:ef7eb2e8f9f7 490 #define ADC_MG_MG_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 491 #define ADC_MG_MG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 492 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 495 #define ADC_CLPD_CLPD_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 496 #define ADC_CLPD_CLPD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 497 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 500 #define ADC_CLPS_CLPS_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 501 #define ADC_CLPS_CLPS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 502 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 505 #define ADC_CLP4_CLP4_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 506 #define ADC_CLP4_CLP4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 510 #define ADC_CLP3_CLP3_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 511 #define ADC_CLP3_CLP3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 512 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 515 #define ADC_CLP2_CLP2_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 516 #define ADC_CLP2_CLP2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 517 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 520 #define ADC_CLP1_CLP1_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 521 #define ADC_CLP1_CLP1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 522 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 525 #define ADC_CLP0_CLP0_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 526 #define ADC_CLP0_CLP0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 527 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 530 #define ADC_CLMD_CLMD_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 531 #define ADC_CLMD_CLMD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 532 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 535 #define ADC_CLMS_CLMS_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 536 #define ADC_CLMS_CLMS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 537 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 540 #define ADC_CLM4_CLM4_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 541 #define ADC_CLM4_CLM4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 542 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 545 #define ADC_CLM3_CLM3_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 546 #define ADC_CLM3_CLM3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 547 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 550 #define ADC_CLM2_CLM2_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 551 #define ADC_CLM2_CLM2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 552 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 555 #define ADC_CLM1_CLM1_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 556 #define ADC_CLM1_CLM1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 557 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 560 #define ADC_CLM0_CLM0_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 561 #define ADC_CLM0_CLM0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 562 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /*!
<> 144:ef7eb2e8f9f7 566 * @}
<> 144:ef7eb2e8f9f7 567 */ /* end of group ADC_Register_Masks */
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* ADC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 571 /** Peripheral ADC0 base address */
<> 144:ef7eb2e8f9f7 572 #define ADC0_BASE (0x4003B000u)
<> 144:ef7eb2e8f9f7 573 /** Peripheral ADC0 base pointer */
<> 144:ef7eb2e8f9f7 574 #define ADC0 ((ADC_Type *)ADC0_BASE)
<> 144:ef7eb2e8f9f7 575 /** Array initializer of ADC peripheral base addresses */
<> 144:ef7eb2e8f9f7 576 #define ADC_BASE_ADDRS { ADC0_BASE }
<> 144:ef7eb2e8f9f7 577 /** Array initializer of ADC peripheral base pointers */
<> 144:ef7eb2e8f9f7 578 #define ADC_BASE_PTRS { ADC0 }
<> 144:ef7eb2e8f9f7 579 /** Interrupt vectors for the ADC peripheral type */
<> 144:ef7eb2e8f9f7 580 #define ADC_IRQS { ADC0_IRQn }
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /*!
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */ /* end of group ADC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 588 -- CMP Peripheral Access Layer
<> 144:ef7eb2e8f9f7 589 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /*!
<> 144:ef7eb2e8f9f7 592 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
<> 144:ef7eb2e8f9f7 593 * @{
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /** CMP - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 597 typedef struct {
<> 144:ef7eb2e8f9f7 598 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
<> 144:ef7eb2e8f9f7 599 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
<> 144:ef7eb2e8f9f7 600 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 601 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 602 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 603 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 604 } CMP_Type;
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 607 -- CMP Register Masks
<> 144:ef7eb2e8f9f7 608 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /*!
<> 144:ef7eb2e8f9f7 611 * @addtogroup CMP_Register_Masks CMP Register Masks
<> 144:ef7eb2e8f9f7 612 * @{
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /*! @name CR0 - CMP Control Register 0 */
<> 144:ef7eb2e8f9f7 616 #define CMP_CR0_HYSTCTR_MASK (0x3U)
<> 144:ef7eb2e8f9f7 617 #define CMP_CR0_HYSTCTR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 618 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
<> 144:ef7eb2e8f9f7 619 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
<> 144:ef7eb2e8f9f7 620 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 621 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /*! @name CR1 - CMP Control Register 1 */
<> 144:ef7eb2e8f9f7 624 #define CMP_CR1_EN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 625 #define CMP_CR1_EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 626 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
<> 144:ef7eb2e8f9f7 627 #define CMP_CR1_OPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 628 #define CMP_CR1_OPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 629 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
<> 144:ef7eb2e8f9f7 630 #define CMP_CR1_COS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 631 #define CMP_CR1_COS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 632 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
<> 144:ef7eb2e8f9f7 633 #define CMP_CR1_INV_MASK (0x8U)
<> 144:ef7eb2e8f9f7 634 #define CMP_CR1_INV_SHIFT (3U)
<> 144:ef7eb2e8f9f7 635 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
<> 144:ef7eb2e8f9f7 636 #define CMP_CR1_PMODE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 637 #define CMP_CR1_PMODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 638 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
<> 144:ef7eb2e8f9f7 639 #define CMP_CR1_TRIGM_MASK (0x20U)
<> 144:ef7eb2e8f9f7 640 #define CMP_CR1_TRIGM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 641 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
<> 144:ef7eb2e8f9f7 642 #define CMP_CR1_WE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 643 #define CMP_CR1_WE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 644 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
<> 144:ef7eb2e8f9f7 645 #define CMP_CR1_SE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 646 #define CMP_CR1_SE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 647 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /*! @name FPR - CMP Filter Period Register */
<> 144:ef7eb2e8f9f7 650 #define CMP_FPR_FILT_PER_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 651 #define CMP_FPR_FILT_PER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 652 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /*! @name SCR - CMP Status and Control Register */
<> 144:ef7eb2e8f9f7 655 #define CMP_SCR_COUT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 656 #define CMP_SCR_COUT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 657 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
<> 144:ef7eb2e8f9f7 658 #define CMP_SCR_CFF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 659 #define CMP_SCR_CFF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 660 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
<> 144:ef7eb2e8f9f7 661 #define CMP_SCR_CFR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 662 #define CMP_SCR_CFR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 663 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
<> 144:ef7eb2e8f9f7 664 #define CMP_SCR_IEF_MASK (0x8U)
<> 144:ef7eb2e8f9f7 665 #define CMP_SCR_IEF_SHIFT (3U)
<> 144:ef7eb2e8f9f7 666 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
<> 144:ef7eb2e8f9f7 667 #define CMP_SCR_IER_MASK (0x10U)
<> 144:ef7eb2e8f9f7 668 #define CMP_SCR_IER_SHIFT (4U)
<> 144:ef7eb2e8f9f7 669 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
<> 144:ef7eb2e8f9f7 670 #define CMP_SCR_DMAEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 671 #define CMP_SCR_DMAEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 672 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /*! @name DACCR - DAC Control Register */
<> 144:ef7eb2e8f9f7 675 #define CMP_DACCR_VOSEL_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 676 #define CMP_DACCR_VOSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 677 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
<> 144:ef7eb2e8f9f7 678 #define CMP_DACCR_VRSEL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 679 #define CMP_DACCR_VRSEL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 680 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
<> 144:ef7eb2e8f9f7 681 #define CMP_DACCR_DACEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 682 #define CMP_DACCR_DACEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 683 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /*! @name MUXCR - MUX Control Register */
<> 144:ef7eb2e8f9f7 686 #define CMP_MUXCR_MSEL_MASK (0x7U)
<> 144:ef7eb2e8f9f7 687 #define CMP_MUXCR_MSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 688 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
<> 144:ef7eb2e8f9f7 689 #define CMP_MUXCR_PSEL_MASK (0x38U)
<> 144:ef7eb2e8f9f7 690 #define CMP_MUXCR_PSEL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 691 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
<> 144:ef7eb2e8f9f7 692 #define CMP_MUXCR_PSTM_MASK (0x80U)
<> 144:ef7eb2e8f9f7 693 #define CMP_MUXCR_PSTM_SHIFT (7U)
<> 144:ef7eb2e8f9f7 694 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /*!
<> 144:ef7eb2e8f9f7 698 * @}
<> 144:ef7eb2e8f9f7 699 */ /* end of group CMP_Register_Masks */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* CMP - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 703 /** Peripheral CMP0 base address */
<> 144:ef7eb2e8f9f7 704 #define CMP0_BASE (0x40073000u)
<> 144:ef7eb2e8f9f7 705 /** Peripheral CMP0 base pointer */
<> 144:ef7eb2e8f9f7 706 #define CMP0 ((CMP_Type *)CMP0_BASE)
<> 144:ef7eb2e8f9f7 707 /** Array initializer of CMP peripheral base addresses */
<> 144:ef7eb2e8f9f7 708 #define CMP_BASE_ADDRS { CMP0_BASE }
<> 144:ef7eb2e8f9f7 709 /** Array initializer of CMP peripheral base pointers */
<> 144:ef7eb2e8f9f7 710 #define CMP_BASE_PTRS { CMP0 }
<> 144:ef7eb2e8f9f7 711 /** Interrupt vectors for the CMP peripheral type */
<> 144:ef7eb2e8f9f7 712 #define CMP_IRQS { CMP0_IRQn }
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /*!
<> 144:ef7eb2e8f9f7 715 * @}
<> 144:ef7eb2e8f9f7 716 */ /* end of group CMP_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 720 -- DAC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 721 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /*!
<> 144:ef7eb2e8f9f7 724 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 725 * @{
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /** DAC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 729 typedef struct {
<> 144:ef7eb2e8f9f7 730 struct { /* offset: 0x0, array step: 0x2 */
<> 144:ef7eb2e8f9f7 731 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
<> 144:ef7eb2e8f9f7 732 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
<> 144:ef7eb2e8f9f7 733 } DAT[2];
<> 144:ef7eb2e8f9f7 734 uint8_t RESERVED_0[28];
<> 144:ef7eb2e8f9f7 735 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 736 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
<> 144:ef7eb2e8f9f7 737 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
<> 144:ef7eb2e8f9f7 738 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
<> 144:ef7eb2e8f9f7 739 } DAC_Type;
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 742 -- DAC Register Masks
<> 144:ef7eb2e8f9f7 743 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /*!
<> 144:ef7eb2e8f9f7 746 * @addtogroup DAC_Register_Masks DAC Register Masks
<> 144:ef7eb2e8f9f7 747 * @{
<> 144:ef7eb2e8f9f7 748 */
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /*! @name DATL - DAC Data Low Register */
<> 144:ef7eb2e8f9f7 751 #define DAC_DATL_DATA0_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 752 #define DAC_DATL_DATA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 753 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* The count of DAC_DATL */
<> 144:ef7eb2e8f9f7 756 #define DAC_DATL_COUNT (2U)
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /*! @name DATH - DAC Data High Register */
<> 144:ef7eb2e8f9f7 759 #define DAC_DATH_DATA1_MASK (0xFU)
<> 144:ef7eb2e8f9f7 760 #define DAC_DATH_DATA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 761 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* The count of DAC_DATH */
<> 144:ef7eb2e8f9f7 764 #define DAC_DATH_COUNT (2U)
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /*! @name SR - DAC Status Register */
<> 144:ef7eb2e8f9f7 767 #define DAC_SR_DACBFRPBF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 768 #define DAC_SR_DACBFRPBF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 769 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
<> 144:ef7eb2e8f9f7 770 #define DAC_SR_DACBFRPTF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 771 #define DAC_SR_DACBFRPTF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 772 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /*! @name C0 - DAC Control Register */
<> 144:ef7eb2e8f9f7 775 #define DAC_C0_DACBBIEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 776 #define DAC_C0_DACBBIEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 777 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
<> 144:ef7eb2e8f9f7 778 #define DAC_C0_DACBTIEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 779 #define DAC_C0_DACBTIEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 780 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
<> 144:ef7eb2e8f9f7 781 #define DAC_C0_LPEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 782 #define DAC_C0_LPEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 783 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
<> 144:ef7eb2e8f9f7 784 #define DAC_C0_DACSWTRG_MASK (0x10U)
<> 144:ef7eb2e8f9f7 785 #define DAC_C0_DACSWTRG_SHIFT (4U)
<> 144:ef7eb2e8f9f7 786 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
<> 144:ef7eb2e8f9f7 787 #define DAC_C0_DACTRGSEL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 788 #define DAC_C0_DACTRGSEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 789 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
<> 144:ef7eb2e8f9f7 790 #define DAC_C0_DACRFS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 791 #define DAC_C0_DACRFS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 792 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
<> 144:ef7eb2e8f9f7 793 #define DAC_C0_DACEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 794 #define DAC_C0_DACEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 795 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /*! @name C1 - DAC Control Register 1 */
<> 144:ef7eb2e8f9f7 798 #define DAC_C1_DACBFEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 799 #define DAC_C1_DACBFEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 800 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
<> 144:ef7eb2e8f9f7 801 #define DAC_C1_DACBFMD_MASK (0x6U)
<> 144:ef7eb2e8f9f7 802 #define DAC_C1_DACBFMD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 803 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
<> 144:ef7eb2e8f9f7 804 #define DAC_C1_DMAEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 805 #define DAC_C1_DMAEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 806 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /*! @name C2 - DAC Control Register 2 */
<> 144:ef7eb2e8f9f7 809 #define DAC_C2_DACBFUP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 810 #define DAC_C2_DACBFUP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 811 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
<> 144:ef7eb2e8f9f7 812 #define DAC_C2_DACBFRP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 813 #define DAC_C2_DACBFRP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 814 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /*!
<> 144:ef7eb2e8f9f7 818 * @}
<> 144:ef7eb2e8f9f7 819 */ /* end of group DAC_Register_Masks */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* DAC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 823 /** Peripheral DAC0 base address */
<> 144:ef7eb2e8f9f7 824 #define DAC0_BASE (0x4003F000u)
<> 144:ef7eb2e8f9f7 825 /** Peripheral DAC0 base pointer */
<> 144:ef7eb2e8f9f7 826 #define DAC0 ((DAC_Type *)DAC0_BASE)
<> 144:ef7eb2e8f9f7 827 /** Array initializer of DAC peripheral base addresses */
<> 144:ef7eb2e8f9f7 828 #define DAC_BASE_ADDRS { DAC0_BASE }
<> 144:ef7eb2e8f9f7 829 /** Array initializer of DAC peripheral base pointers */
<> 144:ef7eb2e8f9f7 830 #define DAC_BASE_PTRS { DAC0 }
<> 144:ef7eb2e8f9f7 831 /** Interrupt vectors for the DAC peripheral type */
<> 144:ef7eb2e8f9f7 832 #define DAC_IRQS { DAC0_IRQn }
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /*!
<> 144:ef7eb2e8f9f7 835 * @}
<> 144:ef7eb2e8f9f7 836 */ /* end of group DAC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 840 -- DMA Peripheral Access Layer
<> 144:ef7eb2e8f9f7 841 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /*!
<> 144:ef7eb2e8f9f7 844 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
<> 144:ef7eb2e8f9f7 845 * @{
<> 144:ef7eb2e8f9f7 846 */
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /** DMA - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 849 typedef struct {
<> 144:ef7eb2e8f9f7 850 uint8_t RESERVED_0[256];
<> 144:ef7eb2e8f9f7 851 struct { /* offset: 0x100, array step: 0x10 */
<> 144:ef7eb2e8f9f7 852 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
<> 144:ef7eb2e8f9f7 853 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
<> 144:ef7eb2e8f9f7 854 union { /* offset: 0x108, array step: 0x10 */
<> 144:ef7eb2e8f9f7 855 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
<> 144:ef7eb2e8f9f7 856 struct { /* offset: 0x108, array step: 0x10 */
<> 144:ef7eb2e8f9f7 857 uint8_t RESERVED_0[3];
<> 144:ef7eb2e8f9f7 858 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
<> 144:ef7eb2e8f9f7 859 } DMA_DSR_ACCESS8BIT;
<> 144:ef7eb2e8f9f7 860 };
<> 144:ef7eb2e8f9f7 861 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
<> 144:ef7eb2e8f9f7 862 } DMA[4];
<> 144:ef7eb2e8f9f7 863 } DMA_Type;
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 866 -- DMA Register Masks
<> 144:ef7eb2e8f9f7 867 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /*!
<> 144:ef7eb2e8f9f7 870 * @addtogroup DMA_Register_Masks DMA Register Masks
<> 144:ef7eb2e8f9f7 871 * @{
<> 144:ef7eb2e8f9f7 872 */
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /*! @name SAR - Source Address Register */
<> 144:ef7eb2e8f9f7 875 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 876 #define DMA_SAR_SAR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 877 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* The count of DMA_SAR */
<> 144:ef7eb2e8f9f7 880 #define DMA_SAR_COUNT (4U)
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /*! @name DAR - Destination Address Register */
<> 144:ef7eb2e8f9f7 883 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 884 #define DMA_DAR_DAR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 885 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* The count of DMA_DAR */
<> 144:ef7eb2e8f9f7 888 #define DMA_DAR_COUNT (4U)
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */
<> 144:ef7eb2e8f9f7 891 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
<> 144:ef7eb2e8f9f7 892 #define DMA_DSR_BCR_BCR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 893 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
<> 144:ef7eb2e8f9f7 894 #define DMA_DSR_BCR_DONE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 895 #define DMA_DSR_BCR_DONE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 896 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
<> 144:ef7eb2e8f9f7 897 #define DMA_DSR_BCR_BSY_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 898 #define DMA_DSR_BCR_BSY_SHIFT (25U)
<> 144:ef7eb2e8f9f7 899 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
<> 144:ef7eb2e8f9f7 900 #define DMA_DSR_BCR_REQ_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 901 #define DMA_DSR_BCR_REQ_SHIFT (26U)
<> 144:ef7eb2e8f9f7 902 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
<> 144:ef7eb2e8f9f7 903 #define DMA_DSR_BCR_BED_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 904 #define DMA_DSR_BCR_BED_SHIFT (28U)
<> 144:ef7eb2e8f9f7 905 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
<> 144:ef7eb2e8f9f7 906 #define DMA_DSR_BCR_BES_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 907 #define DMA_DSR_BCR_BES_SHIFT (29U)
<> 144:ef7eb2e8f9f7 908 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
<> 144:ef7eb2e8f9f7 909 #define DMA_DSR_BCR_CE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 910 #define DMA_DSR_BCR_CE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 911 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* The count of DMA_DSR_BCR */
<> 144:ef7eb2e8f9f7 914 #define DMA_DSR_BCR_COUNT (4U)
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* The count of DMA_DSR */
<> 144:ef7eb2e8f9f7 917 #define DMA_DSR_COUNT (4U)
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /*! @name DCR - DMA Control Register */
<> 144:ef7eb2e8f9f7 920 #define DMA_DCR_LCH2_MASK (0x3U)
<> 144:ef7eb2e8f9f7 921 #define DMA_DCR_LCH2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 922 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
<> 144:ef7eb2e8f9f7 923 #define DMA_DCR_LCH1_MASK (0xCU)
<> 144:ef7eb2e8f9f7 924 #define DMA_DCR_LCH1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 925 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
<> 144:ef7eb2e8f9f7 926 #define DMA_DCR_LINKCC_MASK (0x30U)
<> 144:ef7eb2e8f9f7 927 #define DMA_DCR_LINKCC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 928 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
<> 144:ef7eb2e8f9f7 929 #define DMA_DCR_D_REQ_MASK (0x80U)
<> 144:ef7eb2e8f9f7 930 #define DMA_DCR_D_REQ_SHIFT (7U)
<> 144:ef7eb2e8f9f7 931 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
<> 144:ef7eb2e8f9f7 932 #define DMA_DCR_DMOD_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 933 #define DMA_DCR_DMOD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 934 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
<> 144:ef7eb2e8f9f7 935 #define DMA_DCR_SMOD_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 936 #define DMA_DCR_SMOD_SHIFT (12U)
<> 144:ef7eb2e8f9f7 937 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
<> 144:ef7eb2e8f9f7 938 #define DMA_DCR_START_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 939 #define DMA_DCR_START_SHIFT (16U)
<> 144:ef7eb2e8f9f7 940 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
<> 144:ef7eb2e8f9f7 941 #define DMA_DCR_DSIZE_MASK (0x60000U)
<> 144:ef7eb2e8f9f7 942 #define DMA_DCR_DSIZE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 943 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
<> 144:ef7eb2e8f9f7 944 #define DMA_DCR_DINC_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 945 #define DMA_DCR_DINC_SHIFT (19U)
<> 144:ef7eb2e8f9f7 946 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
<> 144:ef7eb2e8f9f7 947 #define DMA_DCR_SSIZE_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 948 #define DMA_DCR_SSIZE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 949 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
<> 144:ef7eb2e8f9f7 950 #define DMA_DCR_SINC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 951 #define DMA_DCR_SINC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 952 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
<> 144:ef7eb2e8f9f7 953 #define DMA_DCR_EADREQ_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 954 #define DMA_DCR_EADREQ_SHIFT (23U)
<> 144:ef7eb2e8f9f7 955 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
<> 144:ef7eb2e8f9f7 956 #define DMA_DCR_AA_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 957 #define DMA_DCR_AA_SHIFT (28U)
<> 144:ef7eb2e8f9f7 958 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
<> 144:ef7eb2e8f9f7 959 #define DMA_DCR_CS_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 960 #define DMA_DCR_CS_SHIFT (29U)
<> 144:ef7eb2e8f9f7 961 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
<> 144:ef7eb2e8f9f7 962 #define DMA_DCR_ERQ_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 963 #define DMA_DCR_ERQ_SHIFT (30U)
<> 144:ef7eb2e8f9f7 964 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
<> 144:ef7eb2e8f9f7 965 #define DMA_DCR_EINT_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 966 #define DMA_DCR_EINT_SHIFT (31U)
<> 144:ef7eb2e8f9f7 967 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* The count of DMA_DCR */
<> 144:ef7eb2e8f9f7 970 #define DMA_DCR_COUNT (4U)
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /*!
<> 144:ef7eb2e8f9f7 974 * @}
<> 144:ef7eb2e8f9f7 975 */ /* end of group DMA_Register_Masks */
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 /* DMA - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 979 /** Peripheral DMA base address */
<> 144:ef7eb2e8f9f7 980 #define DMA_BASE (0x40008000u)
<> 144:ef7eb2e8f9f7 981 /** Peripheral DMA base pointer */
<> 144:ef7eb2e8f9f7 982 #define DMA0 ((DMA_Type *)DMA_BASE)
<> 144:ef7eb2e8f9f7 983 /** Array initializer of DMA peripheral base addresses */
<> 144:ef7eb2e8f9f7 984 #define DMA_BASE_ADDRS { DMA_BASE }
<> 144:ef7eb2e8f9f7 985 /** Array initializer of DMA peripheral base pointers */
<> 144:ef7eb2e8f9f7 986 #define DMA_BASE_PTRS { DMA0 }
<> 144:ef7eb2e8f9f7 987 /** Interrupt vectors for the DMA peripheral type */
<> 144:ef7eb2e8f9f7 988 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /*!
<> 144:ef7eb2e8f9f7 991 * @}
<> 144:ef7eb2e8f9f7 992 */ /* end of group DMA_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 996 -- DMAMUX Peripheral Access Layer
<> 144:ef7eb2e8f9f7 997 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /*!
<> 144:ef7eb2e8f9f7 1000 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1001 * @{
<> 144:ef7eb2e8f9f7 1002 */
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /** DMAMUX - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 1005 typedef struct {
<> 144:ef7eb2e8f9f7 1006 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
<> 144:ef7eb2e8f9f7 1007 } DMAMUX_Type;
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1010 -- DMAMUX Register Masks
<> 144:ef7eb2e8f9f7 1011 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /*!
<> 144:ef7eb2e8f9f7 1014 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
<> 144:ef7eb2e8f9f7 1015 * @{
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /*! @name CHCFG - Channel Configuration register */
<> 144:ef7eb2e8f9f7 1019 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 1020 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1021 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
<> 144:ef7eb2e8f9f7 1022 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1023 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1024 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
<> 144:ef7eb2e8f9f7 1025 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1026 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1027 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* The count of DMAMUX_CHCFG */
<> 144:ef7eb2e8f9f7 1030 #define DMAMUX_CHCFG_COUNT (4U)
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /*!
<> 144:ef7eb2e8f9f7 1034 * @}
<> 144:ef7eb2e8f9f7 1035 */ /* end of group DMAMUX_Register_Masks */
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* DMAMUX - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 1039 /** Peripheral DMAMUX0 base address */
<> 144:ef7eb2e8f9f7 1040 #define DMAMUX0_BASE (0x40021000u)
<> 144:ef7eb2e8f9f7 1041 /** Peripheral DMAMUX0 base pointer */
<> 144:ef7eb2e8f9f7 1042 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
<> 144:ef7eb2e8f9f7 1043 /** Array initializer of DMAMUX peripheral base addresses */
<> 144:ef7eb2e8f9f7 1044 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
<> 144:ef7eb2e8f9f7 1045 /** Array initializer of DMAMUX peripheral base pointers */
<> 144:ef7eb2e8f9f7 1046 #define DMAMUX_BASE_PTRS { DMAMUX0 }
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 /*!
<> 144:ef7eb2e8f9f7 1049 * @}
<> 144:ef7eb2e8f9f7 1050 */ /* end of group DMAMUX_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1054 -- FLEXIO Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1055 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /*!
<> 144:ef7eb2e8f9f7 1058 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1059 * @{
<> 144:ef7eb2e8f9f7 1060 */
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /** FLEXIO - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 1063 typedef struct {
<> 144:ef7eb2e8f9f7 1064 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 1065 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 1066 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 1067 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 1068 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 1069 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 1070 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 1071 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 1072 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
<> 144:ef7eb2e8f9f7 1073 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
<> 144:ef7eb2e8f9f7 1074 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 1075 uint8_t RESERVED_2[4];
<> 144:ef7eb2e8f9f7 1076 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
<> 144:ef7eb2e8f9f7 1077 uint8_t RESERVED_3[76];
<> 144:ef7eb2e8f9f7 1078 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1079 uint8_t RESERVED_4[112];
<> 144:ef7eb2e8f9f7 1080 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1081 uint8_t RESERVED_5[240];
<> 144:ef7eb2e8f9f7 1082 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1083 uint8_t RESERVED_6[112];
<> 144:ef7eb2e8f9f7 1084 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1085 uint8_t RESERVED_7[112];
<> 144:ef7eb2e8f9f7 1086 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1087 uint8_t RESERVED_8[112];
<> 144:ef7eb2e8f9f7 1088 __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1089 uint8_t RESERVED_9[112];
<> 144:ef7eb2e8f9f7 1090 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1091 uint8_t RESERVED_10[112];
<> 144:ef7eb2e8f9f7 1092 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1093 uint8_t RESERVED_11[112];
<> 144:ef7eb2e8f9f7 1094 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1095 } FLEXIO_Type;
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1098 -- FLEXIO Register Masks
<> 144:ef7eb2e8f9f7 1099 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /*!
<> 144:ef7eb2e8f9f7 1102 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
<> 144:ef7eb2e8f9f7 1103 * @{
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /*! @name VERID - Version ID Register */
<> 144:ef7eb2e8f9f7 1107 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 1108 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1109 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
<> 144:ef7eb2e8f9f7 1110 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 1111 #define FLEXIO_VERID_MINOR_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1112 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
<> 144:ef7eb2e8f9f7 1113 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 1114 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1115 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /*! @name PARAM - Parameter Register */
<> 144:ef7eb2e8f9f7 1118 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1119 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1120 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
<> 144:ef7eb2e8f9f7 1121 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 1122 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1123 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
<> 144:ef7eb2e8f9f7 1124 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 1125 #define FLEXIO_PARAM_PIN_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1126 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
<> 144:ef7eb2e8f9f7 1127 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 1128 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1129 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /*! @name CTRL - FlexIO Control Register */
<> 144:ef7eb2e8f9f7 1132 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1133 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1134 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
<> 144:ef7eb2e8f9f7 1135 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1136 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1137 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
<> 144:ef7eb2e8f9f7 1138 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1139 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1140 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
<> 144:ef7eb2e8f9f7 1141 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1142 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1143 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
<> 144:ef7eb2e8f9f7 1144 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 1145 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 1146 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /*! @name SHIFTSTAT - Shifter Status Register */
<> 144:ef7eb2e8f9f7 1149 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1150 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1151 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /*! @name SHIFTERR - Shifter Error Register */
<> 144:ef7eb2e8f9f7 1154 #define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1155 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1156 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /*! @name TIMSTAT - Timer Status Register */
<> 144:ef7eb2e8f9f7 1159 #define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1160 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1161 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
<> 144:ef7eb2e8f9f7 1164 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1165 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1166 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 1169 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1170 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1171 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /*! @name TIMIEN - Timer Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 1174 #define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1175 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1176 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
<> 144:ef7eb2e8f9f7 1179 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1180 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1181 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /*! @name SHIFTCTL - Shifter Control N Register */
<> 144:ef7eb2e8f9f7 1184 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
<> 144:ef7eb2e8f9f7 1185 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1186 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
<> 144:ef7eb2e8f9f7 1187 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1188 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1189 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
<> 144:ef7eb2e8f9f7 1190 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U)
<> 144:ef7eb2e8f9f7 1191 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1192 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
<> 144:ef7eb2e8f9f7 1193 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 1194 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1195 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
<> 144:ef7eb2e8f9f7 1196 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 1197 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
<> 144:ef7eb2e8f9f7 1198 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
<> 144:ef7eb2e8f9f7 1199 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 1200 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1201 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* The count of FLEXIO_SHIFTCTL */
<> 144:ef7eb2e8f9f7 1204 #define FLEXIO_SHIFTCTL_COUNT (4U)
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /*! @name SHIFTCFG - Shifter Configuration N Register */
<> 144:ef7eb2e8f9f7 1207 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
<> 144:ef7eb2e8f9f7 1208 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1209 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
<> 144:ef7eb2e8f9f7 1210 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
<> 144:ef7eb2e8f9f7 1211 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1212 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
<> 144:ef7eb2e8f9f7 1213 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1214 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1215 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 /* The count of FLEXIO_SHIFTCFG */
<> 144:ef7eb2e8f9f7 1218 #define FLEXIO_SHIFTCFG_COUNT (4U)
<> 144:ef7eb2e8f9f7 1219
<> 144:ef7eb2e8f9f7 1220 /*! @name SHIFTBUF - Shifter Buffer N Register */
<> 144:ef7eb2e8f9f7 1221 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1222 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1223 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* The count of FLEXIO_SHIFTBUF */
<> 144:ef7eb2e8f9f7 1226 #define FLEXIO_SHIFTBUF_COUNT (4U)
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
<> 144:ef7eb2e8f9f7 1229 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1230 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1231 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /* The count of FLEXIO_SHIFTBUFBIS */
<> 144:ef7eb2e8f9f7 1234 #define FLEXIO_SHIFTBUFBIS_COUNT (4U)
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
<> 144:ef7eb2e8f9f7 1237 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1238 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1239 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* The count of FLEXIO_SHIFTBUFBYS */
<> 144:ef7eb2e8f9f7 1242 #define FLEXIO_SHIFTBUFBYS_COUNT (4U)
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
<> 144:ef7eb2e8f9f7 1245 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1246 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1247 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* The count of FLEXIO_SHIFTBUFBBS */
<> 144:ef7eb2e8f9f7 1250 #define FLEXIO_SHIFTBUFBBS_COUNT (4U)
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /*! @name TIMCTL - Timer Control N Register */
<> 144:ef7eb2e8f9f7 1253 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
<> 144:ef7eb2e8f9f7 1254 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1255 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
<> 144:ef7eb2e8f9f7 1256 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1257 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1258 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
<> 144:ef7eb2e8f9f7 1259 #define FLEXIO_TIMCTL_PINSEL_MASK (0x700U)
<> 144:ef7eb2e8f9f7 1260 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1261 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
<> 144:ef7eb2e8f9f7 1262 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 1263 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1264 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
<> 144:ef7eb2e8f9f7 1265 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1266 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1267 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
<> 144:ef7eb2e8f9f7 1268 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 1269 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
<> 144:ef7eb2e8f9f7 1270 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
<> 144:ef7eb2e8f9f7 1271 #define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 1272 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1273 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* The count of FLEXIO_TIMCTL */
<> 144:ef7eb2e8f9f7 1276 #define FLEXIO_TIMCTL_COUNT (4U)
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /*! @name TIMCFG - Timer Configuration N Register */
<> 144:ef7eb2e8f9f7 1279 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1280 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1281 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
<> 144:ef7eb2e8f9f7 1282 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
<> 144:ef7eb2e8f9f7 1283 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1284 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
<> 144:ef7eb2e8f9f7 1285 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
<> 144:ef7eb2e8f9f7 1286 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1287 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
<> 144:ef7eb2e8f9f7 1288 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 1289 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1290 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
<> 144:ef7eb2e8f9f7 1291 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
<> 144:ef7eb2e8f9f7 1292 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1293 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
<> 144:ef7eb2e8f9f7 1294 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 1295 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1296 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
<> 144:ef7eb2e8f9f7 1297 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 1298 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1299 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /* The count of FLEXIO_TIMCFG */
<> 144:ef7eb2e8f9f7 1302 #define FLEXIO_TIMCFG_COUNT (4U)
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /*! @name TIMCMP - Timer Compare N Register */
<> 144:ef7eb2e8f9f7 1305 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 1306 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1307 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* The count of FLEXIO_TIMCMP */
<> 144:ef7eb2e8f9f7 1310 #define FLEXIO_TIMCMP_COUNT (4U)
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /*!
<> 144:ef7eb2e8f9f7 1314 * @}
<> 144:ef7eb2e8f9f7 1315 */ /* end of group FLEXIO_Register_Masks */
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /* FLEXIO - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 1319 /** Peripheral FLEXIO base address */
<> 144:ef7eb2e8f9f7 1320 #define FLEXIO_BASE (0x4005F000u)
<> 144:ef7eb2e8f9f7 1321 /** Peripheral FLEXIO base pointer */
<> 144:ef7eb2e8f9f7 1322 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
<> 144:ef7eb2e8f9f7 1323 /** Array initializer of FLEXIO peripheral base addresses */
<> 144:ef7eb2e8f9f7 1324 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
<> 144:ef7eb2e8f9f7 1325 /** Array initializer of FLEXIO peripheral base pointers */
<> 144:ef7eb2e8f9f7 1326 #define FLEXIO_BASE_PTRS { FLEXIO }
<> 144:ef7eb2e8f9f7 1327 /** Interrupt vectors for the FLEXIO peripheral type */
<> 144:ef7eb2e8f9f7 1328 #define FLEXIO_IRQS { UART2_FLEXIO_IRQn }
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /*!
<> 144:ef7eb2e8f9f7 1331 * @}
<> 144:ef7eb2e8f9f7 1332 */ /* end of group FLEXIO_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334
<> 144:ef7eb2e8f9f7 1335 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1336 -- FTFA Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1337 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /*!
<> 144:ef7eb2e8f9f7 1340 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1341 * @{
<> 144:ef7eb2e8f9f7 1342 */
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /** FTFA - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 1345 typedef struct {
<> 144:ef7eb2e8f9f7 1346 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 1347 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 1348 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 1349 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 1350 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
<> 144:ef7eb2e8f9f7 1351 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
<> 144:ef7eb2e8f9f7 1352 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
<> 144:ef7eb2e8f9f7 1353 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
<> 144:ef7eb2e8f9f7 1354 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
<> 144:ef7eb2e8f9f7 1355 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
<> 144:ef7eb2e8f9f7 1356 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
<> 144:ef7eb2e8f9f7 1357 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
<> 144:ef7eb2e8f9f7 1358 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
<> 144:ef7eb2e8f9f7 1359 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
<> 144:ef7eb2e8f9f7 1360 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
<> 144:ef7eb2e8f9f7 1361 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
<> 144:ef7eb2e8f9f7 1362 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
<> 144:ef7eb2e8f9f7 1363 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
<> 144:ef7eb2e8f9f7 1364 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
<> 144:ef7eb2e8f9f7 1365 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
<> 144:ef7eb2e8f9f7 1366 } FTFA_Type;
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1369 -- FTFA Register Masks
<> 144:ef7eb2e8f9f7 1370 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /*!
<> 144:ef7eb2e8f9f7 1373 * @addtogroup FTFA_Register_Masks FTFA Register Masks
<> 144:ef7eb2e8f9f7 1374 * @{
<> 144:ef7eb2e8f9f7 1375 */
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /*! @name FSTAT - Flash Status Register */
<> 144:ef7eb2e8f9f7 1378 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1379 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1380 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
<> 144:ef7eb2e8f9f7 1381 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1382 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1383 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
<> 144:ef7eb2e8f9f7 1384 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1385 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1386 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
<> 144:ef7eb2e8f9f7 1387 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1388 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1389 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
<> 144:ef7eb2e8f9f7 1390 #define FTFA_FSTAT_CCIF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1391 #define FTFA_FSTAT_CCIF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1392 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /*! @name FCNFG - Flash Configuration Register */
<> 144:ef7eb2e8f9f7 1395 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1396 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1397 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
<> 144:ef7eb2e8f9f7 1398 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1399 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1400 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
<> 144:ef7eb2e8f9f7 1401 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1402 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1403 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
<> 144:ef7eb2e8f9f7 1404 #define FTFA_FCNFG_CCIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1405 #define FTFA_FCNFG_CCIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1406 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /*! @name FSEC - Flash Security Register */
<> 144:ef7eb2e8f9f7 1409 #define FTFA_FSEC_SEC_MASK (0x3U)
<> 144:ef7eb2e8f9f7 1410 #define FTFA_FSEC_SEC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1411 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
<> 144:ef7eb2e8f9f7 1412 #define FTFA_FSEC_FSLACC_MASK (0xCU)
<> 144:ef7eb2e8f9f7 1413 #define FTFA_FSEC_FSLACC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1414 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
<> 144:ef7eb2e8f9f7 1415 #define FTFA_FSEC_MEEN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 1416 #define FTFA_FSEC_MEEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1417 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
<> 144:ef7eb2e8f9f7 1418 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 1419 #define FTFA_FSEC_KEYEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1420 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /*! @name FOPT - Flash Option Register */
<> 144:ef7eb2e8f9f7 1423 #define FTFA_FOPT_OPT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1424 #define FTFA_FOPT_OPT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1425 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /*! @name FCCOB3 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1428 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1429 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1430 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /*! @name FCCOB2 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1433 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1434 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1435 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /*! @name FCCOB1 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1438 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1439 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1440 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 /*! @name FCCOB0 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1443 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1444 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1445 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 /*! @name FCCOB7 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1448 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1449 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1450 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /*! @name FCCOB6 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1453 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1454 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1455 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /*! @name FCCOB5 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1458 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1459 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1460 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /*! @name FCCOB4 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1463 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1464 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1465 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /*! @name FCCOBB - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1468 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1469 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1470 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 /*! @name FCCOBA - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1473 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1474 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1475 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 /*! @name FCCOB9 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1478 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1479 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1480 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 /*! @name FCCOB8 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 1483 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1484 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1485 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /*! @name FPROT3 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 1488 #define FTFA_FPROT3_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1489 #define FTFA_FPROT3_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1490 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /*! @name FPROT2 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 1493 #define FTFA_FPROT2_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1494 #define FTFA_FPROT2_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1495 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /*! @name FPROT1 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 1498 #define FTFA_FPROT1_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1499 #define FTFA_FPROT1_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1500 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 /*! @name FPROT0 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 1503 #define FTFA_FPROT0_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1504 #define FTFA_FPROT0_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1505 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /*!
<> 144:ef7eb2e8f9f7 1509 * @}
<> 144:ef7eb2e8f9f7 1510 */ /* end of group FTFA_Register_Masks */
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /* FTFA - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 1514 /** Peripheral FTFA base address */
<> 144:ef7eb2e8f9f7 1515 #define FTFA_BASE (0x40020000u)
<> 144:ef7eb2e8f9f7 1516 /** Peripheral FTFA base pointer */
<> 144:ef7eb2e8f9f7 1517 #define FTFA ((FTFA_Type *)FTFA_BASE)
<> 144:ef7eb2e8f9f7 1518 /** Array initializer of FTFA peripheral base addresses */
<> 144:ef7eb2e8f9f7 1519 #define FTFA_BASE_ADDRS { FTFA_BASE }
<> 144:ef7eb2e8f9f7 1520 /** Array initializer of FTFA peripheral base pointers */
<> 144:ef7eb2e8f9f7 1521 #define FTFA_BASE_PTRS { FTFA }
<> 144:ef7eb2e8f9f7 1522 /** Interrupt vectors for the FTFA peripheral type */
<> 144:ef7eb2e8f9f7 1523 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /*!
<> 144:ef7eb2e8f9f7 1526 * @}
<> 144:ef7eb2e8f9f7 1527 */ /* end of group FTFA_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1531 -- GPIO Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1532 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 /*!
<> 144:ef7eb2e8f9f7 1535 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1536 * @{
<> 144:ef7eb2e8f9f7 1537 */
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 /** GPIO - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 1540 typedef struct {
<> 144:ef7eb2e8f9f7 1541 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 1542 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 1543 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 1544 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 1545 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 1546 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 1547 } GPIO_Type;
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1550 -- GPIO Register Masks
<> 144:ef7eb2e8f9f7 1551 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /*!
<> 144:ef7eb2e8f9f7 1554 * @addtogroup GPIO_Register_Masks GPIO Register Masks
<> 144:ef7eb2e8f9f7 1555 * @{
<> 144:ef7eb2e8f9f7 1556 */
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 /*! @name PDOR - Port Data Output Register */
<> 144:ef7eb2e8f9f7 1559 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1560 #define GPIO_PDOR_PDO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1561 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /*! @name PSOR - Port Set Output Register */
<> 144:ef7eb2e8f9f7 1564 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1565 #define GPIO_PSOR_PTSO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1566 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 /*! @name PCOR - Port Clear Output Register */
<> 144:ef7eb2e8f9f7 1569 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1570 #define GPIO_PCOR_PTCO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1571 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 /*! @name PTOR - Port Toggle Output Register */
<> 144:ef7eb2e8f9f7 1574 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1575 #define GPIO_PTOR_PTTO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1576 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /*! @name PDIR - Port Data Input Register */
<> 144:ef7eb2e8f9f7 1579 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1580 #define GPIO_PDIR_PDI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1581 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 /*! @name PDDR - Port Data Direction Register */
<> 144:ef7eb2e8f9f7 1584 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1585 #define GPIO_PDDR_PDD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1586 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /*!
<> 144:ef7eb2e8f9f7 1590 * @}
<> 144:ef7eb2e8f9f7 1591 */ /* end of group GPIO_Register_Masks */
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /* GPIO - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 1595 /** Peripheral GPIOA base address */
<> 144:ef7eb2e8f9f7 1596 #define GPIOA_BASE (0x400FF000u)
<> 144:ef7eb2e8f9f7 1597 /** Peripheral GPIOA base pointer */
<> 144:ef7eb2e8f9f7 1598 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
<> 144:ef7eb2e8f9f7 1599 /** Peripheral GPIOB base address */
<> 144:ef7eb2e8f9f7 1600 #define GPIOB_BASE (0x400FF040u)
<> 144:ef7eb2e8f9f7 1601 /** Peripheral GPIOB base pointer */
<> 144:ef7eb2e8f9f7 1602 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
<> 144:ef7eb2e8f9f7 1603 /** Peripheral GPIOC base address */
<> 144:ef7eb2e8f9f7 1604 #define GPIOC_BASE (0x400FF080u)
<> 144:ef7eb2e8f9f7 1605 /** Peripheral GPIOC base pointer */
<> 144:ef7eb2e8f9f7 1606 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
<> 144:ef7eb2e8f9f7 1607 /** Peripheral GPIOD base address */
<> 144:ef7eb2e8f9f7 1608 #define GPIOD_BASE (0x400FF0C0u)
<> 144:ef7eb2e8f9f7 1609 /** Peripheral GPIOD base pointer */
<> 144:ef7eb2e8f9f7 1610 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
<> 144:ef7eb2e8f9f7 1611 /** Peripheral GPIOE base address */
<> 144:ef7eb2e8f9f7 1612 #define GPIOE_BASE (0x400FF100u)
<> 144:ef7eb2e8f9f7 1613 /** Peripheral GPIOE base pointer */
<> 144:ef7eb2e8f9f7 1614 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
<> 144:ef7eb2e8f9f7 1615 /** Array initializer of GPIO peripheral base addresses */
<> 144:ef7eb2e8f9f7 1616 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
<> 144:ef7eb2e8f9f7 1617 /** Array initializer of GPIO peripheral base pointers */
<> 144:ef7eb2e8f9f7 1618 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /*!
<> 144:ef7eb2e8f9f7 1621 * @}
<> 144:ef7eb2e8f9f7 1622 */ /* end of group GPIO_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1626 -- I2C Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1627 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 /*!
<> 144:ef7eb2e8f9f7 1630 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1631 * @{
<> 144:ef7eb2e8f9f7 1632 */
<> 144:ef7eb2e8f9f7 1633
<> 144:ef7eb2e8f9f7 1634 /** I2C - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 1635 typedef struct {
<> 144:ef7eb2e8f9f7 1636 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
<> 144:ef7eb2e8f9f7 1637 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 1638 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
<> 144:ef7eb2e8f9f7 1639 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 1640 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 1641 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
<> 144:ef7eb2e8f9f7 1642 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 1643 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 1644 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 1645 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
<> 144:ef7eb2e8f9f7 1646 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
<> 144:ef7eb2e8f9f7 1647 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
<> 144:ef7eb2e8f9f7 1648 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
<> 144:ef7eb2e8f9f7 1649 } I2C_Type;
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1652 -- I2C Register Masks
<> 144:ef7eb2e8f9f7 1653 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /*!
<> 144:ef7eb2e8f9f7 1656 * @addtogroup I2C_Register_Masks I2C Register Masks
<> 144:ef7eb2e8f9f7 1657 * @{
<> 144:ef7eb2e8f9f7 1658 */
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 /*! @name A1 - I2C Address Register 1 */
<> 144:ef7eb2e8f9f7 1661 #define I2C_A1_AD_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 1662 #define I2C_A1_AD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1663 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /*! @name F - I2C Frequency Divider register */
<> 144:ef7eb2e8f9f7 1666 #define I2C_F_ICR_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 1667 #define I2C_F_ICR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1668 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
<> 144:ef7eb2e8f9f7 1669 #define I2C_F_MULT_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 1670 #define I2C_F_MULT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1671 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 /*! @name C1 - I2C Control Register 1 */
<> 144:ef7eb2e8f9f7 1674 #define I2C_C1_DMAEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1675 #define I2C_C1_DMAEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1676 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 1677 #define I2C_C1_WUEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1678 #define I2C_C1_WUEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1679 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
<> 144:ef7eb2e8f9f7 1680 #define I2C_C1_RSTA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1681 #define I2C_C1_RSTA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1682 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
<> 144:ef7eb2e8f9f7 1683 #define I2C_C1_TXAK_MASK (0x8U)
<> 144:ef7eb2e8f9f7 1684 #define I2C_C1_TXAK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 1685 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
<> 144:ef7eb2e8f9f7 1686 #define I2C_C1_TX_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1687 #define I2C_C1_TX_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1688 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
<> 144:ef7eb2e8f9f7 1689 #define I2C_C1_MST_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1690 #define I2C_C1_MST_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1691 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
<> 144:ef7eb2e8f9f7 1692 #define I2C_C1_IICIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1693 #define I2C_C1_IICIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1694 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
<> 144:ef7eb2e8f9f7 1695 #define I2C_C1_IICEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1696 #define I2C_C1_IICEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1697 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 /*! @name S - I2C Status register */
<> 144:ef7eb2e8f9f7 1700 #define I2C_S_RXAK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1701 #define I2C_S_RXAK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1702 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
<> 144:ef7eb2e8f9f7 1703 #define I2C_S_IICIF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1704 #define I2C_S_IICIF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1705 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
<> 144:ef7eb2e8f9f7 1706 #define I2C_S_SRW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1707 #define I2C_S_SRW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1708 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
<> 144:ef7eb2e8f9f7 1709 #define I2C_S_RAM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 1710 #define I2C_S_RAM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 1711 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
<> 144:ef7eb2e8f9f7 1712 #define I2C_S_ARBL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1713 #define I2C_S_ARBL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1714 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
<> 144:ef7eb2e8f9f7 1715 #define I2C_S_BUSY_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1716 #define I2C_S_BUSY_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1717 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
<> 144:ef7eb2e8f9f7 1718 #define I2C_S_IAAS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1719 #define I2C_S_IAAS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1720 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
<> 144:ef7eb2e8f9f7 1721 #define I2C_S_TCF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1722 #define I2C_S_TCF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1723 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
<> 144:ef7eb2e8f9f7 1724
<> 144:ef7eb2e8f9f7 1725 /*! @name D - I2C Data I/O register */
<> 144:ef7eb2e8f9f7 1726 #define I2C_D_DATA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1727 #define I2C_D_DATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1728 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
<> 144:ef7eb2e8f9f7 1729
<> 144:ef7eb2e8f9f7 1730 /*! @name C2 - I2C Control Register 2 */
<> 144:ef7eb2e8f9f7 1731 #define I2C_C2_AD_MASK (0x7U)
<> 144:ef7eb2e8f9f7 1732 #define I2C_C2_AD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1733 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
<> 144:ef7eb2e8f9f7 1734 #define I2C_C2_RMEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 1735 #define I2C_C2_RMEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 1736 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
<> 144:ef7eb2e8f9f7 1737 #define I2C_C2_SBRC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1738 #define I2C_C2_SBRC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1739 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
<> 144:ef7eb2e8f9f7 1740 #define I2C_C2_HDRS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1741 #define I2C_C2_HDRS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1742 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
<> 144:ef7eb2e8f9f7 1743 #define I2C_C2_ADEXT_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1744 #define I2C_C2_ADEXT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1745 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
<> 144:ef7eb2e8f9f7 1746 #define I2C_C2_GCAEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1747 #define I2C_C2_GCAEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1748 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
<> 144:ef7eb2e8f9f7 1751 #define I2C_FLT_FLT_MASK (0xFU)
<> 144:ef7eb2e8f9f7 1752 #define I2C_FLT_FLT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1753 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
<> 144:ef7eb2e8f9f7 1754 #define I2C_FLT_STARTF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1755 #define I2C_FLT_STARTF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1756 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
<> 144:ef7eb2e8f9f7 1757 #define I2C_FLT_SSIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1758 #define I2C_FLT_SSIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1759 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
<> 144:ef7eb2e8f9f7 1760 #define I2C_FLT_STOPF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1761 #define I2C_FLT_STOPF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1762 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
<> 144:ef7eb2e8f9f7 1763 #define I2C_FLT_SHEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1764 #define I2C_FLT_SHEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1765 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
<> 144:ef7eb2e8f9f7 1766
<> 144:ef7eb2e8f9f7 1767 /*! @name RA - I2C Range Address register */
<> 144:ef7eb2e8f9f7 1768 #define I2C_RA_RAD_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 1769 #define I2C_RA_RAD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1770 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
<> 144:ef7eb2e8f9f7 1771
<> 144:ef7eb2e8f9f7 1772 /*! @name SMB - I2C SMBus Control and Status register */
<> 144:ef7eb2e8f9f7 1773 #define I2C_SMB_SHTF2IE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1774 #define I2C_SMB_SHTF2IE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1775 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
<> 144:ef7eb2e8f9f7 1776 #define I2C_SMB_SHTF2_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1777 #define I2C_SMB_SHTF2_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1778 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
<> 144:ef7eb2e8f9f7 1779 #define I2C_SMB_SHTF1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1780 #define I2C_SMB_SHTF1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1781 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
<> 144:ef7eb2e8f9f7 1782 #define I2C_SMB_SLTF_MASK (0x8U)
<> 144:ef7eb2e8f9f7 1783 #define I2C_SMB_SLTF_SHIFT (3U)
<> 144:ef7eb2e8f9f7 1784 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
<> 144:ef7eb2e8f9f7 1785 #define I2C_SMB_TCKSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1786 #define I2C_SMB_TCKSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1787 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
<> 144:ef7eb2e8f9f7 1788 #define I2C_SMB_SIICAEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1789 #define I2C_SMB_SIICAEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1790 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
<> 144:ef7eb2e8f9f7 1791 #define I2C_SMB_ALERTEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1792 #define I2C_SMB_ALERTEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1793 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
<> 144:ef7eb2e8f9f7 1794 #define I2C_SMB_FACK_MASK (0x80U)
<> 144:ef7eb2e8f9f7 1795 #define I2C_SMB_FACK_SHIFT (7U)
<> 144:ef7eb2e8f9f7 1796 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 /*! @name A2 - I2C Address Register 2 */
<> 144:ef7eb2e8f9f7 1799 #define I2C_A2_SAD_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 1800 #define I2C_A2_SAD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1801 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 /*! @name SLTH - I2C SCL Low Timeout Register High */
<> 144:ef7eb2e8f9f7 1804 #define I2C_SLTH_SSLT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1805 #define I2C_SLTH_SSLT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1806 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /*! @name SLTL - I2C SCL Low Timeout Register Low */
<> 144:ef7eb2e8f9f7 1809 #define I2C_SLTL_SSLT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1810 #define I2C_SLTL_SSLT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1811 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /*! @name S2 - I2C Status register 2 */
<> 144:ef7eb2e8f9f7 1814 #define I2C_S2_EMPTY_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1815 #define I2C_S2_EMPTY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1816 #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
<> 144:ef7eb2e8f9f7 1817 #define I2C_S2_ERROR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1818 #define I2C_S2_ERROR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1819 #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /*!
<> 144:ef7eb2e8f9f7 1823 * @}
<> 144:ef7eb2e8f9f7 1824 */ /* end of group I2C_Register_Masks */
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826
<> 144:ef7eb2e8f9f7 1827 /* I2C - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 1828 /** Peripheral I2C0 base address */
<> 144:ef7eb2e8f9f7 1829 #define I2C0_BASE (0x40066000u)
<> 144:ef7eb2e8f9f7 1830 /** Peripheral I2C0 base pointer */
<> 144:ef7eb2e8f9f7 1831 #define I2C0 ((I2C_Type *)I2C0_BASE)
<> 144:ef7eb2e8f9f7 1832 /** Peripheral I2C1 base address */
<> 144:ef7eb2e8f9f7 1833 #define I2C1_BASE (0x40067000u)
<> 144:ef7eb2e8f9f7 1834 /** Peripheral I2C1 base pointer */
<> 144:ef7eb2e8f9f7 1835 #define I2C1 ((I2C_Type *)I2C1_BASE)
<> 144:ef7eb2e8f9f7 1836 /** Array initializer of I2C peripheral base addresses */
<> 144:ef7eb2e8f9f7 1837 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
<> 144:ef7eb2e8f9f7 1838 /** Array initializer of I2C peripheral base pointers */
<> 144:ef7eb2e8f9f7 1839 #define I2C_BASE_PTRS { I2C0, I2C1 }
<> 144:ef7eb2e8f9f7 1840 /** Interrupt vectors for the I2C peripheral type */
<> 144:ef7eb2e8f9f7 1841 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
<> 144:ef7eb2e8f9f7 1842
<> 144:ef7eb2e8f9f7 1843 /*!
<> 144:ef7eb2e8f9f7 1844 * @}
<> 144:ef7eb2e8f9f7 1845 */ /* end of group I2C_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1849 -- I2S Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1850 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /*!
<> 144:ef7eb2e8f9f7 1853 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
<> 144:ef7eb2e8f9f7 1854 * @{
<> 144:ef7eb2e8f9f7 1855 */
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /** I2S - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 1858 typedef struct {
<> 144:ef7eb2e8f9f7 1859 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 1860 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 1861 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 1862 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 1863 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 1864 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 1865 uint8_t RESERVED_1[8];
<> 144:ef7eb2e8f9f7 1866 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1867 uint8_t RESERVED_2[60];
<> 144:ef7eb2e8f9f7 1868 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
<> 144:ef7eb2e8f9f7 1869 uint8_t RESERVED_3[28];
<> 144:ef7eb2e8f9f7 1870 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 1871 uint8_t RESERVED_4[4];
<> 144:ef7eb2e8f9f7 1872 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
<> 144:ef7eb2e8f9f7 1873 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
<> 144:ef7eb2e8f9f7 1874 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
<> 144:ef7eb2e8f9f7 1875 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
<> 144:ef7eb2e8f9f7 1876 uint8_t RESERVED_5[8];
<> 144:ef7eb2e8f9f7 1877 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 1878 uint8_t RESERVED_6[60];
<> 144:ef7eb2e8f9f7 1879 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
<> 144:ef7eb2e8f9f7 1880 uint8_t RESERVED_7[28];
<> 144:ef7eb2e8f9f7 1881 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 1882 } I2S_Type;
<> 144:ef7eb2e8f9f7 1883
<> 144:ef7eb2e8f9f7 1884 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1885 -- I2S Register Masks
<> 144:ef7eb2e8f9f7 1886 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 1887
<> 144:ef7eb2e8f9f7 1888 /*!
<> 144:ef7eb2e8f9f7 1889 * @addtogroup I2S_Register_Masks I2S Register Masks
<> 144:ef7eb2e8f9f7 1890 * @{
<> 144:ef7eb2e8f9f7 1891 */
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893 /*! @name TCSR - SAI Transmit Control Register */
<> 144:ef7eb2e8f9f7 1894 #define I2S_TCSR_FWDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1895 #define I2S_TCSR_FWDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1896 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
<> 144:ef7eb2e8f9f7 1897 #define I2S_TCSR_FWIE_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1898 #define I2S_TCSR_FWIE_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1899 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
<> 144:ef7eb2e8f9f7 1900 #define I2S_TCSR_FEIE_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1901 #define I2S_TCSR_FEIE_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1902 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
<> 144:ef7eb2e8f9f7 1903 #define I2S_TCSR_SEIE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 1904 #define I2S_TCSR_SEIE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 1905 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
<> 144:ef7eb2e8f9f7 1906 #define I2S_TCSR_WSIE_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1907 #define I2S_TCSR_WSIE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1908 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
<> 144:ef7eb2e8f9f7 1909 #define I2S_TCSR_FWF_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1910 #define I2S_TCSR_FWF_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1911 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
<> 144:ef7eb2e8f9f7 1912 #define I2S_TCSR_FEF_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1913 #define I2S_TCSR_FEF_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1914 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
<> 144:ef7eb2e8f9f7 1915 #define I2S_TCSR_SEF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 1916 #define I2S_TCSR_SEF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 1917 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
<> 144:ef7eb2e8f9f7 1918 #define I2S_TCSR_WSF_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1919 #define I2S_TCSR_WSF_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1920 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
<> 144:ef7eb2e8f9f7 1921 #define I2S_TCSR_SR_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1922 #define I2S_TCSR_SR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1923 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
<> 144:ef7eb2e8f9f7 1924 #define I2S_TCSR_FR_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1925 #define I2S_TCSR_FR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1926 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
<> 144:ef7eb2e8f9f7 1927 #define I2S_TCSR_BCE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1928 #define I2S_TCSR_BCE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1929 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
<> 144:ef7eb2e8f9f7 1930 #define I2S_TCSR_DBGE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1931 #define I2S_TCSR_DBGE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1932 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
<> 144:ef7eb2e8f9f7 1933 #define I2S_TCSR_STOPE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1934 #define I2S_TCSR_STOPE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1935 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
<> 144:ef7eb2e8f9f7 1936 #define I2S_TCSR_TE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 1937 #define I2S_TCSR_TE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 1938 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
<> 144:ef7eb2e8f9f7 1939
<> 144:ef7eb2e8f9f7 1940 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
<> 144:ef7eb2e8f9f7 1941 #define I2S_TCR2_DIV_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 1942 #define I2S_TCR2_DIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1943 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
<> 144:ef7eb2e8f9f7 1944 #define I2S_TCR2_BCD_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1945 #define I2S_TCR2_BCD_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1946 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
<> 144:ef7eb2e8f9f7 1947 #define I2S_TCR2_BCP_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1948 #define I2S_TCR2_BCP_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1949 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
<> 144:ef7eb2e8f9f7 1950 #define I2S_TCR2_MSEL_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 1951 #define I2S_TCR2_MSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1952 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
<> 144:ef7eb2e8f9f7 1953 #define I2S_TCR2_BCI_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1954 #define I2S_TCR2_BCI_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1955 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
<> 144:ef7eb2e8f9f7 1956 #define I2S_TCR2_BCS_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1957 #define I2S_TCR2_BCS_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1958 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
<> 144:ef7eb2e8f9f7 1959 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 1960 #define I2S_TCR2_SYNC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1961 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
<> 144:ef7eb2e8f9f7 1962
<> 144:ef7eb2e8f9f7 1963 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
<> 144:ef7eb2e8f9f7 1964 #define I2S_TCR3_WDFL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1965 #define I2S_TCR3_WDFL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1966 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
<> 144:ef7eb2e8f9f7 1967 #define I2S_TCR3_TCE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1968 #define I2S_TCR3_TCE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1969 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
<> 144:ef7eb2e8f9f7 1970
<> 144:ef7eb2e8f9f7 1971 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
<> 144:ef7eb2e8f9f7 1972 #define I2S_TCR4_FSD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1973 #define I2S_TCR4_FSD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1974 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
<> 144:ef7eb2e8f9f7 1975 #define I2S_TCR4_FSP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1976 #define I2S_TCR4_FSP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1977 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
<> 144:ef7eb2e8f9f7 1978 #define I2S_TCR4_ONDEM_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1979 #define I2S_TCR4_ONDEM_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1980 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
<> 144:ef7eb2e8f9f7 1981 #define I2S_TCR4_FSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 1982 #define I2S_TCR4_FSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 1983 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
<> 144:ef7eb2e8f9f7 1984 #define I2S_TCR4_MF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1985 #define I2S_TCR4_MF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1986 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
<> 144:ef7eb2e8f9f7 1987 #define I2S_TCR4_SYWD_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 1988 #define I2S_TCR4_SYWD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1989 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
<> 144:ef7eb2e8f9f7 1990 #define I2S_TCR4_FRSZ_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1991 #define I2S_TCR4_FRSZ_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1992 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
<> 144:ef7eb2e8f9f7 1993 #define I2S_TCR4_FPACK_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 1994 #define I2S_TCR4_FPACK_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1995 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
<> 144:ef7eb2e8f9f7 1996 #define I2S_TCR4_FCONT_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1997 #define I2S_TCR4_FCONT_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1998 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
<> 144:ef7eb2e8f9f7 2001 #define I2S_TCR5_FBT_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 2002 #define I2S_TCR5_FBT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2003 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
<> 144:ef7eb2e8f9f7 2004 #define I2S_TCR5_W0W_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 2005 #define I2S_TCR5_W0W_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2006 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
<> 144:ef7eb2e8f9f7 2007 #define I2S_TCR5_WNW_MASK (0x1F000000U)
<> 144:ef7eb2e8f9f7 2008 #define I2S_TCR5_WNW_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2009 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
<> 144:ef7eb2e8f9f7 2010
<> 144:ef7eb2e8f9f7 2011 /*! @name TDR - SAI Transmit Data Register */
<> 144:ef7eb2e8f9f7 2012 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2013 #define I2S_TDR_TDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2014 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
<> 144:ef7eb2e8f9f7 2015
<> 144:ef7eb2e8f9f7 2016 /* The count of I2S_TDR */
<> 144:ef7eb2e8f9f7 2017 #define I2S_TDR_COUNT (1U)
<> 144:ef7eb2e8f9f7 2018
<> 144:ef7eb2e8f9f7 2019 /*! @name TMR - SAI Transmit Mask Register */
<> 144:ef7eb2e8f9f7 2020 #define I2S_TMR_TWM_MASK (0x3U)
<> 144:ef7eb2e8f9f7 2021 #define I2S_TMR_TWM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2022 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /*! @name RCSR - SAI Receive Control Register */
<> 144:ef7eb2e8f9f7 2025 #define I2S_RCSR_FWDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2026 #define I2S_RCSR_FWDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2027 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
<> 144:ef7eb2e8f9f7 2028 #define I2S_RCSR_FWIE_MASK (0x200U)
<> 144:ef7eb2e8f9f7 2029 #define I2S_RCSR_FWIE_SHIFT (9U)
<> 144:ef7eb2e8f9f7 2030 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
<> 144:ef7eb2e8f9f7 2031 #define I2S_RCSR_FEIE_MASK (0x400U)
<> 144:ef7eb2e8f9f7 2032 #define I2S_RCSR_FEIE_SHIFT (10U)
<> 144:ef7eb2e8f9f7 2033 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
<> 144:ef7eb2e8f9f7 2034 #define I2S_RCSR_SEIE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 2035 #define I2S_RCSR_SEIE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 2036 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
<> 144:ef7eb2e8f9f7 2037 #define I2S_RCSR_WSIE_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 2038 #define I2S_RCSR_WSIE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2039 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
<> 144:ef7eb2e8f9f7 2040 #define I2S_RCSR_FWF_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 2041 #define I2S_RCSR_FWF_SHIFT (17U)
<> 144:ef7eb2e8f9f7 2042 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
<> 144:ef7eb2e8f9f7 2043 #define I2S_RCSR_FEF_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 2044 #define I2S_RCSR_FEF_SHIFT (18U)
<> 144:ef7eb2e8f9f7 2045 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
<> 144:ef7eb2e8f9f7 2046 #define I2S_RCSR_SEF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 2047 #define I2S_RCSR_SEF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 2048 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
<> 144:ef7eb2e8f9f7 2049 #define I2S_RCSR_WSF_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 2050 #define I2S_RCSR_WSF_SHIFT (20U)
<> 144:ef7eb2e8f9f7 2051 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
<> 144:ef7eb2e8f9f7 2052 #define I2S_RCSR_SR_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 2053 #define I2S_RCSR_SR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2054 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
<> 144:ef7eb2e8f9f7 2055 #define I2S_RCSR_FR_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 2056 #define I2S_RCSR_FR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 2057 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
<> 144:ef7eb2e8f9f7 2058 #define I2S_RCSR_BCE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 2059 #define I2S_RCSR_BCE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2060 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
<> 144:ef7eb2e8f9f7 2061 #define I2S_RCSR_DBGE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 2062 #define I2S_RCSR_DBGE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 2063 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
<> 144:ef7eb2e8f9f7 2064 #define I2S_RCSR_STOPE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 2065 #define I2S_RCSR_STOPE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 2066 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
<> 144:ef7eb2e8f9f7 2067 #define I2S_RCSR_RE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 2068 #define I2S_RCSR_RE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 2069 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
<> 144:ef7eb2e8f9f7 2070
<> 144:ef7eb2e8f9f7 2071 /*! @name RCR2 - SAI Receive Configuration 2 Register */
<> 144:ef7eb2e8f9f7 2072 #define I2S_RCR2_DIV_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2073 #define I2S_RCR2_DIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2074 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
<> 144:ef7eb2e8f9f7 2075 #define I2S_RCR2_BCD_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 2076 #define I2S_RCR2_BCD_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2077 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
<> 144:ef7eb2e8f9f7 2078 #define I2S_RCR2_BCP_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 2079 #define I2S_RCR2_BCP_SHIFT (25U)
<> 144:ef7eb2e8f9f7 2080 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
<> 144:ef7eb2e8f9f7 2081 #define I2S_RCR2_MSEL_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 2082 #define I2S_RCR2_MSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 2083 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
<> 144:ef7eb2e8f9f7 2084 #define I2S_RCR2_BCI_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 2085 #define I2S_RCR2_BCI_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2086 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
<> 144:ef7eb2e8f9f7 2087 #define I2S_RCR2_BCS_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 2088 #define I2S_RCR2_BCS_SHIFT (29U)
<> 144:ef7eb2e8f9f7 2089 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
<> 144:ef7eb2e8f9f7 2090 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 2091 #define I2S_RCR2_SYNC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 2092 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
<> 144:ef7eb2e8f9f7 2093
<> 144:ef7eb2e8f9f7 2094 /*! @name RCR3 - SAI Receive Configuration 3 Register */
<> 144:ef7eb2e8f9f7 2095 #define I2S_RCR3_WDFL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2096 #define I2S_RCR3_WDFL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2097 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
<> 144:ef7eb2e8f9f7 2098 #define I2S_RCR3_RCE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 2099 #define I2S_RCR3_RCE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2100 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 /*! @name RCR4 - SAI Receive Configuration 4 Register */
<> 144:ef7eb2e8f9f7 2103 #define I2S_RCR4_FSD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2104 #define I2S_RCR4_FSD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2105 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
<> 144:ef7eb2e8f9f7 2106 #define I2S_RCR4_FSP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2107 #define I2S_RCR4_FSP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2108 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
<> 144:ef7eb2e8f9f7 2109 #define I2S_RCR4_ONDEM_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2110 #define I2S_RCR4_ONDEM_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2111 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
<> 144:ef7eb2e8f9f7 2112 #define I2S_RCR4_FSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 2113 #define I2S_RCR4_FSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 2114 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
<> 144:ef7eb2e8f9f7 2115 #define I2S_RCR4_MF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 2116 #define I2S_RCR4_MF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 2117 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
<> 144:ef7eb2e8f9f7 2118 #define I2S_RCR4_SYWD_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 2119 #define I2S_RCR4_SYWD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2120 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
<> 144:ef7eb2e8f9f7 2121 #define I2S_RCR4_FRSZ_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 2122 #define I2S_RCR4_FRSZ_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2123 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
<> 144:ef7eb2e8f9f7 2124 #define I2S_RCR4_FPACK_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 2125 #define I2S_RCR4_FPACK_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2126 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
<> 144:ef7eb2e8f9f7 2127 #define I2S_RCR4_FCONT_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 2128 #define I2S_RCR4_FCONT_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2129 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
<> 144:ef7eb2e8f9f7 2130
<> 144:ef7eb2e8f9f7 2131 /*! @name RCR5 - SAI Receive Configuration 5 Register */
<> 144:ef7eb2e8f9f7 2132 #define I2S_RCR5_FBT_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 2133 #define I2S_RCR5_FBT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2134 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
<> 144:ef7eb2e8f9f7 2135 #define I2S_RCR5_W0W_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 2136 #define I2S_RCR5_W0W_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2137 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
<> 144:ef7eb2e8f9f7 2138 #define I2S_RCR5_WNW_MASK (0x1F000000U)
<> 144:ef7eb2e8f9f7 2139 #define I2S_RCR5_WNW_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2140 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
<> 144:ef7eb2e8f9f7 2141
<> 144:ef7eb2e8f9f7 2142 /*! @name RDR - SAI Receive Data Register */
<> 144:ef7eb2e8f9f7 2143 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2144 #define I2S_RDR_RDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2145 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
<> 144:ef7eb2e8f9f7 2146
<> 144:ef7eb2e8f9f7 2147 /* The count of I2S_RDR */
<> 144:ef7eb2e8f9f7 2148 #define I2S_RDR_COUNT (1U)
<> 144:ef7eb2e8f9f7 2149
<> 144:ef7eb2e8f9f7 2150 /*! @name RMR - SAI Receive Mask Register */
<> 144:ef7eb2e8f9f7 2151 #define I2S_RMR_RWM_MASK (0x3U)
<> 144:ef7eb2e8f9f7 2152 #define I2S_RMR_RWM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2153 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 /*! @name MCR - SAI MCLK Control Register */
<> 144:ef7eb2e8f9f7 2156 #define I2S_MCR_MICS_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 2157 #define I2S_MCR_MICS_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2158 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
<> 144:ef7eb2e8f9f7 2159 #define I2S_MCR_MOE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 2160 #define I2S_MCR_MOE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 2161 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
<> 144:ef7eb2e8f9f7 2162 #define I2S_MCR_DUF_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 2163 #define I2S_MCR_DUF_SHIFT (31U)
<> 144:ef7eb2e8f9f7 2164 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
<> 144:ef7eb2e8f9f7 2165
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 /*!
<> 144:ef7eb2e8f9f7 2168 * @}
<> 144:ef7eb2e8f9f7 2169 */ /* end of group I2S_Register_Masks */
<> 144:ef7eb2e8f9f7 2170
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 /* I2S - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 2173 /** Peripheral I2S0 base address */
<> 144:ef7eb2e8f9f7 2174 #define I2S0_BASE (0x4002F000u)
<> 144:ef7eb2e8f9f7 2175 /** Peripheral I2S0 base pointer */
<> 144:ef7eb2e8f9f7 2176 #define I2S0 ((I2S_Type *)I2S0_BASE)
<> 144:ef7eb2e8f9f7 2177 /** Array initializer of I2S peripheral base addresses */
<> 144:ef7eb2e8f9f7 2178 #define I2S_BASE_ADDRS { I2S0_BASE }
<> 144:ef7eb2e8f9f7 2179 /** Array initializer of I2S peripheral base pointers */
<> 144:ef7eb2e8f9f7 2180 #define I2S_BASE_PTRS { I2S0 }
<> 144:ef7eb2e8f9f7 2181 /** Interrupt vectors for the I2S peripheral type */
<> 144:ef7eb2e8f9f7 2182 #define I2S_RX_IRQS { I2S0_IRQn }
<> 144:ef7eb2e8f9f7 2183 #define I2S_TX_IRQS { I2S0_IRQn }
<> 144:ef7eb2e8f9f7 2184
<> 144:ef7eb2e8f9f7 2185 /*!
<> 144:ef7eb2e8f9f7 2186 * @}
<> 144:ef7eb2e8f9f7 2187 */ /* end of group I2S_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 2188
<> 144:ef7eb2e8f9f7 2189
<> 144:ef7eb2e8f9f7 2190 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2191 -- LCD Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2192 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 /*!
<> 144:ef7eb2e8f9f7 2195 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2196 * @{
<> 144:ef7eb2e8f9f7 2197 */
<> 144:ef7eb2e8f9f7 2198
<> 144:ef7eb2e8f9f7 2199 /** LCD - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 2200 typedef struct {
<> 144:ef7eb2e8f9f7 2201 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 2202 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 2203 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 2204 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 2205 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2206 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2207 union { /* offset: 0x20 */
<> 144:ef7eb2e8f9f7 2208 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2209 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
<> 144:ef7eb2e8f9f7 2210 };
<> 144:ef7eb2e8f9f7 2211 } LCD_Type;
<> 144:ef7eb2e8f9f7 2212
<> 144:ef7eb2e8f9f7 2213 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2214 -- LCD Register Masks
<> 144:ef7eb2e8f9f7 2215 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2216
<> 144:ef7eb2e8f9f7 2217 /*!
<> 144:ef7eb2e8f9f7 2218 * @addtogroup LCD_Register_Masks LCD Register Masks
<> 144:ef7eb2e8f9f7 2219 * @{
<> 144:ef7eb2e8f9f7 2220 */
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /*! @name GCR - LCD General Control Register */
<> 144:ef7eb2e8f9f7 2223 #define LCD_GCR_DUTY_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2224 #define LCD_GCR_DUTY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2225 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_DUTY_SHIFT)) & LCD_GCR_DUTY_MASK)
<> 144:ef7eb2e8f9f7 2226 #define LCD_GCR_LCLK_MASK (0x38U)
<> 144:ef7eb2e8f9f7 2227 #define LCD_GCR_LCLK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 2228 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCLK_SHIFT)) & LCD_GCR_LCLK_MASK)
<> 144:ef7eb2e8f9f7 2229 #define LCD_GCR_SOURCE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 2230 #define LCD_GCR_SOURCE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 2231 #define LCD_GCR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_SOURCE_SHIFT)) & LCD_GCR_SOURCE_MASK)
<> 144:ef7eb2e8f9f7 2232 #define LCD_GCR_LCDEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 2233 #define LCD_GCR_LCDEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 2234 #define LCD_GCR_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDEN_SHIFT)) & LCD_GCR_LCDEN_MASK)
<> 144:ef7eb2e8f9f7 2235 #define LCD_GCR_LCDSTP_MASK (0x100U)
<> 144:ef7eb2e8f9f7 2236 #define LCD_GCR_LCDSTP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2237 #define LCD_GCR_LCDSTP(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDSTP_SHIFT)) & LCD_GCR_LCDSTP_MASK)
<> 144:ef7eb2e8f9f7 2238 #define LCD_GCR_LCDDOZE_MASK (0x200U)
<> 144:ef7eb2e8f9f7 2239 #define LCD_GCR_LCDDOZE_SHIFT (9U)
<> 144:ef7eb2e8f9f7 2240 #define LCD_GCR_LCDDOZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDDOZE_SHIFT)) & LCD_GCR_LCDDOZE_MASK)
<> 144:ef7eb2e8f9f7 2241 #define LCD_GCR_FFR_MASK (0x400U)
<> 144:ef7eb2e8f9f7 2242 #define LCD_GCR_FFR_SHIFT (10U)
<> 144:ef7eb2e8f9f7 2243 #define LCD_GCR_FFR(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FFR_SHIFT)) & LCD_GCR_FFR_MASK)
<> 144:ef7eb2e8f9f7 2244 #define LCD_GCR_ALTSOURCE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 2245 #define LCD_GCR_ALTSOURCE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 2246 #define LCD_GCR_ALTSOURCE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTSOURCE_SHIFT)) & LCD_GCR_ALTSOURCE_MASK)
<> 144:ef7eb2e8f9f7 2247 #define LCD_GCR_ALTDIV_MASK (0x3000U)
<> 144:ef7eb2e8f9f7 2248 #define LCD_GCR_ALTDIV_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2249 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTDIV_SHIFT)) & LCD_GCR_ALTDIV_MASK)
<> 144:ef7eb2e8f9f7 2250 #define LCD_GCR_FDCIEN_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 2251 #define LCD_GCR_FDCIEN_SHIFT (14U)
<> 144:ef7eb2e8f9f7 2252 #define LCD_GCR_FDCIEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FDCIEN_SHIFT)) & LCD_GCR_FDCIEN_MASK)
<> 144:ef7eb2e8f9f7 2253 #define LCD_GCR_PADSAFE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 2254 #define LCD_GCR_PADSAFE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 2255 #define LCD_GCR_PADSAFE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_PADSAFE_SHIFT)) & LCD_GCR_PADSAFE_MASK)
<> 144:ef7eb2e8f9f7 2256 #define LCD_GCR_VSUPPLY_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 2257 #define LCD_GCR_VSUPPLY_SHIFT (17U)
<> 144:ef7eb2e8f9f7 2258 #define LCD_GCR_VSUPPLY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_VSUPPLY_SHIFT)) & LCD_GCR_VSUPPLY_MASK)
<> 144:ef7eb2e8f9f7 2259 #define LCD_GCR_LADJ_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 2260 #define LCD_GCR_LADJ_SHIFT (20U)
<> 144:ef7eb2e8f9f7 2261 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LADJ_SHIFT)) & LCD_GCR_LADJ_MASK)
<> 144:ef7eb2e8f9f7 2262 #define LCD_GCR_CPSEL_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 2263 #define LCD_GCR_CPSEL_SHIFT (23U)
<> 144:ef7eb2e8f9f7 2264 #define LCD_GCR_CPSEL(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_CPSEL_SHIFT)) & LCD_GCR_CPSEL_MASK)
<> 144:ef7eb2e8f9f7 2265 #define LCD_GCR_RVTRIM_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 2266 #define LCD_GCR_RVTRIM_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2267 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVTRIM_SHIFT)) & LCD_GCR_RVTRIM_MASK)
<> 144:ef7eb2e8f9f7 2268 #define LCD_GCR_RVEN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 2269 #define LCD_GCR_RVEN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 2270 #define LCD_GCR_RVEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVEN_SHIFT)) & LCD_GCR_RVEN_MASK)
<> 144:ef7eb2e8f9f7 2271
<> 144:ef7eb2e8f9f7 2272 /*! @name AR - LCD Auxiliary Register */
<> 144:ef7eb2e8f9f7 2273 #define LCD_AR_BRATE_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2274 #define LCD_AR_BRATE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2275 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BRATE_SHIFT)) & LCD_AR_BRATE_MASK)
<> 144:ef7eb2e8f9f7 2276 #define LCD_AR_BMODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 2277 #define LCD_AR_BMODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 2278 #define LCD_AR_BMODE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BMODE_SHIFT)) & LCD_AR_BMODE_MASK)
<> 144:ef7eb2e8f9f7 2279 #define LCD_AR_BLANK_MASK (0x20U)
<> 144:ef7eb2e8f9f7 2280 #define LCD_AR_BLANK_SHIFT (5U)
<> 144:ef7eb2e8f9f7 2281 #define LCD_AR_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLANK_SHIFT)) & LCD_AR_BLANK_MASK)
<> 144:ef7eb2e8f9f7 2282 #define LCD_AR_ALT_MASK (0x40U)
<> 144:ef7eb2e8f9f7 2283 #define LCD_AR_ALT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 2284 #define LCD_AR_ALT(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_ALT_SHIFT)) & LCD_AR_ALT_MASK)
<> 144:ef7eb2e8f9f7 2285 #define LCD_AR_BLINK_MASK (0x80U)
<> 144:ef7eb2e8f9f7 2286 #define LCD_AR_BLINK_SHIFT (7U)
<> 144:ef7eb2e8f9f7 2287 #define LCD_AR_BLINK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLINK_SHIFT)) & LCD_AR_BLINK_MASK)
<> 144:ef7eb2e8f9f7 2288
<> 144:ef7eb2e8f9f7 2289 /*! @name FDCR - LCD Fault Detect Control Register */
<> 144:ef7eb2e8f9f7 2290 #define LCD_FDCR_FDPINID_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 2291 #define LCD_FDCR_FDPINID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2292 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPINID_SHIFT)) & LCD_FDCR_FDPINID_MASK)
<> 144:ef7eb2e8f9f7 2293 #define LCD_FDCR_FDBPEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 2294 #define LCD_FDCR_FDBPEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 2295 #define LCD_FDCR_FDBPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDBPEN_SHIFT)) & LCD_FDCR_FDBPEN_MASK)
<> 144:ef7eb2e8f9f7 2296 #define LCD_FDCR_FDEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 2297 #define LCD_FDCR_FDEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 2298 #define LCD_FDCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDEN_SHIFT)) & LCD_FDCR_FDEN_MASK)
<> 144:ef7eb2e8f9f7 2299 #define LCD_FDCR_FDSWW_MASK (0xE00U)
<> 144:ef7eb2e8f9f7 2300 #define LCD_FDCR_FDSWW_SHIFT (9U)
<> 144:ef7eb2e8f9f7 2301 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDSWW_SHIFT)) & LCD_FDCR_FDSWW_MASK)
<> 144:ef7eb2e8f9f7 2302 #define LCD_FDCR_FDPRS_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 2303 #define LCD_FDCR_FDPRS_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2304 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPRS_SHIFT)) & LCD_FDCR_FDPRS_MASK)
<> 144:ef7eb2e8f9f7 2305
<> 144:ef7eb2e8f9f7 2306 /*! @name FDSR - LCD Fault Detect Status Register */
<> 144:ef7eb2e8f9f7 2307 #define LCD_FDSR_FDCNT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2308 #define LCD_FDSR_FDCNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2309 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCNT_SHIFT)) & LCD_FDSR_FDCNT_MASK)
<> 144:ef7eb2e8f9f7 2310 #define LCD_FDSR_FDCF_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 2311 #define LCD_FDSR_FDCF_SHIFT (15U)
<> 144:ef7eb2e8f9f7 2312 #define LCD_FDSR_FDCF(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCF_SHIFT)) & LCD_FDSR_FDCF_MASK)
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 /*! @name PEN - LCD Pin Enable register */
<> 144:ef7eb2e8f9f7 2315 #define LCD_PEN_PEN_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2316 #define LCD_PEN_PEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2317 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PEN_SHIFT)) & LCD_PEN_PEN_MASK)
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 /* The count of LCD_PEN */
<> 144:ef7eb2e8f9f7 2320 #define LCD_PEN_COUNT (2U)
<> 144:ef7eb2e8f9f7 2321
<> 144:ef7eb2e8f9f7 2322 /*! @name BPEN - LCD Back Plane Enable register */
<> 144:ef7eb2e8f9f7 2323 #define LCD_BPEN_BPEN_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2324 #define LCD_BPEN_BPEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2325 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_BPEN_SHIFT)) & LCD_BPEN_BPEN_MASK)
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 /* The count of LCD_BPEN */
<> 144:ef7eb2e8f9f7 2328 #define LCD_BPEN_COUNT (2U)
<> 144:ef7eb2e8f9f7 2329
<> 144:ef7eb2e8f9f7 2330 /*! @name WF - LCD Waveform register */
<> 144:ef7eb2e8f9f7 2331 #define LCD_WF_WF0_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2332 #define LCD_WF_WF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2333 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF0_SHIFT)) & LCD_WF_WF0_MASK)
<> 144:ef7eb2e8f9f7 2334 #define LCD_WF_WF60_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2335 #define LCD_WF_WF60_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2336 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF60_SHIFT)) & LCD_WF_WF60_MASK)
<> 144:ef7eb2e8f9f7 2337 #define LCD_WF_WF56_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2338 #define LCD_WF_WF56_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2339 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF56_SHIFT)) & LCD_WF_WF56_MASK)
<> 144:ef7eb2e8f9f7 2340 #define LCD_WF_WF52_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2341 #define LCD_WF_WF52_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2342 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF52_SHIFT)) & LCD_WF_WF52_MASK)
<> 144:ef7eb2e8f9f7 2343 #define LCD_WF_WF4_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2344 #define LCD_WF_WF4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2345 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF4_SHIFT)) & LCD_WF_WF4_MASK)
<> 144:ef7eb2e8f9f7 2346 #define LCD_WF_WF48_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2347 #define LCD_WF_WF48_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2348 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF48_SHIFT)) & LCD_WF_WF48_MASK)
<> 144:ef7eb2e8f9f7 2349 #define LCD_WF_WF44_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2350 #define LCD_WF_WF44_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2351 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF44_SHIFT)) & LCD_WF_WF44_MASK)
<> 144:ef7eb2e8f9f7 2352 #define LCD_WF_WF40_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2353 #define LCD_WF_WF40_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2354 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF40_SHIFT)) & LCD_WF_WF40_MASK)
<> 144:ef7eb2e8f9f7 2355 #define LCD_WF_WF8_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2356 #define LCD_WF_WF8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2357 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF8_SHIFT)) & LCD_WF_WF8_MASK)
<> 144:ef7eb2e8f9f7 2358 #define LCD_WF_WF36_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2359 #define LCD_WF_WF36_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2360 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF36_SHIFT)) & LCD_WF_WF36_MASK)
<> 144:ef7eb2e8f9f7 2361 #define LCD_WF_WF32_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2362 #define LCD_WF_WF32_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2363 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF32_SHIFT)) & LCD_WF_WF32_MASK)
<> 144:ef7eb2e8f9f7 2364 #define LCD_WF_WF28_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2365 #define LCD_WF_WF28_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2366 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF28_SHIFT)) & LCD_WF_WF28_MASK)
<> 144:ef7eb2e8f9f7 2367 #define LCD_WF_WF12_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2368 #define LCD_WF_WF12_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2369 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF12_SHIFT)) & LCD_WF_WF12_MASK)
<> 144:ef7eb2e8f9f7 2370 #define LCD_WF_WF24_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2371 #define LCD_WF_WF24_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2372 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF24_SHIFT)) & LCD_WF_WF24_MASK)
<> 144:ef7eb2e8f9f7 2373 #define LCD_WF_WF20_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2374 #define LCD_WF_WF20_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2375 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF20_SHIFT)) & LCD_WF_WF20_MASK)
<> 144:ef7eb2e8f9f7 2376 #define LCD_WF_WF16_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2377 #define LCD_WF_WF16_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2378 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF16_SHIFT)) & LCD_WF_WF16_MASK)
<> 144:ef7eb2e8f9f7 2379 #define LCD_WF_WF5_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2380 #define LCD_WF_WF5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2381 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF5_SHIFT)) & LCD_WF_WF5_MASK)
<> 144:ef7eb2e8f9f7 2382 #define LCD_WF_WF49_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2383 #define LCD_WF_WF49_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2384 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF49_SHIFT)) & LCD_WF_WF49_MASK)
<> 144:ef7eb2e8f9f7 2385 #define LCD_WF_WF45_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2386 #define LCD_WF_WF45_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2387 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF45_SHIFT)) & LCD_WF_WF45_MASK)
<> 144:ef7eb2e8f9f7 2388 #define LCD_WF_WF61_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2389 #define LCD_WF_WF61_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2390 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF61_SHIFT)) & LCD_WF_WF61_MASK)
<> 144:ef7eb2e8f9f7 2391 #define LCD_WF_WF25_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2392 #define LCD_WF_WF25_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2393 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF25_SHIFT)) & LCD_WF_WF25_MASK)
<> 144:ef7eb2e8f9f7 2394 #define LCD_WF_WF17_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2395 #define LCD_WF_WF17_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2396 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF17_SHIFT)) & LCD_WF_WF17_MASK)
<> 144:ef7eb2e8f9f7 2397 #define LCD_WF_WF41_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2398 #define LCD_WF_WF41_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2399 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF41_SHIFT)) & LCD_WF_WF41_MASK)
<> 144:ef7eb2e8f9f7 2400 #define LCD_WF_WF13_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2401 #define LCD_WF_WF13_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2402 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF13_SHIFT)) & LCD_WF_WF13_MASK)
<> 144:ef7eb2e8f9f7 2403 #define LCD_WF_WF57_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2404 #define LCD_WF_WF57_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2405 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF57_SHIFT)) & LCD_WF_WF57_MASK)
<> 144:ef7eb2e8f9f7 2406 #define LCD_WF_WF53_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2407 #define LCD_WF_WF53_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2408 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF53_SHIFT)) & LCD_WF_WF53_MASK)
<> 144:ef7eb2e8f9f7 2409 #define LCD_WF_WF37_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2410 #define LCD_WF_WF37_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2411 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF37_SHIFT)) & LCD_WF_WF37_MASK)
<> 144:ef7eb2e8f9f7 2412 #define LCD_WF_WF9_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2413 #define LCD_WF_WF9_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2414 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF9_SHIFT)) & LCD_WF_WF9_MASK)
<> 144:ef7eb2e8f9f7 2415 #define LCD_WF_WF1_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2416 #define LCD_WF_WF1_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2417 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF1_SHIFT)) & LCD_WF_WF1_MASK)
<> 144:ef7eb2e8f9f7 2418 #define LCD_WF_WF29_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2419 #define LCD_WF_WF29_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2420 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF29_SHIFT)) & LCD_WF_WF29_MASK)
<> 144:ef7eb2e8f9f7 2421 #define LCD_WF_WF33_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2422 #define LCD_WF_WF33_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2423 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF33_SHIFT)) & LCD_WF_WF33_MASK)
<> 144:ef7eb2e8f9f7 2424 #define LCD_WF_WF21_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2425 #define LCD_WF_WF21_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2426 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF21_SHIFT)) & LCD_WF_WF21_MASK)
<> 144:ef7eb2e8f9f7 2427 #define LCD_WF_WF26_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2428 #define LCD_WF_WF26_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2429 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF26_SHIFT)) & LCD_WF_WF26_MASK)
<> 144:ef7eb2e8f9f7 2430 #define LCD_WF_WF46_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2431 #define LCD_WF_WF46_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2432 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF46_SHIFT)) & LCD_WF_WF46_MASK)
<> 144:ef7eb2e8f9f7 2433 #define LCD_WF_WF6_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2434 #define LCD_WF_WF6_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2435 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF6_SHIFT)) & LCD_WF_WF6_MASK)
<> 144:ef7eb2e8f9f7 2436 #define LCD_WF_WF42_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2437 #define LCD_WF_WF42_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2438 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF42_SHIFT)) & LCD_WF_WF42_MASK)
<> 144:ef7eb2e8f9f7 2439 #define LCD_WF_WF18_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2440 #define LCD_WF_WF18_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2441 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF18_SHIFT)) & LCD_WF_WF18_MASK)
<> 144:ef7eb2e8f9f7 2442 #define LCD_WF_WF38_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2443 #define LCD_WF_WF38_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2444 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF38_SHIFT)) & LCD_WF_WF38_MASK)
<> 144:ef7eb2e8f9f7 2445 #define LCD_WF_WF22_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2446 #define LCD_WF_WF22_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2447 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF22_SHIFT)) & LCD_WF_WF22_MASK)
<> 144:ef7eb2e8f9f7 2448 #define LCD_WF_WF34_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2449 #define LCD_WF_WF34_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2450 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF34_SHIFT)) & LCD_WF_WF34_MASK)
<> 144:ef7eb2e8f9f7 2451 #define LCD_WF_WF50_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2452 #define LCD_WF_WF50_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2453 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF50_SHIFT)) & LCD_WF_WF50_MASK)
<> 144:ef7eb2e8f9f7 2454 #define LCD_WF_WF14_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2455 #define LCD_WF_WF14_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2456 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF14_SHIFT)) & LCD_WF_WF14_MASK)
<> 144:ef7eb2e8f9f7 2457 #define LCD_WF_WF54_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2458 #define LCD_WF_WF54_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2459 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF54_SHIFT)) & LCD_WF_WF54_MASK)
<> 144:ef7eb2e8f9f7 2460 #define LCD_WF_WF2_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2461 #define LCD_WF_WF2_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2462 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF2_SHIFT)) & LCD_WF_WF2_MASK)
<> 144:ef7eb2e8f9f7 2463 #define LCD_WF_WF58_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2464 #define LCD_WF_WF58_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2465 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF58_SHIFT)) & LCD_WF_WF58_MASK)
<> 144:ef7eb2e8f9f7 2466 #define LCD_WF_WF30_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2467 #define LCD_WF_WF30_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2468 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF30_SHIFT)) & LCD_WF_WF30_MASK)
<> 144:ef7eb2e8f9f7 2469 #define LCD_WF_WF62_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2470 #define LCD_WF_WF62_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2471 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF62_SHIFT)) & LCD_WF_WF62_MASK)
<> 144:ef7eb2e8f9f7 2472 #define LCD_WF_WF10_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2473 #define LCD_WF_WF10_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2474 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF10_SHIFT)) & LCD_WF_WF10_MASK)
<> 144:ef7eb2e8f9f7 2475 #define LCD_WF_WF63_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2476 #define LCD_WF_WF63_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2477 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF63_SHIFT)) & LCD_WF_WF63_MASK)
<> 144:ef7eb2e8f9f7 2478 #define LCD_WF_WF59_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2479 #define LCD_WF_WF59_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2480 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF59_SHIFT)) & LCD_WF_WF59_MASK)
<> 144:ef7eb2e8f9f7 2481 #define LCD_WF_WF55_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2482 #define LCD_WF_WF55_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2483 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF55_SHIFT)) & LCD_WF_WF55_MASK)
<> 144:ef7eb2e8f9f7 2484 #define LCD_WF_WF3_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2485 #define LCD_WF_WF3_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2486 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF3_SHIFT)) & LCD_WF_WF3_MASK)
<> 144:ef7eb2e8f9f7 2487 #define LCD_WF_WF51_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2488 #define LCD_WF_WF51_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2489 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF51_SHIFT)) & LCD_WF_WF51_MASK)
<> 144:ef7eb2e8f9f7 2490 #define LCD_WF_WF47_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2491 #define LCD_WF_WF47_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2492 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF47_SHIFT)) & LCD_WF_WF47_MASK)
<> 144:ef7eb2e8f9f7 2493 #define LCD_WF_WF43_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2494 #define LCD_WF_WF43_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2495 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF43_SHIFT)) & LCD_WF_WF43_MASK)
<> 144:ef7eb2e8f9f7 2496 #define LCD_WF_WF7_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2497 #define LCD_WF_WF7_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2498 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF7_SHIFT)) & LCD_WF_WF7_MASK)
<> 144:ef7eb2e8f9f7 2499 #define LCD_WF_WF39_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2500 #define LCD_WF_WF39_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2501 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF39_SHIFT)) & LCD_WF_WF39_MASK)
<> 144:ef7eb2e8f9f7 2502 #define LCD_WF_WF35_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2503 #define LCD_WF_WF35_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2504 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF35_SHIFT)) & LCD_WF_WF35_MASK)
<> 144:ef7eb2e8f9f7 2505 #define LCD_WF_WF31_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2506 #define LCD_WF_WF31_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2507 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF31_SHIFT)) & LCD_WF_WF31_MASK)
<> 144:ef7eb2e8f9f7 2508 #define LCD_WF_WF11_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2509 #define LCD_WF_WF11_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2510 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF11_SHIFT)) & LCD_WF_WF11_MASK)
<> 144:ef7eb2e8f9f7 2511 #define LCD_WF_WF27_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2512 #define LCD_WF_WF27_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2513 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF27_SHIFT)) & LCD_WF_WF27_MASK)
<> 144:ef7eb2e8f9f7 2514 #define LCD_WF_WF23_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2515 #define LCD_WF_WF23_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2516 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF23_SHIFT)) & LCD_WF_WF23_MASK)
<> 144:ef7eb2e8f9f7 2517 #define LCD_WF_WF19_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2518 #define LCD_WF_WF19_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2519 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF19_SHIFT)) & LCD_WF_WF19_MASK)
<> 144:ef7eb2e8f9f7 2520 #define LCD_WF_WF15_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2521 #define LCD_WF_WF15_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2522 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF15_SHIFT)) & LCD_WF_WF15_MASK)
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /* The count of LCD_WF */
<> 144:ef7eb2e8f9f7 2525 #define LCD_WF_COUNT (16U)
<> 144:ef7eb2e8f9f7 2526
<> 144:ef7eb2e8f9f7 2527 /*! @name WF8B - LCD Waveform Register 0...LCD Waveform Register 63. */
<> 144:ef7eb2e8f9f7 2528 #define LCD_WF8B_BPALCD0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2529 #define LCD_WF8B_BPALCD0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2530 #define LCD_WF8B_BPALCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD0_SHIFT)) & LCD_WF8B_BPALCD0_MASK)
<> 144:ef7eb2e8f9f7 2531 #define LCD_WF8B_BPALCD63_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2532 #define LCD_WF8B_BPALCD63_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2533 #define LCD_WF8B_BPALCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD63_SHIFT)) & LCD_WF8B_BPALCD63_MASK)
<> 144:ef7eb2e8f9f7 2534 #define LCD_WF8B_BPALCD62_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2535 #define LCD_WF8B_BPALCD62_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2536 #define LCD_WF8B_BPALCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD62_SHIFT)) & LCD_WF8B_BPALCD62_MASK)
<> 144:ef7eb2e8f9f7 2537 #define LCD_WF8B_BPALCD61_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2538 #define LCD_WF8B_BPALCD61_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2539 #define LCD_WF8B_BPALCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD61_SHIFT)) & LCD_WF8B_BPALCD61_MASK)
<> 144:ef7eb2e8f9f7 2540 #define LCD_WF8B_BPALCD60_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2541 #define LCD_WF8B_BPALCD60_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2542 #define LCD_WF8B_BPALCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD60_SHIFT)) & LCD_WF8B_BPALCD60_MASK)
<> 144:ef7eb2e8f9f7 2543 #define LCD_WF8B_BPALCD59_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2544 #define LCD_WF8B_BPALCD59_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2545 #define LCD_WF8B_BPALCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD59_SHIFT)) & LCD_WF8B_BPALCD59_MASK)
<> 144:ef7eb2e8f9f7 2546 #define LCD_WF8B_BPALCD58_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2547 #define LCD_WF8B_BPALCD58_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2548 #define LCD_WF8B_BPALCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD58_SHIFT)) & LCD_WF8B_BPALCD58_MASK)
<> 144:ef7eb2e8f9f7 2549 #define LCD_WF8B_BPALCD57_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2550 #define LCD_WF8B_BPALCD57_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2551 #define LCD_WF8B_BPALCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD57_SHIFT)) & LCD_WF8B_BPALCD57_MASK)
<> 144:ef7eb2e8f9f7 2552 #define LCD_WF8B_BPALCD1_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2553 #define LCD_WF8B_BPALCD1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2554 #define LCD_WF8B_BPALCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD1_SHIFT)) & LCD_WF8B_BPALCD1_MASK)
<> 144:ef7eb2e8f9f7 2555 #define LCD_WF8B_BPALCD56_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2556 #define LCD_WF8B_BPALCD56_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2557 #define LCD_WF8B_BPALCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD56_SHIFT)) & LCD_WF8B_BPALCD56_MASK)
<> 144:ef7eb2e8f9f7 2558 #define LCD_WF8B_BPALCD55_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2559 #define LCD_WF8B_BPALCD55_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2560 #define LCD_WF8B_BPALCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD55_SHIFT)) & LCD_WF8B_BPALCD55_MASK)
<> 144:ef7eb2e8f9f7 2561 #define LCD_WF8B_BPALCD54_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2562 #define LCD_WF8B_BPALCD54_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2563 #define LCD_WF8B_BPALCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD54_SHIFT)) & LCD_WF8B_BPALCD54_MASK)
<> 144:ef7eb2e8f9f7 2564 #define LCD_WF8B_BPALCD53_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2565 #define LCD_WF8B_BPALCD53_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2566 #define LCD_WF8B_BPALCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD53_SHIFT)) & LCD_WF8B_BPALCD53_MASK)
<> 144:ef7eb2e8f9f7 2567 #define LCD_WF8B_BPALCD52_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2568 #define LCD_WF8B_BPALCD52_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2569 #define LCD_WF8B_BPALCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD52_SHIFT)) & LCD_WF8B_BPALCD52_MASK)
<> 144:ef7eb2e8f9f7 2570 #define LCD_WF8B_BPALCD51_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2571 #define LCD_WF8B_BPALCD51_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2572 #define LCD_WF8B_BPALCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD51_SHIFT)) & LCD_WF8B_BPALCD51_MASK)
<> 144:ef7eb2e8f9f7 2573 #define LCD_WF8B_BPALCD50_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2574 #define LCD_WF8B_BPALCD50_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2575 #define LCD_WF8B_BPALCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD50_SHIFT)) & LCD_WF8B_BPALCD50_MASK)
<> 144:ef7eb2e8f9f7 2576 #define LCD_WF8B_BPALCD2_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2577 #define LCD_WF8B_BPALCD2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2578 #define LCD_WF8B_BPALCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD2_SHIFT)) & LCD_WF8B_BPALCD2_MASK)
<> 144:ef7eb2e8f9f7 2579 #define LCD_WF8B_BPALCD49_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2580 #define LCD_WF8B_BPALCD49_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2581 #define LCD_WF8B_BPALCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD49_SHIFT)) & LCD_WF8B_BPALCD49_MASK)
<> 144:ef7eb2e8f9f7 2582 #define LCD_WF8B_BPALCD48_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2583 #define LCD_WF8B_BPALCD48_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2584 #define LCD_WF8B_BPALCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD48_SHIFT)) & LCD_WF8B_BPALCD48_MASK)
<> 144:ef7eb2e8f9f7 2585 #define LCD_WF8B_BPALCD47_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2586 #define LCD_WF8B_BPALCD47_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2587 #define LCD_WF8B_BPALCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD47_SHIFT)) & LCD_WF8B_BPALCD47_MASK)
<> 144:ef7eb2e8f9f7 2588 #define LCD_WF8B_BPALCD46_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2589 #define LCD_WF8B_BPALCD46_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2590 #define LCD_WF8B_BPALCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD46_SHIFT)) & LCD_WF8B_BPALCD46_MASK)
<> 144:ef7eb2e8f9f7 2591 #define LCD_WF8B_BPALCD45_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2592 #define LCD_WF8B_BPALCD45_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2593 #define LCD_WF8B_BPALCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD45_SHIFT)) & LCD_WF8B_BPALCD45_MASK)
<> 144:ef7eb2e8f9f7 2594 #define LCD_WF8B_BPALCD44_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2595 #define LCD_WF8B_BPALCD44_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2596 #define LCD_WF8B_BPALCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD44_SHIFT)) & LCD_WF8B_BPALCD44_MASK)
<> 144:ef7eb2e8f9f7 2597 #define LCD_WF8B_BPALCD43_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2598 #define LCD_WF8B_BPALCD43_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2599 #define LCD_WF8B_BPALCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD43_SHIFT)) & LCD_WF8B_BPALCD43_MASK)
<> 144:ef7eb2e8f9f7 2600 #define LCD_WF8B_BPALCD3_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2601 #define LCD_WF8B_BPALCD3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2602 #define LCD_WF8B_BPALCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD3_SHIFT)) & LCD_WF8B_BPALCD3_MASK)
<> 144:ef7eb2e8f9f7 2603 #define LCD_WF8B_BPALCD42_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2604 #define LCD_WF8B_BPALCD42_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2605 #define LCD_WF8B_BPALCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD42_SHIFT)) & LCD_WF8B_BPALCD42_MASK)
<> 144:ef7eb2e8f9f7 2606 #define LCD_WF8B_BPALCD41_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2607 #define LCD_WF8B_BPALCD41_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2608 #define LCD_WF8B_BPALCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD41_SHIFT)) & LCD_WF8B_BPALCD41_MASK)
<> 144:ef7eb2e8f9f7 2609 #define LCD_WF8B_BPALCD40_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2610 #define LCD_WF8B_BPALCD40_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2611 #define LCD_WF8B_BPALCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD40_SHIFT)) & LCD_WF8B_BPALCD40_MASK)
<> 144:ef7eb2e8f9f7 2612 #define LCD_WF8B_BPALCD39_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2613 #define LCD_WF8B_BPALCD39_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2614 #define LCD_WF8B_BPALCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD39_SHIFT)) & LCD_WF8B_BPALCD39_MASK)
<> 144:ef7eb2e8f9f7 2615 #define LCD_WF8B_BPALCD38_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2616 #define LCD_WF8B_BPALCD38_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2617 #define LCD_WF8B_BPALCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD38_SHIFT)) & LCD_WF8B_BPALCD38_MASK)
<> 144:ef7eb2e8f9f7 2618 #define LCD_WF8B_BPALCD37_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2619 #define LCD_WF8B_BPALCD37_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2620 #define LCD_WF8B_BPALCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD37_SHIFT)) & LCD_WF8B_BPALCD37_MASK)
<> 144:ef7eb2e8f9f7 2621 #define LCD_WF8B_BPALCD36_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2622 #define LCD_WF8B_BPALCD36_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2623 #define LCD_WF8B_BPALCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD36_SHIFT)) & LCD_WF8B_BPALCD36_MASK)
<> 144:ef7eb2e8f9f7 2624 #define LCD_WF8B_BPALCD4_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2625 #define LCD_WF8B_BPALCD4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2626 #define LCD_WF8B_BPALCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD4_SHIFT)) & LCD_WF8B_BPALCD4_MASK)
<> 144:ef7eb2e8f9f7 2627 #define LCD_WF8B_BPALCD35_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2628 #define LCD_WF8B_BPALCD35_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2629 #define LCD_WF8B_BPALCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD35_SHIFT)) & LCD_WF8B_BPALCD35_MASK)
<> 144:ef7eb2e8f9f7 2630 #define LCD_WF8B_BPALCD34_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2631 #define LCD_WF8B_BPALCD34_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2632 #define LCD_WF8B_BPALCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD34_SHIFT)) & LCD_WF8B_BPALCD34_MASK)
<> 144:ef7eb2e8f9f7 2633 #define LCD_WF8B_BPALCD33_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2634 #define LCD_WF8B_BPALCD33_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2635 #define LCD_WF8B_BPALCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD33_SHIFT)) & LCD_WF8B_BPALCD33_MASK)
<> 144:ef7eb2e8f9f7 2636 #define LCD_WF8B_BPALCD32_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2637 #define LCD_WF8B_BPALCD32_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2638 #define LCD_WF8B_BPALCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD32_SHIFT)) & LCD_WF8B_BPALCD32_MASK)
<> 144:ef7eb2e8f9f7 2639 #define LCD_WF8B_BPALCD31_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2640 #define LCD_WF8B_BPALCD31_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2641 #define LCD_WF8B_BPALCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD31_SHIFT)) & LCD_WF8B_BPALCD31_MASK)
<> 144:ef7eb2e8f9f7 2642 #define LCD_WF8B_BPALCD30_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2643 #define LCD_WF8B_BPALCD30_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2644 #define LCD_WF8B_BPALCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD30_SHIFT)) & LCD_WF8B_BPALCD30_MASK)
<> 144:ef7eb2e8f9f7 2645 #define LCD_WF8B_BPALCD29_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2646 #define LCD_WF8B_BPALCD29_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2647 #define LCD_WF8B_BPALCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD29_SHIFT)) & LCD_WF8B_BPALCD29_MASK)
<> 144:ef7eb2e8f9f7 2648 #define LCD_WF8B_BPALCD5_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2649 #define LCD_WF8B_BPALCD5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2650 #define LCD_WF8B_BPALCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD5_SHIFT)) & LCD_WF8B_BPALCD5_MASK)
<> 144:ef7eb2e8f9f7 2651 #define LCD_WF8B_BPALCD28_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2652 #define LCD_WF8B_BPALCD28_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2653 #define LCD_WF8B_BPALCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD28_SHIFT)) & LCD_WF8B_BPALCD28_MASK)
<> 144:ef7eb2e8f9f7 2654 #define LCD_WF8B_BPALCD27_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2655 #define LCD_WF8B_BPALCD27_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2656 #define LCD_WF8B_BPALCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD27_SHIFT)) & LCD_WF8B_BPALCD27_MASK)
<> 144:ef7eb2e8f9f7 2657 #define LCD_WF8B_BPALCD26_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2658 #define LCD_WF8B_BPALCD26_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2659 #define LCD_WF8B_BPALCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD26_SHIFT)) & LCD_WF8B_BPALCD26_MASK)
<> 144:ef7eb2e8f9f7 2660 #define LCD_WF8B_BPALCD25_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2661 #define LCD_WF8B_BPALCD25_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2662 #define LCD_WF8B_BPALCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD25_SHIFT)) & LCD_WF8B_BPALCD25_MASK)
<> 144:ef7eb2e8f9f7 2663 #define LCD_WF8B_BPALCD24_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2664 #define LCD_WF8B_BPALCD24_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2665 #define LCD_WF8B_BPALCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD24_SHIFT)) & LCD_WF8B_BPALCD24_MASK)
<> 144:ef7eb2e8f9f7 2666 #define LCD_WF8B_BPALCD23_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2667 #define LCD_WF8B_BPALCD23_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2668 #define LCD_WF8B_BPALCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD23_SHIFT)) & LCD_WF8B_BPALCD23_MASK)
<> 144:ef7eb2e8f9f7 2669 #define LCD_WF8B_BPALCD22_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2670 #define LCD_WF8B_BPALCD22_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2671 #define LCD_WF8B_BPALCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD22_SHIFT)) & LCD_WF8B_BPALCD22_MASK)
<> 144:ef7eb2e8f9f7 2672 #define LCD_WF8B_BPALCD6_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2673 #define LCD_WF8B_BPALCD6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2674 #define LCD_WF8B_BPALCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD6_SHIFT)) & LCD_WF8B_BPALCD6_MASK)
<> 144:ef7eb2e8f9f7 2675 #define LCD_WF8B_BPALCD21_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2676 #define LCD_WF8B_BPALCD21_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2677 #define LCD_WF8B_BPALCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD21_SHIFT)) & LCD_WF8B_BPALCD21_MASK)
<> 144:ef7eb2e8f9f7 2678 #define LCD_WF8B_BPALCD20_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2679 #define LCD_WF8B_BPALCD20_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2680 #define LCD_WF8B_BPALCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD20_SHIFT)) & LCD_WF8B_BPALCD20_MASK)
<> 144:ef7eb2e8f9f7 2681 #define LCD_WF8B_BPALCD19_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2682 #define LCD_WF8B_BPALCD19_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2683 #define LCD_WF8B_BPALCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD19_SHIFT)) & LCD_WF8B_BPALCD19_MASK)
<> 144:ef7eb2e8f9f7 2684 #define LCD_WF8B_BPALCD18_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2685 #define LCD_WF8B_BPALCD18_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2686 #define LCD_WF8B_BPALCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD18_SHIFT)) & LCD_WF8B_BPALCD18_MASK)
<> 144:ef7eb2e8f9f7 2687 #define LCD_WF8B_BPALCD17_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2688 #define LCD_WF8B_BPALCD17_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2689 #define LCD_WF8B_BPALCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD17_SHIFT)) & LCD_WF8B_BPALCD17_MASK)
<> 144:ef7eb2e8f9f7 2690 #define LCD_WF8B_BPALCD16_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2691 #define LCD_WF8B_BPALCD16_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2692 #define LCD_WF8B_BPALCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD16_SHIFT)) & LCD_WF8B_BPALCD16_MASK)
<> 144:ef7eb2e8f9f7 2693 #define LCD_WF8B_BPALCD15_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2694 #define LCD_WF8B_BPALCD15_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2695 #define LCD_WF8B_BPALCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD15_SHIFT)) & LCD_WF8B_BPALCD15_MASK)
<> 144:ef7eb2e8f9f7 2696 #define LCD_WF8B_BPALCD7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2697 #define LCD_WF8B_BPALCD7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2698 #define LCD_WF8B_BPALCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD7_SHIFT)) & LCD_WF8B_BPALCD7_MASK)
<> 144:ef7eb2e8f9f7 2699 #define LCD_WF8B_BPALCD14_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2700 #define LCD_WF8B_BPALCD14_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2701 #define LCD_WF8B_BPALCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD14_SHIFT)) & LCD_WF8B_BPALCD14_MASK)
<> 144:ef7eb2e8f9f7 2702 #define LCD_WF8B_BPALCD13_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2703 #define LCD_WF8B_BPALCD13_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2704 #define LCD_WF8B_BPALCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD13_SHIFT)) & LCD_WF8B_BPALCD13_MASK)
<> 144:ef7eb2e8f9f7 2705 #define LCD_WF8B_BPALCD12_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2706 #define LCD_WF8B_BPALCD12_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2707 #define LCD_WF8B_BPALCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD12_SHIFT)) & LCD_WF8B_BPALCD12_MASK)
<> 144:ef7eb2e8f9f7 2708 #define LCD_WF8B_BPALCD11_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2709 #define LCD_WF8B_BPALCD11_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2710 #define LCD_WF8B_BPALCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD11_SHIFT)) & LCD_WF8B_BPALCD11_MASK)
<> 144:ef7eb2e8f9f7 2711 #define LCD_WF8B_BPALCD10_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2712 #define LCD_WF8B_BPALCD10_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2713 #define LCD_WF8B_BPALCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD10_SHIFT)) & LCD_WF8B_BPALCD10_MASK)
<> 144:ef7eb2e8f9f7 2714 #define LCD_WF8B_BPALCD9_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2715 #define LCD_WF8B_BPALCD9_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2716 #define LCD_WF8B_BPALCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD9_SHIFT)) & LCD_WF8B_BPALCD9_MASK)
<> 144:ef7eb2e8f9f7 2717 #define LCD_WF8B_BPALCD8_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2718 #define LCD_WF8B_BPALCD8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2719 #define LCD_WF8B_BPALCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD8_SHIFT)) & LCD_WF8B_BPALCD8_MASK)
<> 144:ef7eb2e8f9f7 2720 #define LCD_WF8B_BPBLCD1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2721 #define LCD_WF8B_BPBLCD1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2722 #define LCD_WF8B_BPBLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD1_SHIFT)) & LCD_WF8B_BPBLCD1_MASK)
<> 144:ef7eb2e8f9f7 2723 #define LCD_WF8B_BPBLCD32_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2724 #define LCD_WF8B_BPBLCD32_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2725 #define LCD_WF8B_BPBLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD32_SHIFT)) & LCD_WF8B_BPBLCD32_MASK)
<> 144:ef7eb2e8f9f7 2726 #define LCD_WF8B_BPBLCD30_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2727 #define LCD_WF8B_BPBLCD30_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2728 #define LCD_WF8B_BPBLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD30_SHIFT)) & LCD_WF8B_BPBLCD30_MASK)
<> 144:ef7eb2e8f9f7 2729 #define LCD_WF8B_BPBLCD60_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2730 #define LCD_WF8B_BPBLCD60_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2731 #define LCD_WF8B_BPBLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD60_SHIFT)) & LCD_WF8B_BPBLCD60_MASK)
<> 144:ef7eb2e8f9f7 2732 #define LCD_WF8B_BPBLCD24_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2733 #define LCD_WF8B_BPBLCD24_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2734 #define LCD_WF8B_BPBLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD24_SHIFT)) & LCD_WF8B_BPBLCD24_MASK)
<> 144:ef7eb2e8f9f7 2735 #define LCD_WF8B_BPBLCD28_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2736 #define LCD_WF8B_BPBLCD28_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2737 #define LCD_WF8B_BPBLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD28_SHIFT)) & LCD_WF8B_BPBLCD28_MASK)
<> 144:ef7eb2e8f9f7 2738 #define LCD_WF8B_BPBLCD23_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2739 #define LCD_WF8B_BPBLCD23_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2740 #define LCD_WF8B_BPBLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD23_SHIFT)) & LCD_WF8B_BPBLCD23_MASK)
<> 144:ef7eb2e8f9f7 2741 #define LCD_WF8B_BPBLCD48_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2742 #define LCD_WF8B_BPBLCD48_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2743 #define LCD_WF8B_BPBLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD48_SHIFT)) & LCD_WF8B_BPBLCD48_MASK)
<> 144:ef7eb2e8f9f7 2744 #define LCD_WF8B_BPBLCD10_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2745 #define LCD_WF8B_BPBLCD10_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2746 #define LCD_WF8B_BPBLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD10_SHIFT)) & LCD_WF8B_BPBLCD10_MASK)
<> 144:ef7eb2e8f9f7 2747 #define LCD_WF8B_BPBLCD15_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2748 #define LCD_WF8B_BPBLCD15_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2749 #define LCD_WF8B_BPBLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD15_SHIFT)) & LCD_WF8B_BPBLCD15_MASK)
<> 144:ef7eb2e8f9f7 2750 #define LCD_WF8B_BPBLCD36_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2751 #define LCD_WF8B_BPBLCD36_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2752 #define LCD_WF8B_BPBLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD36_SHIFT)) & LCD_WF8B_BPBLCD36_MASK)
<> 144:ef7eb2e8f9f7 2753 #define LCD_WF8B_BPBLCD44_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2754 #define LCD_WF8B_BPBLCD44_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2755 #define LCD_WF8B_BPBLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD44_SHIFT)) & LCD_WF8B_BPBLCD44_MASK)
<> 144:ef7eb2e8f9f7 2756 #define LCD_WF8B_BPBLCD62_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2757 #define LCD_WF8B_BPBLCD62_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2758 #define LCD_WF8B_BPBLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD62_SHIFT)) & LCD_WF8B_BPBLCD62_MASK)
<> 144:ef7eb2e8f9f7 2759 #define LCD_WF8B_BPBLCD53_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2760 #define LCD_WF8B_BPBLCD53_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2761 #define LCD_WF8B_BPBLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD53_SHIFT)) & LCD_WF8B_BPBLCD53_MASK)
<> 144:ef7eb2e8f9f7 2762 #define LCD_WF8B_BPBLCD22_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2763 #define LCD_WF8B_BPBLCD22_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2764 #define LCD_WF8B_BPBLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD22_SHIFT)) & LCD_WF8B_BPBLCD22_MASK)
<> 144:ef7eb2e8f9f7 2765 #define LCD_WF8B_BPBLCD47_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2766 #define LCD_WF8B_BPBLCD47_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2767 #define LCD_WF8B_BPBLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD47_SHIFT)) & LCD_WF8B_BPBLCD47_MASK)
<> 144:ef7eb2e8f9f7 2768 #define LCD_WF8B_BPBLCD33_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2769 #define LCD_WF8B_BPBLCD33_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2770 #define LCD_WF8B_BPBLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD33_SHIFT)) & LCD_WF8B_BPBLCD33_MASK)
<> 144:ef7eb2e8f9f7 2771 #define LCD_WF8B_BPBLCD2_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2772 #define LCD_WF8B_BPBLCD2_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2773 #define LCD_WF8B_BPBLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD2_SHIFT)) & LCD_WF8B_BPBLCD2_MASK)
<> 144:ef7eb2e8f9f7 2774 #define LCD_WF8B_BPBLCD49_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2775 #define LCD_WF8B_BPBLCD49_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2776 #define LCD_WF8B_BPBLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD49_SHIFT)) & LCD_WF8B_BPBLCD49_MASK)
<> 144:ef7eb2e8f9f7 2777 #define LCD_WF8B_BPBLCD0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2778 #define LCD_WF8B_BPBLCD0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2779 #define LCD_WF8B_BPBLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD0_SHIFT)) & LCD_WF8B_BPBLCD0_MASK)
<> 144:ef7eb2e8f9f7 2780 #define LCD_WF8B_BPBLCD55_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2781 #define LCD_WF8B_BPBLCD55_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2782 #define LCD_WF8B_BPBLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD55_SHIFT)) & LCD_WF8B_BPBLCD55_MASK)
<> 144:ef7eb2e8f9f7 2783 #define LCD_WF8B_BPBLCD56_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2784 #define LCD_WF8B_BPBLCD56_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2785 #define LCD_WF8B_BPBLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD56_SHIFT)) & LCD_WF8B_BPBLCD56_MASK)
<> 144:ef7eb2e8f9f7 2786 #define LCD_WF8B_BPBLCD21_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2787 #define LCD_WF8B_BPBLCD21_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2788 #define LCD_WF8B_BPBLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD21_SHIFT)) & LCD_WF8B_BPBLCD21_MASK)
<> 144:ef7eb2e8f9f7 2789 #define LCD_WF8B_BPBLCD6_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2790 #define LCD_WF8B_BPBLCD6_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2791 #define LCD_WF8B_BPBLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD6_SHIFT)) & LCD_WF8B_BPBLCD6_MASK)
<> 144:ef7eb2e8f9f7 2792 #define LCD_WF8B_BPBLCD29_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2793 #define LCD_WF8B_BPBLCD29_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2794 #define LCD_WF8B_BPBLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD29_SHIFT)) & LCD_WF8B_BPBLCD29_MASK)
<> 144:ef7eb2e8f9f7 2795 #define LCD_WF8B_BPBLCD25_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2796 #define LCD_WF8B_BPBLCD25_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2797 #define LCD_WF8B_BPBLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD25_SHIFT)) & LCD_WF8B_BPBLCD25_MASK)
<> 144:ef7eb2e8f9f7 2798 #define LCD_WF8B_BPBLCD8_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2799 #define LCD_WF8B_BPBLCD8_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2800 #define LCD_WF8B_BPBLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD8_SHIFT)) & LCD_WF8B_BPBLCD8_MASK)
<> 144:ef7eb2e8f9f7 2801 #define LCD_WF8B_BPBLCD54_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2802 #define LCD_WF8B_BPBLCD54_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2803 #define LCD_WF8B_BPBLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD54_SHIFT)) & LCD_WF8B_BPBLCD54_MASK)
<> 144:ef7eb2e8f9f7 2804 #define LCD_WF8B_BPBLCD38_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2805 #define LCD_WF8B_BPBLCD38_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2806 #define LCD_WF8B_BPBLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD38_SHIFT)) & LCD_WF8B_BPBLCD38_MASK)
<> 144:ef7eb2e8f9f7 2807 #define LCD_WF8B_BPBLCD43_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2808 #define LCD_WF8B_BPBLCD43_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2809 #define LCD_WF8B_BPBLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD43_SHIFT)) & LCD_WF8B_BPBLCD43_MASK)
<> 144:ef7eb2e8f9f7 2810 #define LCD_WF8B_BPBLCD20_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2811 #define LCD_WF8B_BPBLCD20_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2812 #define LCD_WF8B_BPBLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD20_SHIFT)) & LCD_WF8B_BPBLCD20_MASK)
<> 144:ef7eb2e8f9f7 2813 #define LCD_WF8B_BPBLCD9_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2814 #define LCD_WF8B_BPBLCD9_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2815 #define LCD_WF8B_BPBLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD9_SHIFT)) & LCD_WF8B_BPBLCD9_MASK)
<> 144:ef7eb2e8f9f7 2816 #define LCD_WF8B_BPBLCD7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2817 #define LCD_WF8B_BPBLCD7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2818 #define LCD_WF8B_BPBLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD7_SHIFT)) & LCD_WF8B_BPBLCD7_MASK)
<> 144:ef7eb2e8f9f7 2819 #define LCD_WF8B_BPBLCD50_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2820 #define LCD_WF8B_BPBLCD50_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2821 #define LCD_WF8B_BPBLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD50_SHIFT)) & LCD_WF8B_BPBLCD50_MASK)
<> 144:ef7eb2e8f9f7 2822 #define LCD_WF8B_BPBLCD40_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2823 #define LCD_WF8B_BPBLCD40_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2824 #define LCD_WF8B_BPBLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD40_SHIFT)) & LCD_WF8B_BPBLCD40_MASK)
<> 144:ef7eb2e8f9f7 2825 #define LCD_WF8B_BPBLCD63_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2826 #define LCD_WF8B_BPBLCD63_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2827 #define LCD_WF8B_BPBLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD63_SHIFT)) & LCD_WF8B_BPBLCD63_MASK)
<> 144:ef7eb2e8f9f7 2828 #define LCD_WF8B_BPBLCD26_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2829 #define LCD_WF8B_BPBLCD26_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2830 #define LCD_WF8B_BPBLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD26_SHIFT)) & LCD_WF8B_BPBLCD26_MASK)
<> 144:ef7eb2e8f9f7 2831 #define LCD_WF8B_BPBLCD12_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2832 #define LCD_WF8B_BPBLCD12_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2833 #define LCD_WF8B_BPBLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD12_SHIFT)) & LCD_WF8B_BPBLCD12_MASK)
<> 144:ef7eb2e8f9f7 2834 #define LCD_WF8B_BPBLCD19_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2835 #define LCD_WF8B_BPBLCD19_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2836 #define LCD_WF8B_BPBLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD19_SHIFT)) & LCD_WF8B_BPBLCD19_MASK)
<> 144:ef7eb2e8f9f7 2837 #define LCD_WF8B_BPBLCD34_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2838 #define LCD_WF8B_BPBLCD34_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2839 #define LCD_WF8B_BPBLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD34_SHIFT)) & LCD_WF8B_BPBLCD34_MASK)
<> 144:ef7eb2e8f9f7 2840 #define LCD_WF8B_BPBLCD39_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2841 #define LCD_WF8B_BPBLCD39_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2842 #define LCD_WF8B_BPBLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD39_SHIFT)) & LCD_WF8B_BPBLCD39_MASK)
<> 144:ef7eb2e8f9f7 2843 #define LCD_WF8B_BPBLCD59_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2844 #define LCD_WF8B_BPBLCD59_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2845 #define LCD_WF8B_BPBLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD59_SHIFT)) & LCD_WF8B_BPBLCD59_MASK)
<> 144:ef7eb2e8f9f7 2846 #define LCD_WF8B_BPBLCD61_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2847 #define LCD_WF8B_BPBLCD61_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2848 #define LCD_WF8B_BPBLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD61_SHIFT)) & LCD_WF8B_BPBLCD61_MASK)
<> 144:ef7eb2e8f9f7 2849 #define LCD_WF8B_BPBLCD37_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2850 #define LCD_WF8B_BPBLCD37_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2851 #define LCD_WF8B_BPBLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD37_SHIFT)) & LCD_WF8B_BPBLCD37_MASK)
<> 144:ef7eb2e8f9f7 2852 #define LCD_WF8B_BPBLCD31_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2853 #define LCD_WF8B_BPBLCD31_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2854 #define LCD_WF8B_BPBLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD31_SHIFT)) & LCD_WF8B_BPBLCD31_MASK)
<> 144:ef7eb2e8f9f7 2855 #define LCD_WF8B_BPBLCD58_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2856 #define LCD_WF8B_BPBLCD58_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2857 #define LCD_WF8B_BPBLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD58_SHIFT)) & LCD_WF8B_BPBLCD58_MASK)
<> 144:ef7eb2e8f9f7 2858 #define LCD_WF8B_BPBLCD18_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2859 #define LCD_WF8B_BPBLCD18_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2860 #define LCD_WF8B_BPBLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD18_SHIFT)) & LCD_WF8B_BPBLCD18_MASK)
<> 144:ef7eb2e8f9f7 2861 #define LCD_WF8B_BPBLCD45_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2862 #define LCD_WF8B_BPBLCD45_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2863 #define LCD_WF8B_BPBLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD45_SHIFT)) & LCD_WF8B_BPBLCD45_MASK)
<> 144:ef7eb2e8f9f7 2864 #define LCD_WF8B_BPBLCD27_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2865 #define LCD_WF8B_BPBLCD27_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2866 #define LCD_WF8B_BPBLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD27_SHIFT)) & LCD_WF8B_BPBLCD27_MASK)
<> 144:ef7eb2e8f9f7 2867 #define LCD_WF8B_BPBLCD14_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2868 #define LCD_WF8B_BPBLCD14_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2869 #define LCD_WF8B_BPBLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD14_SHIFT)) & LCD_WF8B_BPBLCD14_MASK)
<> 144:ef7eb2e8f9f7 2870 #define LCD_WF8B_BPBLCD51_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2871 #define LCD_WF8B_BPBLCD51_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2872 #define LCD_WF8B_BPBLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD51_SHIFT)) & LCD_WF8B_BPBLCD51_MASK)
<> 144:ef7eb2e8f9f7 2873 #define LCD_WF8B_BPBLCD52_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2874 #define LCD_WF8B_BPBLCD52_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2875 #define LCD_WF8B_BPBLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD52_SHIFT)) & LCD_WF8B_BPBLCD52_MASK)
<> 144:ef7eb2e8f9f7 2876 #define LCD_WF8B_BPBLCD4_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2877 #define LCD_WF8B_BPBLCD4_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2878 #define LCD_WF8B_BPBLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD4_SHIFT)) & LCD_WF8B_BPBLCD4_MASK)
<> 144:ef7eb2e8f9f7 2879 #define LCD_WF8B_BPBLCD35_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2880 #define LCD_WF8B_BPBLCD35_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2881 #define LCD_WF8B_BPBLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD35_SHIFT)) & LCD_WF8B_BPBLCD35_MASK)
<> 144:ef7eb2e8f9f7 2882 #define LCD_WF8B_BPBLCD17_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2883 #define LCD_WF8B_BPBLCD17_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2884 #define LCD_WF8B_BPBLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD17_SHIFT)) & LCD_WF8B_BPBLCD17_MASK)
<> 144:ef7eb2e8f9f7 2885 #define LCD_WF8B_BPBLCD41_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2886 #define LCD_WF8B_BPBLCD41_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2887 #define LCD_WF8B_BPBLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD41_SHIFT)) & LCD_WF8B_BPBLCD41_MASK)
<> 144:ef7eb2e8f9f7 2888 #define LCD_WF8B_BPBLCD11_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2889 #define LCD_WF8B_BPBLCD11_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2890 #define LCD_WF8B_BPBLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD11_SHIFT)) & LCD_WF8B_BPBLCD11_MASK)
<> 144:ef7eb2e8f9f7 2891 #define LCD_WF8B_BPBLCD46_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2892 #define LCD_WF8B_BPBLCD46_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2893 #define LCD_WF8B_BPBLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD46_SHIFT)) & LCD_WF8B_BPBLCD46_MASK)
<> 144:ef7eb2e8f9f7 2894 #define LCD_WF8B_BPBLCD57_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2895 #define LCD_WF8B_BPBLCD57_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2896 #define LCD_WF8B_BPBLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD57_SHIFT)) & LCD_WF8B_BPBLCD57_MASK)
<> 144:ef7eb2e8f9f7 2897 #define LCD_WF8B_BPBLCD42_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2898 #define LCD_WF8B_BPBLCD42_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2899 #define LCD_WF8B_BPBLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD42_SHIFT)) & LCD_WF8B_BPBLCD42_MASK)
<> 144:ef7eb2e8f9f7 2900 #define LCD_WF8B_BPBLCD5_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2901 #define LCD_WF8B_BPBLCD5_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2902 #define LCD_WF8B_BPBLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD5_SHIFT)) & LCD_WF8B_BPBLCD5_MASK)
<> 144:ef7eb2e8f9f7 2903 #define LCD_WF8B_BPBLCD3_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2904 #define LCD_WF8B_BPBLCD3_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2905 #define LCD_WF8B_BPBLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD3_SHIFT)) & LCD_WF8B_BPBLCD3_MASK)
<> 144:ef7eb2e8f9f7 2906 #define LCD_WF8B_BPBLCD16_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2907 #define LCD_WF8B_BPBLCD16_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2908 #define LCD_WF8B_BPBLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD16_SHIFT)) & LCD_WF8B_BPBLCD16_MASK)
<> 144:ef7eb2e8f9f7 2909 #define LCD_WF8B_BPBLCD13_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2910 #define LCD_WF8B_BPBLCD13_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2911 #define LCD_WF8B_BPBLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD13_SHIFT)) & LCD_WF8B_BPBLCD13_MASK)
<> 144:ef7eb2e8f9f7 2912 #define LCD_WF8B_BPCLCD10_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2913 #define LCD_WF8B_BPCLCD10_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2914 #define LCD_WF8B_BPCLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD10_SHIFT)) & LCD_WF8B_BPCLCD10_MASK)
<> 144:ef7eb2e8f9f7 2915 #define LCD_WF8B_BPCLCD55_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2916 #define LCD_WF8B_BPCLCD55_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2917 #define LCD_WF8B_BPCLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD55_SHIFT)) & LCD_WF8B_BPCLCD55_MASK)
<> 144:ef7eb2e8f9f7 2918 #define LCD_WF8B_BPCLCD2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2919 #define LCD_WF8B_BPCLCD2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2920 #define LCD_WF8B_BPCLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD2_SHIFT)) & LCD_WF8B_BPCLCD2_MASK)
<> 144:ef7eb2e8f9f7 2921 #define LCD_WF8B_BPCLCD23_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2922 #define LCD_WF8B_BPCLCD23_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2923 #define LCD_WF8B_BPCLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD23_SHIFT)) & LCD_WF8B_BPCLCD23_MASK)
<> 144:ef7eb2e8f9f7 2924 #define LCD_WF8B_BPCLCD48_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2925 #define LCD_WF8B_BPCLCD48_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2926 #define LCD_WF8B_BPCLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD48_SHIFT)) & LCD_WF8B_BPCLCD48_MASK)
<> 144:ef7eb2e8f9f7 2927 #define LCD_WF8B_BPCLCD24_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2928 #define LCD_WF8B_BPCLCD24_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2929 #define LCD_WF8B_BPCLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD24_SHIFT)) & LCD_WF8B_BPCLCD24_MASK)
<> 144:ef7eb2e8f9f7 2930 #define LCD_WF8B_BPCLCD60_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2931 #define LCD_WF8B_BPCLCD60_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2932 #define LCD_WF8B_BPCLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD60_SHIFT)) & LCD_WF8B_BPCLCD60_MASK)
<> 144:ef7eb2e8f9f7 2933 #define LCD_WF8B_BPCLCD47_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2934 #define LCD_WF8B_BPCLCD47_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2935 #define LCD_WF8B_BPCLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD47_SHIFT)) & LCD_WF8B_BPCLCD47_MASK)
<> 144:ef7eb2e8f9f7 2936 #define LCD_WF8B_BPCLCD22_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2937 #define LCD_WF8B_BPCLCD22_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2938 #define LCD_WF8B_BPCLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD22_SHIFT)) & LCD_WF8B_BPCLCD22_MASK)
<> 144:ef7eb2e8f9f7 2939 #define LCD_WF8B_BPCLCD8_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2940 #define LCD_WF8B_BPCLCD8_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2941 #define LCD_WF8B_BPCLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD8_SHIFT)) & LCD_WF8B_BPCLCD8_MASK)
<> 144:ef7eb2e8f9f7 2942 #define LCD_WF8B_BPCLCD21_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2943 #define LCD_WF8B_BPCLCD21_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2944 #define LCD_WF8B_BPCLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD21_SHIFT)) & LCD_WF8B_BPCLCD21_MASK)
<> 144:ef7eb2e8f9f7 2945 #define LCD_WF8B_BPCLCD49_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2946 #define LCD_WF8B_BPCLCD49_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2947 #define LCD_WF8B_BPCLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD49_SHIFT)) & LCD_WF8B_BPCLCD49_MASK)
<> 144:ef7eb2e8f9f7 2948 #define LCD_WF8B_BPCLCD25_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2949 #define LCD_WF8B_BPCLCD25_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2950 #define LCD_WF8B_BPCLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD25_SHIFT)) & LCD_WF8B_BPCLCD25_MASK)
<> 144:ef7eb2e8f9f7 2951 #define LCD_WF8B_BPCLCD1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2952 #define LCD_WF8B_BPCLCD1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2953 #define LCD_WF8B_BPCLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD1_SHIFT)) & LCD_WF8B_BPCLCD1_MASK)
<> 144:ef7eb2e8f9f7 2954 #define LCD_WF8B_BPCLCD20_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2955 #define LCD_WF8B_BPCLCD20_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2956 #define LCD_WF8B_BPCLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD20_SHIFT)) & LCD_WF8B_BPCLCD20_MASK)
<> 144:ef7eb2e8f9f7 2957 #define LCD_WF8B_BPCLCD50_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2958 #define LCD_WF8B_BPCLCD50_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2959 #define LCD_WF8B_BPCLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD50_SHIFT)) & LCD_WF8B_BPCLCD50_MASK)
<> 144:ef7eb2e8f9f7 2960 #define LCD_WF8B_BPCLCD19_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2961 #define LCD_WF8B_BPCLCD19_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2962 #define LCD_WF8B_BPCLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD19_SHIFT)) & LCD_WF8B_BPCLCD19_MASK)
<> 144:ef7eb2e8f9f7 2963 #define LCD_WF8B_BPCLCD26_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2964 #define LCD_WF8B_BPCLCD26_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2965 #define LCD_WF8B_BPCLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD26_SHIFT)) & LCD_WF8B_BPCLCD26_MASK)
<> 144:ef7eb2e8f9f7 2966 #define LCD_WF8B_BPCLCD59_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2967 #define LCD_WF8B_BPCLCD59_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2968 #define LCD_WF8B_BPCLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD59_SHIFT)) & LCD_WF8B_BPCLCD59_MASK)
<> 144:ef7eb2e8f9f7 2969 #define LCD_WF8B_BPCLCD61_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2970 #define LCD_WF8B_BPCLCD61_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2971 #define LCD_WF8B_BPCLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD61_SHIFT)) & LCD_WF8B_BPCLCD61_MASK)
<> 144:ef7eb2e8f9f7 2972 #define LCD_WF8B_BPCLCD46_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2973 #define LCD_WF8B_BPCLCD46_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2974 #define LCD_WF8B_BPCLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD46_SHIFT)) & LCD_WF8B_BPCLCD46_MASK)
<> 144:ef7eb2e8f9f7 2975 #define LCD_WF8B_BPCLCD18_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2976 #define LCD_WF8B_BPCLCD18_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2977 #define LCD_WF8B_BPCLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD18_SHIFT)) & LCD_WF8B_BPCLCD18_MASK)
<> 144:ef7eb2e8f9f7 2978 #define LCD_WF8B_BPCLCD5_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2979 #define LCD_WF8B_BPCLCD5_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2980 #define LCD_WF8B_BPCLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD5_SHIFT)) & LCD_WF8B_BPCLCD5_MASK)
<> 144:ef7eb2e8f9f7 2981 #define LCD_WF8B_BPCLCD63_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2982 #define LCD_WF8B_BPCLCD63_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2983 #define LCD_WF8B_BPCLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD63_SHIFT)) & LCD_WF8B_BPCLCD63_MASK)
<> 144:ef7eb2e8f9f7 2984 #define LCD_WF8B_BPCLCD27_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2985 #define LCD_WF8B_BPCLCD27_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2986 #define LCD_WF8B_BPCLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD27_SHIFT)) & LCD_WF8B_BPCLCD27_MASK)
<> 144:ef7eb2e8f9f7 2987 #define LCD_WF8B_BPCLCD17_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2988 #define LCD_WF8B_BPCLCD17_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2989 #define LCD_WF8B_BPCLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD17_SHIFT)) & LCD_WF8B_BPCLCD17_MASK)
<> 144:ef7eb2e8f9f7 2990 #define LCD_WF8B_BPCLCD51_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2991 #define LCD_WF8B_BPCLCD51_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2992 #define LCD_WF8B_BPCLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD51_SHIFT)) & LCD_WF8B_BPCLCD51_MASK)
<> 144:ef7eb2e8f9f7 2993 #define LCD_WF8B_BPCLCD9_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2994 #define LCD_WF8B_BPCLCD9_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2995 #define LCD_WF8B_BPCLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD9_SHIFT)) & LCD_WF8B_BPCLCD9_MASK)
<> 144:ef7eb2e8f9f7 2996 #define LCD_WF8B_BPCLCD54_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2997 #define LCD_WF8B_BPCLCD54_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2998 #define LCD_WF8B_BPCLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD54_SHIFT)) & LCD_WF8B_BPCLCD54_MASK)
<> 144:ef7eb2e8f9f7 2999 #define LCD_WF8B_BPCLCD15_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3000 #define LCD_WF8B_BPCLCD15_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3001 #define LCD_WF8B_BPCLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD15_SHIFT)) & LCD_WF8B_BPCLCD15_MASK)
<> 144:ef7eb2e8f9f7 3002 #define LCD_WF8B_BPCLCD16_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3003 #define LCD_WF8B_BPCLCD16_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3004 #define LCD_WF8B_BPCLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD16_SHIFT)) & LCD_WF8B_BPCLCD16_MASK)
<> 144:ef7eb2e8f9f7 3005 #define LCD_WF8B_BPCLCD14_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3006 #define LCD_WF8B_BPCLCD14_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3007 #define LCD_WF8B_BPCLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD14_SHIFT)) & LCD_WF8B_BPCLCD14_MASK)
<> 144:ef7eb2e8f9f7 3008 #define LCD_WF8B_BPCLCD32_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3009 #define LCD_WF8B_BPCLCD32_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3010 #define LCD_WF8B_BPCLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD32_SHIFT)) & LCD_WF8B_BPCLCD32_MASK)
<> 144:ef7eb2e8f9f7 3011 #define LCD_WF8B_BPCLCD28_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3012 #define LCD_WF8B_BPCLCD28_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3013 #define LCD_WF8B_BPCLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD28_SHIFT)) & LCD_WF8B_BPCLCD28_MASK)
<> 144:ef7eb2e8f9f7 3014 #define LCD_WF8B_BPCLCD53_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3015 #define LCD_WF8B_BPCLCD53_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3016 #define LCD_WF8B_BPCLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD53_SHIFT)) & LCD_WF8B_BPCLCD53_MASK)
<> 144:ef7eb2e8f9f7 3017 #define LCD_WF8B_BPCLCD33_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3018 #define LCD_WF8B_BPCLCD33_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3019 #define LCD_WF8B_BPCLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD33_SHIFT)) & LCD_WF8B_BPCLCD33_MASK)
<> 144:ef7eb2e8f9f7 3020 #define LCD_WF8B_BPCLCD0_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3021 #define LCD_WF8B_BPCLCD0_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3022 #define LCD_WF8B_BPCLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD0_SHIFT)) & LCD_WF8B_BPCLCD0_MASK)
<> 144:ef7eb2e8f9f7 3023 #define LCD_WF8B_BPCLCD43_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3024 #define LCD_WF8B_BPCLCD43_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3025 #define LCD_WF8B_BPCLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD43_SHIFT)) & LCD_WF8B_BPCLCD43_MASK)
<> 144:ef7eb2e8f9f7 3026 #define LCD_WF8B_BPCLCD7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3027 #define LCD_WF8B_BPCLCD7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3028 #define LCD_WF8B_BPCLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD7_SHIFT)) & LCD_WF8B_BPCLCD7_MASK)
<> 144:ef7eb2e8f9f7 3029 #define LCD_WF8B_BPCLCD4_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3030 #define LCD_WF8B_BPCLCD4_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3031 #define LCD_WF8B_BPCLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD4_SHIFT)) & LCD_WF8B_BPCLCD4_MASK)
<> 144:ef7eb2e8f9f7 3032 #define LCD_WF8B_BPCLCD34_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3033 #define LCD_WF8B_BPCLCD34_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3034 #define LCD_WF8B_BPCLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD34_SHIFT)) & LCD_WF8B_BPCLCD34_MASK)
<> 144:ef7eb2e8f9f7 3035 #define LCD_WF8B_BPCLCD29_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3036 #define LCD_WF8B_BPCLCD29_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3037 #define LCD_WF8B_BPCLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD29_SHIFT)) & LCD_WF8B_BPCLCD29_MASK)
<> 144:ef7eb2e8f9f7 3038 #define LCD_WF8B_BPCLCD45_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3039 #define LCD_WF8B_BPCLCD45_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3040 #define LCD_WF8B_BPCLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD45_SHIFT)) & LCD_WF8B_BPCLCD45_MASK)
<> 144:ef7eb2e8f9f7 3041 #define LCD_WF8B_BPCLCD57_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3042 #define LCD_WF8B_BPCLCD57_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3043 #define LCD_WF8B_BPCLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD57_SHIFT)) & LCD_WF8B_BPCLCD57_MASK)
<> 144:ef7eb2e8f9f7 3044 #define LCD_WF8B_BPCLCD42_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3045 #define LCD_WF8B_BPCLCD42_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3046 #define LCD_WF8B_BPCLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD42_SHIFT)) & LCD_WF8B_BPCLCD42_MASK)
<> 144:ef7eb2e8f9f7 3047 #define LCD_WF8B_BPCLCD35_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3048 #define LCD_WF8B_BPCLCD35_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3049 #define LCD_WF8B_BPCLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD35_SHIFT)) & LCD_WF8B_BPCLCD35_MASK)
<> 144:ef7eb2e8f9f7 3050 #define LCD_WF8B_BPCLCD13_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3051 #define LCD_WF8B_BPCLCD13_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3052 #define LCD_WF8B_BPCLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD13_SHIFT)) & LCD_WF8B_BPCLCD13_MASK)
<> 144:ef7eb2e8f9f7 3053 #define LCD_WF8B_BPCLCD36_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3054 #define LCD_WF8B_BPCLCD36_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3055 #define LCD_WF8B_BPCLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD36_SHIFT)) & LCD_WF8B_BPCLCD36_MASK)
<> 144:ef7eb2e8f9f7 3056 #define LCD_WF8B_BPCLCD30_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3057 #define LCD_WF8B_BPCLCD30_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3058 #define LCD_WF8B_BPCLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD30_SHIFT)) & LCD_WF8B_BPCLCD30_MASK)
<> 144:ef7eb2e8f9f7 3059 #define LCD_WF8B_BPCLCD52_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3060 #define LCD_WF8B_BPCLCD52_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3061 #define LCD_WF8B_BPCLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD52_SHIFT)) & LCD_WF8B_BPCLCD52_MASK)
<> 144:ef7eb2e8f9f7 3062 #define LCD_WF8B_BPCLCD58_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3063 #define LCD_WF8B_BPCLCD58_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3064 #define LCD_WF8B_BPCLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD58_SHIFT)) & LCD_WF8B_BPCLCD58_MASK)
<> 144:ef7eb2e8f9f7 3065 #define LCD_WF8B_BPCLCD41_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3066 #define LCD_WF8B_BPCLCD41_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3067 #define LCD_WF8B_BPCLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD41_SHIFT)) & LCD_WF8B_BPCLCD41_MASK)
<> 144:ef7eb2e8f9f7 3068 #define LCD_WF8B_BPCLCD37_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3069 #define LCD_WF8B_BPCLCD37_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3070 #define LCD_WF8B_BPCLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD37_SHIFT)) & LCD_WF8B_BPCLCD37_MASK)
<> 144:ef7eb2e8f9f7 3071 #define LCD_WF8B_BPCLCD3_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3072 #define LCD_WF8B_BPCLCD3_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3073 #define LCD_WF8B_BPCLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD3_SHIFT)) & LCD_WF8B_BPCLCD3_MASK)
<> 144:ef7eb2e8f9f7 3074 #define LCD_WF8B_BPCLCD12_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3075 #define LCD_WF8B_BPCLCD12_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3076 #define LCD_WF8B_BPCLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD12_SHIFT)) & LCD_WF8B_BPCLCD12_MASK)
<> 144:ef7eb2e8f9f7 3077 #define LCD_WF8B_BPCLCD11_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3078 #define LCD_WF8B_BPCLCD11_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3079 #define LCD_WF8B_BPCLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD11_SHIFT)) & LCD_WF8B_BPCLCD11_MASK)
<> 144:ef7eb2e8f9f7 3080 #define LCD_WF8B_BPCLCD38_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3081 #define LCD_WF8B_BPCLCD38_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3082 #define LCD_WF8B_BPCLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD38_SHIFT)) & LCD_WF8B_BPCLCD38_MASK)
<> 144:ef7eb2e8f9f7 3083 #define LCD_WF8B_BPCLCD44_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3084 #define LCD_WF8B_BPCLCD44_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3085 #define LCD_WF8B_BPCLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD44_SHIFT)) & LCD_WF8B_BPCLCD44_MASK)
<> 144:ef7eb2e8f9f7 3086 #define LCD_WF8B_BPCLCD31_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3087 #define LCD_WF8B_BPCLCD31_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3088 #define LCD_WF8B_BPCLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD31_SHIFT)) & LCD_WF8B_BPCLCD31_MASK)
<> 144:ef7eb2e8f9f7 3089 #define LCD_WF8B_BPCLCD40_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3090 #define LCD_WF8B_BPCLCD40_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3091 #define LCD_WF8B_BPCLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD40_SHIFT)) & LCD_WF8B_BPCLCD40_MASK)
<> 144:ef7eb2e8f9f7 3092 #define LCD_WF8B_BPCLCD62_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3093 #define LCD_WF8B_BPCLCD62_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3094 #define LCD_WF8B_BPCLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD62_SHIFT)) & LCD_WF8B_BPCLCD62_MASK)
<> 144:ef7eb2e8f9f7 3095 #define LCD_WF8B_BPCLCD56_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3096 #define LCD_WF8B_BPCLCD56_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3097 #define LCD_WF8B_BPCLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD56_SHIFT)) & LCD_WF8B_BPCLCD56_MASK)
<> 144:ef7eb2e8f9f7 3098 #define LCD_WF8B_BPCLCD39_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3099 #define LCD_WF8B_BPCLCD39_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3100 #define LCD_WF8B_BPCLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD39_SHIFT)) & LCD_WF8B_BPCLCD39_MASK)
<> 144:ef7eb2e8f9f7 3101 #define LCD_WF8B_BPCLCD6_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3102 #define LCD_WF8B_BPCLCD6_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3103 #define LCD_WF8B_BPCLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD6_SHIFT)) & LCD_WF8B_BPCLCD6_MASK)
<> 144:ef7eb2e8f9f7 3104 #define LCD_WF8B_BPDLCD47_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3105 #define LCD_WF8B_BPDLCD47_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3106 #define LCD_WF8B_BPDLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD47_SHIFT)) & LCD_WF8B_BPDLCD47_MASK)
<> 144:ef7eb2e8f9f7 3107 #define LCD_WF8B_BPDLCD23_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3108 #define LCD_WF8B_BPDLCD23_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3109 #define LCD_WF8B_BPDLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD23_SHIFT)) & LCD_WF8B_BPDLCD23_MASK)
<> 144:ef7eb2e8f9f7 3110 #define LCD_WF8B_BPDLCD48_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3111 #define LCD_WF8B_BPDLCD48_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3112 #define LCD_WF8B_BPDLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD48_SHIFT)) & LCD_WF8B_BPDLCD48_MASK)
<> 144:ef7eb2e8f9f7 3113 #define LCD_WF8B_BPDLCD24_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3114 #define LCD_WF8B_BPDLCD24_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3115 #define LCD_WF8B_BPDLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD24_SHIFT)) & LCD_WF8B_BPDLCD24_MASK)
<> 144:ef7eb2e8f9f7 3116 #define LCD_WF8B_BPDLCD15_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3117 #define LCD_WF8B_BPDLCD15_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3118 #define LCD_WF8B_BPDLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD15_SHIFT)) & LCD_WF8B_BPDLCD15_MASK)
<> 144:ef7eb2e8f9f7 3119 #define LCD_WF8B_BPDLCD22_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3120 #define LCD_WF8B_BPDLCD22_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3121 #define LCD_WF8B_BPDLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD22_SHIFT)) & LCD_WF8B_BPDLCD22_MASK)
<> 144:ef7eb2e8f9f7 3122 #define LCD_WF8B_BPDLCD60_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3123 #define LCD_WF8B_BPDLCD60_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3124 #define LCD_WF8B_BPDLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD60_SHIFT)) & LCD_WF8B_BPDLCD60_MASK)
<> 144:ef7eb2e8f9f7 3125 #define LCD_WF8B_BPDLCD10_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3126 #define LCD_WF8B_BPDLCD10_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3127 #define LCD_WF8B_BPDLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD10_SHIFT)) & LCD_WF8B_BPDLCD10_MASK)
<> 144:ef7eb2e8f9f7 3128 #define LCD_WF8B_BPDLCD21_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3129 #define LCD_WF8B_BPDLCD21_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3130 #define LCD_WF8B_BPDLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD21_SHIFT)) & LCD_WF8B_BPDLCD21_MASK)
<> 144:ef7eb2e8f9f7 3131 #define LCD_WF8B_BPDLCD49_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3132 #define LCD_WF8B_BPDLCD49_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3133 #define LCD_WF8B_BPDLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD49_SHIFT)) & LCD_WF8B_BPDLCD49_MASK)
<> 144:ef7eb2e8f9f7 3134 #define LCD_WF8B_BPDLCD1_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3135 #define LCD_WF8B_BPDLCD1_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3136 #define LCD_WF8B_BPDLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD1_SHIFT)) & LCD_WF8B_BPDLCD1_MASK)
<> 144:ef7eb2e8f9f7 3137 #define LCD_WF8B_BPDLCD25_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3138 #define LCD_WF8B_BPDLCD25_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3139 #define LCD_WF8B_BPDLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD25_SHIFT)) & LCD_WF8B_BPDLCD25_MASK)
<> 144:ef7eb2e8f9f7 3140 #define LCD_WF8B_BPDLCD20_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3141 #define LCD_WF8B_BPDLCD20_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3142 #define LCD_WF8B_BPDLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD20_SHIFT)) & LCD_WF8B_BPDLCD20_MASK)
<> 144:ef7eb2e8f9f7 3143 #define LCD_WF8B_BPDLCD2_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3144 #define LCD_WF8B_BPDLCD2_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3145 #define LCD_WF8B_BPDLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD2_SHIFT)) & LCD_WF8B_BPDLCD2_MASK)
<> 144:ef7eb2e8f9f7 3146 #define LCD_WF8B_BPDLCD55_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3147 #define LCD_WF8B_BPDLCD55_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3148 #define LCD_WF8B_BPDLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD55_SHIFT)) & LCD_WF8B_BPDLCD55_MASK)
<> 144:ef7eb2e8f9f7 3149 #define LCD_WF8B_BPDLCD59_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3150 #define LCD_WF8B_BPDLCD59_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3151 #define LCD_WF8B_BPDLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD59_SHIFT)) & LCD_WF8B_BPDLCD59_MASK)
<> 144:ef7eb2e8f9f7 3152 #define LCD_WF8B_BPDLCD5_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3153 #define LCD_WF8B_BPDLCD5_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3154 #define LCD_WF8B_BPDLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD5_SHIFT)) & LCD_WF8B_BPDLCD5_MASK)
<> 144:ef7eb2e8f9f7 3155 #define LCD_WF8B_BPDLCD19_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3156 #define LCD_WF8B_BPDLCD19_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3157 #define LCD_WF8B_BPDLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD19_SHIFT)) & LCD_WF8B_BPDLCD19_MASK)
<> 144:ef7eb2e8f9f7 3158 #define LCD_WF8B_BPDLCD6_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3159 #define LCD_WF8B_BPDLCD6_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3160 #define LCD_WF8B_BPDLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD6_SHIFT)) & LCD_WF8B_BPDLCD6_MASK)
<> 144:ef7eb2e8f9f7 3161 #define LCD_WF8B_BPDLCD26_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3162 #define LCD_WF8B_BPDLCD26_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3163 #define LCD_WF8B_BPDLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD26_SHIFT)) & LCD_WF8B_BPDLCD26_MASK)
<> 144:ef7eb2e8f9f7 3164 #define LCD_WF8B_BPDLCD0_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3165 #define LCD_WF8B_BPDLCD0_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3166 #define LCD_WF8B_BPDLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD0_SHIFT)) & LCD_WF8B_BPDLCD0_MASK)
<> 144:ef7eb2e8f9f7 3167 #define LCD_WF8B_BPDLCD50_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3168 #define LCD_WF8B_BPDLCD50_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3169 #define LCD_WF8B_BPDLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD50_SHIFT)) & LCD_WF8B_BPDLCD50_MASK)
<> 144:ef7eb2e8f9f7 3170 #define LCD_WF8B_BPDLCD46_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3171 #define LCD_WF8B_BPDLCD46_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3172 #define LCD_WF8B_BPDLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD46_SHIFT)) & LCD_WF8B_BPDLCD46_MASK)
<> 144:ef7eb2e8f9f7 3173 #define LCD_WF8B_BPDLCD18_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3174 #define LCD_WF8B_BPDLCD18_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3175 #define LCD_WF8B_BPDLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD18_SHIFT)) & LCD_WF8B_BPDLCD18_MASK)
<> 144:ef7eb2e8f9f7 3176 #define LCD_WF8B_BPDLCD61_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3177 #define LCD_WF8B_BPDLCD61_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3178 #define LCD_WF8B_BPDLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD61_SHIFT)) & LCD_WF8B_BPDLCD61_MASK)
<> 144:ef7eb2e8f9f7 3179 #define LCD_WF8B_BPDLCD9_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3180 #define LCD_WF8B_BPDLCD9_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3181 #define LCD_WF8B_BPDLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD9_SHIFT)) & LCD_WF8B_BPDLCD9_MASK)
<> 144:ef7eb2e8f9f7 3182 #define LCD_WF8B_BPDLCD17_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3183 #define LCD_WF8B_BPDLCD17_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3184 #define LCD_WF8B_BPDLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD17_SHIFT)) & LCD_WF8B_BPDLCD17_MASK)
<> 144:ef7eb2e8f9f7 3185 #define LCD_WF8B_BPDLCD27_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3186 #define LCD_WF8B_BPDLCD27_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3187 #define LCD_WF8B_BPDLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD27_SHIFT)) & LCD_WF8B_BPDLCD27_MASK)
<> 144:ef7eb2e8f9f7 3188 #define LCD_WF8B_BPDLCD53_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3189 #define LCD_WF8B_BPDLCD53_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3190 #define LCD_WF8B_BPDLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD53_SHIFT)) & LCD_WF8B_BPDLCD53_MASK)
<> 144:ef7eb2e8f9f7 3191 #define LCD_WF8B_BPDLCD51_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3192 #define LCD_WF8B_BPDLCD51_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3193 #define LCD_WF8B_BPDLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD51_SHIFT)) & LCD_WF8B_BPDLCD51_MASK)
<> 144:ef7eb2e8f9f7 3194 #define LCD_WF8B_BPDLCD54_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3195 #define LCD_WF8B_BPDLCD54_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3196 #define LCD_WF8B_BPDLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD54_SHIFT)) & LCD_WF8B_BPDLCD54_MASK)
<> 144:ef7eb2e8f9f7 3197 #define LCD_WF8B_BPDLCD13_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3198 #define LCD_WF8B_BPDLCD13_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3199 #define LCD_WF8B_BPDLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD13_SHIFT)) & LCD_WF8B_BPDLCD13_MASK)
<> 144:ef7eb2e8f9f7 3200 #define LCD_WF8B_BPDLCD16_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3201 #define LCD_WF8B_BPDLCD16_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3202 #define LCD_WF8B_BPDLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD16_SHIFT)) & LCD_WF8B_BPDLCD16_MASK)
<> 144:ef7eb2e8f9f7 3203 #define LCD_WF8B_BPDLCD32_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3204 #define LCD_WF8B_BPDLCD32_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3205 #define LCD_WF8B_BPDLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD32_SHIFT)) & LCD_WF8B_BPDLCD32_MASK)
<> 144:ef7eb2e8f9f7 3206 #define LCD_WF8B_BPDLCD14_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3207 #define LCD_WF8B_BPDLCD14_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3208 #define LCD_WF8B_BPDLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD14_SHIFT)) & LCD_WF8B_BPDLCD14_MASK)
<> 144:ef7eb2e8f9f7 3209 #define LCD_WF8B_BPDLCD28_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3210 #define LCD_WF8B_BPDLCD28_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3211 #define LCD_WF8B_BPDLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD28_SHIFT)) & LCD_WF8B_BPDLCD28_MASK)
<> 144:ef7eb2e8f9f7 3212 #define LCD_WF8B_BPDLCD43_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3213 #define LCD_WF8B_BPDLCD43_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3214 #define LCD_WF8B_BPDLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD43_SHIFT)) & LCD_WF8B_BPDLCD43_MASK)
<> 144:ef7eb2e8f9f7 3215 #define LCD_WF8B_BPDLCD4_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3216 #define LCD_WF8B_BPDLCD4_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3217 #define LCD_WF8B_BPDLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD4_SHIFT)) & LCD_WF8B_BPDLCD4_MASK)
<> 144:ef7eb2e8f9f7 3218 #define LCD_WF8B_BPDLCD45_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3219 #define LCD_WF8B_BPDLCD45_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3220 #define LCD_WF8B_BPDLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD45_SHIFT)) & LCD_WF8B_BPDLCD45_MASK)
<> 144:ef7eb2e8f9f7 3221 #define LCD_WF8B_BPDLCD8_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3222 #define LCD_WF8B_BPDLCD8_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3223 #define LCD_WF8B_BPDLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD8_SHIFT)) & LCD_WF8B_BPDLCD8_MASK)
<> 144:ef7eb2e8f9f7 3224 #define LCD_WF8B_BPDLCD62_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3225 #define LCD_WF8B_BPDLCD62_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3226 #define LCD_WF8B_BPDLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD62_SHIFT)) & LCD_WF8B_BPDLCD62_MASK)
<> 144:ef7eb2e8f9f7 3227 #define LCD_WF8B_BPDLCD33_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3228 #define LCD_WF8B_BPDLCD33_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3229 #define LCD_WF8B_BPDLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD33_SHIFT)) & LCD_WF8B_BPDLCD33_MASK)
<> 144:ef7eb2e8f9f7 3230 #define LCD_WF8B_BPDLCD34_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3231 #define LCD_WF8B_BPDLCD34_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3232 #define LCD_WF8B_BPDLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD34_SHIFT)) & LCD_WF8B_BPDLCD34_MASK)
<> 144:ef7eb2e8f9f7 3233 #define LCD_WF8B_BPDLCD29_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3234 #define LCD_WF8B_BPDLCD29_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3235 #define LCD_WF8B_BPDLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD29_SHIFT)) & LCD_WF8B_BPDLCD29_MASK)
<> 144:ef7eb2e8f9f7 3236 #define LCD_WF8B_BPDLCD58_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3237 #define LCD_WF8B_BPDLCD58_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3238 #define LCD_WF8B_BPDLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD58_SHIFT)) & LCD_WF8B_BPDLCD58_MASK)
<> 144:ef7eb2e8f9f7 3239 #define LCD_WF8B_BPDLCD57_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3240 #define LCD_WF8B_BPDLCD57_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3241 #define LCD_WF8B_BPDLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD57_SHIFT)) & LCD_WF8B_BPDLCD57_MASK)
<> 144:ef7eb2e8f9f7 3242 #define LCD_WF8B_BPDLCD42_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3243 #define LCD_WF8B_BPDLCD42_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3244 #define LCD_WF8B_BPDLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD42_SHIFT)) & LCD_WF8B_BPDLCD42_MASK)
<> 144:ef7eb2e8f9f7 3245 #define LCD_WF8B_BPDLCD35_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3246 #define LCD_WF8B_BPDLCD35_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3247 #define LCD_WF8B_BPDLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD35_SHIFT)) & LCD_WF8B_BPDLCD35_MASK)
<> 144:ef7eb2e8f9f7 3248 #define LCD_WF8B_BPDLCD52_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3249 #define LCD_WF8B_BPDLCD52_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3250 #define LCD_WF8B_BPDLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD52_SHIFT)) & LCD_WF8B_BPDLCD52_MASK)
<> 144:ef7eb2e8f9f7 3251 #define LCD_WF8B_BPDLCD7_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3252 #define LCD_WF8B_BPDLCD7_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3253 #define LCD_WF8B_BPDLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD7_SHIFT)) & LCD_WF8B_BPDLCD7_MASK)
<> 144:ef7eb2e8f9f7 3254 #define LCD_WF8B_BPDLCD36_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3255 #define LCD_WF8B_BPDLCD36_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3256 #define LCD_WF8B_BPDLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD36_SHIFT)) & LCD_WF8B_BPDLCD36_MASK)
<> 144:ef7eb2e8f9f7 3257 #define LCD_WF8B_BPDLCD30_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3258 #define LCD_WF8B_BPDLCD30_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3259 #define LCD_WF8B_BPDLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD30_SHIFT)) & LCD_WF8B_BPDLCD30_MASK)
<> 144:ef7eb2e8f9f7 3260 #define LCD_WF8B_BPDLCD41_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3261 #define LCD_WF8B_BPDLCD41_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3262 #define LCD_WF8B_BPDLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD41_SHIFT)) & LCD_WF8B_BPDLCD41_MASK)
<> 144:ef7eb2e8f9f7 3263 #define LCD_WF8B_BPDLCD37_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3264 #define LCD_WF8B_BPDLCD37_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3265 #define LCD_WF8B_BPDLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD37_SHIFT)) & LCD_WF8B_BPDLCD37_MASK)
<> 144:ef7eb2e8f9f7 3266 #define LCD_WF8B_BPDLCD44_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3267 #define LCD_WF8B_BPDLCD44_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3268 #define LCD_WF8B_BPDLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD44_SHIFT)) & LCD_WF8B_BPDLCD44_MASK)
<> 144:ef7eb2e8f9f7 3269 #define LCD_WF8B_BPDLCD63_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3270 #define LCD_WF8B_BPDLCD63_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3271 #define LCD_WF8B_BPDLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD63_SHIFT)) & LCD_WF8B_BPDLCD63_MASK)
<> 144:ef7eb2e8f9f7 3272 #define LCD_WF8B_BPDLCD38_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3273 #define LCD_WF8B_BPDLCD38_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3274 #define LCD_WF8B_BPDLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD38_SHIFT)) & LCD_WF8B_BPDLCD38_MASK)
<> 144:ef7eb2e8f9f7 3275 #define LCD_WF8B_BPDLCD56_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3276 #define LCD_WF8B_BPDLCD56_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3277 #define LCD_WF8B_BPDLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD56_SHIFT)) & LCD_WF8B_BPDLCD56_MASK)
<> 144:ef7eb2e8f9f7 3278 #define LCD_WF8B_BPDLCD40_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3279 #define LCD_WF8B_BPDLCD40_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3280 #define LCD_WF8B_BPDLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD40_SHIFT)) & LCD_WF8B_BPDLCD40_MASK)
<> 144:ef7eb2e8f9f7 3281 #define LCD_WF8B_BPDLCD31_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3282 #define LCD_WF8B_BPDLCD31_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3283 #define LCD_WF8B_BPDLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD31_SHIFT)) & LCD_WF8B_BPDLCD31_MASK)
<> 144:ef7eb2e8f9f7 3284 #define LCD_WF8B_BPDLCD12_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3285 #define LCD_WF8B_BPDLCD12_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3286 #define LCD_WF8B_BPDLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD12_SHIFT)) & LCD_WF8B_BPDLCD12_MASK)
<> 144:ef7eb2e8f9f7 3287 #define LCD_WF8B_BPDLCD39_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3288 #define LCD_WF8B_BPDLCD39_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3289 #define LCD_WF8B_BPDLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD39_SHIFT)) & LCD_WF8B_BPDLCD39_MASK)
<> 144:ef7eb2e8f9f7 3290 #define LCD_WF8B_BPDLCD3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3291 #define LCD_WF8B_BPDLCD3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3292 #define LCD_WF8B_BPDLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD3_SHIFT)) & LCD_WF8B_BPDLCD3_MASK)
<> 144:ef7eb2e8f9f7 3293 #define LCD_WF8B_BPDLCD11_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3294 #define LCD_WF8B_BPDLCD11_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3295 #define LCD_WF8B_BPDLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD11_SHIFT)) & LCD_WF8B_BPDLCD11_MASK)
<> 144:ef7eb2e8f9f7 3296 #define LCD_WF8B_BPELCD12_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3297 #define LCD_WF8B_BPELCD12_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3298 #define LCD_WF8B_BPELCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD12_SHIFT)) & LCD_WF8B_BPELCD12_MASK)
<> 144:ef7eb2e8f9f7 3299 #define LCD_WF8B_BPELCD39_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3300 #define LCD_WF8B_BPELCD39_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3301 #define LCD_WF8B_BPELCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD39_SHIFT)) & LCD_WF8B_BPELCD39_MASK)
<> 144:ef7eb2e8f9f7 3302 #define LCD_WF8B_BPELCD3_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3303 #define LCD_WF8B_BPELCD3_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3304 #define LCD_WF8B_BPELCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD3_SHIFT)) & LCD_WF8B_BPELCD3_MASK)
<> 144:ef7eb2e8f9f7 3305 #define LCD_WF8B_BPELCD38_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3306 #define LCD_WF8B_BPELCD38_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3307 #define LCD_WF8B_BPELCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD38_SHIFT)) & LCD_WF8B_BPELCD38_MASK)
<> 144:ef7eb2e8f9f7 3308 #define LCD_WF8B_BPELCD40_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3309 #define LCD_WF8B_BPELCD40_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3310 #define LCD_WF8B_BPELCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD40_SHIFT)) & LCD_WF8B_BPELCD40_MASK)
<> 144:ef7eb2e8f9f7 3311 #define LCD_WF8B_BPELCD37_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3312 #define LCD_WF8B_BPELCD37_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3313 #define LCD_WF8B_BPELCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD37_SHIFT)) & LCD_WF8B_BPELCD37_MASK)
<> 144:ef7eb2e8f9f7 3314 #define LCD_WF8B_BPELCD41_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3315 #define LCD_WF8B_BPELCD41_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3316 #define LCD_WF8B_BPELCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD41_SHIFT)) & LCD_WF8B_BPELCD41_MASK)
<> 144:ef7eb2e8f9f7 3317 #define LCD_WF8B_BPELCD36_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3318 #define LCD_WF8B_BPELCD36_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3319 #define LCD_WF8B_BPELCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD36_SHIFT)) & LCD_WF8B_BPELCD36_MASK)
<> 144:ef7eb2e8f9f7 3320 #define LCD_WF8B_BPELCD8_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3321 #define LCD_WF8B_BPELCD8_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3322 #define LCD_WF8B_BPELCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD8_SHIFT)) & LCD_WF8B_BPELCD8_MASK)
<> 144:ef7eb2e8f9f7 3323 #define LCD_WF8B_BPELCD35_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3324 #define LCD_WF8B_BPELCD35_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3325 #define LCD_WF8B_BPELCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD35_SHIFT)) & LCD_WF8B_BPELCD35_MASK)
<> 144:ef7eb2e8f9f7 3326 #define LCD_WF8B_BPELCD42_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3327 #define LCD_WF8B_BPELCD42_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3328 #define LCD_WF8B_BPELCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD42_SHIFT)) & LCD_WF8B_BPELCD42_MASK)
<> 144:ef7eb2e8f9f7 3329 #define LCD_WF8B_BPELCD34_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3330 #define LCD_WF8B_BPELCD34_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3331 #define LCD_WF8B_BPELCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD34_SHIFT)) & LCD_WF8B_BPELCD34_MASK)
<> 144:ef7eb2e8f9f7 3332 #define LCD_WF8B_BPELCD33_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3333 #define LCD_WF8B_BPELCD33_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3334 #define LCD_WF8B_BPELCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD33_SHIFT)) & LCD_WF8B_BPELCD33_MASK)
<> 144:ef7eb2e8f9f7 3335 #define LCD_WF8B_BPELCD11_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3336 #define LCD_WF8B_BPELCD11_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3337 #define LCD_WF8B_BPELCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD11_SHIFT)) & LCD_WF8B_BPELCD11_MASK)
<> 144:ef7eb2e8f9f7 3338 #define LCD_WF8B_BPELCD43_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3339 #define LCD_WF8B_BPELCD43_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3340 #define LCD_WF8B_BPELCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD43_SHIFT)) & LCD_WF8B_BPELCD43_MASK)
<> 144:ef7eb2e8f9f7 3341 #define LCD_WF8B_BPELCD32_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3342 #define LCD_WF8B_BPELCD32_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3343 #define LCD_WF8B_BPELCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD32_SHIFT)) & LCD_WF8B_BPELCD32_MASK)
<> 144:ef7eb2e8f9f7 3344 #define LCD_WF8B_BPELCD31_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3345 #define LCD_WF8B_BPELCD31_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3346 #define LCD_WF8B_BPELCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD31_SHIFT)) & LCD_WF8B_BPELCD31_MASK)
<> 144:ef7eb2e8f9f7 3347 #define LCD_WF8B_BPELCD44_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3348 #define LCD_WF8B_BPELCD44_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3349 #define LCD_WF8B_BPELCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD44_SHIFT)) & LCD_WF8B_BPELCD44_MASK)
<> 144:ef7eb2e8f9f7 3350 #define LCD_WF8B_BPELCD30_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3351 #define LCD_WF8B_BPELCD30_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3352 #define LCD_WF8B_BPELCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD30_SHIFT)) & LCD_WF8B_BPELCD30_MASK)
<> 144:ef7eb2e8f9f7 3353 #define LCD_WF8B_BPELCD29_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3354 #define LCD_WF8B_BPELCD29_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3355 #define LCD_WF8B_BPELCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD29_SHIFT)) & LCD_WF8B_BPELCD29_MASK)
<> 144:ef7eb2e8f9f7 3356 #define LCD_WF8B_BPELCD7_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3357 #define LCD_WF8B_BPELCD7_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3358 #define LCD_WF8B_BPELCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD7_SHIFT)) & LCD_WF8B_BPELCD7_MASK)
<> 144:ef7eb2e8f9f7 3359 #define LCD_WF8B_BPELCD45_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3360 #define LCD_WF8B_BPELCD45_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3361 #define LCD_WF8B_BPELCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD45_SHIFT)) & LCD_WF8B_BPELCD45_MASK)
<> 144:ef7eb2e8f9f7 3362 #define LCD_WF8B_BPELCD28_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3363 #define LCD_WF8B_BPELCD28_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3364 #define LCD_WF8B_BPELCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD28_SHIFT)) & LCD_WF8B_BPELCD28_MASK)
<> 144:ef7eb2e8f9f7 3365 #define LCD_WF8B_BPELCD2_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3366 #define LCD_WF8B_BPELCD2_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3367 #define LCD_WF8B_BPELCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD2_SHIFT)) & LCD_WF8B_BPELCD2_MASK)
<> 144:ef7eb2e8f9f7 3368 #define LCD_WF8B_BPELCD27_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3369 #define LCD_WF8B_BPELCD27_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3370 #define LCD_WF8B_BPELCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD27_SHIFT)) & LCD_WF8B_BPELCD27_MASK)
<> 144:ef7eb2e8f9f7 3371 #define LCD_WF8B_BPELCD46_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3372 #define LCD_WF8B_BPELCD46_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3373 #define LCD_WF8B_BPELCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD46_SHIFT)) & LCD_WF8B_BPELCD46_MASK)
<> 144:ef7eb2e8f9f7 3374 #define LCD_WF8B_BPELCD26_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3375 #define LCD_WF8B_BPELCD26_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3376 #define LCD_WF8B_BPELCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD26_SHIFT)) & LCD_WF8B_BPELCD26_MASK)
<> 144:ef7eb2e8f9f7 3377 #define LCD_WF8B_BPELCD10_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3378 #define LCD_WF8B_BPELCD10_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3379 #define LCD_WF8B_BPELCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD10_SHIFT)) & LCD_WF8B_BPELCD10_MASK)
<> 144:ef7eb2e8f9f7 3380 #define LCD_WF8B_BPELCD13_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3381 #define LCD_WF8B_BPELCD13_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3382 #define LCD_WF8B_BPELCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD13_SHIFT)) & LCD_WF8B_BPELCD13_MASK)
<> 144:ef7eb2e8f9f7 3383 #define LCD_WF8B_BPELCD25_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3384 #define LCD_WF8B_BPELCD25_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3385 #define LCD_WF8B_BPELCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD25_SHIFT)) & LCD_WF8B_BPELCD25_MASK)
<> 144:ef7eb2e8f9f7 3386 #define LCD_WF8B_BPELCD5_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3387 #define LCD_WF8B_BPELCD5_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3388 #define LCD_WF8B_BPELCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD5_SHIFT)) & LCD_WF8B_BPELCD5_MASK)
<> 144:ef7eb2e8f9f7 3389 #define LCD_WF8B_BPELCD24_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3390 #define LCD_WF8B_BPELCD24_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3391 #define LCD_WF8B_BPELCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD24_SHIFT)) & LCD_WF8B_BPELCD24_MASK)
<> 144:ef7eb2e8f9f7 3392 #define LCD_WF8B_BPELCD47_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3393 #define LCD_WF8B_BPELCD47_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3394 #define LCD_WF8B_BPELCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD47_SHIFT)) & LCD_WF8B_BPELCD47_MASK)
<> 144:ef7eb2e8f9f7 3395 #define LCD_WF8B_BPELCD23_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3396 #define LCD_WF8B_BPELCD23_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3397 #define LCD_WF8B_BPELCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD23_SHIFT)) & LCD_WF8B_BPELCD23_MASK)
<> 144:ef7eb2e8f9f7 3398 #define LCD_WF8B_BPELCD22_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3399 #define LCD_WF8B_BPELCD22_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3400 #define LCD_WF8B_BPELCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD22_SHIFT)) & LCD_WF8B_BPELCD22_MASK)
<> 144:ef7eb2e8f9f7 3401 #define LCD_WF8B_BPELCD48_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3402 #define LCD_WF8B_BPELCD48_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3403 #define LCD_WF8B_BPELCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD48_SHIFT)) & LCD_WF8B_BPELCD48_MASK)
<> 144:ef7eb2e8f9f7 3404 #define LCD_WF8B_BPELCD21_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3405 #define LCD_WF8B_BPELCD21_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3406 #define LCD_WF8B_BPELCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD21_SHIFT)) & LCD_WF8B_BPELCD21_MASK)
<> 144:ef7eb2e8f9f7 3407 #define LCD_WF8B_BPELCD49_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3408 #define LCD_WF8B_BPELCD49_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3409 #define LCD_WF8B_BPELCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD49_SHIFT)) & LCD_WF8B_BPELCD49_MASK)
<> 144:ef7eb2e8f9f7 3410 #define LCD_WF8B_BPELCD20_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3411 #define LCD_WF8B_BPELCD20_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3412 #define LCD_WF8B_BPELCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD20_SHIFT)) & LCD_WF8B_BPELCD20_MASK)
<> 144:ef7eb2e8f9f7 3413 #define LCD_WF8B_BPELCD19_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3414 #define LCD_WF8B_BPELCD19_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3415 #define LCD_WF8B_BPELCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD19_SHIFT)) & LCD_WF8B_BPELCD19_MASK)
<> 144:ef7eb2e8f9f7 3416 #define LCD_WF8B_BPELCD9_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3417 #define LCD_WF8B_BPELCD9_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3418 #define LCD_WF8B_BPELCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD9_SHIFT)) & LCD_WF8B_BPELCD9_MASK)
<> 144:ef7eb2e8f9f7 3419 #define LCD_WF8B_BPELCD50_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3420 #define LCD_WF8B_BPELCD50_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3421 #define LCD_WF8B_BPELCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD50_SHIFT)) & LCD_WF8B_BPELCD50_MASK)
<> 144:ef7eb2e8f9f7 3422 #define LCD_WF8B_BPELCD18_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3423 #define LCD_WF8B_BPELCD18_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3424 #define LCD_WF8B_BPELCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD18_SHIFT)) & LCD_WF8B_BPELCD18_MASK)
<> 144:ef7eb2e8f9f7 3425 #define LCD_WF8B_BPELCD6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3426 #define LCD_WF8B_BPELCD6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3427 #define LCD_WF8B_BPELCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD6_SHIFT)) & LCD_WF8B_BPELCD6_MASK)
<> 144:ef7eb2e8f9f7 3428 #define LCD_WF8B_BPELCD17_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3429 #define LCD_WF8B_BPELCD17_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3430 #define LCD_WF8B_BPELCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD17_SHIFT)) & LCD_WF8B_BPELCD17_MASK)
<> 144:ef7eb2e8f9f7 3431 #define LCD_WF8B_BPELCD51_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3432 #define LCD_WF8B_BPELCD51_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3433 #define LCD_WF8B_BPELCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD51_SHIFT)) & LCD_WF8B_BPELCD51_MASK)
<> 144:ef7eb2e8f9f7 3434 #define LCD_WF8B_BPELCD16_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3435 #define LCD_WF8B_BPELCD16_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3436 #define LCD_WF8B_BPELCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD16_SHIFT)) & LCD_WF8B_BPELCD16_MASK)
<> 144:ef7eb2e8f9f7 3437 #define LCD_WF8B_BPELCD56_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3438 #define LCD_WF8B_BPELCD56_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3439 #define LCD_WF8B_BPELCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD56_SHIFT)) & LCD_WF8B_BPELCD56_MASK)
<> 144:ef7eb2e8f9f7 3440 #define LCD_WF8B_BPELCD57_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3441 #define LCD_WF8B_BPELCD57_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3442 #define LCD_WF8B_BPELCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD57_SHIFT)) & LCD_WF8B_BPELCD57_MASK)
<> 144:ef7eb2e8f9f7 3443 #define LCD_WF8B_BPELCD52_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3444 #define LCD_WF8B_BPELCD52_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3445 #define LCD_WF8B_BPELCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD52_SHIFT)) & LCD_WF8B_BPELCD52_MASK)
<> 144:ef7eb2e8f9f7 3446 #define LCD_WF8B_BPELCD1_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3447 #define LCD_WF8B_BPELCD1_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3448 #define LCD_WF8B_BPELCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD1_SHIFT)) & LCD_WF8B_BPELCD1_MASK)
<> 144:ef7eb2e8f9f7 3449 #define LCD_WF8B_BPELCD58_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3450 #define LCD_WF8B_BPELCD58_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3451 #define LCD_WF8B_BPELCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD58_SHIFT)) & LCD_WF8B_BPELCD58_MASK)
<> 144:ef7eb2e8f9f7 3452 #define LCD_WF8B_BPELCD59_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3453 #define LCD_WF8B_BPELCD59_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3454 #define LCD_WF8B_BPELCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD59_SHIFT)) & LCD_WF8B_BPELCD59_MASK)
<> 144:ef7eb2e8f9f7 3455 #define LCD_WF8B_BPELCD53_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3456 #define LCD_WF8B_BPELCD53_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3457 #define LCD_WF8B_BPELCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD53_SHIFT)) & LCD_WF8B_BPELCD53_MASK)
<> 144:ef7eb2e8f9f7 3458 #define LCD_WF8B_BPELCD14_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3459 #define LCD_WF8B_BPELCD14_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3460 #define LCD_WF8B_BPELCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD14_SHIFT)) & LCD_WF8B_BPELCD14_MASK)
<> 144:ef7eb2e8f9f7 3461 #define LCD_WF8B_BPELCD0_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3462 #define LCD_WF8B_BPELCD0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3463 #define LCD_WF8B_BPELCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD0_SHIFT)) & LCD_WF8B_BPELCD0_MASK)
<> 144:ef7eb2e8f9f7 3464 #define LCD_WF8B_BPELCD60_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3465 #define LCD_WF8B_BPELCD60_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3466 #define LCD_WF8B_BPELCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD60_SHIFT)) & LCD_WF8B_BPELCD60_MASK)
<> 144:ef7eb2e8f9f7 3467 #define LCD_WF8B_BPELCD15_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3468 #define LCD_WF8B_BPELCD15_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3469 #define LCD_WF8B_BPELCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD15_SHIFT)) & LCD_WF8B_BPELCD15_MASK)
<> 144:ef7eb2e8f9f7 3470 #define LCD_WF8B_BPELCD61_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3471 #define LCD_WF8B_BPELCD61_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3472 #define LCD_WF8B_BPELCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD61_SHIFT)) & LCD_WF8B_BPELCD61_MASK)
<> 144:ef7eb2e8f9f7 3473 #define LCD_WF8B_BPELCD54_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3474 #define LCD_WF8B_BPELCD54_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3475 #define LCD_WF8B_BPELCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD54_SHIFT)) & LCD_WF8B_BPELCD54_MASK)
<> 144:ef7eb2e8f9f7 3476 #define LCD_WF8B_BPELCD62_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3477 #define LCD_WF8B_BPELCD62_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3478 #define LCD_WF8B_BPELCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD62_SHIFT)) & LCD_WF8B_BPELCD62_MASK)
<> 144:ef7eb2e8f9f7 3479 #define LCD_WF8B_BPELCD63_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3480 #define LCD_WF8B_BPELCD63_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3481 #define LCD_WF8B_BPELCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD63_SHIFT)) & LCD_WF8B_BPELCD63_MASK)
<> 144:ef7eb2e8f9f7 3482 #define LCD_WF8B_BPELCD55_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3483 #define LCD_WF8B_BPELCD55_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3484 #define LCD_WF8B_BPELCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD55_SHIFT)) & LCD_WF8B_BPELCD55_MASK)
<> 144:ef7eb2e8f9f7 3485 #define LCD_WF8B_BPELCD4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3486 #define LCD_WF8B_BPELCD4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3487 #define LCD_WF8B_BPELCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD4_SHIFT)) & LCD_WF8B_BPELCD4_MASK)
<> 144:ef7eb2e8f9f7 3488 #define LCD_WF8B_BPFLCD13_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3489 #define LCD_WF8B_BPFLCD13_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3490 #define LCD_WF8B_BPFLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD13_SHIFT)) & LCD_WF8B_BPFLCD13_MASK)
<> 144:ef7eb2e8f9f7 3491 #define LCD_WF8B_BPFLCD39_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3492 #define LCD_WF8B_BPFLCD39_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3493 #define LCD_WF8B_BPFLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD39_SHIFT)) & LCD_WF8B_BPFLCD39_MASK)
<> 144:ef7eb2e8f9f7 3494 #define LCD_WF8B_BPFLCD55_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3495 #define LCD_WF8B_BPFLCD55_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3496 #define LCD_WF8B_BPFLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD55_SHIFT)) & LCD_WF8B_BPFLCD55_MASK)
<> 144:ef7eb2e8f9f7 3497 #define LCD_WF8B_BPFLCD47_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3498 #define LCD_WF8B_BPFLCD47_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3499 #define LCD_WF8B_BPFLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD47_SHIFT)) & LCD_WF8B_BPFLCD47_MASK)
<> 144:ef7eb2e8f9f7 3500 #define LCD_WF8B_BPFLCD63_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3501 #define LCD_WF8B_BPFLCD63_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3502 #define LCD_WF8B_BPFLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD63_SHIFT)) & LCD_WF8B_BPFLCD63_MASK)
<> 144:ef7eb2e8f9f7 3503 #define LCD_WF8B_BPFLCD43_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3504 #define LCD_WF8B_BPFLCD43_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3505 #define LCD_WF8B_BPFLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD43_SHIFT)) & LCD_WF8B_BPFLCD43_MASK)
<> 144:ef7eb2e8f9f7 3506 #define LCD_WF8B_BPFLCD5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3507 #define LCD_WF8B_BPFLCD5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3508 #define LCD_WF8B_BPFLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD5_SHIFT)) & LCD_WF8B_BPFLCD5_MASK)
<> 144:ef7eb2e8f9f7 3509 #define LCD_WF8B_BPFLCD62_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3510 #define LCD_WF8B_BPFLCD62_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3511 #define LCD_WF8B_BPFLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD62_SHIFT)) & LCD_WF8B_BPFLCD62_MASK)
<> 144:ef7eb2e8f9f7 3512 #define LCD_WF8B_BPFLCD14_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3513 #define LCD_WF8B_BPFLCD14_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3514 #define LCD_WF8B_BPFLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD14_SHIFT)) & LCD_WF8B_BPFLCD14_MASK)
<> 144:ef7eb2e8f9f7 3515 #define LCD_WF8B_BPFLCD24_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3516 #define LCD_WF8B_BPFLCD24_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3517 #define LCD_WF8B_BPFLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD24_SHIFT)) & LCD_WF8B_BPFLCD24_MASK)
<> 144:ef7eb2e8f9f7 3518 #define LCD_WF8B_BPFLCD54_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3519 #define LCD_WF8B_BPFLCD54_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3520 #define LCD_WF8B_BPFLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD54_SHIFT)) & LCD_WF8B_BPFLCD54_MASK)
<> 144:ef7eb2e8f9f7 3521 #define LCD_WF8B_BPFLCD15_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3522 #define LCD_WF8B_BPFLCD15_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3523 #define LCD_WF8B_BPFLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD15_SHIFT)) & LCD_WF8B_BPFLCD15_MASK)
<> 144:ef7eb2e8f9f7 3524 #define LCD_WF8B_BPFLCD32_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3525 #define LCD_WF8B_BPFLCD32_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3526 #define LCD_WF8B_BPFLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD32_SHIFT)) & LCD_WF8B_BPFLCD32_MASK)
<> 144:ef7eb2e8f9f7 3527 #define LCD_WF8B_BPFLCD61_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3528 #define LCD_WF8B_BPFLCD61_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3529 #define LCD_WF8B_BPFLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD61_SHIFT)) & LCD_WF8B_BPFLCD61_MASK)
<> 144:ef7eb2e8f9f7 3530 #define LCD_WF8B_BPFLCD25_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3531 #define LCD_WF8B_BPFLCD25_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3532 #define LCD_WF8B_BPFLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD25_SHIFT)) & LCD_WF8B_BPFLCD25_MASK)
<> 144:ef7eb2e8f9f7 3533 #define LCD_WF8B_BPFLCD60_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3534 #define LCD_WF8B_BPFLCD60_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3535 #define LCD_WF8B_BPFLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD60_SHIFT)) & LCD_WF8B_BPFLCD60_MASK)
<> 144:ef7eb2e8f9f7 3536 #define LCD_WF8B_BPFLCD41_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3537 #define LCD_WF8B_BPFLCD41_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3538 #define LCD_WF8B_BPFLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD41_SHIFT)) & LCD_WF8B_BPFLCD41_MASK)
<> 144:ef7eb2e8f9f7 3539 #define LCD_WF8B_BPFLCD33_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3540 #define LCD_WF8B_BPFLCD33_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3541 #define LCD_WF8B_BPFLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD33_SHIFT)) & LCD_WF8B_BPFLCD33_MASK)
<> 144:ef7eb2e8f9f7 3542 #define LCD_WF8B_BPFLCD53_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3543 #define LCD_WF8B_BPFLCD53_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3544 #define LCD_WF8B_BPFLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD53_SHIFT)) & LCD_WF8B_BPFLCD53_MASK)
<> 144:ef7eb2e8f9f7 3545 #define LCD_WF8B_BPFLCD59_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3546 #define LCD_WF8B_BPFLCD59_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3547 #define LCD_WF8B_BPFLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD59_SHIFT)) & LCD_WF8B_BPFLCD59_MASK)
<> 144:ef7eb2e8f9f7 3548 #define LCD_WF8B_BPFLCD0_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3549 #define LCD_WF8B_BPFLCD0_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3550 #define LCD_WF8B_BPFLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD0_SHIFT)) & LCD_WF8B_BPFLCD0_MASK)
<> 144:ef7eb2e8f9f7 3551 #define LCD_WF8B_BPFLCD46_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3552 #define LCD_WF8B_BPFLCD46_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3553 #define LCD_WF8B_BPFLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD46_SHIFT)) & LCD_WF8B_BPFLCD46_MASK)
<> 144:ef7eb2e8f9f7 3554 #define LCD_WF8B_BPFLCD58_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3555 #define LCD_WF8B_BPFLCD58_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3556 #define LCD_WF8B_BPFLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD58_SHIFT)) & LCD_WF8B_BPFLCD58_MASK)
<> 144:ef7eb2e8f9f7 3557 #define LCD_WF8B_BPFLCD26_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3558 #define LCD_WF8B_BPFLCD26_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3559 #define LCD_WF8B_BPFLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD26_SHIFT)) & LCD_WF8B_BPFLCD26_MASK)
<> 144:ef7eb2e8f9f7 3560 #define LCD_WF8B_BPFLCD36_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3561 #define LCD_WF8B_BPFLCD36_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3562 #define LCD_WF8B_BPFLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD36_SHIFT)) & LCD_WF8B_BPFLCD36_MASK)
<> 144:ef7eb2e8f9f7 3563 #define LCD_WF8B_BPFLCD10_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3564 #define LCD_WF8B_BPFLCD10_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3565 #define LCD_WF8B_BPFLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD10_SHIFT)) & LCD_WF8B_BPFLCD10_MASK)
<> 144:ef7eb2e8f9f7 3566 #define LCD_WF8B_BPFLCD52_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3567 #define LCD_WF8B_BPFLCD52_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3568 #define LCD_WF8B_BPFLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD52_SHIFT)) & LCD_WF8B_BPFLCD52_MASK)
<> 144:ef7eb2e8f9f7 3569 #define LCD_WF8B_BPFLCD57_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3570 #define LCD_WF8B_BPFLCD57_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3571 #define LCD_WF8B_BPFLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD57_SHIFT)) & LCD_WF8B_BPFLCD57_MASK)
<> 144:ef7eb2e8f9f7 3572 #define LCD_WF8B_BPFLCD27_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3573 #define LCD_WF8B_BPFLCD27_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3574 #define LCD_WF8B_BPFLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD27_SHIFT)) & LCD_WF8B_BPFLCD27_MASK)
<> 144:ef7eb2e8f9f7 3575 #define LCD_WF8B_BPFLCD11_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3576 #define LCD_WF8B_BPFLCD11_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3577 #define LCD_WF8B_BPFLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD11_SHIFT)) & LCD_WF8B_BPFLCD11_MASK)
<> 144:ef7eb2e8f9f7 3578 #define LCD_WF8B_BPFLCD56_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3579 #define LCD_WF8B_BPFLCD56_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3580 #define LCD_WF8B_BPFLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD56_SHIFT)) & LCD_WF8B_BPFLCD56_MASK)
<> 144:ef7eb2e8f9f7 3581 #define LCD_WF8B_BPFLCD1_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3582 #define LCD_WF8B_BPFLCD1_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3583 #define LCD_WF8B_BPFLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD1_SHIFT)) & LCD_WF8B_BPFLCD1_MASK)
<> 144:ef7eb2e8f9f7 3584 #define LCD_WF8B_BPFLCD8_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3585 #define LCD_WF8B_BPFLCD8_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3586 #define LCD_WF8B_BPFLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD8_SHIFT)) & LCD_WF8B_BPFLCD8_MASK)
<> 144:ef7eb2e8f9f7 3587 #define LCD_WF8B_BPFLCD40_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3588 #define LCD_WF8B_BPFLCD40_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3589 #define LCD_WF8B_BPFLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD40_SHIFT)) & LCD_WF8B_BPFLCD40_MASK)
<> 144:ef7eb2e8f9f7 3590 #define LCD_WF8B_BPFLCD51_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3591 #define LCD_WF8B_BPFLCD51_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3592 #define LCD_WF8B_BPFLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD51_SHIFT)) & LCD_WF8B_BPFLCD51_MASK)
<> 144:ef7eb2e8f9f7 3593 #define LCD_WF8B_BPFLCD16_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3594 #define LCD_WF8B_BPFLCD16_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3595 #define LCD_WF8B_BPFLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD16_SHIFT)) & LCD_WF8B_BPFLCD16_MASK)
<> 144:ef7eb2e8f9f7 3596 #define LCD_WF8B_BPFLCD45_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3597 #define LCD_WF8B_BPFLCD45_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3598 #define LCD_WF8B_BPFLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD45_SHIFT)) & LCD_WF8B_BPFLCD45_MASK)
<> 144:ef7eb2e8f9f7 3599 #define LCD_WF8B_BPFLCD6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3600 #define LCD_WF8B_BPFLCD6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3601 #define LCD_WF8B_BPFLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD6_SHIFT)) & LCD_WF8B_BPFLCD6_MASK)
<> 144:ef7eb2e8f9f7 3602 #define LCD_WF8B_BPFLCD17_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3603 #define LCD_WF8B_BPFLCD17_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3604 #define LCD_WF8B_BPFLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD17_SHIFT)) & LCD_WF8B_BPFLCD17_MASK)
<> 144:ef7eb2e8f9f7 3605 #define LCD_WF8B_BPFLCD28_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3606 #define LCD_WF8B_BPFLCD28_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3607 #define LCD_WF8B_BPFLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD28_SHIFT)) & LCD_WF8B_BPFLCD28_MASK)
<> 144:ef7eb2e8f9f7 3608 #define LCD_WF8B_BPFLCD42_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3609 #define LCD_WF8B_BPFLCD42_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3610 #define LCD_WF8B_BPFLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD42_SHIFT)) & LCD_WF8B_BPFLCD42_MASK)
<> 144:ef7eb2e8f9f7 3611 #define LCD_WF8B_BPFLCD29_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3612 #define LCD_WF8B_BPFLCD29_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3613 #define LCD_WF8B_BPFLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD29_SHIFT)) & LCD_WF8B_BPFLCD29_MASK)
<> 144:ef7eb2e8f9f7 3614 #define LCD_WF8B_BPFLCD50_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3615 #define LCD_WF8B_BPFLCD50_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3616 #define LCD_WF8B_BPFLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD50_SHIFT)) & LCD_WF8B_BPFLCD50_MASK)
<> 144:ef7eb2e8f9f7 3617 #define LCD_WF8B_BPFLCD18_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3618 #define LCD_WF8B_BPFLCD18_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3619 #define LCD_WF8B_BPFLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD18_SHIFT)) & LCD_WF8B_BPFLCD18_MASK)
<> 144:ef7eb2e8f9f7 3620 #define LCD_WF8B_BPFLCD34_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3621 #define LCD_WF8B_BPFLCD34_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3622 #define LCD_WF8B_BPFLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD34_SHIFT)) & LCD_WF8B_BPFLCD34_MASK)
<> 144:ef7eb2e8f9f7 3623 #define LCD_WF8B_BPFLCD19_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3624 #define LCD_WF8B_BPFLCD19_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3625 #define LCD_WF8B_BPFLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD19_SHIFT)) & LCD_WF8B_BPFLCD19_MASK)
<> 144:ef7eb2e8f9f7 3626 #define LCD_WF8B_BPFLCD2_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3627 #define LCD_WF8B_BPFLCD2_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3628 #define LCD_WF8B_BPFLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD2_SHIFT)) & LCD_WF8B_BPFLCD2_MASK)
<> 144:ef7eb2e8f9f7 3629 #define LCD_WF8B_BPFLCD9_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3630 #define LCD_WF8B_BPFLCD9_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3631 #define LCD_WF8B_BPFLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD9_SHIFT)) & LCD_WF8B_BPFLCD9_MASK)
<> 144:ef7eb2e8f9f7 3632 #define LCD_WF8B_BPFLCD3_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3633 #define LCD_WF8B_BPFLCD3_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3634 #define LCD_WF8B_BPFLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD3_SHIFT)) & LCD_WF8B_BPFLCD3_MASK)
<> 144:ef7eb2e8f9f7 3635 #define LCD_WF8B_BPFLCD37_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3636 #define LCD_WF8B_BPFLCD37_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3637 #define LCD_WF8B_BPFLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD37_SHIFT)) & LCD_WF8B_BPFLCD37_MASK)
<> 144:ef7eb2e8f9f7 3638 #define LCD_WF8B_BPFLCD49_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3639 #define LCD_WF8B_BPFLCD49_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3640 #define LCD_WF8B_BPFLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD49_SHIFT)) & LCD_WF8B_BPFLCD49_MASK)
<> 144:ef7eb2e8f9f7 3641 #define LCD_WF8B_BPFLCD20_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3642 #define LCD_WF8B_BPFLCD20_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3643 #define LCD_WF8B_BPFLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD20_SHIFT)) & LCD_WF8B_BPFLCD20_MASK)
<> 144:ef7eb2e8f9f7 3644 #define LCD_WF8B_BPFLCD44_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3645 #define LCD_WF8B_BPFLCD44_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3646 #define LCD_WF8B_BPFLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD44_SHIFT)) & LCD_WF8B_BPFLCD44_MASK)
<> 144:ef7eb2e8f9f7 3647 #define LCD_WF8B_BPFLCD30_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3648 #define LCD_WF8B_BPFLCD30_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3649 #define LCD_WF8B_BPFLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD30_SHIFT)) & LCD_WF8B_BPFLCD30_MASK)
<> 144:ef7eb2e8f9f7 3650 #define LCD_WF8B_BPFLCD21_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3651 #define LCD_WF8B_BPFLCD21_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3652 #define LCD_WF8B_BPFLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD21_SHIFT)) & LCD_WF8B_BPFLCD21_MASK)
<> 144:ef7eb2e8f9f7 3653 #define LCD_WF8B_BPFLCD35_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3654 #define LCD_WF8B_BPFLCD35_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3655 #define LCD_WF8B_BPFLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD35_SHIFT)) & LCD_WF8B_BPFLCD35_MASK)
<> 144:ef7eb2e8f9f7 3656 #define LCD_WF8B_BPFLCD4_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3657 #define LCD_WF8B_BPFLCD4_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3658 #define LCD_WF8B_BPFLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD4_SHIFT)) & LCD_WF8B_BPFLCD4_MASK)
<> 144:ef7eb2e8f9f7 3659 #define LCD_WF8B_BPFLCD31_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3660 #define LCD_WF8B_BPFLCD31_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3661 #define LCD_WF8B_BPFLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD31_SHIFT)) & LCD_WF8B_BPFLCD31_MASK)
<> 144:ef7eb2e8f9f7 3662 #define LCD_WF8B_BPFLCD48_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3663 #define LCD_WF8B_BPFLCD48_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3664 #define LCD_WF8B_BPFLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD48_SHIFT)) & LCD_WF8B_BPFLCD48_MASK)
<> 144:ef7eb2e8f9f7 3665 #define LCD_WF8B_BPFLCD7_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3666 #define LCD_WF8B_BPFLCD7_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3667 #define LCD_WF8B_BPFLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD7_SHIFT)) & LCD_WF8B_BPFLCD7_MASK)
<> 144:ef7eb2e8f9f7 3668 #define LCD_WF8B_BPFLCD22_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3669 #define LCD_WF8B_BPFLCD22_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3670 #define LCD_WF8B_BPFLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD22_SHIFT)) & LCD_WF8B_BPFLCD22_MASK)
<> 144:ef7eb2e8f9f7 3671 #define LCD_WF8B_BPFLCD38_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3672 #define LCD_WF8B_BPFLCD38_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3673 #define LCD_WF8B_BPFLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD38_SHIFT)) & LCD_WF8B_BPFLCD38_MASK)
<> 144:ef7eb2e8f9f7 3674 #define LCD_WF8B_BPFLCD12_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3675 #define LCD_WF8B_BPFLCD12_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3676 #define LCD_WF8B_BPFLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD12_SHIFT)) & LCD_WF8B_BPFLCD12_MASK)
<> 144:ef7eb2e8f9f7 3677 #define LCD_WF8B_BPFLCD23_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3678 #define LCD_WF8B_BPFLCD23_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3679 #define LCD_WF8B_BPFLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD23_SHIFT)) & LCD_WF8B_BPFLCD23_MASK)
<> 144:ef7eb2e8f9f7 3680 #define LCD_WF8B_BPGLCD14_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3681 #define LCD_WF8B_BPGLCD14_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3682 #define LCD_WF8B_BPGLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD14_SHIFT)) & LCD_WF8B_BPGLCD14_MASK)
<> 144:ef7eb2e8f9f7 3683 #define LCD_WF8B_BPGLCD55_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3684 #define LCD_WF8B_BPGLCD55_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3685 #define LCD_WF8B_BPGLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD55_SHIFT)) & LCD_WF8B_BPGLCD55_MASK)
<> 144:ef7eb2e8f9f7 3686 #define LCD_WF8B_BPGLCD63_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3687 #define LCD_WF8B_BPGLCD63_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3688 #define LCD_WF8B_BPGLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD63_SHIFT)) & LCD_WF8B_BPGLCD63_MASK)
<> 144:ef7eb2e8f9f7 3689 #define LCD_WF8B_BPGLCD15_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3690 #define LCD_WF8B_BPGLCD15_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3691 #define LCD_WF8B_BPGLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD15_SHIFT)) & LCD_WF8B_BPGLCD15_MASK)
<> 144:ef7eb2e8f9f7 3692 #define LCD_WF8B_BPGLCD62_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3693 #define LCD_WF8B_BPGLCD62_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3694 #define LCD_WF8B_BPGLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD62_SHIFT)) & LCD_WF8B_BPGLCD62_MASK)
<> 144:ef7eb2e8f9f7 3695 #define LCD_WF8B_BPGLCD54_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3696 #define LCD_WF8B_BPGLCD54_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3697 #define LCD_WF8B_BPGLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD54_SHIFT)) & LCD_WF8B_BPGLCD54_MASK)
<> 144:ef7eb2e8f9f7 3698 #define LCD_WF8B_BPGLCD61_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3699 #define LCD_WF8B_BPGLCD61_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3700 #define LCD_WF8B_BPGLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD61_SHIFT)) & LCD_WF8B_BPGLCD61_MASK)
<> 144:ef7eb2e8f9f7 3701 #define LCD_WF8B_BPGLCD60_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3702 #define LCD_WF8B_BPGLCD60_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3703 #define LCD_WF8B_BPGLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD60_SHIFT)) & LCD_WF8B_BPGLCD60_MASK)
<> 144:ef7eb2e8f9f7 3704 #define LCD_WF8B_BPGLCD59_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3705 #define LCD_WF8B_BPGLCD59_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3706 #define LCD_WF8B_BPGLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD59_SHIFT)) & LCD_WF8B_BPGLCD59_MASK)
<> 144:ef7eb2e8f9f7 3707 #define LCD_WF8B_BPGLCD53_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3708 #define LCD_WF8B_BPGLCD53_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3709 #define LCD_WF8B_BPGLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD53_SHIFT)) & LCD_WF8B_BPGLCD53_MASK)
<> 144:ef7eb2e8f9f7 3710 #define LCD_WF8B_BPGLCD58_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3711 #define LCD_WF8B_BPGLCD58_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3712 #define LCD_WF8B_BPGLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD58_SHIFT)) & LCD_WF8B_BPGLCD58_MASK)
<> 144:ef7eb2e8f9f7 3713 #define LCD_WF8B_BPGLCD0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3714 #define LCD_WF8B_BPGLCD0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3715 #define LCD_WF8B_BPGLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD0_SHIFT)) & LCD_WF8B_BPGLCD0_MASK)
<> 144:ef7eb2e8f9f7 3716 #define LCD_WF8B_BPGLCD57_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3717 #define LCD_WF8B_BPGLCD57_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3718 #define LCD_WF8B_BPGLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD57_SHIFT)) & LCD_WF8B_BPGLCD57_MASK)
<> 144:ef7eb2e8f9f7 3719 #define LCD_WF8B_BPGLCD52_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3720 #define LCD_WF8B_BPGLCD52_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3721 #define LCD_WF8B_BPGLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD52_SHIFT)) & LCD_WF8B_BPGLCD52_MASK)
<> 144:ef7eb2e8f9f7 3722 #define LCD_WF8B_BPGLCD7_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3723 #define LCD_WF8B_BPGLCD7_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3724 #define LCD_WF8B_BPGLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD7_SHIFT)) & LCD_WF8B_BPGLCD7_MASK)
<> 144:ef7eb2e8f9f7 3725 #define LCD_WF8B_BPGLCD56_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3726 #define LCD_WF8B_BPGLCD56_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3727 #define LCD_WF8B_BPGLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD56_SHIFT)) & LCD_WF8B_BPGLCD56_MASK)
<> 144:ef7eb2e8f9f7 3728 #define LCD_WF8B_BPGLCD6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3729 #define LCD_WF8B_BPGLCD6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3730 #define LCD_WF8B_BPGLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD6_SHIFT)) & LCD_WF8B_BPGLCD6_MASK)
<> 144:ef7eb2e8f9f7 3731 #define LCD_WF8B_BPGLCD51_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3732 #define LCD_WF8B_BPGLCD51_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3733 #define LCD_WF8B_BPGLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD51_SHIFT)) & LCD_WF8B_BPGLCD51_MASK)
<> 144:ef7eb2e8f9f7 3734 #define LCD_WF8B_BPGLCD16_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3735 #define LCD_WF8B_BPGLCD16_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3736 #define LCD_WF8B_BPGLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD16_SHIFT)) & LCD_WF8B_BPGLCD16_MASK)
<> 144:ef7eb2e8f9f7 3737 #define LCD_WF8B_BPGLCD1_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3738 #define LCD_WF8B_BPGLCD1_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3739 #define LCD_WF8B_BPGLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD1_SHIFT)) & LCD_WF8B_BPGLCD1_MASK)
<> 144:ef7eb2e8f9f7 3740 #define LCD_WF8B_BPGLCD17_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3741 #define LCD_WF8B_BPGLCD17_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3742 #define LCD_WF8B_BPGLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD17_SHIFT)) & LCD_WF8B_BPGLCD17_MASK)
<> 144:ef7eb2e8f9f7 3743 #define LCD_WF8B_BPGLCD50_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3744 #define LCD_WF8B_BPGLCD50_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3745 #define LCD_WF8B_BPGLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD50_SHIFT)) & LCD_WF8B_BPGLCD50_MASK)
<> 144:ef7eb2e8f9f7 3746 #define LCD_WF8B_BPGLCD18_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3747 #define LCD_WF8B_BPGLCD18_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3748 #define LCD_WF8B_BPGLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD18_SHIFT)) & LCD_WF8B_BPGLCD18_MASK)
<> 144:ef7eb2e8f9f7 3749 #define LCD_WF8B_BPGLCD19_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3750 #define LCD_WF8B_BPGLCD19_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3751 #define LCD_WF8B_BPGLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD19_SHIFT)) & LCD_WF8B_BPGLCD19_MASK)
<> 144:ef7eb2e8f9f7 3752 #define LCD_WF8B_BPGLCD8_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3753 #define LCD_WF8B_BPGLCD8_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3754 #define LCD_WF8B_BPGLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD8_SHIFT)) & LCD_WF8B_BPGLCD8_MASK)
<> 144:ef7eb2e8f9f7 3755 #define LCD_WF8B_BPGLCD49_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3756 #define LCD_WF8B_BPGLCD49_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3757 #define LCD_WF8B_BPGLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD49_SHIFT)) & LCD_WF8B_BPGLCD49_MASK)
<> 144:ef7eb2e8f9f7 3758 #define LCD_WF8B_BPGLCD20_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3759 #define LCD_WF8B_BPGLCD20_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3760 #define LCD_WF8B_BPGLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD20_SHIFT)) & LCD_WF8B_BPGLCD20_MASK)
<> 144:ef7eb2e8f9f7 3761 #define LCD_WF8B_BPGLCD9_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3762 #define LCD_WF8B_BPGLCD9_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3763 #define LCD_WF8B_BPGLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD9_SHIFT)) & LCD_WF8B_BPGLCD9_MASK)
<> 144:ef7eb2e8f9f7 3764 #define LCD_WF8B_BPGLCD21_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3765 #define LCD_WF8B_BPGLCD21_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3766 #define LCD_WF8B_BPGLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD21_SHIFT)) & LCD_WF8B_BPGLCD21_MASK)
<> 144:ef7eb2e8f9f7 3767 #define LCD_WF8B_BPGLCD13_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3768 #define LCD_WF8B_BPGLCD13_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3769 #define LCD_WF8B_BPGLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD13_SHIFT)) & LCD_WF8B_BPGLCD13_MASK)
<> 144:ef7eb2e8f9f7 3770 #define LCD_WF8B_BPGLCD48_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3771 #define LCD_WF8B_BPGLCD48_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3772 #define LCD_WF8B_BPGLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD48_SHIFT)) & LCD_WF8B_BPGLCD48_MASK)
<> 144:ef7eb2e8f9f7 3773 #define LCD_WF8B_BPGLCD22_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3774 #define LCD_WF8B_BPGLCD22_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3775 #define LCD_WF8B_BPGLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD22_SHIFT)) & LCD_WF8B_BPGLCD22_MASK)
<> 144:ef7eb2e8f9f7 3776 #define LCD_WF8B_BPGLCD5_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3777 #define LCD_WF8B_BPGLCD5_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3778 #define LCD_WF8B_BPGLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD5_SHIFT)) & LCD_WF8B_BPGLCD5_MASK)
<> 144:ef7eb2e8f9f7 3779 #define LCD_WF8B_BPGLCD47_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3780 #define LCD_WF8B_BPGLCD47_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3781 #define LCD_WF8B_BPGLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD47_SHIFT)) & LCD_WF8B_BPGLCD47_MASK)
<> 144:ef7eb2e8f9f7 3782 #define LCD_WF8B_BPGLCD23_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3783 #define LCD_WF8B_BPGLCD23_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3784 #define LCD_WF8B_BPGLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD23_SHIFT)) & LCD_WF8B_BPGLCD23_MASK)
<> 144:ef7eb2e8f9f7 3785 #define LCD_WF8B_BPGLCD24_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3786 #define LCD_WF8B_BPGLCD24_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3787 #define LCD_WF8B_BPGLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD24_SHIFT)) & LCD_WF8B_BPGLCD24_MASK)
<> 144:ef7eb2e8f9f7 3788 #define LCD_WF8B_BPGLCD25_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3789 #define LCD_WF8B_BPGLCD25_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3790 #define LCD_WF8B_BPGLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD25_SHIFT)) & LCD_WF8B_BPGLCD25_MASK)
<> 144:ef7eb2e8f9f7 3791 #define LCD_WF8B_BPGLCD46_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3792 #define LCD_WF8B_BPGLCD46_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3793 #define LCD_WF8B_BPGLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD46_SHIFT)) & LCD_WF8B_BPGLCD46_MASK)
<> 144:ef7eb2e8f9f7 3794 #define LCD_WF8B_BPGLCD26_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3795 #define LCD_WF8B_BPGLCD26_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3796 #define LCD_WF8B_BPGLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD26_SHIFT)) & LCD_WF8B_BPGLCD26_MASK)
<> 144:ef7eb2e8f9f7 3797 #define LCD_WF8B_BPGLCD27_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3798 #define LCD_WF8B_BPGLCD27_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3799 #define LCD_WF8B_BPGLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD27_SHIFT)) & LCD_WF8B_BPGLCD27_MASK)
<> 144:ef7eb2e8f9f7 3800 #define LCD_WF8B_BPGLCD10_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3801 #define LCD_WF8B_BPGLCD10_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3802 #define LCD_WF8B_BPGLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD10_SHIFT)) & LCD_WF8B_BPGLCD10_MASK)
<> 144:ef7eb2e8f9f7 3803 #define LCD_WF8B_BPGLCD45_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3804 #define LCD_WF8B_BPGLCD45_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3805 #define LCD_WF8B_BPGLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD45_SHIFT)) & LCD_WF8B_BPGLCD45_MASK)
<> 144:ef7eb2e8f9f7 3806 #define LCD_WF8B_BPGLCD28_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3807 #define LCD_WF8B_BPGLCD28_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3808 #define LCD_WF8B_BPGLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD28_SHIFT)) & LCD_WF8B_BPGLCD28_MASK)
<> 144:ef7eb2e8f9f7 3809 #define LCD_WF8B_BPGLCD29_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3810 #define LCD_WF8B_BPGLCD29_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3811 #define LCD_WF8B_BPGLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD29_SHIFT)) & LCD_WF8B_BPGLCD29_MASK)
<> 144:ef7eb2e8f9f7 3812 #define LCD_WF8B_BPGLCD4_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3813 #define LCD_WF8B_BPGLCD4_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3814 #define LCD_WF8B_BPGLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD4_SHIFT)) & LCD_WF8B_BPGLCD4_MASK)
<> 144:ef7eb2e8f9f7 3815 #define LCD_WF8B_BPGLCD44_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3816 #define LCD_WF8B_BPGLCD44_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3817 #define LCD_WF8B_BPGLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD44_SHIFT)) & LCD_WF8B_BPGLCD44_MASK)
<> 144:ef7eb2e8f9f7 3818 #define LCD_WF8B_BPGLCD30_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3819 #define LCD_WF8B_BPGLCD30_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3820 #define LCD_WF8B_BPGLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD30_SHIFT)) & LCD_WF8B_BPGLCD30_MASK)
<> 144:ef7eb2e8f9f7 3821 #define LCD_WF8B_BPGLCD2_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3822 #define LCD_WF8B_BPGLCD2_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3823 #define LCD_WF8B_BPGLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD2_SHIFT)) & LCD_WF8B_BPGLCD2_MASK)
<> 144:ef7eb2e8f9f7 3824 #define LCD_WF8B_BPGLCD31_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3825 #define LCD_WF8B_BPGLCD31_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3826 #define LCD_WF8B_BPGLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD31_SHIFT)) & LCD_WF8B_BPGLCD31_MASK)
<> 144:ef7eb2e8f9f7 3827 #define LCD_WF8B_BPGLCD43_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3828 #define LCD_WF8B_BPGLCD43_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3829 #define LCD_WF8B_BPGLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD43_SHIFT)) & LCD_WF8B_BPGLCD43_MASK)
<> 144:ef7eb2e8f9f7 3830 #define LCD_WF8B_BPGLCD32_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3831 #define LCD_WF8B_BPGLCD32_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3832 #define LCD_WF8B_BPGLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD32_SHIFT)) & LCD_WF8B_BPGLCD32_MASK)
<> 144:ef7eb2e8f9f7 3833 #define LCD_WF8B_BPGLCD33_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3834 #define LCD_WF8B_BPGLCD33_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3835 #define LCD_WF8B_BPGLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD33_SHIFT)) & LCD_WF8B_BPGLCD33_MASK)
<> 144:ef7eb2e8f9f7 3836 #define LCD_WF8B_BPGLCD42_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3837 #define LCD_WF8B_BPGLCD42_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3838 #define LCD_WF8B_BPGLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD42_SHIFT)) & LCD_WF8B_BPGLCD42_MASK)
<> 144:ef7eb2e8f9f7 3839 #define LCD_WF8B_BPGLCD34_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3840 #define LCD_WF8B_BPGLCD34_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3841 #define LCD_WF8B_BPGLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD34_SHIFT)) & LCD_WF8B_BPGLCD34_MASK)
<> 144:ef7eb2e8f9f7 3842 #define LCD_WF8B_BPGLCD11_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3843 #define LCD_WF8B_BPGLCD11_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3844 #define LCD_WF8B_BPGLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD11_SHIFT)) & LCD_WF8B_BPGLCD11_MASK)
<> 144:ef7eb2e8f9f7 3845 #define LCD_WF8B_BPGLCD35_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3846 #define LCD_WF8B_BPGLCD35_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3847 #define LCD_WF8B_BPGLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD35_SHIFT)) & LCD_WF8B_BPGLCD35_MASK)
<> 144:ef7eb2e8f9f7 3848 #define LCD_WF8B_BPGLCD12_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3849 #define LCD_WF8B_BPGLCD12_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3850 #define LCD_WF8B_BPGLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD12_SHIFT)) & LCD_WF8B_BPGLCD12_MASK)
<> 144:ef7eb2e8f9f7 3851 #define LCD_WF8B_BPGLCD41_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3852 #define LCD_WF8B_BPGLCD41_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3853 #define LCD_WF8B_BPGLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD41_SHIFT)) & LCD_WF8B_BPGLCD41_MASK)
<> 144:ef7eb2e8f9f7 3854 #define LCD_WF8B_BPGLCD36_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3855 #define LCD_WF8B_BPGLCD36_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3856 #define LCD_WF8B_BPGLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD36_SHIFT)) & LCD_WF8B_BPGLCD36_MASK)
<> 144:ef7eb2e8f9f7 3857 #define LCD_WF8B_BPGLCD3_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3858 #define LCD_WF8B_BPGLCD3_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3859 #define LCD_WF8B_BPGLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD3_SHIFT)) & LCD_WF8B_BPGLCD3_MASK)
<> 144:ef7eb2e8f9f7 3860 #define LCD_WF8B_BPGLCD37_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3861 #define LCD_WF8B_BPGLCD37_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3862 #define LCD_WF8B_BPGLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD37_SHIFT)) & LCD_WF8B_BPGLCD37_MASK)
<> 144:ef7eb2e8f9f7 3863 #define LCD_WF8B_BPGLCD40_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3864 #define LCD_WF8B_BPGLCD40_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3865 #define LCD_WF8B_BPGLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD40_SHIFT)) & LCD_WF8B_BPGLCD40_MASK)
<> 144:ef7eb2e8f9f7 3866 #define LCD_WF8B_BPGLCD38_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3867 #define LCD_WF8B_BPGLCD38_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3868 #define LCD_WF8B_BPGLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD38_SHIFT)) & LCD_WF8B_BPGLCD38_MASK)
<> 144:ef7eb2e8f9f7 3869 #define LCD_WF8B_BPGLCD39_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3870 #define LCD_WF8B_BPGLCD39_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3871 #define LCD_WF8B_BPGLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD39_SHIFT)) & LCD_WF8B_BPGLCD39_MASK)
<> 144:ef7eb2e8f9f7 3872 #define LCD_WF8B_BPHLCD63_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3873 #define LCD_WF8B_BPHLCD63_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3874 #define LCD_WF8B_BPHLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD63_SHIFT)) & LCD_WF8B_BPHLCD63_MASK)
<> 144:ef7eb2e8f9f7 3875 #define LCD_WF8B_BPHLCD62_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3876 #define LCD_WF8B_BPHLCD62_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3877 #define LCD_WF8B_BPHLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD62_SHIFT)) & LCD_WF8B_BPHLCD62_MASK)
<> 144:ef7eb2e8f9f7 3878 #define LCD_WF8B_BPHLCD61_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3879 #define LCD_WF8B_BPHLCD61_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3880 #define LCD_WF8B_BPHLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD61_SHIFT)) & LCD_WF8B_BPHLCD61_MASK)
<> 144:ef7eb2e8f9f7 3881 #define LCD_WF8B_BPHLCD60_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3882 #define LCD_WF8B_BPHLCD60_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3883 #define LCD_WF8B_BPHLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD60_SHIFT)) & LCD_WF8B_BPHLCD60_MASK)
<> 144:ef7eb2e8f9f7 3884 #define LCD_WF8B_BPHLCD59_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3885 #define LCD_WF8B_BPHLCD59_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3886 #define LCD_WF8B_BPHLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD59_SHIFT)) & LCD_WF8B_BPHLCD59_MASK)
<> 144:ef7eb2e8f9f7 3887 #define LCD_WF8B_BPHLCD58_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3888 #define LCD_WF8B_BPHLCD58_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3889 #define LCD_WF8B_BPHLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD58_SHIFT)) & LCD_WF8B_BPHLCD58_MASK)
<> 144:ef7eb2e8f9f7 3890 #define LCD_WF8B_BPHLCD57_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3891 #define LCD_WF8B_BPHLCD57_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3892 #define LCD_WF8B_BPHLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD57_SHIFT)) & LCD_WF8B_BPHLCD57_MASK)
<> 144:ef7eb2e8f9f7 3893 #define LCD_WF8B_BPHLCD0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3894 #define LCD_WF8B_BPHLCD0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3895 #define LCD_WF8B_BPHLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD0_SHIFT)) & LCD_WF8B_BPHLCD0_MASK)
<> 144:ef7eb2e8f9f7 3896 #define LCD_WF8B_BPHLCD56_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3897 #define LCD_WF8B_BPHLCD56_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3898 #define LCD_WF8B_BPHLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD56_SHIFT)) & LCD_WF8B_BPHLCD56_MASK)
<> 144:ef7eb2e8f9f7 3899 #define LCD_WF8B_BPHLCD55_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3900 #define LCD_WF8B_BPHLCD55_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3901 #define LCD_WF8B_BPHLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD55_SHIFT)) & LCD_WF8B_BPHLCD55_MASK)
<> 144:ef7eb2e8f9f7 3902 #define LCD_WF8B_BPHLCD54_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3903 #define LCD_WF8B_BPHLCD54_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3904 #define LCD_WF8B_BPHLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD54_SHIFT)) & LCD_WF8B_BPHLCD54_MASK)
<> 144:ef7eb2e8f9f7 3905 #define LCD_WF8B_BPHLCD53_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3906 #define LCD_WF8B_BPHLCD53_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3907 #define LCD_WF8B_BPHLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD53_SHIFT)) & LCD_WF8B_BPHLCD53_MASK)
<> 144:ef7eb2e8f9f7 3908 #define LCD_WF8B_BPHLCD52_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3909 #define LCD_WF8B_BPHLCD52_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3910 #define LCD_WF8B_BPHLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD52_SHIFT)) & LCD_WF8B_BPHLCD52_MASK)
<> 144:ef7eb2e8f9f7 3911 #define LCD_WF8B_BPHLCD51_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3912 #define LCD_WF8B_BPHLCD51_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3913 #define LCD_WF8B_BPHLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD51_SHIFT)) & LCD_WF8B_BPHLCD51_MASK)
<> 144:ef7eb2e8f9f7 3914 #define LCD_WF8B_BPHLCD50_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3915 #define LCD_WF8B_BPHLCD50_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3916 #define LCD_WF8B_BPHLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD50_SHIFT)) & LCD_WF8B_BPHLCD50_MASK)
<> 144:ef7eb2e8f9f7 3917 #define LCD_WF8B_BPHLCD1_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3918 #define LCD_WF8B_BPHLCD1_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3919 #define LCD_WF8B_BPHLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD1_SHIFT)) & LCD_WF8B_BPHLCD1_MASK)
<> 144:ef7eb2e8f9f7 3920 #define LCD_WF8B_BPHLCD49_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3921 #define LCD_WF8B_BPHLCD49_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3922 #define LCD_WF8B_BPHLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD49_SHIFT)) & LCD_WF8B_BPHLCD49_MASK)
<> 144:ef7eb2e8f9f7 3923 #define LCD_WF8B_BPHLCD48_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3924 #define LCD_WF8B_BPHLCD48_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3925 #define LCD_WF8B_BPHLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD48_SHIFT)) & LCD_WF8B_BPHLCD48_MASK)
<> 144:ef7eb2e8f9f7 3926 #define LCD_WF8B_BPHLCD47_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3927 #define LCD_WF8B_BPHLCD47_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3928 #define LCD_WF8B_BPHLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD47_SHIFT)) & LCD_WF8B_BPHLCD47_MASK)
<> 144:ef7eb2e8f9f7 3929 #define LCD_WF8B_BPHLCD46_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3930 #define LCD_WF8B_BPHLCD46_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3931 #define LCD_WF8B_BPHLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD46_SHIFT)) & LCD_WF8B_BPHLCD46_MASK)
<> 144:ef7eb2e8f9f7 3932 #define LCD_WF8B_BPHLCD45_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3933 #define LCD_WF8B_BPHLCD45_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3934 #define LCD_WF8B_BPHLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD45_SHIFT)) & LCD_WF8B_BPHLCD45_MASK)
<> 144:ef7eb2e8f9f7 3935 #define LCD_WF8B_BPHLCD44_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3936 #define LCD_WF8B_BPHLCD44_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3937 #define LCD_WF8B_BPHLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD44_SHIFT)) & LCD_WF8B_BPHLCD44_MASK)
<> 144:ef7eb2e8f9f7 3938 #define LCD_WF8B_BPHLCD43_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3939 #define LCD_WF8B_BPHLCD43_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3940 #define LCD_WF8B_BPHLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD43_SHIFT)) & LCD_WF8B_BPHLCD43_MASK)
<> 144:ef7eb2e8f9f7 3941 #define LCD_WF8B_BPHLCD2_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3942 #define LCD_WF8B_BPHLCD2_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3943 #define LCD_WF8B_BPHLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD2_SHIFT)) & LCD_WF8B_BPHLCD2_MASK)
<> 144:ef7eb2e8f9f7 3944 #define LCD_WF8B_BPHLCD42_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3945 #define LCD_WF8B_BPHLCD42_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3946 #define LCD_WF8B_BPHLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD42_SHIFT)) & LCD_WF8B_BPHLCD42_MASK)
<> 144:ef7eb2e8f9f7 3947 #define LCD_WF8B_BPHLCD41_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3948 #define LCD_WF8B_BPHLCD41_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3949 #define LCD_WF8B_BPHLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD41_SHIFT)) & LCD_WF8B_BPHLCD41_MASK)
<> 144:ef7eb2e8f9f7 3950 #define LCD_WF8B_BPHLCD40_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3951 #define LCD_WF8B_BPHLCD40_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3952 #define LCD_WF8B_BPHLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD40_SHIFT)) & LCD_WF8B_BPHLCD40_MASK)
<> 144:ef7eb2e8f9f7 3953 #define LCD_WF8B_BPHLCD39_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3954 #define LCD_WF8B_BPHLCD39_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3955 #define LCD_WF8B_BPHLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD39_SHIFT)) & LCD_WF8B_BPHLCD39_MASK)
<> 144:ef7eb2e8f9f7 3956 #define LCD_WF8B_BPHLCD38_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3957 #define LCD_WF8B_BPHLCD38_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3958 #define LCD_WF8B_BPHLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD38_SHIFT)) & LCD_WF8B_BPHLCD38_MASK)
<> 144:ef7eb2e8f9f7 3959 #define LCD_WF8B_BPHLCD37_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3960 #define LCD_WF8B_BPHLCD37_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3961 #define LCD_WF8B_BPHLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD37_SHIFT)) & LCD_WF8B_BPHLCD37_MASK)
<> 144:ef7eb2e8f9f7 3962 #define LCD_WF8B_BPHLCD36_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3963 #define LCD_WF8B_BPHLCD36_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3964 #define LCD_WF8B_BPHLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD36_SHIFT)) & LCD_WF8B_BPHLCD36_MASK)
<> 144:ef7eb2e8f9f7 3965 #define LCD_WF8B_BPHLCD3_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3966 #define LCD_WF8B_BPHLCD3_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3967 #define LCD_WF8B_BPHLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD3_SHIFT)) & LCD_WF8B_BPHLCD3_MASK)
<> 144:ef7eb2e8f9f7 3968 #define LCD_WF8B_BPHLCD35_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3969 #define LCD_WF8B_BPHLCD35_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3970 #define LCD_WF8B_BPHLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD35_SHIFT)) & LCD_WF8B_BPHLCD35_MASK)
<> 144:ef7eb2e8f9f7 3971 #define LCD_WF8B_BPHLCD34_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3972 #define LCD_WF8B_BPHLCD34_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3973 #define LCD_WF8B_BPHLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD34_SHIFT)) & LCD_WF8B_BPHLCD34_MASK)
<> 144:ef7eb2e8f9f7 3974 #define LCD_WF8B_BPHLCD33_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3975 #define LCD_WF8B_BPHLCD33_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3976 #define LCD_WF8B_BPHLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD33_SHIFT)) & LCD_WF8B_BPHLCD33_MASK)
<> 144:ef7eb2e8f9f7 3977 #define LCD_WF8B_BPHLCD32_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3978 #define LCD_WF8B_BPHLCD32_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3979 #define LCD_WF8B_BPHLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD32_SHIFT)) & LCD_WF8B_BPHLCD32_MASK)
<> 144:ef7eb2e8f9f7 3980 #define LCD_WF8B_BPHLCD31_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3981 #define LCD_WF8B_BPHLCD31_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3982 #define LCD_WF8B_BPHLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD31_SHIFT)) & LCD_WF8B_BPHLCD31_MASK)
<> 144:ef7eb2e8f9f7 3983 #define LCD_WF8B_BPHLCD30_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3984 #define LCD_WF8B_BPHLCD30_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3985 #define LCD_WF8B_BPHLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD30_SHIFT)) & LCD_WF8B_BPHLCD30_MASK)
<> 144:ef7eb2e8f9f7 3986 #define LCD_WF8B_BPHLCD29_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3987 #define LCD_WF8B_BPHLCD29_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3988 #define LCD_WF8B_BPHLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD29_SHIFT)) & LCD_WF8B_BPHLCD29_MASK)
<> 144:ef7eb2e8f9f7 3989 #define LCD_WF8B_BPHLCD4_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3990 #define LCD_WF8B_BPHLCD4_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3991 #define LCD_WF8B_BPHLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD4_SHIFT)) & LCD_WF8B_BPHLCD4_MASK)
<> 144:ef7eb2e8f9f7 3992 #define LCD_WF8B_BPHLCD28_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3993 #define LCD_WF8B_BPHLCD28_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3994 #define LCD_WF8B_BPHLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD28_SHIFT)) & LCD_WF8B_BPHLCD28_MASK)
<> 144:ef7eb2e8f9f7 3995 #define LCD_WF8B_BPHLCD27_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3996 #define LCD_WF8B_BPHLCD27_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3997 #define LCD_WF8B_BPHLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD27_SHIFT)) & LCD_WF8B_BPHLCD27_MASK)
<> 144:ef7eb2e8f9f7 3998 #define LCD_WF8B_BPHLCD26_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3999 #define LCD_WF8B_BPHLCD26_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4000 #define LCD_WF8B_BPHLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD26_SHIFT)) & LCD_WF8B_BPHLCD26_MASK)
<> 144:ef7eb2e8f9f7 4001 #define LCD_WF8B_BPHLCD25_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4002 #define LCD_WF8B_BPHLCD25_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4003 #define LCD_WF8B_BPHLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD25_SHIFT)) & LCD_WF8B_BPHLCD25_MASK)
<> 144:ef7eb2e8f9f7 4004 #define LCD_WF8B_BPHLCD24_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4005 #define LCD_WF8B_BPHLCD24_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4006 #define LCD_WF8B_BPHLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD24_SHIFT)) & LCD_WF8B_BPHLCD24_MASK)
<> 144:ef7eb2e8f9f7 4007 #define LCD_WF8B_BPHLCD23_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4008 #define LCD_WF8B_BPHLCD23_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4009 #define LCD_WF8B_BPHLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD23_SHIFT)) & LCD_WF8B_BPHLCD23_MASK)
<> 144:ef7eb2e8f9f7 4010 #define LCD_WF8B_BPHLCD22_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4011 #define LCD_WF8B_BPHLCD22_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4012 #define LCD_WF8B_BPHLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD22_SHIFT)) & LCD_WF8B_BPHLCD22_MASK)
<> 144:ef7eb2e8f9f7 4013 #define LCD_WF8B_BPHLCD5_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4014 #define LCD_WF8B_BPHLCD5_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4015 #define LCD_WF8B_BPHLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD5_SHIFT)) & LCD_WF8B_BPHLCD5_MASK)
<> 144:ef7eb2e8f9f7 4016 #define LCD_WF8B_BPHLCD21_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4017 #define LCD_WF8B_BPHLCD21_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4018 #define LCD_WF8B_BPHLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD21_SHIFT)) & LCD_WF8B_BPHLCD21_MASK)
<> 144:ef7eb2e8f9f7 4019 #define LCD_WF8B_BPHLCD20_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4020 #define LCD_WF8B_BPHLCD20_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4021 #define LCD_WF8B_BPHLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD20_SHIFT)) & LCD_WF8B_BPHLCD20_MASK)
<> 144:ef7eb2e8f9f7 4022 #define LCD_WF8B_BPHLCD19_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4023 #define LCD_WF8B_BPHLCD19_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4024 #define LCD_WF8B_BPHLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD19_SHIFT)) & LCD_WF8B_BPHLCD19_MASK)
<> 144:ef7eb2e8f9f7 4025 #define LCD_WF8B_BPHLCD18_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4026 #define LCD_WF8B_BPHLCD18_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4027 #define LCD_WF8B_BPHLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD18_SHIFT)) & LCD_WF8B_BPHLCD18_MASK)
<> 144:ef7eb2e8f9f7 4028 #define LCD_WF8B_BPHLCD17_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4029 #define LCD_WF8B_BPHLCD17_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4030 #define LCD_WF8B_BPHLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD17_SHIFT)) & LCD_WF8B_BPHLCD17_MASK)
<> 144:ef7eb2e8f9f7 4031 #define LCD_WF8B_BPHLCD16_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4032 #define LCD_WF8B_BPHLCD16_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4033 #define LCD_WF8B_BPHLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD16_SHIFT)) & LCD_WF8B_BPHLCD16_MASK)
<> 144:ef7eb2e8f9f7 4034 #define LCD_WF8B_BPHLCD15_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4035 #define LCD_WF8B_BPHLCD15_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4036 #define LCD_WF8B_BPHLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD15_SHIFT)) & LCD_WF8B_BPHLCD15_MASK)
<> 144:ef7eb2e8f9f7 4037 #define LCD_WF8B_BPHLCD6_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4038 #define LCD_WF8B_BPHLCD6_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4039 #define LCD_WF8B_BPHLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD6_SHIFT)) & LCD_WF8B_BPHLCD6_MASK)
<> 144:ef7eb2e8f9f7 4040 #define LCD_WF8B_BPHLCD14_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4041 #define LCD_WF8B_BPHLCD14_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4042 #define LCD_WF8B_BPHLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD14_SHIFT)) & LCD_WF8B_BPHLCD14_MASK)
<> 144:ef7eb2e8f9f7 4043 #define LCD_WF8B_BPHLCD13_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4044 #define LCD_WF8B_BPHLCD13_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4045 #define LCD_WF8B_BPHLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD13_SHIFT)) & LCD_WF8B_BPHLCD13_MASK)
<> 144:ef7eb2e8f9f7 4046 #define LCD_WF8B_BPHLCD12_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4047 #define LCD_WF8B_BPHLCD12_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4048 #define LCD_WF8B_BPHLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD12_SHIFT)) & LCD_WF8B_BPHLCD12_MASK)
<> 144:ef7eb2e8f9f7 4049 #define LCD_WF8B_BPHLCD11_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4050 #define LCD_WF8B_BPHLCD11_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4051 #define LCD_WF8B_BPHLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD11_SHIFT)) & LCD_WF8B_BPHLCD11_MASK)
<> 144:ef7eb2e8f9f7 4052 #define LCD_WF8B_BPHLCD10_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4053 #define LCD_WF8B_BPHLCD10_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4054 #define LCD_WF8B_BPHLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD10_SHIFT)) & LCD_WF8B_BPHLCD10_MASK)
<> 144:ef7eb2e8f9f7 4055 #define LCD_WF8B_BPHLCD9_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4056 #define LCD_WF8B_BPHLCD9_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4057 #define LCD_WF8B_BPHLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD9_SHIFT)) & LCD_WF8B_BPHLCD9_MASK)
<> 144:ef7eb2e8f9f7 4058 #define LCD_WF8B_BPHLCD8_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4059 #define LCD_WF8B_BPHLCD8_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4060 #define LCD_WF8B_BPHLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD8_SHIFT)) & LCD_WF8B_BPHLCD8_MASK)
<> 144:ef7eb2e8f9f7 4061 #define LCD_WF8B_BPHLCD7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4062 #define LCD_WF8B_BPHLCD7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4063 #define LCD_WF8B_BPHLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD7_SHIFT)) & LCD_WF8B_BPHLCD7_MASK)
<> 144:ef7eb2e8f9f7 4064
<> 144:ef7eb2e8f9f7 4065 /* The count of LCD_WF8B */
<> 144:ef7eb2e8f9f7 4066 #define LCD_WF8B_COUNT (64U)
<> 144:ef7eb2e8f9f7 4067
<> 144:ef7eb2e8f9f7 4068
<> 144:ef7eb2e8f9f7 4069 /*!
<> 144:ef7eb2e8f9f7 4070 * @}
<> 144:ef7eb2e8f9f7 4071 */ /* end of group LCD_Register_Masks */
<> 144:ef7eb2e8f9f7 4072
<> 144:ef7eb2e8f9f7 4073
<> 144:ef7eb2e8f9f7 4074 /* LCD - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 4075 /** Peripheral LCD base address */
<> 144:ef7eb2e8f9f7 4076 #define LCD_BASE (0x40053000u)
<> 144:ef7eb2e8f9f7 4077 /** Peripheral LCD base pointer */
<> 144:ef7eb2e8f9f7 4078 #define LCD ((LCD_Type *)LCD_BASE)
<> 144:ef7eb2e8f9f7 4079 /** Array initializer of LCD peripheral base addresses */
<> 144:ef7eb2e8f9f7 4080 #define LCD_BASE_ADDRS { LCD_BASE }
<> 144:ef7eb2e8f9f7 4081 /** Array initializer of LCD peripheral base pointers */
<> 144:ef7eb2e8f9f7 4082 #define LCD_BASE_PTRS { LCD }
<> 144:ef7eb2e8f9f7 4083 /** Interrupt vectors for the LCD peripheral type */
<> 144:ef7eb2e8f9f7 4084 #define LCD_LCD_IRQS { LCD_IRQn }
<> 144:ef7eb2e8f9f7 4085
<> 144:ef7eb2e8f9f7 4086 /*!
<> 144:ef7eb2e8f9f7 4087 * @}
<> 144:ef7eb2e8f9f7 4088 */ /* end of group LCD_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 4089
<> 144:ef7eb2e8f9f7 4090
<> 144:ef7eb2e8f9f7 4091 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4092 -- LLWU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4093 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4094
<> 144:ef7eb2e8f9f7 4095 /*!
<> 144:ef7eb2e8f9f7 4096 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4097 * @{
<> 144:ef7eb2e8f9f7 4098 */
<> 144:ef7eb2e8f9f7 4099
<> 144:ef7eb2e8f9f7 4100 /** LLWU - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 4101 typedef struct {
<> 144:ef7eb2e8f9f7 4102 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 4103 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 4104 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 4105 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 4106 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 4107 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 4108 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 4109 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 4110 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 4111 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
<> 144:ef7eb2e8f9f7 4112 } LLWU_Type;
<> 144:ef7eb2e8f9f7 4113
<> 144:ef7eb2e8f9f7 4114 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4115 -- LLWU Register Masks
<> 144:ef7eb2e8f9f7 4116 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4117
<> 144:ef7eb2e8f9f7 4118 /*!
<> 144:ef7eb2e8f9f7 4119 * @addtogroup LLWU_Register_Masks LLWU Register Masks
<> 144:ef7eb2e8f9f7 4120 * @{
<> 144:ef7eb2e8f9f7 4121 */
<> 144:ef7eb2e8f9f7 4122
<> 144:ef7eb2e8f9f7 4123 /*! @name PE1 - LLWU Pin Enable 1 register */
<> 144:ef7eb2e8f9f7 4124 #define LLWU_PE1_WUPE0_MASK (0x3U)
<> 144:ef7eb2e8f9f7 4125 #define LLWU_PE1_WUPE0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4126 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
<> 144:ef7eb2e8f9f7 4127 #define LLWU_PE1_WUPE1_MASK (0xCU)
<> 144:ef7eb2e8f9f7 4128 #define LLWU_PE1_WUPE1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4129 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
<> 144:ef7eb2e8f9f7 4130 #define LLWU_PE1_WUPE2_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4131 #define LLWU_PE1_WUPE2_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4132 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
<> 144:ef7eb2e8f9f7 4133 #define LLWU_PE1_WUPE3_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 4134 #define LLWU_PE1_WUPE3_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4135 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
<> 144:ef7eb2e8f9f7 4136
<> 144:ef7eb2e8f9f7 4137 /*! @name PE2 - LLWU Pin Enable 2 register */
<> 144:ef7eb2e8f9f7 4138 #define LLWU_PE2_WUPE4_MASK (0x3U)
<> 144:ef7eb2e8f9f7 4139 #define LLWU_PE2_WUPE4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4140 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
<> 144:ef7eb2e8f9f7 4141 #define LLWU_PE2_WUPE5_MASK (0xCU)
<> 144:ef7eb2e8f9f7 4142 #define LLWU_PE2_WUPE5_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4143 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
<> 144:ef7eb2e8f9f7 4144 #define LLWU_PE2_WUPE6_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4145 #define LLWU_PE2_WUPE6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4146 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
<> 144:ef7eb2e8f9f7 4147 #define LLWU_PE2_WUPE7_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 4148 #define LLWU_PE2_WUPE7_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4149 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
<> 144:ef7eb2e8f9f7 4150
<> 144:ef7eb2e8f9f7 4151 /*! @name PE3 - LLWU Pin Enable 3 register */
<> 144:ef7eb2e8f9f7 4152 #define LLWU_PE3_WUPE8_MASK (0x3U)
<> 144:ef7eb2e8f9f7 4153 #define LLWU_PE3_WUPE8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4154 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
<> 144:ef7eb2e8f9f7 4155 #define LLWU_PE3_WUPE9_MASK (0xCU)
<> 144:ef7eb2e8f9f7 4156 #define LLWU_PE3_WUPE9_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4157 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
<> 144:ef7eb2e8f9f7 4158 #define LLWU_PE3_WUPE10_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4159 #define LLWU_PE3_WUPE10_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4160 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
<> 144:ef7eb2e8f9f7 4161 #define LLWU_PE3_WUPE11_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 4162 #define LLWU_PE3_WUPE11_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4163 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
<> 144:ef7eb2e8f9f7 4164
<> 144:ef7eb2e8f9f7 4165 /*! @name PE4 - LLWU Pin Enable 4 register */
<> 144:ef7eb2e8f9f7 4166 #define LLWU_PE4_WUPE12_MASK (0x3U)
<> 144:ef7eb2e8f9f7 4167 #define LLWU_PE4_WUPE12_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4168 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
<> 144:ef7eb2e8f9f7 4169 #define LLWU_PE4_WUPE13_MASK (0xCU)
<> 144:ef7eb2e8f9f7 4170 #define LLWU_PE4_WUPE13_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4171 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
<> 144:ef7eb2e8f9f7 4172 #define LLWU_PE4_WUPE14_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4173 #define LLWU_PE4_WUPE14_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4174 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
<> 144:ef7eb2e8f9f7 4175 #define LLWU_PE4_WUPE15_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 4176 #define LLWU_PE4_WUPE15_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4177 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
<> 144:ef7eb2e8f9f7 4178
<> 144:ef7eb2e8f9f7 4179 /*! @name ME - LLWU Module Enable register */
<> 144:ef7eb2e8f9f7 4180 #define LLWU_ME_WUME0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4181 #define LLWU_ME_WUME0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4182 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
<> 144:ef7eb2e8f9f7 4183 #define LLWU_ME_WUME1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4184 #define LLWU_ME_WUME1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4185 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
<> 144:ef7eb2e8f9f7 4186 #define LLWU_ME_WUME2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4187 #define LLWU_ME_WUME2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4188 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
<> 144:ef7eb2e8f9f7 4189 #define LLWU_ME_WUME3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4190 #define LLWU_ME_WUME3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4191 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
<> 144:ef7eb2e8f9f7 4192 #define LLWU_ME_WUME4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4193 #define LLWU_ME_WUME4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4194 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
<> 144:ef7eb2e8f9f7 4195 #define LLWU_ME_WUME5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4196 #define LLWU_ME_WUME5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4197 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
<> 144:ef7eb2e8f9f7 4198 #define LLWU_ME_WUME6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4199 #define LLWU_ME_WUME6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4200 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
<> 144:ef7eb2e8f9f7 4201 #define LLWU_ME_WUME7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4202 #define LLWU_ME_WUME7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4203 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
<> 144:ef7eb2e8f9f7 4204
<> 144:ef7eb2e8f9f7 4205 /*! @name F1 - LLWU Flag 1 register */
<> 144:ef7eb2e8f9f7 4206 #define LLWU_F1_WUF0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4207 #define LLWU_F1_WUF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4208 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
<> 144:ef7eb2e8f9f7 4209 #define LLWU_F1_WUF1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4210 #define LLWU_F1_WUF1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4211 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
<> 144:ef7eb2e8f9f7 4212 #define LLWU_F1_WUF2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4213 #define LLWU_F1_WUF2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4214 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
<> 144:ef7eb2e8f9f7 4215 #define LLWU_F1_WUF3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4216 #define LLWU_F1_WUF3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4217 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
<> 144:ef7eb2e8f9f7 4218 #define LLWU_F1_WUF4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4219 #define LLWU_F1_WUF4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4220 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
<> 144:ef7eb2e8f9f7 4221 #define LLWU_F1_WUF5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4222 #define LLWU_F1_WUF5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4223 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
<> 144:ef7eb2e8f9f7 4224 #define LLWU_F1_WUF6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4225 #define LLWU_F1_WUF6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4226 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
<> 144:ef7eb2e8f9f7 4227 #define LLWU_F1_WUF7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4228 #define LLWU_F1_WUF7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4229 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
<> 144:ef7eb2e8f9f7 4230
<> 144:ef7eb2e8f9f7 4231 /*! @name F2 - LLWU Flag 2 register */
<> 144:ef7eb2e8f9f7 4232 #define LLWU_F2_WUF8_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4233 #define LLWU_F2_WUF8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4234 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
<> 144:ef7eb2e8f9f7 4235 #define LLWU_F2_WUF9_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4236 #define LLWU_F2_WUF9_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4237 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
<> 144:ef7eb2e8f9f7 4238 #define LLWU_F2_WUF10_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4239 #define LLWU_F2_WUF10_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4240 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
<> 144:ef7eb2e8f9f7 4241 #define LLWU_F2_WUF11_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4242 #define LLWU_F2_WUF11_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4243 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
<> 144:ef7eb2e8f9f7 4244 #define LLWU_F2_WUF12_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4245 #define LLWU_F2_WUF12_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4246 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
<> 144:ef7eb2e8f9f7 4247 #define LLWU_F2_WUF13_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4248 #define LLWU_F2_WUF13_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4249 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
<> 144:ef7eb2e8f9f7 4250 #define LLWU_F2_WUF14_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4251 #define LLWU_F2_WUF14_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4252 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
<> 144:ef7eb2e8f9f7 4253 #define LLWU_F2_WUF15_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4254 #define LLWU_F2_WUF15_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4255 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
<> 144:ef7eb2e8f9f7 4256
<> 144:ef7eb2e8f9f7 4257 /*! @name F3 - LLWU Flag 3 register */
<> 144:ef7eb2e8f9f7 4258 #define LLWU_F3_MWUF0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4259 #define LLWU_F3_MWUF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4260 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
<> 144:ef7eb2e8f9f7 4261 #define LLWU_F3_MWUF1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4262 #define LLWU_F3_MWUF1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4263 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
<> 144:ef7eb2e8f9f7 4264 #define LLWU_F3_MWUF2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4265 #define LLWU_F3_MWUF2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4266 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
<> 144:ef7eb2e8f9f7 4267 #define LLWU_F3_MWUF3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4268 #define LLWU_F3_MWUF3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4269 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
<> 144:ef7eb2e8f9f7 4270 #define LLWU_F3_MWUF4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4271 #define LLWU_F3_MWUF4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4272 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
<> 144:ef7eb2e8f9f7 4273 #define LLWU_F3_MWUF5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4274 #define LLWU_F3_MWUF5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4275 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
<> 144:ef7eb2e8f9f7 4276 #define LLWU_F3_MWUF6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4277 #define LLWU_F3_MWUF6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4278 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
<> 144:ef7eb2e8f9f7 4279 #define LLWU_F3_MWUF7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4280 #define LLWU_F3_MWUF7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4281 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
<> 144:ef7eb2e8f9f7 4282
<> 144:ef7eb2e8f9f7 4283 /*! @name FILT1 - LLWU Pin Filter 1 register */
<> 144:ef7eb2e8f9f7 4284 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4285 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4286 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
<> 144:ef7eb2e8f9f7 4287 #define LLWU_FILT1_FILTE_MASK (0x60U)
<> 144:ef7eb2e8f9f7 4288 #define LLWU_FILT1_FILTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4289 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
<> 144:ef7eb2e8f9f7 4290 #define LLWU_FILT1_FILTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4291 #define LLWU_FILT1_FILTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4292 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
<> 144:ef7eb2e8f9f7 4293
<> 144:ef7eb2e8f9f7 4294 /*! @name FILT2 - LLWU Pin Filter 2 register */
<> 144:ef7eb2e8f9f7 4295 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4296 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4297 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
<> 144:ef7eb2e8f9f7 4298 #define LLWU_FILT2_FILTE_MASK (0x60U)
<> 144:ef7eb2e8f9f7 4299 #define LLWU_FILT2_FILTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4300 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
<> 144:ef7eb2e8f9f7 4301 #define LLWU_FILT2_FILTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4302 #define LLWU_FILT2_FILTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4303 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
<> 144:ef7eb2e8f9f7 4304
<> 144:ef7eb2e8f9f7 4305
<> 144:ef7eb2e8f9f7 4306 /*!
<> 144:ef7eb2e8f9f7 4307 * @}
<> 144:ef7eb2e8f9f7 4308 */ /* end of group LLWU_Register_Masks */
<> 144:ef7eb2e8f9f7 4309
<> 144:ef7eb2e8f9f7 4310
<> 144:ef7eb2e8f9f7 4311 /* LLWU - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 4312 /** Peripheral LLWU base address */
<> 144:ef7eb2e8f9f7 4313 #define LLWU_BASE (0x4007C000u)
<> 144:ef7eb2e8f9f7 4314 /** Peripheral LLWU base pointer */
<> 144:ef7eb2e8f9f7 4315 #define LLWU ((LLWU_Type *)LLWU_BASE)
<> 144:ef7eb2e8f9f7 4316 /** Array initializer of LLWU peripheral base addresses */
<> 144:ef7eb2e8f9f7 4317 #define LLWU_BASE_ADDRS { LLWU_BASE }
<> 144:ef7eb2e8f9f7 4318 /** Array initializer of LLWU peripheral base pointers */
<> 144:ef7eb2e8f9f7 4319 #define LLWU_BASE_PTRS { LLWU }
<> 144:ef7eb2e8f9f7 4320 /** Interrupt vectors for the LLWU peripheral type */
<> 144:ef7eb2e8f9f7 4321 #define LLWU_IRQS { LLWU_IRQn }
<> 144:ef7eb2e8f9f7 4322
<> 144:ef7eb2e8f9f7 4323 /*!
<> 144:ef7eb2e8f9f7 4324 * @}
<> 144:ef7eb2e8f9f7 4325 */ /* end of group LLWU_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 4326
<> 144:ef7eb2e8f9f7 4327
<> 144:ef7eb2e8f9f7 4328 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4329 -- LPTMR Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4330 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4331
<> 144:ef7eb2e8f9f7 4332 /*!
<> 144:ef7eb2e8f9f7 4333 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4334 * @{
<> 144:ef7eb2e8f9f7 4335 */
<> 144:ef7eb2e8f9f7 4336
<> 144:ef7eb2e8f9f7 4337 /** LPTMR - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 4338 typedef struct {
<> 144:ef7eb2e8f9f7 4339 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 4340 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 4341 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 4342 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 4343 } LPTMR_Type;
<> 144:ef7eb2e8f9f7 4344
<> 144:ef7eb2e8f9f7 4345 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4346 -- LPTMR Register Masks
<> 144:ef7eb2e8f9f7 4347 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4348
<> 144:ef7eb2e8f9f7 4349 /*!
<> 144:ef7eb2e8f9f7 4350 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
<> 144:ef7eb2e8f9f7 4351 * @{
<> 144:ef7eb2e8f9f7 4352 */
<> 144:ef7eb2e8f9f7 4353
<> 144:ef7eb2e8f9f7 4354 /*! @name CSR - Low Power Timer Control Status Register */
<> 144:ef7eb2e8f9f7 4355 #define LPTMR_CSR_TEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4356 #define LPTMR_CSR_TEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4357 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
<> 144:ef7eb2e8f9f7 4358 #define LPTMR_CSR_TMS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4359 #define LPTMR_CSR_TMS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4360 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
<> 144:ef7eb2e8f9f7 4361 #define LPTMR_CSR_TFC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4362 #define LPTMR_CSR_TFC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4363 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
<> 144:ef7eb2e8f9f7 4364 #define LPTMR_CSR_TPP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4365 #define LPTMR_CSR_TPP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4366 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
<> 144:ef7eb2e8f9f7 4367 #define LPTMR_CSR_TPS_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4368 #define LPTMR_CSR_TPS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4369 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
<> 144:ef7eb2e8f9f7 4370 #define LPTMR_CSR_TIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4371 #define LPTMR_CSR_TIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4372 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
<> 144:ef7eb2e8f9f7 4373 #define LPTMR_CSR_TCF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4374 #define LPTMR_CSR_TCF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4375 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
<> 144:ef7eb2e8f9f7 4376
<> 144:ef7eb2e8f9f7 4377 /*! @name PSR - Low Power Timer Prescale Register */
<> 144:ef7eb2e8f9f7 4378 #define LPTMR_PSR_PCS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 4379 #define LPTMR_PSR_PCS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4380 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
<> 144:ef7eb2e8f9f7 4381 #define LPTMR_PSR_PBYP_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4382 #define LPTMR_PSR_PBYP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4383 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
<> 144:ef7eb2e8f9f7 4384 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
<> 144:ef7eb2e8f9f7 4385 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4386 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
<> 144:ef7eb2e8f9f7 4387
<> 144:ef7eb2e8f9f7 4388 /*! @name CMR - Low Power Timer Compare Register */
<> 144:ef7eb2e8f9f7 4389 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 4390 #define LPTMR_CMR_COMPARE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4391 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
<> 144:ef7eb2e8f9f7 4392
<> 144:ef7eb2e8f9f7 4393 /*! @name CNR - Low Power Timer Counter Register */
<> 144:ef7eb2e8f9f7 4394 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 4395 #define LPTMR_CNR_COUNTER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4396 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
<> 144:ef7eb2e8f9f7 4397
<> 144:ef7eb2e8f9f7 4398
<> 144:ef7eb2e8f9f7 4399 /*!
<> 144:ef7eb2e8f9f7 4400 * @}
<> 144:ef7eb2e8f9f7 4401 */ /* end of group LPTMR_Register_Masks */
<> 144:ef7eb2e8f9f7 4402
<> 144:ef7eb2e8f9f7 4403
<> 144:ef7eb2e8f9f7 4404 /* LPTMR - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 4405 /** Peripheral LPTMR0 base address */
<> 144:ef7eb2e8f9f7 4406 #define LPTMR0_BASE (0x40040000u)
<> 144:ef7eb2e8f9f7 4407 /** Peripheral LPTMR0 base pointer */
<> 144:ef7eb2e8f9f7 4408 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
<> 144:ef7eb2e8f9f7 4409 /** Array initializer of LPTMR peripheral base addresses */
<> 144:ef7eb2e8f9f7 4410 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
<> 144:ef7eb2e8f9f7 4411 /** Array initializer of LPTMR peripheral base pointers */
<> 144:ef7eb2e8f9f7 4412 #define LPTMR_BASE_PTRS { LPTMR0 }
<> 144:ef7eb2e8f9f7 4413 /** Interrupt vectors for the LPTMR peripheral type */
<> 144:ef7eb2e8f9f7 4414 #define LPTMR_IRQS { LPTMR0_IRQn }
<> 144:ef7eb2e8f9f7 4415
<> 144:ef7eb2e8f9f7 4416 /*!
<> 144:ef7eb2e8f9f7 4417 * @}
<> 144:ef7eb2e8f9f7 4418 */ /* end of group LPTMR_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 4419
<> 144:ef7eb2e8f9f7 4420
<> 144:ef7eb2e8f9f7 4421 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4422 -- LPUART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4423 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4424
<> 144:ef7eb2e8f9f7 4425 /*!
<> 144:ef7eb2e8f9f7 4426 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4427 * @{
<> 144:ef7eb2e8f9f7 4428 */
<> 144:ef7eb2e8f9f7 4429
<> 144:ef7eb2e8f9f7 4430 /** LPUART - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 4431 typedef struct {
<> 144:ef7eb2e8f9f7 4432 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 4433 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 4434 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 4435 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 4436 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 4437 } LPUART_Type;
<> 144:ef7eb2e8f9f7 4438
<> 144:ef7eb2e8f9f7 4439 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4440 -- LPUART Register Masks
<> 144:ef7eb2e8f9f7 4441 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4442
<> 144:ef7eb2e8f9f7 4443 /*!
<> 144:ef7eb2e8f9f7 4444 * @addtogroup LPUART_Register_Masks LPUART Register Masks
<> 144:ef7eb2e8f9f7 4445 * @{
<> 144:ef7eb2e8f9f7 4446 */
<> 144:ef7eb2e8f9f7 4447
<> 144:ef7eb2e8f9f7 4448 /*! @name BAUD - LPUART Baud Rate Register */
<> 144:ef7eb2e8f9f7 4449 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
<> 144:ef7eb2e8f9f7 4450 #define LPUART_BAUD_SBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4451 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
<> 144:ef7eb2e8f9f7 4452 #define LPUART_BAUD_SBNS_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4453 #define LPUART_BAUD_SBNS_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4454 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
<> 144:ef7eb2e8f9f7 4455 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4456 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4457 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
<> 144:ef7eb2e8f9f7 4458 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4459 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4460 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
<> 144:ef7eb2e8f9f7 4461 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4462 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4463 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
<> 144:ef7eb2e8f9f7 4464 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4465 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4466 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
<> 144:ef7eb2e8f9f7 4467 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 4468 #define LPUART_BAUD_MATCFG_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4469 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
<> 144:ef7eb2e8f9f7 4470 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4471 #define LPUART_BAUD_RDMAE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4472 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
<> 144:ef7eb2e8f9f7 4473 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4474 #define LPUART_BAUD_TDMAE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4475 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
<> 144:ef7eb2e8f9f7 4476 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
<> 144:ef7eb2e8f9f7 4477 #define LPUART_BAUD_OSR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4478 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
<> 144:ef7eb2e8f9f7 4479 #define LPUART_BAUD_M10_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4480 #define LPUART_BAUD_M10_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4481 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
<> 144:ef7eb2e8f9f7 4482 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4483 #define LPUART_BAUD_MAEN2_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4484 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
<> 144:ef7eb2e8f9f7 4485 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4486 #define LPUART_BAUD_MAEN1_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4487 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
<> 144:ef7eb2e8f9f7 4488
<> 144:ef7eb2e8f9f7 4489 /*! @name STAT - LPUART Status Register */
<> 144:ef7eb2e8f9f7 4490 #define LPUART_STAT_MA2F_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4491 #define LPUART_STAT_MA2F_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4492 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
<> 144:ef7eb2e8f9f7 4493 #define LPUART_STAT_MA1F_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4494 #define LPUART_STAT_MA1F_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4495 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
<> 144:ef7eb2e8f9f7 4496 #define LPUART_STAT_PF_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4497 #define LPUART_STAT_PF_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4498 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
<> 144:ef7eb2e8f9f7 4499 #define LPUART_STAT_FE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4500 #define LPUART_STAT_FE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4501 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
<> 144:ef7eb2e8f9f7 4502 #define LPUART_STAT_NF_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4503 #define LPUART_STAT_NF_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4504 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
<> 144:ef7eb2e8f9f7 4505 #define LPUART_STAT_OR_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4506 #define LPUART_STAT_OR_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4507 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
<> 144:ef7eb2e8f9f7 4508 #define LPUART_STAT_IDLE_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4509 #define LPUART_STAT_IDLE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4510 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
<> 144:ef7eb2e8f9f7 4511 #define LPUART_STAT_RDRF_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4512 #define LPUART_STAT_RDRF_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4513 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
<> 144:ef7eb2e8f9f7 4514 #define LPUART_STAT_TC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4515 #define LPUART_STAT_TC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4516 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
<> 144:ef7eb2e8f9f7 4517 #define LPUART_STAT_TDRE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4518 #define LPUART_STAT_TDRE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4519 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
<> 144:ef7eb2e8f9f7 4520 #define LPUART_STAT_RAF_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4521 #define LPUART_STAT_RAF_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4522 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
<> 144:ef7eb2e8f9f7 4523 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4524 #define LPUART_STAT_LBKDE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4525 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
<> 144:ef7eb2e8f9f7 4526 #define LPUART_STAT_BRK13_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4527 #define LPUART_STAT_BRK13_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4528 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
<> 144:ef7eb2e8f9f7 4529 #define LPUART_STAT_RWUID_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4530 #define LPUART_STAT_RWUID_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4531 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
<> 144:ef7eb2e8f9f7 4532 #define LPUART_STAT_RXINV_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4533 #define LPUART_STAT_RXINV_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4534 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
<> 144:ef7eb2e8f9f7 4535 #define LPUART_STAT_MSBF_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4536 #define LPUART_STAT_MSBF_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4537 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
<> 144:ef7eb2e8f9f7 4538 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4539 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4540 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
<> 144:ef7eb2e8f9f7 4541 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4542 #define LPUART_STAT_LBKDIF_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4543 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
<> 144:ef7eb2e8f9f7 4544
<> 144:ef7eb2e8f9f7 4545 /*! @name CTRL - LPUART Control Register */
<> 144:ef7eb2e8f9f7 4546 #define LPUART_CTRL_PT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4547 #define LPUART_CTRL_PT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4548 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
<> 144:ef7eb2e8f9f7 4549 #define LPUART_CTRL_PE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4550 #define LPUART_CTRL_PE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4551 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
<> 144:ef7eb2e8f9f7 4552 #define LPUART_CTRL_ILT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4553 #define LPUART_CTRL_ILT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4554 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
<> 144:ef7eb2e8f9f7 4555 #define LPUART_CTRL_WAKE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4556 #define LPUART_CTRL_WAKE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4557 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
<> 144:ef7eb2e8f9f7 4558 #define LPUART_CTRL_M_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4559 #define LPUART_CTRL_M_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4560 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
<> 144:ef7eb2e8f9f7 4561 #define LPUART_CTRL_RSRC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4562 #define LPUART_CTRL_RSRC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4563 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
<> 144:ef7eb2e8f9f7 4564 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4565 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4566 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
<> 144:ef7eb2e8f9f7 4567 #define LPUART_CTRL_LOOPS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4568 #define LPUART_CTRL_LOOPS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4569 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
<> 144:ef7eb2e8f9f7 4570 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
<> 144:ef7eb2e8f9f7 4571 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4572 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
<> 144:ef7eb2e8f9f7 4573 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4574 #define LPUART_CTRL_MA2IE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4575 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
<> 144:ef7eb2e8f9f7 4576 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4577 #define LPUART_CTRL_MA1IE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4578 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
<> 144:ef7eb2e8f9f7 4579 #define LPUART_CTRL_SBK_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4580 #define LPUART_CTRL_SBK_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4581 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
<> 144:ef7eb2e8f9f7 4582 #define LPUART_CTRL_RWU_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4583 #define LPUART_CTRL_RWU_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4584 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
<> 144:ef7eb2e8f9f7 4585 #define LPUART_CTRL_RE_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4586 #define LPUART_CTRL_RE_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4587 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
<> 144:ef7eb2e8f9f7 4588 #define LPUART_CTRL_TE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4589 #define LPUART_CTRL_TE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4590 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
<> 144:ef7eb2e8f9f7 4591 #define LPUART_CTRL_ILIE_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4592 #define LPUART_CTRL_ILIE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4593 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
<> 144:ef7eb2e8f9f7 4594 #define LPUART_CTRL_RIE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4595 #define LPUART_CTRL_RIE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4596 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
<> 144:ef7eb2e8f9f7 4597 #define LPUART_CTRL_TCIE_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4598 #define LPUART_CTRL_TCIE_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4599 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
<> 144:ef7eb2e8f9f7 4600 #define LPUART_CTRL_TIE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4601 #define LPUART_CTRL_TIE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4602 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
<> 144:ef7eb2e8f9f7 4603 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4604 #define LPUART_CTRL_PEIE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4605 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
<> 144:ef7eb2e8f9f7 4606 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4607 #define LPUART_CTRL_FEIE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4608 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
<> 144:ef7eb2e8f9f7 4609 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4610 #define LPUART_CTRL_NEIE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4611 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
<> 144:ef7eb2e8f9f7 4612 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4613 #define LPUART_CTRL_ORIE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4614 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
<> 144:ef7eb2e8f9f7 4615 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4616 #define LPUART_CTRL_TXINV_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4617 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
<> 144:ef7eb2e8f9f7 4618 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4619 #define LPUART_CTRL_TXDIR_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4620 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
<> 144:ef7eb2e8f9f7 4621 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4622 #define LPUART_CTRL_R9T8_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4623 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
<> 144:ef7eb2e8f9f7 4624 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4625 #define LPUART_CTRL_R8T9_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4626 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
<> 144:ef7eb2e8f9f7 4627
<> 144:ef7eb2e8f9f7 4628 /*! @name DATA - LPUART Data Register */
<> 144:ef7eb2e8f9f7 4629 #define LPUART_DATA_R0T0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4630 #define LPUART_DATA_R0T0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4631 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
<> 144:ef7eb2e8f9f7 4632 #define LPUART_DATA_R1T1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4633 #define LPUART_DATA_R1T1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4634 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
<> 144:ef7eb2e8f9f7 4635 #define LPUART_DATA_R2T2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4636 #define LPUART_DATA_R2T2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4637 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
<> 144:ef7eb2e8f9f7 4638 #define LPUART_DATA_R3T3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4639 #define LPUART_DATA_R3T3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4640 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
<> 144:ef7eb2e8f9f7 4641 #define LPUART_DATA_R4T4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4642 #define LPUART_DATA_R4T4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4643 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
<> 144:ef7eb2e8f9f7 4644 #define LPUART_DATA_R5T5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4645 #define LPUART_DATA_R5T5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4646 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
<> 144:ef7eb2e8f9f7 4647 #define LPUART_DATA_R6T6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4648 #define LPUART_DATA_R6T6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4649 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
<> 144:ef7eb2e8f9f7 4650 #define LPUART_DATA_R7T7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4651 #define LPUART_DATA_R7T7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4652 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
<> 144:ef7eb2e8f9f7 4653 #define LPUART_DATA_R8T8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 4654 #define LPUART_DATA_R8T8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4655 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
<> 144:ef7eb2e8f9f7 4656 #define LPUART_DATA_R9T9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4657 #define LPUART_DATA_R9T9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4658 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
<> 144:ef7eb2e8f9f7 4659 #define LPUART_DATA_IDLINE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4660 #define LPUART_DATA_IDLINE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4661 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
<> 144:ef7eb2e8f9f7 4662 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4663 #define LPUART_DATA_RXEMPT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4664 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
<> 144:ef7eb2e8f9f7 4665 #define LPUART_DATA_FRETSC_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4666 #define LPUART_DATA_FRETSC_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4667 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
<> 144:ef7eb2e8f9f7 4668 #define LPUART_DATA_PARITYE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4669 #define LPUART_DATA_PARITYE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4670 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
<> 144:ef7eb2e8f9f7 4671 #define LPUART_DATA_NOISY_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4672 #define LPUART_DATA_NOISY_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4673 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
<> 144:ef7eb2e8f9f7 4674
<> 144:ef7eb2e8f9f7 4675 /*! @name MATCH - LPUART Match Address Register */
<> 144:ef7eb2e8f9f7 4676 #define LPUART_MATCH_MA1_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 4677 #define LPUART_MATCH_MA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4678 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
<> 144:ef7eb2e8f9f7 4679 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 4680 #define LPUART_MATCH_MA2_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4681 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
<> 144:ef7eb2e8f9f7 4682
<> 144:ef7eb2e8f9f7 4683
<> 144:ef7eb2e8f9f7 4684 /*!
<> 144:ef7eb2e8f9f7 4685 * @}
<> 144:ef7eb2e8f9f7 4686 */ /* end of group LPUART_Register_Masks */
<> 144:ef7eb2e8f9f7 4687
<> 144:ef7eb2e8f9f7 4688
<> 144:ef7eb2e8f9f7 4689 /* LPUART - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 4690 /** Peripheral LPUART0 base address */
<> 144:ef7eb2e8f9f7 4691 #define LPUART0_BASE (0x40054000u)
<> 144:ef7eb2e8f9f7 4692 /** Peripheral LPUART0 base pointer */
<> 144:ef7eb2e8f9f7 4693 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
<> 144:ef7eb2e8f9f7 4694 /** Peripheral LPUART1 base address */
<> 144:ef7eb2e8f9f7 4695 #define LPUART1_BASE (0x40055000u)
<> 144:ef7eb2e8f9f7 4696 /** Peripheral LPUART1 base pointer */
<> 144:ef7eb2e8f9f7 4697 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
<> 144:ef7eb2e8f9f7 4698 /** Array initializer of LPUART peripheral base addresses */
<> 144:ef7eb2e8f9f7 4699 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
<> 144:ef7eb2e8f9f7 4700 /** Array initializer of LPUART peripheral base pointers */
<> 144:ef7eb2e8f9f7 4701 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
<> 144:ef7eb2e8f9f7 4702 /** Interrupt vectors for the LPUART peripheral type */
<> 144:ef7eb2e8f9f7 4703 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
<> 144:ef7eb2e8f9f7 4704 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
<> 144:ef7eb2e8f9f7 4705
<> 144:ef7eb2e8f9f7 4706 /*!
<> 144:ef7eb2e8f9f7 4707 * @}
<> 144:ef7eb2e8f9f7 4708 */ /* end of group LPUART_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 4709
<> 144:ef7eb2e8f9f7 4710
<> 144:ef7eb2e8f9f7 4711 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4712 -- MCG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4713 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4714
<> 144:ef7eb2e8f9f7 4715 /*!
<> 144:ef7eb2e8f9f7 4716 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4717 * @{
<> 144:ef7eb2e8f9f7 4718 */
<> 144:ef7eb2e8f9f7 4719
<> 144:ef7eb2e8f9f7 4720 /** MCG - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 4721 typedef struct {
<> 144:ef7eb2e8f9f7 4722 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
<> 144:ef7eb2e8f9f7 4723 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
<> 144:ef7eb2e8f9f7 4724 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 4725 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 4726 uint8_t RESERVED_1[1];
<> 144:ef7eb2e8f9f7 4727 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 4728 uint8_t RESERVED_2[11];
<> 144:ef7eb2e8f9f7 4729 __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 4730 __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
<> 144:ef7eb2e8f9f7 4731 __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
<> 144:ef7eb2e8f9f7 4732 uint8_t RESERVED_3[1];
<> 144:ef7eb2e8f9f7 4733 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 4734 __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
<> 144:ef7eb2e8f9f7 4735 __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
<> 144:ef7eb2e8f9f7 4736 __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
<> 144:ef7eb2e8f9f7 4737 } MCG_Type;
<> 144:ef7eb2e8f9f7 4738
<> 144:ef7eb2e8f9f7 4739 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4740 -- MCG Register Masks
<> 144:ef7eb2e8f9f7 4741 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4742
<> 144:ef7eb2e8f9f7 4743 /*!
<> 144:ef7eb2e8f9f7 4744 * @addtogroup MCG_Register_Masks MCG Register Masks
<> 144:ef7eb2e8f9f7 4745 * @{
<> 144:ef7eb2e8f9f7 4746 */
<> 144:ef7eb2e8f9f7 4747
<> 144:ef7eb2e8f9f7 4748 /*! @name C1 - MCG Control Register 1 */
<> 144:ef7eb2e8f9f7 4749 #define MCG_C1_IREFSTEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4750 #define MCG_C1_IREFSTEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4751 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
<> 144:ef7eb2e8f9f7 4752 #define MCG_C1_IRCLKEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4753 #define MCG_C1_IRCLKEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4754 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
<> 144:ef7eb2e8f9f7 4755 #define MCG_C1_CLKS_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 4756 #define MCG_C1_CLKS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4757 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
<> 144:ef7eb2e8f9f7 4758
<> 144:ef7eb2e8f9f7 4759 /*! @name C2 - MCG Control Register 2 */
<> 144:ef7eb2e8f9f7 4760 #define MCG_C2_IRCS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4761 #define MCG_C2_IRCS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4762 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
<> 144:ef7eb2e8f9f7 4763 #define MCG_C2_EREFS0_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4764 #define MCG_C2_EREFS0_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4765 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
<> 144:ef7eb2e8f9f7 4766 #define MCG_C2_HGO0_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4767 #define MCG_C2_HGO0_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4768 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
<> 144:ef7eb2e8f9f7 4769 #define MCG_C2_RANGE0_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4770 #define MCG_C2_RANGE0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4771 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
<> 144:ef7eb2e8f9f7 4772
<> 144:ef7eb2e8f9f7 4773 /*! @name S - MCG Status Register */
<> 144:ef7eb2e8f9f7 4774 #define MCG_S_OSCINIT0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4775 #define MCG_S_OSCINIT0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4776 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
<> 144:ef7eb2e8f9f7 4777 #define MCG_S_CLKST_MASK (0xCU)
<> 144:ef7eb2e8f9f7 4778 #define MCG_S_CLKST_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4779 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
<> 144:ef7eb2e8f9f7 4780
<> 144:ef7eb2e8f9f7 4781 /*! @name SC - MCG Status and Control Register */
<> 144:ef7eb2e8f9f7 4782 #define MCG_SC_FCRDIV_MASK (0xEU)
<> 144:ef7eb2e8f9f7 4783 #define MCG_SC_FCRDIV_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4784 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
<> 144:ef7eb2e8f9f7 4785
<> 144:ef7eb2e8f9f7 4786 /*! @name HCTRIM - MCG High-frequency IRC Coarse Trim Register */
<> 144:ef7eb2e8f9f7 4787 #define MCG_HCTRIM_COARSE_TRIM_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 4788 #define MCG_HCTRIM_COARSE_TRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4789 #define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_HCTRIM_COARSE_TRIM_SHIFT)) & MCG_HCTRIM_COARSE_TRIM_MASK)
<> 144:ef7eb2e8f9f7 4790
<> 144:ef7eb2e8f9f7 4791 /*! @name HTTRIM - MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register */
<> 144:ef7eb2e8f9f7 4792 #define MCG_HTTRIM_TEMPCO_TRIM_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4793 #define MCG_HTTRIM_TEMPCO_TRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4794 #define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_HTTRIM_TEMPCO_TRIM_SHIFT)) & MCG_HTTRIM_TEMPCO_TRIM_MASK)
<> 144:ef7eb2e8f9f7 4795
<> 144:ef7eb2e8f9f7 4796 /*! @name HFTRIM - MCG High-frequency IRC Fine Trim Register */
<> 144:ef7eb2e8f9f7 4797 #define MCG_HFTRIM_FINE_TRIM_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 4798 #define MCG_HFTRIM_FINE_TRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4799 #define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_HFTRIM_FINE_TRIM_SHIFT)) & MCG_HFTRIM_FINE_TRIM_MASK)
<> 144:ef7eb2e8f9f7 4800
<> 144:ef7eb2e8f9f7 4801 /*! @name MC - MCG Miscellaneous Control Register */
<> 144:ef7eb2e8f9f7 4802 #define MCG_MC_LIRC_DIV2_MASK (0x7U)
<> 144:ef7eb2e8f9f7 4803 #define MCG_MC_LIRC_DIV2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4804 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK)
<> 144:ef7eb2e8f9f7 4805 #define MCG_MC_HIRCEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4806 #define MCG_MC_HIRCEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4807 #define MCG_MC_HIRCEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK)
<> 144:ef7eb2e8f9f7 4808
<> 144:ef7eb2e8f9f7 4809 /*! @name LTRIMRNG - MCG Low-frequency IRC Trim Range Register */
<> 144:ef7eb2e8f9f7 4810 #define MCG_LTRIMRNG_STRIMRNG_MASK (0x3U)
<> 144:ef7eb2e8f9f7 4811 #define MCG_LTRIMRNG_STRIMRNG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4812 #define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x)) << MCG_LTRIMRNG_STRIMRNG_SHIFT)) & MCG_LTRIMRNG_STRIMRNG_MASK)
<> 144:ef7eb2e8f9f7 4813 #define MCG_LTRIMRNG_FTRIMRNG_MASK (0xCU)
<> 144:ef7eb2e8f9f7 4814 #define MCG_LTRIMRNG_FTRIMRNG_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4815 #define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x)) << MCG_LTRIMRNG_FTRIMRNG_SHIFT)) & MCG_LTRIMRNG_FTRIMRNG_MASK)
<> 144:ef7eb2e8f9f7 4816
<> 144:ef7eb2e8f9f7 4817 /*! @name LFTRIM - MCG Low-frequency IRC8M Trim Register */
<> 144:ef7eb2e8f9f7 4818 #define MCG_LFTRIM_LIRC_FTRIM_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 4819 #define MCG_LFTRIM_LIRC_FTRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4820 #define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_LFTRIM_LIRC_FTRIM_SHIFT)) & MCG_LFTRIM_LIRC_FTRIM_MASK)
<> 144:ef7eb2e8f9f7 4821
<> 144:ef7eb2e8f9f7 4822 /*! @name LSTRIM - MCG Low-frequency IRC2M Trim Register */
<> 144:ef7eb2e8f9f7 4823 #define MCG_LSTRIM_LIRC_STRIM_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 4824 #define MCG_LSTRIM_LIRC_STRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4825 #define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_LSTRIM_LIRC_STRIM_SHIFT)) & MCG_LSTRIM_LIRC_STRIM_MASK)
<> 144:ef7eb2e8f9f7 4826
<> 144:ef7eb2e8f9f7 4827
<> 144:ef7eb2e8f9f7 4828 /*!
<> 144:ef7eb2e8f9f7 4829 * @}
<> 144:ef7eb2e8f9f7 4830 */ /* end of group MCG_Register_Masks */
<> 144:ef7eb2e8f9f7 4831
<> 144:ef7eb2e8f9f7 4832
<> 144:ef7eb2e8f9f7 4833 /* MCG - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 4834 /** Peripheral MCG base address */
<> 144:ef7eb2e8f9f7 4835 #define MCG_BASE (0x40064000u)
<> 144:ef7eb2e8f9f7 4836 /** Peripheral MCG base pointer */
<> 144:ef7eb2e8f9f7 4837 #define MCG ((MCG_Type *)MCG_BASE)
<> 144:ef7eb2e8f9f7 4838 /** Array initializer of MCG peripheral base addresses */
<> 144:ef7eb2e8f9f7 4839 #define MCG_BASE_ADDRS { MCG_BASE }
<> 144:ef7eb2e8f9f7 4840 /** Array initializer of MCG peripheral base pointers */
<> 144:ef7eb2e8f9f7 4841 #define MCG_BASE_PTRS { MCG }
<> 144:ef7eb2e8f9f7 4842
<> 144:ef7eb2e8f9f7 4843 /*!
<> 144:ef7eb2e8f9f7 4844 * @}
<> 144:ef7eb2e8f9f7 4845 */ /* end of group MCG_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 4846
<> 144:ef7eb2e8f9f7 4847
<> 144:ef7eb2e8f9f7 4848 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4849 -- MCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4850 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4851
<> 144:ef7eb2e8f9f7 4852 /*!
<> 144:ef7eb2e8f9f7 4853 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4854 * @{
<> 144:ef7eb2e8f9f7 4855 */
<> 144:ef7eb2e8f9f7 4856
<> 144:ef7eb2e8f9f7 4857 /** MCM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 4858 typedef struct {
<> 144:ef7eb2e8f9f7 4859 uint8_t RESERVED_0[8];
<> 144:ef7eb2e8f9f7 4860 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
<> 144:ef7eb2e8f9f7 4861 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
<> 144:ef7eb2e8f9f7 4862 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 4863 uint8_t RESERVED_1[48];
<> 144:ef7eb2e8f9f7 4864 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 4865 } MCM_Type;
<> 144:ef7eb2e8f9f7 4866
<> 144:ef7eb2e8f9f7 4867 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4868 -- MCM Register Masks
<> 144:ef7eb2e8f9f7 4869 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4870
<> 144:ef7eb2e8f9f7 4871 /*!
<> 144:ef7eb2e8f9f7 4872 * @addtogroup MCM_Register_Masks MCM Register Masks
<> 144:ef7eb2e8f9f7 4873 * @{
<> 144:ef7eb2e8f9f7 4874 */
<> 144:ef7eb2e8f9f7 4875
<> 144:ef7eb2e8f9f7 4876 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
<> 144:ef7eb2e8f9f7 4877 #define MCM_PLASC_ASC_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 4878 #define MCM_PLASC_ASC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4879 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
<> 144:ef7eb2e8f9f7 4880
<> 144:ef7eb2e8f9f7 4881 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
<> 144:ef7eb2e8f9f7 4882 #define MCM_PLAMC_AMC_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 4883 #define MCM_PLAMC_AMC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4884 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
<> 144:ef7eb2e8f9f7 4885
<> 144:ef7eb2e8f9f7 4886 /*! @name PLACR - Platform Control Register */
<> 144:ef7eb2e8f9f7 4887 #define MCM_PLACR_ARB_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4888 #define MCM_PLACR_ARB_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4889 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
<> 144:ef7eb2e8f9f7 4890 #define MCM_PLACR_CFCC_MASK (0x400U)
<> 144:ef7eb2e8f9f7 4891 #define MCM_PLACR_CFCC_SHIFT (10U)
<> 144:ef7eb2e8f9f7 4892 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
<> 144:ef7eb2e8f9f7 4893 #define MCM_PLACR_DFCDA_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4894 #define MCM_PLACR_DFCDA_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4895 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
<> 144:ef7eb2e8f9f7 4896 #define MCM_PLACR_DFCIC_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4897 #define MCM_PLACR_DFCIC_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4898 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
<> 144:ef7eb2e8f9f7 4899 #define MCM_PLACR_DFCC_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4900 #define MCM_PLACR_DFCC_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4901 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
<> 144:ef7eb2e8f9f7 4902 #define MCM_PLACR_EFDS_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4903 #define MCM_PLACR_EFDS_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4904 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
<> 144:ef7eb2e8f9f7 4905 #define MCM_PLACR_DFCS_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4906 #define MCM_PLACR_DFCS_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4907 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
<> 144:ef7eb2e8f9f7 4908 #define MCM_PLACR_ESFC_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4909 #define MCM_PLACR_ESFC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4910 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
<> 144:ef7eb2e8f9f7 4911
<> 144:ef7eb2e8f9f7 4912 /*! @name CPO - Compute Operation Control Register */
<> 144:ef7eb2e8f9f7 4913 #define MCM_CPO_CPOREQ_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4914 #define MCM_CPO_CPOREQ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4915 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
<> 144:ef7eb2e8f9f7 4916 #define MCM_CPO_CPOACK_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4917 #define MCM_CPO_CPOACK_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4918 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
<> 144:ef7eb2e8f9f7 4919 #define MCM_CPO_CPOWOI_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4920 #define MCM_CPO_CPOWOI_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4921 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
<> 144:ef7eb2e8f9f7 4922
<> 144:ef7eb2e8f9f7 4923
<> 144:ef7eb2e8f9f7 4924 /*!
<> 144:ef7eb2e8f9f7 4925 * @}
<> 144:ef7eb2e8f9f7 4926 */ /* end of group MCM_Register_Masks */
<> 144:ef7eb2e8f9f7 4927
<> 144:ef7eb2e8f9f7 4928
<> 144:ef7eb2e8f9f7 4929 /* MCM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 4930 /** Peripheral MCM base address */
<> 144:ef7eb2e8f9f7 4931 #define MCM_BASE (0xF0003000u)
<> 144:ef7eb2e8f9f7 4932 /** Peripheral MCM base pointer */
<> 144:ef7eb2e8f9f7 4933 #define MCM ((MCM_Type *)MCM_BASE)
<> 144:ef7eb2e8f9f7 4934 /** Array initializer of MCM peripheral base addresses */
<> 144:ef7eb2e8f9f7 4935 #define MCM_BASE_ADDRS { MCM_BASE }
<> 144:ef7eb2e8f9f7 4936 /** Array initializer of MCM peripheral base pointers */
<> 144:ef7eb2e8f9f7 4937 #define MCM_BASE_PTRS { MCM }
<> 144:ef7eb2e8f9f7 4938
<> 144:ef7eb2e8f9f7 4939 /*!
<> 144:ef7eb2e8f9f7 4940 * @}
<> 144:ef7eb2e8f9f7 4941 */ /* end of group MCM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 4942
<> 144:ef7eb2e8f9f7 4943
<> 144:ef7eb2e8f9f7 4944 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4945 -- MTB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4946 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4947
<> 144:ef7eb2e8f9f7 4948 /*!
<> 144:ef7eb2e8f9f7 4949 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 4950 * @{
<> 144:ef7eb2e8f9f7 4951 */
<> 144:ef7eb2e8f9f7 4952
<> 144:ef7eb2e8f9f7 4953 /** MTB - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 4954 typedef struct {
<> 144:ef7eb2e8f9f7 4955 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 4956 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 4957 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 4958 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 4959 uint8_t RESERVED_0[3824];
<> 144:ef7eb2e8f9f7 4960 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
<> 144:ef7eb2e8f9f7 4961 uint8_t RESERVED_1[156];
<> 144:ef7eb2e8f9f7 4962 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
<> 144:ef7eb2e8f9f7 4963 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
<> 144:ef7eb2e8f9f7 4964 uint8_t RESERVED_2[8];
<> 144:ef7eb2e8f9f7 4965 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
<> 144:ef7eb2e8f9f7 4966 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
<> 144:ef7eb2e8f9f7 4967 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
<> 144:ef7eb2e8f9f7 4968 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
<> 144:ef7eb2e8f9f7 4969 uint8_t RESERVED_3[8];
<> 144:ef7eb2e8f9f7 4970 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
<> 144:ef7eb2e8f9f7 4971 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
<> 144:ef7eb2e8f9f7 4972 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 4973 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 4974 } MTB_Type;
<> 144:ef7eb2e8f9f7 4975
<> 144:ef7eb2e8f9f7 4976 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4977 -- MTB Register Masks
<> 144:ef7eb2e8f9f7 4978 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 4979
<> 144:ef7eb2e8f9f7 4980 /*!
<> 144:ef7eb2e8f9f7 4981 * @addtogroup MTB_Register_Masks MTB Register Masks
<> 144:ef7eb2e8f9f7 4982 * @{
<> 144:ef7eb2e8f9f7 4983 */
<> 144:ef7eb2e8f9f7 4984
<> 144:ef7eb2e8f9f7 4985 /*! @name POSITION - MTB Position Register */
<> 144:ef7eb2e8f9f7 4986 #define MTB_POSITION_WRAP_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4987 #define MTB_POSITION_WRAP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4988 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
<> 144:ef7eb2e8f9f7 4989 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
<> 144:ef7eb2e8f9f7 4990 #define MTB_POSITION_POINTER_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4991 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
<> 144:ef7eb2e8f9f7 4992
<> 144:ef7eb2e8f9f7 4993 /*! @name MASTER - MTB Master Register */
<> 144:ef7eb2e8f9f7 4994 #define MTB_MASTER_MASK_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4995 #define MTB_MASTER_MASK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4996 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
<> 144:ef7eb2e8f9f7 4997 #define MTB_MASTER_TSTARTEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4998 #define MTB_MASTER_TSTARTEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4999 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
<> 144:ef7eb2e8f9f7 5000 #define MTB_MASTER_TSTOPEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5001 #define MTB_MASTER_TSTOPEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5002 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
<> 144:ef7eb2e8f9f7 5003 #define MTB_MASTER_SFRWPRIV_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5004 #define MTB_MASTER_SFRWPRIV_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5005 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
<> 144:ef7eb2e8f9f7 5006 #define MTB_MASTER_RAMPRIV_MASK (0x100U)
<> 144:ef7eb2e8f9f7 5007 #define MTB_MASTER_RAMPRIV_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5008 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
<> 144:ef7eb2e8f9f7 5009 #define MTB_MASTER_HALTREQ_MASK (0x200U)
<> 144:ef7eb2e8f9f7 5010 #define MTB_MASTER_HALTREQ_SHIFT (9U)
<> 144:ef7eb2e8f9f7 5011 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
<> 144:ef7eb2e8f9f7 5012 #define MTB_MASTER_EN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 5013 #define MTB_MASTER_EN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 5014 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
<> 144:ef7eb2e8f9f7 5015
<> 144:ef7eb2e8f9f7 5016 /*! @name FLOW - MTB Flow Register */
<> 144:ef7eb2e8f9f7 5017 #define MTB_FLOW_AUTOSTOP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5018 #define MTB_FLOW_AUTOSTOP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5019 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
<> 144:ef7eb2e8f9f7 5020 #define MTB_FLOW_AUTOHALT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5021 #define MTB_FLOW_AUTOHALT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5022 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
<> 144:ef7eb2e8f9f7 5023 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
<> 144:ef7eb2e8f9f7 5024 #define MTB_FLOW_WATERMARK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5025 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
<> 144:ef7eb2e8f9f7 5026
<> 144:ef7eb2e8f9f7 5027 /*! @name BASE - MTB Base Register */
<> 144:ef7eb2e8f9f7 5028 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5029 #define MTB_BASE_BASEADDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5030 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
<> 144:ef7eb2e8f9f7 5031
<> 144:ef7eb2e8f9f7 5032 /*! @name MODECTRL - Integration Mode Control Register */
<> 144:ef7eb2e8f9f7 5033 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5034 #define MTB_MODECTRL_MODECTRL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5035 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
<> 144:ef7eb2e8f9f7 5036
<> 144:ef7eb2e8f9f7 5037 /*! @name TAGSET - Claim TAG Set Register */
<> 144:ef7eb2e8f9f7 5038 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5039 #define MTB_TAGSET_TAGSET_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5040 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
<> 144:ef7eb2e8f9f7 5041
<> 144:ef7eb2e8f9f7 5042 /*! @name TAGCLEAR - Claim TAG Clear Register */
<> 144:ef7eb2e8f9f7 5043 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5044 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5045 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
<> 144:ef7eb2e8f9f7 5046
<> 144:ef7eb2e8f9f7 5047 /*! @name LOCKACCESS - Lock Access Register */
<> 144:ef7eb2e8f9f7 5048 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5049 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5050 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
<> 144:ef7eb2e8f9f7 5051
<> 144:ef7eb2e8f9f7 5052 /*! @name LOCKSTAT - Lock Status Register */
<> 144:ef7eb2e8f9f7 5053 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5054 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5055 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
<> 144:ef7eb2e8f9f7 5056
<> 144:ef7eb2e8f9f7 5057 /*! @name AUTHSTAT - Authentication Status Register */
<> 144:ef7eb2e8f9f7 5058 #define MTB_AUTHSTAT_BIT0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5059 #define MTB_AUTHSTAT_BIT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5060 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
<> 144:ef7eb2e8f9f7 5061 #define MTB_AUTHSTAT_BIT1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5062 #define MTB_AUTHSTAT_BIT1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5063 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
<> 144:ef7eb2e8f9f7 5064 #define MTB_AUTHSTAT_BIT2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5065 #define MTB_AUTHSTAT_BIT2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5066 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
<> 144:ef7eb2e8f9f7 5067 #define MTB_AUTHSTAT_BIT3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5068 #define MTB_AUTHSTAT_BIT3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5069 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 /*! @name DEVICEARCH - Device Architecture Register */
<> 144:ef7eb2e8f9f7 5072 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5073 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5074 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
<> 144:ef7eb2e8f9f7 5075
<> 144:ef7eb2e8f9f7 5076 /*! @name DEVICECFG - Device Configuration Register */
<> 144:ef7eb2e8f9f7 5077 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5078 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5079 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
<> 144:ef7eb2e8f9f7 5080
<> 144:ef7eb2e8f9f7 5081 /*! @name DEVICETYPID - Device Type Identifier Register */
<> 144:ef7eb2e8f9f7 5082 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5083 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5084 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
<> 144:ef7eb2e8f9f7 5085
<> 144:ef7eb2e8f9f7 5086 /*! @name PERIPHID - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 5087 #define MTB_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5088 #define MTB_PERIPHID_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5089 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID_PERIPHID_SHIFT)) & MTB_PERIPHID_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 5090
<> 144:ef7eb2e8f9f7 5091 /* The count of MTB_PERIPHID */
<> 144:ef7eb2e8f9f7 5092 #define MTB_PERIPHID_COUNT (8U)
<> 144:ef7eb2e8f9f7 5093
<> 144:ef7eb2e8f9f7 5094 /*! @name COMPID - Component ID Register */
<> 144:ef7eb2e8f9f7 5095 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5096 #define MTB_COMPID_COMPID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5097 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
<> 144:ef7eb2e8f9f7 5098
<> 144:ef7eb2e8f9f7 5099 /* The count of MTB_COMPID */
<> 144:ef7eb2e8f9f7 5100 #define MTB_COMPID_COUNT (4U)
<> 144:ef7eb2e8f9f7 5101
<> 144:ef7eb2e8f9f7 5102
<> 144:ef7eb2e8f9f7 5103 /*!
<> 144:ef7eb2e8f9f7 5104 * @}
<> 144:ef7eb2e8f9f7 5105 */ /* end of group MTB_Register_Masks */
<> 144:ef7eb2e8f9f7 5106
<> 144:ef7eb2e8f9f7 5107
<> 144:ef7eb2e8f9f7 5108 /* MTB - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5109 /** Peripheral MTB base address */
<> 144:ef7eb2e8f9f7 5110 #define MTB_BASE (0xF0000000u)
<> 144:ef7eb2e8f9f7 5111 /** Peripheral MTB base pointer */
<> 144:ef7eb2e8f9f7 5112 #define MTB ((MTB_Type *)MTB_BASE)
<> 144:ef7eb2e8f9f7 5113 /** Array initializer of MTB peripheral base addresses */
<> 144:ef7eb2e8f9f7 5114 #define MTB_BASE_ADDRS { MTB_BASE }
<> 144:ef7eb2e8f9f7 5115 /** Array initializer of MTB peripheral base pointers */
<> 144:ef7eb2e8f9f7 5116 #define MTB_BASE_PTRS { MTB }
<> 144:ef7eb2e8f9f7 5117
<> 144:ef7eb2e8f9f7 5118 /*!
<> 144:ef7eb2e8f9f7 5119 * @}
<> 144:ef7eb2e8f9f7 5120 */ /* end of group MTB_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5121
<> 144:ef7eb2e8f9f7 5122
<> 144:ef7eb2e8f9f7 5123 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5124 -- MTBDWT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5125 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5126
<> 144:ef7eb2e8f9f7 5127 /*!
<> 144:ef7eb2e8f9f7 5128 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5129 * @{
<> 144:ef7eb2e8f9f7 5130 */
<> 144:ef7eb2e8f9f7 5131
<> 144:ef7eb2e8f9f7 5132 /** MTBDWT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5133 typedef struct {
<> 144:ef7eb2e8f9f7 5134 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 5135 uint8_t RESERVED_0[28];
<> 144:ef7eb2e8f9f7 5136 struct { /* offset: 0x20, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5137 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5138 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5139 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5140 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 5141 } COMPARATOR[2];
<> 144:ef7eb2e8f9f7 5142 uint8_t RESERVED_1[448];
<> 144:ef7eb2e8f9f7 5143 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
<> 144:ef7eb2e8f9f7 5144 uint8_t RESERVED_2[3524];
<> 144:ef7eb2e8f9f7 5145 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
<> 144:ef7eb2e8f9f7 5146 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
<> 144:ef7eb2e8f9f7 5147 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 5148 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 5149 } MTBDWT_Type;
<> 144:ef7eb2e8f9f7 5150
<> 144:ef7eb2e8f9f7 5151 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5152 -- MTBDWT Register Masks
<> 144:ef7eb2e8f9f7 5153 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5154
<> 144:ef7eb2e8f9f7 5155 /*!
<> 144:ef7eb2e8f9f7 5156 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
<> 144:ef7eb2e8f9f7 5157 * @{
<> 144:ef7eb2e8f9f7 5158 */
<> 144:ef7eb2e8f9f7 5159
<> 144:ef7eb2e8f9f7 5160 /*! @name CTRL - MTB DWT Control Register */
<> 144:ef7eb2e8f9f7 5161 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
<> 144:ef7eb2e8f9f7 5162 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5163 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
<> 144:ef7eb2e8f9f7 5164 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 5165 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
<> 144:ef7eb2e8f9f7 5166 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
<> 144:ef7eb2e8f9f7 5167
<> 144:ef7eb2e8f9f7 5168 /*! @name COMP - MTB_DWT Comparator Register */
<> 144:ef7eb2e8f9f7 5169 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5170 #define MTBDWT_COMP_COMP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5171 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
<> 144:ef7eb2e8f9f7 5172
<> 144:ef7eb2e8f9f7 5173 /* The count of MTBDWT_COMP */
<> 144:ef7eb2e8f9f7 5174 #define MTBDWT_COMP_COUNT (2U)
<> 144:ef7eb2e8f9f7 5175
<> 144:ef7eb2e8f9f7 5176 /*! @name MASK - MTB_DWT Comparator Mask Register */
<> 144:ef7eb2e8f9f7 5177 #define MTBDWT_MASK_MASK_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 5178 #define MTBDWT_MASK_MASK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5179 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
<> 144:ef7eb2e8f9f7 5180
<> 144:ef7eb2e8f9f7 5181 /* The count of MTBDWT_MASK */
<> 144:ef7eb2e8f9f7 5182 #define MTBDWT_MASK_COUNT (2U)
<> 144:ef7eb2e8f9f7 5183
<> 144:ef7eb2e8f9f7 5184 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
<> 144:ef7eb2e8f9f7 5185 #define MTBDWT_FCT_FUNCTION_MASK (0xFU)
<> 144:ef7eb2e8f9f7 5186 #define MTBDWT_FCT_FUNCTION_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5187 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
<> 144:ef7eb2e8f9f7 5188 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
<> 144:ef7eb2e8f9f7 5189 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5190 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
<> 144:ef7eb2e8f9f7 5191 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
<> 144:ef7eb2e8f9f7 5192 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
<> 144:ef7eb2e8f9f7 5193 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
<> 144:ef7eb2e8f9f7 5194 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 5195 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
<> 144:ef7eb2e8f9f7 5196 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
<> 144:ef7eb2e8f9f7 5197 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 5198 #define MTBDWT_FCT_MATCHED_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5199 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
<> 144:ef7eb2e8f9f7 5200
<> 144:ef7eb2e8f9f7 5201 /* The count of MTBDWT_FCT */
<> 144:ef7eb2e8f9f7 5202 #define MTBDWT_FCT_COUNT (2U)
<> 144:ef7eb2e8f9f7 5203
<> 144:ef7eb2e8f9f7 5204 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
<> 144:ef7eb2e8f9f7 5205 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5206 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5207 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
<> 144:ef7eb2e8f9f7 5208 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5209 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5210 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
<> 144:ef7eb2e8f9f7 5211 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 5212 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
<> 144:ef7eb2e8f9f7 5213 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
<> 144:ef7eb2e8f9f7 5214
<> 144:ef7eb2e8f9f7 5215 /*! @name DEVICECFG - Device Configuration Register */
<> 144:ef7eb2e8f9f7 5216 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5217 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5218 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
<> 144:ef7eb2e8f9f7 5219
<> 144:ef7eb2e8f9f7 5220 /*! @name DEVICETYPID - Device Type Identifier Register */
<> 144:ef7eb2e8f9f7 5221 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5222 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5223 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
<> 144:ef7eb2e8f9f7 5224
<> 144:ef7eb2e8f9f7 5225 /*! @name PERIPHID - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 5226 #define MTBDWT_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5227 #define MTBDWT_PERIPHID_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5228 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID_PERIPHID_SHIFT)) & MTBDWT_PERIPHID_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 5229
<> 144:ef7eb2e8f9f7 5230 /* The count of MTBDWT_PERIPHID */
<> 144:ef7eb2e8f9f7 5231 #define MTBDWT_PERIPHID_COUNT (8U)
<> 144:ef7eb2e8f9f7 5232
<> 144:ef7eb2e8f9f7 5233 /*! @name COMPID - Component ID Register */
<> 144:ef7eb2e8f9f7 5234 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5235 #define MTBDWT_COMPID_COMPID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5236 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
<> 144:ef7eb2e8f9f7 5237
<> 144:ef7eb2e8f9f7 5238 /* The count of MTBDWT_COMPID */
<> 144:ef7eb2e8f9f7 5239 #define MTBDWT_COMPID_COUNT (4U)
<> 144:ef7eb2e8f9f7 5240
<> 144:ef7eb2e8f9f7 5241
<> 144:ef7eb2e8f9f7 5242 /*!
<> 144:ef7eb2e8f9f7 5243 * @}
<> 144:ef7eb2e8f9f7 5244 */ /* end of group MTBDWT_Register_Masks */
<> 144:ef7eb2e8f9f7 5245
<> 144:ef7eb2e8f9f7 5246
<> 144:ef7eb2e8f9f7 5247 /* MTBDWT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5248 /** Peripheral MTBDWT base address */
<> 144:ef7eb2e8f9f7 5249 #define MTBDWT_BASE (0xF0001000u)
<> 144:ef7eb2e8f9f7 5250 /** Peripheral MTBDWT base pointer */
<> 144:ef7eb2e8f9f7 5251 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
<> 144:ef7eb2e8f9f7 5252 /** Array initializer of MTBDWT peripheral base addresses */
<> 144:ef7eb2e8f9f7 5253 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
<> 144:ef7eb2e8f9f7 5254 /** Array initializer of MTBDWT peripheral base pointers */
<> 144:ef7eb2e8f9f7 5255 #define MTBDWT_BASE_PTRS { MTBDWT }
<> 144:ef7eb2e8f9f7 5256
<> 144:ef7eb2e8f9f7 5257 /*!
<> 144:ef7eb2e8f9f7 5258 * @}
<> 144:ef7eb2e8f9f7 5259 */ /* end of group MTBDWT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5260
<> 144:ef7eb2e8f9f7 5261
<> 144:ef7eb2e8f9f7 5262 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5263 -- NV Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5264 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5265
<> 144:ef7eb2e8f9f7 5266 /*!
<> 144:ef7eb2e8f9f7 5267 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5268 * @{
<> 144:ef7eb2e8f9f7 5269 */
<> 144:ef7eb2e8f9f7 5270
<> 144:ef7eb2e8f9f7 5271 /** NV - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5272 typedef struct {
<> 144:ef7eb2e8f9f7 5273 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
<> 144:ef7eb2e8f9f7 5274 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
<> 144:ef7eb2e8f9f7 5275 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
<> 144:ef7eb2e8f9f7 5276 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
<> 144:ef7eb2e8f9f7 5277 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
<> 144:ef7eb2e8f9f7 5278 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
<> 144:ef7eb2e8f9f7 5279 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
<> 144:ef7eb2e8f9f7 5280 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
<> 144:ef7eb2e8f9f7 5281 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 5282 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
<> 144:ef7eb2e8f9f7 5283 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
<> 144:ef7eb2e8f9f7 5284 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
<> 144:ef7eb2e8f9f7 5285 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 5286 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
<> 144:ef7eb2e8f9f7 5287 } NV_Type;
<> 144:ef7eb2e8f9f7 5288
<> 144:ef7eb2e8f9f7 5289 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5290 -- NV Register Masks
<> 144:ef7eb2e8f9f7 5291 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5292
<> 144:ef7eb2e8f9f7 5293 /*!
<> 144:ef7eb2e8f9f7 5294 * @addtogroup NV_Register_Masks NV Register Masks
<> 144:ef7eb2e8f9f7 5295 * @{
<> 144:ef7eb2e8f9f7 5296 */
<> 144:ef7eb2e8f9f7 5297
<> 144:ef7eb2e8f9f7 5298 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
<> 144:ef7eb2e8f9f7 5299 #define NV_BACKKEY3_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5300 #define NV_BACKKEY3_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5301 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
<> 144:ef7eb2e8f9f7 5302
<> 144:ef7eb2e8f9f7 5303 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
<> 144:ef7eb2e8f9f7 5304 #define NV_BACKKEY2_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5305 #define NV_BACKKEY2_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5306 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
<> 144:ef7eb2e8f9f7 5307
<> 144:ef7eb2e8f9f7 5308 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
<> 144:ef7eb2e8f9f7 5309 #define NV_BACKKEY1_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5310 #define NV_BACKKEY1_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5311 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
<> 144:ef7eb2e8f9f7 5312
<> 144:ef7eb2e8f9f7 5313 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
<> 144:ef7eb2e8f9f7 5314 #define NV_BACKKEY0_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5315 #define NV_BACKKEY0_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5316 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
<> 144:ef7eb2e8f9f7 5317
<> 144:ef7eb2e8f9f7 5318 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
<> 144:ef7eb2e8f9f7 5319 #define NV_BACKKEY7_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5320 #define NV_BACKKEY7_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5321 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
<> 144:ef7eb2e8f9f7 5322
<> 144:ef7eb2e8f9f7 5323 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
<> 144:ef7eb2e8f9f7 5324 #define NV_BACKKEY6_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5325 #define NV_BACKKEY6_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5326 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
<> 144:ef7eb2e8f9f7 5327
<> 144:ef7eb2e8f9f7 5328 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
<> 144:ef7eb2e8f9f7 5329 #define NV_BACKKEY5_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5330 #define NV_BACKKEY5_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5331 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
<> 144:ef7eb2e8f9f7 5332
<> 144:ef7eb2e8f9f7 5333 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
<> 144:ef7eb2e8f9f7 5334 #define NV_BACKKEY4_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5335 #define NV_BACKKEY4_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5336 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
<> 144:ef7eb2e8f9f7 5337
<> 144:ef7eb2e8f9f7 5338 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
<> 144:ef7eb2e8f9f7 5339 #define NV_FPROT3_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5340 #define NV_FPROT3_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5341 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
<> 144:ef7eb2e8f9f7 5342
<> 144:ef7eb2e8f9f7 5343 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
<> 144:ef7eb2e8f9f7 5344 #define NV_FPROT2_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5345 #define NV_FPROT2_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5346 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
<> 144:ef7eb2e8f9f7 5347
<> 144:ef7eb2e8f9f7 5348 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
<> 144:ef7eb2e8f9f7 5349 #define NV_FPROT1_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5350 #define NV_FPROT1_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5351 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
<> 144:ef7eb2e8f9f7 5352
<> 144:ef7eb2e8f9f7 5353 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
<> 144:ef7eb2e8f9f7 5354 #define NV_FPROT0_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5355 #define NV_FPROT0_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5356 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
<> 144:ef7eb2e8f9f7 5357
<> 144:ef7eb2e8f9f7 5358 /*! @name FSEC - Non-volatile Flash Security Register */
<> 144:ef7eb2e8f9f7 5359 #define NV_FSEC_SEC_MASK (0x3U)
<> 144:ef7eb2e8f9f7 5360 #define NV_FSEC_SEC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5361 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
<> 144:ef7eb2e8f9f7 5362 #define NV_FSEC_FSLACC_MASK (0xCU)
<> 144:ef7eb2e8f9f7 5363 #define NV_FSEC_FSLACC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5364 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
<> 144:ef7eb2e8f9f7 5365 #define NV_FSEC_MEEN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 5366 #define NV_FSEC_MEEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5367 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
<> 144:ef7eb2e8f9f7 5368 #define NV_FSEC_KEYEN_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 5369 #define NV_FSEC_KEYEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5370 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
<> 144:ef7eb2e8f9f7 5371
<> 144:ef7eb2e8f9f7 5372 /*! @name FOPT - Non-volatile Flash Option Register */
<> 144:ef7eb2e8f9f7 5373 #define NV_FOPT_LPBOOT0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5374 #define NV_FOPT_LPBOOT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5375 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
<> 144:ef7eb2e8f9f7 5376 #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5377 #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5378 #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
<> 144:ef7eb2e8f9f7 5379 #define NV_FOPT_NMI_DIS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5380 #define NV_FOPT_NMI_DIS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5381 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
<> 144:ef7eb2e8f9f7 5382 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5383 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5384 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
<> 144:ef7eb2e8f9f7 5385 #define NV_FOPT_LPBOOT1_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5386 #define NV_FOPT_LPBOOT1_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5387 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
<> 144:ef7eb2e8f9f7 5388 #define NV_FOPT_FAST_INIT_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5389 #define NV_FOPT_FAST_INIT_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5390 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
<> 144:ef7eb2e8f9f7 5391 #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 5392 #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5393 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
<> 144:ef7eb2e8f9f7 5394
<> 144:ef7eb2e8f9f7 5395
<> 144:ef7eb2e8f9f7 5396 /*!
<> 144:ef7eb2e8f9f7 5397 * @}
<> 144:ef7eb2e8f9f7 5398 */ /* end of group NV_Register_Masks */
<> 144:ef7eb2e8f9f7 5399
<> 144:ef7eb2e8f9f7 5400
<> 144:ef7eb2e8f9f7 5401 /* NV - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5402 /** Peripheral FTFA_FlashConfig base address */
<> 144:ef7eb2e8f9f7 5403 #define FTFA_FlashConfig_BASE (0x400u)
<> 144:ef7eb2e8f9f7 5404 /** Peripheral FTFA_FlashConfig base pointer */
<> 144:ef7eb2e8f9f7 5405 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
<> 144:ef7eb2e8f9f7 5406 /** Array initializer of NV peripheral base addresses */
<> 144:ef7eb2e8f9f7 5407 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
<> 144:ef7eb2e8f9f7 5408 /** Array initializer of NV peripheral base pointers */
<> 144:ef7eb2e8f9f7 5409 #define NV_BASE_PTRS { FTFA_FlashConfig }
<> 144:ef7eb2e8f9f7 5410
<> 144:ef7eb2e8f9f7 5411 /*!
<> 144:ef7eb2e8f9f7 5412 * @}
<> 144:ef7eb2e8f9f7 5413 */ /* end of group NV_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5414
<> 144:ef7eb2e8f9f7 5415
<> 144:ef7eb2e8f9f7 5416 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5417 -- OSC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5418 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5419
<> 144:ef7eb2e8f9f7 5420 /*!
<> 144:ef7eb2e8f9f7 5421 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5422 * @{
<> 144:ef7eb2e8f9f7 5423 */
<> 144:ef7eb2e8f9f7 5424
<> 144:ef7eb2e8f9f7 5425 /** OSC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5426 typedef struct {
<> 144:ef7eb2e8f9f7 5427 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 5428 } OSC_Type;
<> 144:ef7eb2e8f9f7 5429
<> 144:ef7eb2e8f9f7 5430 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5431 -- OSC Register Masks
<> 144:ef7eb2e8f9f7 5432 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5433
<> 144:ef7eb2e8f9f7 5434 /*!
<> 144:ef7eb2e8f9f7 5435 * @addtogroup OSC_Register_Masks OSC Register Masks
<> 144:ef7eb2e8f9f7 5436 * @{
<> 144:ef7eb2e8f9f7 5437 */
<> 144:ef7eb2e8f9f7 5438
<> 144:ef7eb2e8f9f7 5439 /*! @name CR - OSC Control Register */
<> 144:ef7eb2e8f9f7 5440 #define OSC_CR_SC16P_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5441 #define OSC_CR_SC16P_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5442 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
<> 144:ef7eb2e8f9f7 5443 #define OSC_CR_SC8P_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5444 #define OSC_CR_SC8P_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5445 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
<> 144:ef7eb2e8f9f7 5446 #define OSC_CR_SC4P_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5447 #define OSC_CR_SC4P_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5448 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
<> 144:ef7eb2e8f9f7 5449 #define OSC_CR_SC2P_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5450 #define OSC_CR_SC2P_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5451 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
<> 144:ef7eb2e8f9f7 5452 #define OSC_CR_EREFSTEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5453 #define OSC_CR_EREFSTEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5454 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
<> 144:ef7eb2e8f9f7 5455 #define OSC_CR_ERCLKEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5456 #define OSC_CR_ERCLKEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5457 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
<> 144:ef7eb2e8f9f7 5458
<> 144:ef7eb2e8f9f7 5459
<> 144:ef7eb2e8f9f7 5460 /*!
<> 144:ef7eb2e8f9f7 5461 * @}
<> 144:ef7eb2e8f9f7 5462 */ /* end of group OSC_Register_Masks */
<> 144:ef7eb2e8f9f7 5463
<> 144:ef7eb2e8f9f7 5464
<> 144:ef7eb2e8f9f7 5465 /* OSC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5466 /** Peripheral OSC0 base address */
<> 144:ef7eb2e8f9f7 5467 #define OSC0_BASE (0x40065000u)
<> 144:ef7eb2e8f9f7 5468 /** Peripheral OSC0 base pointer */
<> 144:ef7eb2e8f9f7 5469 #define OSC0 ((OSC_Type *)OSC0_BASE)
<> 144:ef7eb2e8f9f7 5470 /** Array initializer of OSC peripheral base addresses */
<> 144:ef7eb2e8f9f7 5471 #define OSC_BASE_ADDRS { OSC0_BASE }
<> 144:ef7eb2e8f9f7 5472 /** Array initializer of OSC peripheral base pointers */
<> 144:ef7eb2e8f9f7 5473 #define OSC_BASE_PTRS { OSC0 }
<> 144:ef7eb2e8f9f7 5474
<> 144:ef7eb2e8f9f7 5475 /*!
<> 144:ef7eb2e8f9f7 5476 * @}
<> 144:ef7eb2e8f9f7 5477 */ /* end of group OSC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5478
<> 144:ef7eb2e8f9f7 5479
<> 144:ef7eb2e8f9f7 5480 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5481 -- PIT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5482 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5483
<> 144:ef7eb2e8f9f7 5484 /*!
<> 144:ef7eb2e8f9f7 5485 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5486 * @{
<> 144:ef7eb2e8f9f7 5487 */
<> 144:ef7eb2e8f9f7 5488
<> 144:ef7eb2e8f9f7 5489 /** PIT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5490 typedef struct {
<> 144:ef7eb2e8f9f7 5491 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 5492 uint8_t RESERVED_0[220];
<> 144:ef7eb2e8f9f7 5493 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
<> 144:ef7eb2e8f9f7 5494 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
<> 144:ef7eb2e8f9f7 5495 uint8_t RESERVED_1[24];
<> 144:ef7eb2e8f9f7 5496 struct { /* offset: 0x100, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5497 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5498 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5499 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5500 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
<> 144:ef7eb2e8f9f7 5501 } CHANNEL[2];
<> 144:ef7eb2e8f9f7 5502 } PIT_Type;
<> 144:ef7eb2e8f9f7 5503
<> 144:ef7eb2e8f9f7 5504 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5505 -- PIT Register Masks
<> 144:ef7eb2e8f9f7 5506 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5507
<> 144:ef7eb2e8f9f7 5508 /*!
<> 144:ef7eb2e8f9f7 5509 * @addtogroup PIT_Register_Masks PIT Register Masks
<> 144:ef7eb2e8f9f7 5510 * @{
<> 144:ef7eb2e8f9f7 5511 */
<> 144:ef7eb2e8f9f7 5512
<> 144:ef7eb2e8f9f7 5513 /*! @name MCR - PIT Module Control Register */
<> 144:ef7eb2e8f9f7 5514 #define PIT_MCR_FRZ_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5515 #define PIT_MCR_FRZ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5516 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
<> 144:ef7eb2e8f9f7 5517 #define PIT_MCR_MDIS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5518 #define PIT_MCR_MDIS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5519 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
<> 144:ef7eb2e8f9f7 5520
<> 144:ef7eb2e8f9f7 5521 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
<> 144:ef7eb2e8f9f7 5522 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5523 #define PIT_LTMR64H_LTH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5524 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
<> 144:ef7eb2e8f9f7 5525
<> 144:ef7eb2e8f9f7 5526 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
<> 144:ef7eb2e8f9f7 5527 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5528 #define PIT_LTMR64L_LTL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5529 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
<> 144:ef7eb2e8f9f7 5530
<> 144:ef7eb2e8f9f7 5531 /*! @name LDVAL - Timer Load Value Register */
<> 144:ef7eb2e8f9f7 5532 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5533 #define PIT_LDVAL_TSV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5534 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
<> 144:ef7eb2e8f9f7 5535
<> 144:ef7eb2e8f9f7 5536 /* The count of PIT_LDVAL */
<> 144:ef7eb2e8f9f7 5537 #define PIT_LDVAL_COUNT (2U)
<> 144:ef7eb2e8f9f7 5538
<> 144:ef7eb2e8f9f7 5539 /*! @name CVAL - Current Timer Value Register */
<> 144:ef7eb2e8f9f7 5540 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5541 #define PIT_CVAL_TVL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5542 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
<> 144:ef7eb2e8f9f7 5543
<> 144:ef7eb2e8f9f7 5544 /* The count of PIT_CVAL */
<> 144:ef7eb2e8f9f7 5545 #define PIT_CVAL_COUNT (2U)
<> 144:ef7eb2e8f9f7 5546
<> 144:ef7eb2e8f9f7 5547 /*! @name TCTRL - Timer Control Register */
<> 144:ef7eb2e8f9f7 5548 #define PIT_TCTRL_TEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5549 #define PIT_TCTRL_TEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5550 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
<> 144:ef7eb2e8f9f7 5551 #define PIT_TCTRL_TIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5552 #define PIT_TCTRL_TIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5553 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
<> 144:ef7eb2e8f9f7 5554 #define PIT_TCTRL_CHN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5555 #define PIT_TCTRL_CHN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5556 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
<> 144:ef7eb2e8f9f7 5557
<> 144:ef7eb2e8f9f7 5558 /* The count of PIT_TCTRL */
<> 144:ef7eb2e8f9f7 5559 #define PIT_TCTRL_COUNT (2U)
<> 144:ef7eb2e8f9f7 5560
<> 144:ef7eb2e8f9f7 5561 /*! @name TFLG - Timer Flag Register */
<> 144:ef7eb2e8f9f7 5562 #define PIT_TFLG_TIF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5563 #define PIT_TFLG_TIF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5564 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
<> 144:ef7eb2e8f9f7 5565
<> 144:ef7eb2e8f9f7 5566 /* The count of PIT_TFLG */
<> 144:ef7eb2e8f9f7 5567 #define PIT_TFLG_COUNT (2U)
<> 144:ef7eb2e8f9f7 5568
<> 144:ef7eb2e8f9f7 5569
<> 144:ef7eb2e8f9f7 5570 /*!
<> 144:ef7eb2e8f9f7 5571 * @}
<> 144:ef7eb2e8f9f7 5572 */ /* end of group PIT_Register_Masks */
<> 144:ef7eb2e8f9f7 5573
<> 144:ef7eb2e8f9f7 5574
<> 144:ef7eb2e8f9f7 5575 /* PIT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5576 /** Peripheral PIT base address */
<> 144:ef7eb2e8f9f7 5577 #define PIT_BASE (0x40037000u)
<> 144:ef7eb2e8f9f7 5578 /** Peripheral PIT base pointer */
<> 144:ef7eb2e8f9f7 5579 #define PIT ((PIT_Type *)PIT_BASE)
<> 144:ef7eb2e8f9f7 5580 /** Array initializer of PIT peripheral base addresses */
<> 144:ef7eb2e8f9f7 5581 #define PIT_BASE_ADDRS { PIT_BASE }
<> 144:ef7eb2e8f9f7 5582 /** Array initializer of PIT peripheral base pointers */
<> 144:ef7eb2e8f9f7 5583 #define PIT_BASE_PTRS { PIT }
<> 144:ef7eb2e8f9f7 5584 /** Interrupt vectors for the PIT peripheral type */
<> 144:ef7eb2e8f9f7 5585 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
<> 144:ef7eb2e8f9f7 5586
<> 144:ef7eb2e8f9f7 5587 /*!
<> 144:ef7eb2e8f9f7 5588 * @}
<> 144:ef7eb2e8f9f7 5589 */ /* end of group PIT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5590
<> 144:ef7eb2e8f9f7 5591
<> 144:ef7eb2e8f9f7 5592 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5593 -- PMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5594 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5595
<> 144:ef7eb2e8f9f7 5596 /*!
<> 144:ef7eb2e8f9f7 5597 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5598 * @{
<> 144:ef7eb2e8f9f7 5599 */
<> 144:ef7eb2e8f9f7 5600
<> 144:ef7eb2e8f9f7 5601 /** PMC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5602 typedef struct {
<> 144:ef7eb2e8f9f7 5603 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 5604 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 5605 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 5606 } PMC_Type;
<> 144:ef7eb2e8f9f7 5607
<> 144:ef7eb2e8f9f7 5608 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5609 -- PMC Register Masks
<> 144:ef7eb2e8f9f7 5610 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5611
<> 144:ef7eb2e8f9f7 5612 /*!
<> 144:ef7eb2e8f9f7 5613 * @addtogroup PMC_Register_Masks PMC Register Masks
<> 144:ef7eb2e8f9f7 5614 * @{
<> 144:ef7eb2e8f9f7 5615 */
<> 144:ef7eb2e8f9f7 5616
<> 144:ef7eb2e8f9f7 5617 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
<> 144:ef7eb2e8f9f7 5618 #define PMC_LVDSC1_LVDV_MASK (0x3U)
<> 144:ef7eb2e8f9f7 5619 #define PMC_LVDSC1_LVDV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5620 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
<> 144:ef7eb2e8f9f7 5621 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5622 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5623 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
<> 144:ef7eb2e8f9f7 5624 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5625 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5626 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
<> 144:ef7eb2e8f9f7 5627 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5628 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5629 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
<> 144:ef7eb2e8f9f7 5630 #define PMC_LVDSC1_LVDF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5631 #define PMC_LVDSC1_LVDF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5632 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
<> 144:ef7eb2e8f9f7 5633
<> 144:ef7eb2e8f9f7 5634 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
<> 144:ef7eb2e8f9f7 5635 #define PMC_LVDSC2_LVWV_MASK (0x3U)
<> 144:ef7eb2e8f9f7 5636 #define PMC_LVDSC2_LVWV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5637 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
<> 144:ef7eb2e8f9f7 5638 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5639 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5640 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
<> 144:ef7eb2e8f9f7 5641 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5642 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5643 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
<> 144:ef7eb2e8f9f7 5644 #define PMC_LVDSC2_LVWF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5645 #define PMC_LVDSC2_LVWF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5646 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
<> 144:ef7eb2e8f9f7 5647
<> 144:ef7eb2e8f9f7 5648 /*! @name REGSC - Regulator Status And Control register */
<> 144:ef7eb2e8f9f7 5649 #define PMC_REGSC_BGBE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5650 #define PMC_REGSC_BGBE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5651 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
<> 144:ef7eb2e8f9f7 5652 #define PMC_REGSC_REGONS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5653 #define PMC_REGSC_REGONS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5654 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
<> 144:ef7eb2e8f9f7 5655 #define PMC_REGSC_ACKISO_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5656 #define PMC_REGSC_ACKISO_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5657 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
<> 144:ef7eb2e8f9f7 5658 #define PMC_REGSC_BGEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5659 #define PMC_REGSC_BGEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5660 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
<> 144:ef7eb2e8f9f7 5661
<> 144:ef7eb2e8f9f7 5662
<> 144:ef7eb2e8f9f7 5663 /*!
<> 144:ef7eb2e8f9f7 5664 * @}
<> 144:ef7eb2e8f9f7 5665 */ /* end of group PMC_Register_Masks */
<> 144:ef7eb2e8f9f7 5666
<> 144:ef7eb2e8f9f7 5667
<> 144:ef7eb2e8f9f7 5668 /* PMC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5669 /** Peripheral PMC base address */
<> 144:ef7eb2e8f9f7 5670 #define PMC_BASE (0x4007D000u)
<> 144:ef7eb2e8f9f7 5671 /** Peripheral PMC base pointer */
<> 144:ef7eb2e8f9f7 5672 #define PMC ((PMC_Type *)PMC_BASE)
<> 144:ef7eb2e8f9f7 5673 /** Array initializer of PMC peripheral base addresses */
<> 144:ef7eb2e8f9f7 5674 #define PMC_BASE_ADDRS { PMC_BASE }
<> 144:ef7eb2e8f9f7 5675 /** Array initializer of PMC peripheral base pointers */
<> 144:ef7eb2e8f9f7 5676 #define PMC_BASE_PTRS { PMC }
<> 144:ef7eb2e8f9f7 5677 /** Interrupt vectors for the PMC peripheral type */
<> 144:ef7eb2e8f9f7 5678 #define PMC_IRQS { PMC_IRQn }
<> 144:ef7eb2e8f9f7 5679
<> 144:ef7eb2e8f9f7 5680 /*!
<> 144:ef7eb2e8f9f7 5681 * @}
<> 144:ef7eb2e8f9f7 5682 */ /* end of group PMC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5683
<> 144:ef7eb2e8f9f7 5684
<> 144:ef7eb2e8f9f7 5685 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5686 -- PORT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5687 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5688
<> 144:ef7eb2e8f9f7 5689 /*!
<> 144:ef7eb2e8f9f7 5690 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5691 * @{
<> 144:ef7eb2e8f9f7 5692 */
<> 144:ef7eb2e8f9f7 5693
<> 144:ef7eb2e8f9f7 5694 /** PORT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5695 typedef struct {
<> 144:ef7eb2e8f9f7 5696 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 5697 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 5698 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 5699 uint8_t RESERVED_0[24];
<> 144:ef7eb2e8f9f7 5700 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
<> 144:ef7eb2e8f9f7 5701 } PORT_Type;
<> 144:ef7eb2e8f9f7 5702
<> 144:ef7eb2e8f9f7 5703 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5704 -- PORT Register Masks
<> 144:ef7eb2e8f9f7 5705 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5706
<> 144:ef7eb2e8f9f7 5707 /*!
<> 144:ef7eb2e8f9f7 5708 * @addtogroup PORT_Register_Masks PORT Register Masks
<> 144:ef7eb2e8f9f7 5709 * @{
<> 144:ef7eb2e8f9f7 5710 */
<> 144:ef7eb2e8f9f7 5711
<> 144:ef7eb2e8f9f7 5712 /*! @name PCR - Pin Control Register n */
<> 144:ef7eb2e8f9f7 5713 #define PORT_PCR_PS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5714 #define PORT_PCR_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5715 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
<> 144:ef7eb2e8f9f7 5716 #define PORT_PCR_PE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5717 #define PORT_PCR_PE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5718 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
<> 144:ef7eb2e8f9f7 5719 #define PORT_PCR_SRE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5720 #define PORT_PCR_SRE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5721 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
<> 144:ef7eb2e8f9f7 5722 #define PORT_PCR_PFE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5723 #define PORT_PCR_PFE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5724 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
<> 144:ef7eb2e8f9f7 5725 #define PORT_PCR_DSE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5726 #define PORT_PCR_DSE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5727 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
<> 144:ef7eb2e8f9f7 5728 #define PORT_PCR_MUX_MASK (0x700U)
<> 144:ef7eb2e8f9f7 5729 #define PORT_PCR_MUX_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5730 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
<> 144:ef7eb2e8f9f7 5731 #define PORT_PCR_IRQC_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 5732 #define PORT_PCR_IRQC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5733 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
<> 144:ef7eb2e8f9f7 5734 #define PORT_PCR_ISF_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 5735 #define PORT_PCR_ISF_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5736 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
<> 144:ef7eb2e8f9f7 5737
<> 144:ef7eb2e8f9f7 5738 /* The count of PORT_PCR */
<> 144:ef7eb2e8f9f7 5739 #define PORT_PCR_COUNT (32U)
<> 144:ef7eb2e8f9f7 5740
<> 144:ef7eb2e8f9f7 5741 /*! @name GPCLR - Global Pin Control Low Register */
<> 144:ef7eb2e8f9f7 5742 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5743 #define PORT_GPCLR_GPWD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5744 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
<> 144:ef7eb2e8f9f7 5745 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 5746 #define PORT_GPCLR_GPWE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5747 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
<> 144:ef7eb2e8f9f7 5748
<> 144:ef7eb2e8f9f7 5749 /*! @name GPCHR - Global Pin Control High Register */
<> 144:ef7eb2e8f9f7 5750 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5751 #define PORT_GPCHR_GPWD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5752 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
<> 144:ef7eb2e8f9f7 5753 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 5754 #define PORT_GPCHR_GPWE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5755 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
<> 144:ef7eb2e8f9f7 5756
<> 144:ef7eb2e8f9f7 5757 /*! @name ISFR - Interrupt Status Flag Register */
<> 144:ef7eb2e8f9f7 5758 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5759 #define PORT_ISFR_ISF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5760 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
<> 144:ef7eb2e8f9f7 5761
<> 144:ef7eb2e8f9f7 5762
<> 144:ef7eb2e8f9f7 5763 /*!
<> 144:ef7eb2e8f9f7 5764 * @}
<> 144:ef7eb2e8f9f7 5765 */ /* end of group PORT_Register_Masks */
<> 144:ef7eb2e8f9f7 5766
<> 144:ef7eb2e8f9f7 5767
<> 144:ef7eb2e8f9f7 5768 /* PORT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5769 /** Peripheral PORTA base address */
<> 144:ef7eb2e8f9f7 5770 #define PORTA_BASE (0x40049000u)
<> 144:ef7eb2e8f9f7 5771 /** Peripheral PORTA base pointer */
<> 144:ef7eb2e8f9f7 5772 #define PORTA ((PORT_Type *)PORTA_BASE)
<> 144:ef7eb2e8f9f7 5773 /** Peripheral PORTB base address */
<> 144:ef7eb2e8f9f7 5774 #define PORTB_BASE (0x4004A000u)
<> 144:ef7eb2e8f9f7 5775 /** Peripheral PORTB base pointer */
<> 144:ef7eb2e8f9f7 5776 #define PORTB ((PORT_Type *)PORTB_BASE)
<> 144:ef7eb2e8f9f7 5777 /** Peripheral PORTC base address */
<> 144:ef7eb2e8f9f7 5778 #define PORTC_BASE (0x4004B000u)
<> 144:ef7eb2e8f9f7 5779 /** Peripheral PORTC base pointer */
<> 144:ef7eb2e8f9f7 5780 #define PORTC ((PORT_Type *)PORTC_BASE)
<> 144:ef7eb2e8f9f7 5781 /** Peripheral PORTD base address */
<> 144:ef7eb2e8f9f7 5782 #define PORTD_BASE (0x4004C000u)
<> 144:ef7eb2e8f9f7 5783 /** Peripheral PORTD base pointer */
<> 144:ef7eb2e8f9f7 5784 #define PORTD ((PORT_Type *)PORTD_BASE)
<> 144:ef7eb2e8f9f7 5785 /** Peripheral PORTE base address */
<> 144:ef7eb2e8f9f7 5786 #define PORTE_BASE (0x4004D000u)
<> 144:ef7eb2e8f9f7 5787 /** Peripheral PORTE base pointer */
<> 144:ef7eb2e8f9f7 5788 #define PORTE ((PORT_Type *)PORTE_BASE)
<> 144:ef7eb2e8f9f7 5789 /** Array initializer of PORT peripheral base addresses */
<> 144:ef7eb2e8f9f7 5790 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
<> 144:ef7eb2e8f9f7 5791 /** Array initializer of PORT peripheral base pointers */
<> 144:ef7eb2e8f9f7 5792 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
<> 144:ef7eb2e8f9f7 5793 /** Interrupt vectors for the PORT peripheral type */
<> 144:ef7eb2e8f9f7 5794 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn }
<> 144:ef7eb2e8f9f7 5795
<> 144:ef7eb2e8f9f7 5796 /*!
<> 144:ef7eb2e8f9f7 5797 * @}
<> 144:ef7eb2e8f9f7 5798 */ /* end of group PORT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5799
<> 144:ef7eb2e8f9f7 5800
<> 144:ef7eb2e8f9f7 5801 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5802 -- RCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5803 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5804
<> 144:ef7eb2e8f9f7 5805 /*!
<> 144:ef7eb2e8f9f7 5806 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5807 * @{
<> 144:ef7eb2e8f9f7 5808 */
<> 144:ef7eb2e8f9f7 5809
<> 144:ef7eb2e8f9f7 5810 /** RCM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5811 typedef struct {
<> 144:ef7eb2e8f9f7 5812 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
<> 144:ef7eb2e8f9f7 5813 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
<> 144:ef7eb2e8f9f7 5814 uint8_t RESERVED_0[2];
<> 144:ef7eb2e8f9f7 5815 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 5816 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 5817 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 5818 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 5819 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
<> 144:ef7eb2e8f9f7 5820 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
<> 144:ef7eb2e8f9f7 5821 } RCM_Type;
<> 144:ef7eb2e8f9f7 5822
<> 144:ef7eb2e8f9f7 5823 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5824 -- RCM Register Masks
<> 144:ef7eb2e8f9f7 5825 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5826
<> 144:ef7eb2e8f9f7 5827 /*!
<> 144:ef7eb2e8f9f7 5828 * @addtogroup RCM_Register_Masks RCM Register Masks
<> 144:ef7eb2e8f9f7 5829 * @{
<> 144:ef7eb2e8f9f7 5830 */
<> 144:ef7eb2e8f9f7 5831
<> 144:ef7eb2e8f9f7 5832 /*! @name SRS0 - System Reset Status Register 0 */
<> 144:ef7eb2e8f9f7 5833 #define RCM_SRS0_WAKEUP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5834 #define RCM_SRS0_WAKEUP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5835 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
<> 144:ef7eb2e8f9f7 5836 #define RCM_SRS0_LVD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5837 #define RCM_SRS0_LVD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5838 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
<> 144:ef7eb2e8f9f7 5839 #define RCM_SRS0_WDOG_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5840 #define RCM_SRS0_WDOG_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5841 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
<> 144:ef7eb2e8f9f7 5842 #define RCM_SRS0_PIN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5843 #define RCM_SRS0_PIN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5844 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
<> 144:ef7eb2e8f9f7 5845 #define RCM_SRS0_POR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5846 #define RCM_SRS0_POR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5847 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
<> 144:ef7eb2e8f9f7 5848
<> 144:ef7eb2e8f9f7 5849 /*! @name SRS1 - System Reset Status Register 1 */
<> 144:ef7eb2e8f9f7 5850 #define RCM_SRS1_LOCKUP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5851 #define RCM_SRS1_LOCKUP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5852 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
<> 144:ef7eb2e8f9f7 5853 #define RCM_SRS1_SW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5854 #define RCM_SRS1_SW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5855 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
<> 144:ef7eb2e8f9f7 5856 #define RCM_SRS1_MDM_AP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5857 #define RCM_SRS1_MDM_AP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5858 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
<> 144:ef7eb2e8f9f7 5859 #define RCM_SRS1_SACKERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5860 #define RCM_SRS1_SACKERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5861 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
<> 144:ef7eb2e8f9f7 5862
<> 144:ef7eb2e8f9f7 5863 /*! @name RPFC - Reset Pin Filter Control register */
<> 144:ef7eb2e8f9f7 5864 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
<> 144:ef7eb2e8f9f7 5865 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5866 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
<> 144:ef7eb2e8f9f7 5867 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5868 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5869 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
<> 144:ef7eb2e8f9f7 5870
<> 144:ef7eb2e8f9f7 5871 /*! @name RPFW - Reset Pin Filter Width register */
<> 144:ef7eb2e8f9f7 5872 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 5873 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5874 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
<> 144:ef7eb2e8f9f7 5875
<> 144:ef7eb2e8f9f7 5876 /*! @name FM - Force Mode Register */
<> 144:ef7eb2e8f9f7 5877 #define RCM_FM_FORCEROM_MASK (0x6U)
<> 144:ef7eb2e8f9f7 5878 #define RCM_FM_FORCEROM_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5879 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
<> 144:ef7eb2e8f9f7 5880
<> 144:ef7eb2e8f9f7 5881 /*! @name MR - Mode Register */
<> 144:ef7eb2e8f9f7 5882 #define RCM_MR_BOOTROM_MASK (0x6U)
<> 144:ef7eb2e8f9f7 5883 #define RCM_MR_BOOTROM_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5884 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
<> 144:ef7eb2e8f9f7 5885
<> 144:ef7eb2e8f9f7 5886 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
<> 144:ef7eb2e8f9f7 5887 #define RCM_SSRS0_SWAKEUP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5888 #define RCM_SSRS0_SWAKEUP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5889 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
<> 144:ef7eb2e8f9f7 5890 #define RCM_SSRS0_SLVD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5891 #define RCM_SSRS0_SLVD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5892 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
<> 144:ef7eb2e8f9f7 5893 #define RCM_SSRS0_SWDOG_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5894 #define RCM_SSRS0_SWDOG_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5895 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
<> 144:ef7eb2e8f9f7 5896 #define RCM_SSRS0_SPIN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5897 #define RCM_SSRS0_SPIN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5898 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
<> 144:ef7eb2e8f9f7 5899 #define RCM_SSRS0_SPOR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5900 #define RCM_SSRS0_SPOR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5901 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
<> 144:ef7eb2e8f9f7 5902
<> 144:ef7eb2e8f9f7 5903 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
<> 144:ef7eb2e8f9f7 5904 #define RCM_SSRS1_SLOCKUP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5905 #define RCM_SSRS1_SLOCKUP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5906 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
<> 144:ef7eb2e8f9f7 5907 #define RCM_SSRS1_SSW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5908 #define RCM_SSRS1_SSW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5909 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
<> 144:ef7eb2e8f9f7 5910 #define RCM_SSRS1_SMDM_AP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5911 #define RCM_SSRS1_SMDM_AP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5912 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
<> 144:ef7eb2e8f9f7 5913 #define RCM_SSRS1_SSACKERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5914 #define RCM_SSRS1_SSACKERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5915 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
<> 144:ef7eb2e8f9f7 5916
<> 144:ef7eb2e8f9f7 5917
<> 144:ef7eb2e8f9f7 5918 /*!
<> 144:ef7eb2e8f9f7 5919 * @}
<> 144:ef7eb2e8f9f7 5920 */ /* end of group RCM_Register_Masks */
<> 144:ef7eb2e8f9f7 5921
<> 144:ef7eb2e8f9f7 5922
<> 144:ef7eb2e8f9f7 5923 /* RCM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5924 /** Peripheral RCM base address */
<> 144:ef7eb2e8f9f7 5925 #define RCM_BASE (0x4007F000u)
<> 144:ef7eb2e8f9f7 5926 /** Peripheral RCM base pointer */
<> 144:ef7eb2e8f9f7 5927 #define RCM ((RCM_Type *)RCM_BASE)
<> 144:ef7eb2e8f9f7 5928 /** Array initializer of RCM peripheral base addresses */
<> 144:ef7eb2e8f9f7 5929 #define RCM_BASE_ADDRS { RCM_BASE }
<> 144:ef7eb2e8f9f7 5930 /** Array initializer of RCM peripheral base pointers */
<> 144:ef7eb2e8f9f7 5931 #define RCM_BASE_PTRS { RCM }
<> 144:ef7eb2e8f9f7 5932
<> 144:ef7eb2e8f9f7 5933 /*!
<> 144:ef7eb2e8f9f7 5934 * @}
<> 144:ef7eb2e8f9f7 5935 */ /* end of group RCM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5936
<> 144:ef7eb2e8f9f7 5937
<> 144:ef7eb2e8f9f7 5938 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5939 -- RFSYS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5940 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5941
<> 144:ef7eb2e8f9f7 5942 /*!
<> 144:ef7eb2e8f9f7 5943 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5944 * @{
<> 144:ef7eb2e8f9f7 5945 */
<> 144:ef7eb2e8f9f7 5946
<> 144:ef7eb2e8f9f7 5947 /** RFSYS - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5948 typedef struct {
<> 144:ef7eb2e8f9f7 5949 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 5950 } RFSYS_Type;
<> 144:ef7eb2e8f9f7 5951
<> 144:ef7eb2e8f9f7 5952 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5953 -- RFSYS Register Masks
<> 144:ef7eb2e8f9f7 5954 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5955
<> 144:ef7eb2e8f9f7 5956 /*!
<> 144:ef7eb2e8f9f7 5957 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
<> 144:ef7eb2e8f9f7 5958 * @{
<> 144:ef7eb2e8f9f7 5959 */
<> 144:ef7eb2e8f9f7 5960
<> 144:ef7eb2e8f9f7 5961 /*! @name REG - Register file register */
<> 144:ef7eb2e8f9f7 5962 #define RFSYS_REG_LL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5963 #define RFSYS_REG_LL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5964 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
<> 144:ef7eb2e8f9f7 5965 #define RFSYS_REG_LH_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 5966 #define RFSYS_REG_LH_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5967 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
<> 144:ef7eb2e8f9f7 5968 #define RFSYS_REG_HL_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 5969 #define RFSYS_REG_HL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5970 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
<> 144:ef7eb2e8f9f7 5971 #define RFSYS_REG_HH_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 5972 #define RFSYS_REG_HH_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5973 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
<> 144:ef7eb2e8f9f7 5974
<> 144:ef7eb2e8f9f7 5975 /* The count of RFSYS_REG */
<> 144:ef7eb2e8f9f7 5976 #define RFSYS_REG_COUNT (8U)
<> 144:ef7eb2e8f9f7 5977
<> 144:ef7eb2e8f9f7 5978
<> 144:ef7eb2e8f9f7 5979 /*!
<> 144:ef7eb2e8f9f7 5980 * @}
<> 144:ef7eb2e8f9f7 5981 */ /* end of group RFSYS_Register_Masks */
<> 144:ef7eb2e8f9f7 5982
<> 144:ef7eb2e8f9f7 5983
<> 144:ef7eb2e8f9f7 5984 /* RFSYS - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5985 /** Peripheral RFSYS base address */
<> 144:ef7eb2e8f9f7 5986 #define RFSYS_BASE (0x40041000u)
<> 144:ef7eb2e8f9f7 5987 /** Peripheral RFSYS base pointer */
<> 144:ef7eb2e8f9f7 5988 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
<> 144:ef7eb2e8f9f7 5989 /** Array initializer of RFSYS peripheral base addresses */
<> 144:ef7eb2e8f9f7 5990 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
<> 144:ef7eb2e8f9f7 5991 /** Array initializer of RFSYS peripheral base pointers */
<> 144:ef7eb2e8f9f7 5992 #define RFSYS_BASE_PTRS { RFSYS }
<> 144:ef7eb2e8f9f7 5993
<> 144:ef7eb2e8f9f7 5994 /*!
<> 144:ef7eb2e8f9f7 5995 * @}
<> 144:ef7eb2e8f9f7 5996 */ /* end of group RFSYS_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5997
<> 144:ef7eb2e8f9f7 5998
<> 144:ef7eb2e8f9f7 5999 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6000 -- ROM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6001 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6002
<> 144:ef7eb2e8f9f7 6003 /*!
<> 144:ef7eb2e8f9f7 6004 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6005 * @{
<> 144:ef7eb2e8f9f7 6006 */
<> 144:ef7eb2e8f9f7 6007
<> 144:ef7eb2e8f9f7 6008 /** ROM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6009 typedef struct {
<> 144:ef7eb2e8f9f7 6010 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 6011 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 6012 uint8_t RESERVED_0[4028];
<> 144:ef7eb2e8f9f7 6013 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
<> 144:ef7eb2e8f9f7 6014 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
<> 144:ef7eb2e8f9f7 6015 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
<> 144:ef7eb2e8f9f7 6016 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
<> 144:ef7eb2e8f9f7 6017 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
<> 144:ef7eb2e8f9f7 6018 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
<> 144:ef7eb2e8f9f7 6019 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
<> 144:ef7eb2e8f9f7 6020 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
<> 144:ef7eb2e8f9f7 6021 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
<> 144:ef7eb2e8f9f7 6022 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 6023 } ROM_Type;
<> 144:ef7eb2e8f9f7 6024
<> 144:ef7eb2e8f9f7 6025 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6026 -- ROM Register Masks
<> 144:ef7eb2e8f9f7 6027 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6028
<> 144:ef7eb2e8f9f7 6029 /*!
<> 144:ef7eb2e8f9f7 6030 * @addtogroup ROM_Register_Masks ROM Register Masks
<> 144:ef7eb2e8f9f7 6031 * @{
<> 144:ef7eb2e8f9f7 6032 */
<> 144:ef7eb2e8f9f7 6033
<> 144:ef7eb2e8f9f7 6034 /*! @name ENTRY - Entry */
<> 144:ef7eb2e8f9f7 6035 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6036 #define ROM_ENTRY_ENTRY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6037 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
<> 144:ef7eb2e8f9f7 6038
<> 144:ef7eb2e8f9f7 6039 /* The count of ROM_ENTRY */
<> 144:ef7eb2e8f9f7 6040 #define ROM_ENTRY_COUNT (3U)
<> 144:ef7eb2e8f9f7 6041
<> 144:ef7eb2e8f9f7 6042 /*! @name TABLEMARK - End of Table Marker Register */
<> 144:ef7eb2e8f9f7 6043 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6044 #define ROM_TABLEMARK_MARK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6045 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
<> 144:ef7eb2e8f9f7 6046
<> 144:ef7eb2e8f9f7 6047 /*! @name SYSACCESS - System Access Register */
<> 144:ef7eb2e8f9f7 6048 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6049 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6050 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
<> 144:ef7eb2e8f9f7 6051
<> 144:ef7eb2e8f9f7 6052 /*! @name PERIPHID4 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6053 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6054 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6055 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6056
<> 144:ef7eb2e8f9f7 6057 /*! @name PERIPHID5 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6058 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6059 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6060 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6061
<> 144:ef7eb2e8f9f7 6062 /*! @name PERIPHID6 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6063 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6064 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6065 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6066
<> 144:ef7eb2e8f9f7 6067 /*! @name PERIPHID7 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6068 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6069 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6070 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6071
<> 144:ef7eb2e8f9f7 6072 /*! @name PERIPHID0 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6073 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6074 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6075 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6076
<> 144:ef7eb2e8f9f7 6077 /*! @name PERIPHID1 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6078 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6079 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6080 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6081
<> 144:ef7eb2e8f9f7 6082 /*! @name PERIPHID2 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6083 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6084 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6085 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6086
<> 144:ef7eb2e8f9f7 6087 /*! @name PERIPHID3 - Peripheral ID Register */
<> 144:ef7eb2e8f9f7 6088 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6089 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6090 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
<> 144:ef7eb2e8f9f7 6091
<> 144:ef7eb2e8f9f7 6092 /*! @name COMPID - Component ID Register */
<> 144:ef7eb2e8f9f7 6093 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6094 #define ROM_COMPID_COMPID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6095 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
<> 144:ef7eb2e8f9f7 6096
<> 144:ef7eb2e8f9f7 6097 /* The count of ROM_COMPID */
<> 144:ef7eb2e8f9f7 6098 #define ROM_COMPID_COUNT (4U)
<> 144:ef7eb2e8f9f7 6099
<> 144:ef7eb2e8f9f7 6100
<> 144:ef7eb2e8f9f7 6101 /*!
<> 144:ef7eb2e8f9f7 6102 * @}
<> 144:ef7eb2e8f9f7 6103 */ /* end of group ROM_Register_Masks */
<> 144:ef7eb2e8f9f7 6104
<> 144:ef7eb2e8f9f7 6105
<> 144:ef7eb2e8f9f7 6106 /* ROM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6107 /** Peripheral ROM base address */
<> 144:ef7eb2e8f9f7 6108 #define ROM_BASE (0xF0002000u)
<> 144:ef7eb2e8f9f7 6109 /** Peripheral ROM base pointer */
<> 144:ef7eb2e8f9f7 6110 #define ROM ((ROM_Type *)ROM_BASE)
<> 144:ef7eb2e8f9f7 6111 /** Array initializer of ROM peripheral base addresses */
<> 144:ef7eb2e8f9f7 6112 #define ROM_BASE_ADDRS { ROM_BASE }
<> 144:ef7eb2e8f9f7 6113 /** Array initializer of ROM peripheral base pointers */
<> 144:ef7eb2e8f9f7 6114 #define ROM_BASE_PTRS { ROM }
<> 144:ef7eb2e8f9f7 6115
<> 144:ef7eb2e8f9f7 6116 /*!
<> 144:ef7eb2e8f9f7 6117 * @}
<> 144:ef7eb2e8f9f7 6118 */ /* end of group ROM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6119
<> 144:ef7eb2e8f9f7 6120
<> 144:ef7eb2e8f9f7 6121 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6122 -- RTC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6123 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6124
<> 144:ef7eb2e8f9f7 6125 /*!
<> 144:ef7eb2e8f9f7 6126 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6127 * @{
<> 144:ef7eb2e8f9f7 6128 */
<> 144:ef7eb2e8f9f7 6129
<> 144:ef7eb2e8f9f7 6130 /** RTC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6131 typedef struct {
<> 144:ef7eb2e8f9f7 6132 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6133 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6134 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 6135 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 6136 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 6137 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 6138 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 6139 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 6140 } RTC_Type;
<> 144:ef7eb2e8f9f7 6141
<> 144:ef7eb2e8f9f7 6142 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6143 -- RTC Register Masks
<> 144:ef7eb2e8f9f7 6144 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6145
<> 144:ef7eb2e8f9f7 6146 /*!
<> 144:ef7eb2e8f9f7 6147 * @addtogroup RTC_Register_Masks RTC Register Masks
<> 144:ef7eb2e8f9f7 6148 * @{
<> 144:ef7eb2e8f9f7 6149 */
<> 144:ef7eb2e8f9f7 6150
<> 144:ef7eb2e8f9f7 6151 /*! @name TSR - RTC Time Seconds Register */
<> 144:ef7eb2e8f9f7 6152 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6153 #define RTC_TSR_TSR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6154 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
<> 144:ef7eb2e8f9f7 6155
<> 144:ef7eb2e8f9f7 6156 /*! @name TPR - RTC Time Prescaler Register */
<> 144:ef7eb2e8f9f7 6157 #define RTC_TPR_TPR_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6158 #define RTC_TPR_TPR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6159 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
<> 144:ef7eb2e8f9f7 6160
<> 144:ef7eb2e8f9f7 6161 /*! @name TAR - RTC Time Alarm Register */
<> 144:ef7eb2e8f9f7 6162 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6163 #define RTC_TAR_TAR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6164 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
<> 144:ef7eb2e8f9f7 6165
<> 144:ef7eb2e8f9f7 6166 /*! @name TCR - RTC Time Compensation Register */
<> 144:ef7eb2e8f9f7 6167 #define RTC_TCR_TCR_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6168 #define RTC_TCR_TCR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6169 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
<> 144:ef7eb2e8f9f7 6170 #define RTC_TCR_CIR_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 6171 #define RTC_TCR_CIR_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6172 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
<> 144:ef7eb2e8f9f7 6173 #define RTC_TCR_TCV_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 6174 #define RTC_TCR_TCV_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6175 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
<> 144:ef7eb2e8f9f7 6176 #define RTC_TCR_CIC_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 6177 #define RTC_TCR_CIC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6178 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
<> 144:ef7eb2e8f9f7 6179
<> 144:ef7eb2e8f9f7 6180 /*! @name CR - RTC Control Register */
<> 144:ef7eb2e8f9f7 6181 #define RTC_CR_SWR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6182 #define RTC_CR_SWR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6183 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
<> 144:ef7eb2e8f9f7 6184 #define RTC_CR_WPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6185 #define RTC_CR_WPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6186 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
<> 144:ef7eb2e8f9f7 6187 #define RTC_CR_SUP_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6188 #define RTC_CR_SUP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6189 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
<> 144:ef7eb2e8f9f7 6190 #define RTC_CR_UM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6191 #define RTC_CR_UM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6192 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
<> 144:ef7eb2e8f9f7 6193 #define RTC_CR_WPS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6194 #define RTC_CR_WPS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6195 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
<> 144:ef7eb2e8f9f7 6196 #define RTC_CR_OSCE_MASK (0x100U)
<> 144:ef7eb2e8f9f7 6197 #define RTC_CR_OSCE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6198 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
<> 144:ef7eb2e8f9f7 6199 #define RTC_CR_CLKO_MASK (0x200U)
<> 144:ef7eb2e8f9f7 6200 #define RTC_CR_CLKO_SHIFT (9U)
<> 144:ef7eb2e8f9f7 6201 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
<> 144:ef7eb2e8f9f7 6202 #define RTC_CR_SC16P_MASK (0x400U)
<> 144:ef7eb2e8f9f7 6203 #define RTC_CR_SC16P_SHIFT (10U)
<> 144:ef7eb2e8f9f7 6204 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
<> 144:ef7eb2e8f9f7 6205 #define RTC_CR_SC8P_MASK (0x800U)
<> 144:ef7eb2e8f9f7 6206 #define RTC_CR_SC8P_SHIFT (11U)
<> 144:ef7eb2e8f9f7 6207 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
<> 144:ef7eb2e8f9f7 6208 #define RTC_CR_SC4P_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 6209 #define RTC_CR_SC4P_SHIFT (12U)
<> 144:ef7eb2e8f9f7 6210 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
<> 144:ef7eb2e8f9f7 6211 #define RTC_CR_SC2P_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 6212 #define RTC_CR_SC2P_SHIFT (13U)
<> 144:ef7eb2e8f9f7 6213 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
<> 144:ef7eb2e8f9f7 6214
<> 144:ef7eb2e8f9f7 6215 /*! @name SR - RTC Status Register */
<> 144:ef7eb2e8f9f7 6216 #define RTC_SR_TIF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6217 #define RTC_SR_TIF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6218 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
<> 144:ef7eb2e8f9f7 6219 #define RTC_SR_TOF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6220 #define RTC_SR_TOF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6221 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
<> 144:ef7eb2e8f9f7 6222 #define RTC_SR_TAF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6223 #define RTC_SR_TAF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6224 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
<> 144:ef7eb2e8f9f7 6225 #define RTC_SR_TCE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6226 #define RTC_SR_TCE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6227 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
<> 144:ef7eb2e8f9f7 6228
<> 144:ef7eb2e8f9f7 6229 /*! @name LR - RTC Lock Register */
<> 144:ef7eb2e8f9f7 6230 #define RTC_LR_TCL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6231 #define RTC_LR_TCL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6232 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
<> 144:ef7eb2e8f9f7 6233 #define RTC_LR_CRL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6234 #define RTC_LR_CRL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6235 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
<> 144:ef7eb2e8f9f7 6236 #define RTC_LR_SRL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6237 #define RTC_LR_SRL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6238 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
<> 144:ef7eb2e8f9f7 6239 #define RTC_LR_LRL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6240 #define RTC_LR_LRL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6241 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
<> 144:ef7eb2e8f9f7 6242
<> 144:ef7eb2e8f9f7 6243 /*! @name IER - RTC Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 6244 #define RTC_IER_TIIE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6245 #define RTC_IER_TIIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6246 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
<> 144:ef7eb2e8f9f7 6247 #define RTC_IER_TOIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6248 #define RTC_IER_TOIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6249 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
<> 144:ef7eb2e8f9f7 6250 #define RTC_IER_TAIE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6251 #define RTC_IER_TAIE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6252 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
<> 144:ef7eb2e8f9f7 6253 #define RTC_IER_TSIE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6254 #define RTC_IER_TSIE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6255 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
<> 144:ef7eb2e8f9f7 6256 #define RTC_IER_WPON_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6257 #define RTC_IER_WPON_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6258 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
<> 144:ef7eb2e8f9f7 6259
<> 144:ef7eb2e8f9f7 6260
<> 144:ef7eb2e8f9f7 6261 /*!
<> 144:ef7eb2e8f9f7 6262 * @}
<> 144:ef7eb2e8f9f7 6263 */ /* end of group RTC_Register_Masks */
<> 144:ef7eb2e8f9f7 6264
<> 144:ef7eb2e8f9f7 6265
<> 144:ef7eb2e8f9f7 6266 /* RTC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6267 /** Peripheral RTC base address */
<> 144:ef7eb2e8f9f7 6268 #define RTC_BASE (0x4003D000u)
<> 144:ef7eb2e8f9f7 6269 /** Peripheral RTC base pointer */
<> 144:ef7eb2e8f9f7 6270 #define RTC ((RTC_Type *)RTC_BASE)
<> 144:ef7eb2e8f9f7 6271 /** Array initializer of RTC peripheral base addresses */
<> 144:ef7eb2e8f9f7 6272 #define RTC_BASE_ADDRS { RTC_BASE }
<> 144:ef7eb2e8f9f7 6273 /** Array initializer of RTC peripheral base pointers */
<> 144:ef7eb2e8f9f7 6274 #define RTC_BASE_PTRS { RTC }
<> 144:ef7eb2e8f9f7 6275 /** Interrupt vectors for the RTC peripheral type */
<> 144:ef7eb2e8f9f7 6276 #define RTC_IRQS { RTC_IRQn }
<> 144:ef7eb2e8f9f7 6277 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
<> 144:ef7eb2e8f9f7 6278
<> 144:ef7eb2e8f9f7 6279 /*!
<> 144:ef7eb2e8f9f7 6280 * @}
<> 144:ef7eb2e8f9f7 6281 */ /* end of group RTC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6282
<> 144:ef7eb2e8f9f7 6283
<> 144:ef7eb2e8f9f7 6284 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6285 -- SIM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6286 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6287
<> 144:ef7eb2e8f9f7 6288 /*!
<> 144:ef7eb2e8f9f7 6289 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6290 * @{
<> 144:ef7eb2e8f9f7 6291 */
<> 144:ef7eb2e8f9f7 6292
<> 144:ef7eb2e8f9f7 6293 /** SIM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6294 typedef struct {
<> 144:ef7eb2e8f9f7 6295 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6296 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6297 uint8_t RESERVED_0[4092];
<> 144:ef7eb2e8f9f7 6298 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
<> 144:ef7eb2e8f9f7 6299 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 6300 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
<> 144:ef7eb2e8f9f7 6301 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
<> 144:ef7eb2e8f9f7 6302 uint8_t RESERVED_2[4];
<> 144:ef7eb2e8f9f7 6303 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
<> 144:ef7eb2e8f9f7 6304 uint8_t RESERVED_3[8];
<> 144:ef7eb2e8f9f7 6305 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
<> 144:ef7eb2e8f9f7 6306 uint8_t RESERVED_4[12];
<> 144:ef7eb2e8f9f7 6307 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
<> 144:ef7eb2e8f9f7 6308 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
<> 144:ef7eb2e8f9f7 6309 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
<> 144:ef7eb2e8f9f7 6310 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
<> 144:ef7eb2e8f9f7 6311 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
<> 144:ef7eb2e8f9f7 6312 uint8_t RESERVED_5[4];
<> 144:ef7eb2e8f9f7 6313 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
<> 144:ef7eb2e8f9f7 6314 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
<> 144:ef7eb2e8f9f7 6315 uint8_t RESERVED_6[4];
<> 144:ef7eb2e8f9f7 6316 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
<> 144:ef7eb2e8f9f7 6317 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
<> 144:ef7eb2e8f9f7 6318 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
<> 144:ef7eb2e8f9f7 6319 uint8_t RESERVED_7[156];
<> 144:ef7eb2e8f9f7 6320 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
<> 144:ef7eb2e8f9f7 6321 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
<> 144:ef7eb2e8f9f7 6322 } SIM_Type;
<> 144:ef7eb2e8f9f7 6323
<> 144:ef7eb2e8f9f7 6324 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6325 -- SIM Register Masks
<> 144:ef7eb2e8f9f7 6326 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6327
<> 144:ef7eb2e8f9f7 6328 /*!
<> 144:ef7eb2e8f9f7 6329 * @addtogroup SIM_Register_Masks SIM Register Masks
<> 144:ef7eb2e8f9f7 6330 * @{
<> 144:ef7eb2e8f9f7 6331 */
<> 144:ef7eb2e8f9f7 6332
<> 144:ef7eb2e8f9f7 6333 /*! @name SOPT1 - System Options Register 1 */
<> 144:ef7eb2e8f9f7 6334 #define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 6335 #define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6336 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
<> 144:ef7eb2e8f9f7 6337 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 6338 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6339 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
<> 144:ef7eb2e8f9f7 6340 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 6341 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
<> 144:ef7eb2e8f9f7 6342 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
<> 144:ef7eb2e8f9f7 6343 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 6344 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
<> 144:ef7eb2e8f9f7 6345 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
<> 144:ef7eb2e8f9f7 6346 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 6347 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 6348 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
<> 144:ef7eb2e8f9f7 6349
<> 144:ef7eb2e8f9f7 6350 /*! @name SOPT1CFG - SOPT1 Configuration Register */
<> 144:ef7eb2e8f9f7 6351 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 6352 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6353 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
<> 144:ef7eb2e8f9f7 6354 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 6355 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 6356 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
<> 144:ef7eb2e8f9f7 6357 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 6358 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 6359 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
<> 144:ef7eb2e8f9f7 6360
<> 144:ef7eb2e8f9f7 6361 /*! @name SOPT2 - System Options Register 2 */
<> 144:ef7eb2e8f9f7 6362 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6363 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6364 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
<> 144:ef7eb2e8f9f7 6365 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
<> 144:ef7eb2e8f9f7 6366 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6367 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
<> 144:ef7eb2e8f9f7 6368 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 6369 #define SIM_SOPT2_USBSRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6370 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
<> 144:ef7eb2e8f9f7 6371 #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U)
<> 144:ef7eb2e8f9f7 6372 #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 6373 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK)
<> 144:ef7eb2e8f9f7 6374 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 6375 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6376 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
<> 144:ef7eb2e8f9f7 6377 #define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 6378 #define SIM_SOPT2_LPUART0SRC_SHIFT (26U)
<> 144:ef7eb2e8f9f7 6379 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK)
<> 144:ef7eb2e8f9f7 6380 #define SIM_SOPT2_LPUART1SRC_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 6381 #define SIM_SOPT2_LPUART1SRC_SHIFT (28U)
<> 144:ef7eb2e8f9f7 6382 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART1SRC_SHIFT)) & SIM_SOPT2_LPUART1SRC_MASK)
<> 144:ef7eb2e8f9f7 6383
<> 144:ef7eb2e8f9f7 6384 /*! @name SOPT4 - System Options Register 4 */
<> 144:ef7eb2e8f9f7 6385 #define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 6386 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6387 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
<> 144:ef7eb2e8f9f7 6388 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 6389 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6390 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
<> 144:ef7eb2e8f9f7 6391 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 6392 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6393 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 6394 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 6395 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
<> 144:ef7eb2e8f9f7 6396 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 6397 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 6398 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 6399 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 6400
<> 144:ef7eb2e8f9f7 6401 /*! @name SOPT5 - System Options Register 5 */
<> 144:ef7eb2e8f9f7 6402 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U)
<> 144:ef7eb2e8f9f7 6403 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6404 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
<> 144:ef7eb2e8f9f7 6405 #define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6406 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6407 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
<> 144:ef7eb2e8f9f7 6408 #define SIM_SOPT5_LPUART1TXSRC_MASK (0x30U)
<> 144:ef7eb2e8f9f7 6409 #define SIM_SOPT5_LPUART1TXSRC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6410 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK)
<> 144:ef7eb2e8f9f7 6411 #define SIM_SOPT5_LPUART1RXSRC_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6412 #define SIM_SOPT5_LPUART1RXSRC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6413 #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK)
<> 144:ef7eb2e8f9f7 6414 #define SIM_SOPT5_LPUART0ODE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 6415 #define SIM_SOPT5_LPUART0ODE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6416 #define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK)
<> 144:ef7eb2e8f9f7 6417 #define SIM_SOPT5_LPUART1ODE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 6418 #define SIM_SOPT5_LPUART1ODE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 6419 #define SIM_SOPT5_LPUART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1ODE_SHIFT)) & SIM_SOPT5_LPUART1ODE_MASK)
<> 144:ef7eb2e8f9f7 6420 #define SIM_SOPT5_UART2ODE_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 6421 #define SIM_SOPT5_UART2ODE_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6422 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
<> 144:ef7eb2e8f9f7 6423
<> 144:ef7eb2e8f9f7 6424 /*! @name SOPT7 - System Options Register 7 */
<> 144:ef7eb2e8f9f7 6425 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 6426 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6427 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 6428 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6429 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6430 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
<> 144:ef7eb2e8f9f7 6431 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6432 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6433 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
<> 144:ef7eb2e8f9f7 6434
<> 144:ef7eb2e8f9f7 6435 /*! @name SDID - System Device Identification Register */
<> 144:ef7eb2e8f9f7 6436 #define SIM_SDID_PINID_MASK (0xFU)
<> 144:ef7eb2e8f9f7 6437 #define SIM_SDID_PINID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6438 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
<> 144:ef7eb2e8f9f7 6439 #define SIM_SDID_REVID_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 6440 #define SIM_SDID_REVID_SHIFT (12U)
<> 144:ef7eb2e8f9f7 6441 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
<> 144:ef7eb2e8f9f7 6442 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 6443 #define SIM_SDID_SRAMSIZE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6444 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
<> 144:ef7eb2e8f9f7 6445 #define SIM_SDID_SERIESID_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 6446 #define SIM_SDID_SERIESID_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6447 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
<> 144:ef7eb2e8f9f7 6448 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 6449 #define SIM_SDID_SUBFAMID_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6450 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
<> 144:ef7eb2e8f9f7 6451 #define SIM_SDID_FAMID_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 6452 #define SIM_SDID_FAMID_SHIFT (28U)
<> 144:ef7eb2e8f9f7 6453 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
<> 144:ef7eb2e8f9f7 6454
<> 144:ef7eb2e8f9f7 6455 /*! @name SCGC4 - System Clock Gating Control Register 4 */
<> 144:ef7eb2e8f9f7 6456 #define SIM_SCGC4_I2C0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6457 #define SIM_SCGC4_I2C0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6458 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
<> 144:ef7eb2e8f9f7 6459 #define SIM_SCGC4_I2C1_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6460 #define SIM_SCGC4_I2C1_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6461 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
<> 144:ef7eb2e8f9f7 6462 #define SIM_SCGC4_UART2_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 6463 #define SIM_SCGC4_UART2_SHIFT (12U)
<> 144:ef7eb2e8f9f7 6464 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
<> 144:ef7eb2e8f9f7 6465 #define SIM_SCGC4_USBFS_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 6466 #define SIM_SCGC4_USBFS_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6467 #define SIM_SCGC4_USBFS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBFS_SHIFT)) & SIM_SCGC4_USBFS_MASK)
<> 144:ef7eb2e8f9f7 6468 #define SIM_SCGC4_CMP0_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 6469 #define SIM_SCGC4_CMP0_SHIFT (19U)
<> 144:ef7eb2e8f9f7 6470 #define SIM_SCGC4_CMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK)
<> 144:ef7eb2e8f9f7 6471 #define SIM_SCGC4_VREF_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 6472 #define SIM_SCGC4_VREF_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6473 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
<> 144:ef7eb2e8f9f7 6474 #define SIM_SCGC4_SPI0_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 6475 #define SIM_SCGC4_SPI0_SHIFT (22U)
<> 144:ef7eb2e8f9f7 6476 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
<> 144:ef7eb2e8f9f7 6477 #define SIM_SCGC4_SPI1_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 6478 #define SIM_SCGC4_SPI1_SHIFT (23U)
<> 144:ef7eb2e8f9f7 6479 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
<> 144:ef7eb2e8f9f7 6480
<> 144:ef7eb2e8f9f7 6481 /*! @name SCGC5 - System Clock Gating Control Register 5 */
<> 144:ef7eb2e8f9f7 6482 #define SIM_SCGC5_LPTMR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6483 #define SIM_SCGC5_LPTMR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6484 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
<> 144:ef7eb2e8f9f7 6485 #define SIM_SCGC5_PORTA_MASK (0x200U)
<> 144:ef7eb2e8f9f7 6486 #define SIM_SCGC5_PORTA_SHIFT (9U)
<> 144:ef7eb2e8f9f7 6487 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
<> 144:ef7eb2e8f9f7 6488 #define SIM_SCGC5_PORTB_MASK (0x400U)
<> 144:ef7eb2e8f9f7 6489 #define SIM_SCGC5_PORTB_SHIFT (10U)
<> 144:ef7eb2e8f9f7 6490 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
<> 144:ef7eb2e8f9f7 6491 #define SIM_SCGC5_PORTC_MASK (0x800U)
<> 144:ef7eb2e8f9f7 6492 #define SIM_SCGC5_PORTC_SHIFT (11U)
<> 144:ef7eb2e8f9f7 6493 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
<> 144:ef7eb2e8f9f7 6494 #define SIM_SCGC5_PORTD_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 6495 #define SIM_SCGC5_PORTD_SHIFT (12U)
<> 144:ef7eb2e8f9f7 6496 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
<> 144:ef7eb2e8f9f7 6497 #define SIM_SCGC5_PORTE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 6498 #define SIM_SCGC5_PORTE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 6499 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
<> 144:ef7eb2e8f9f7 6500 #define SIM_SCGC5_SLCD_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 6501 #define SIM_SCGC5_SLCD_SHIFT (19U)
<> 144:ef7eb2e8f9f7 6502 #define SIM_SCGC5_SLCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_SLCD_SHIFT)) & SIM_SCGC5_SLCD_MASK)
<> 144:ef7eb2e8f9f7 6503 #define SIM_SCGC5_LPUART0_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 6504 #define SIM_SCGC5_LPUART0_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6505 #define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
<> 144:ef7eb2e8f9f7 6506 #define SIM_SCGC5_LPUART1_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 6507 #define SIM_SCGC5_LPUART1_SHIFT (21U)
<> 144:ef7eb2e8f9f7 6508 #define SIM_SCGC5_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK)
<> 144:ef7eb2e8f9f7 6509 #define SIM_SCGC5_FLEXIO_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 6510 #define SIM_SCGC5_FLEXIO_SHIFT (31U)
<> 144:ef7eb2e8f9f7 6511 #define SIM_SCGC5_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO_SHIFT)) & SIM_SCGC5_FLEXIO_MASK)
<> 144:ef7eb2e8f9f7 6512
<> 144:ef7eb2e8f9f7 6513 /*! @name SCGC6 - System Clock Gating Control Register 6 */
<> 144:ef7eb2e8f9f7 6514 #define SIM_SCGC6_FTF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6515 #define SIM_SCGC6_FTF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6516 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
<> 144:ef7eb2e8f9f7 6517 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6518 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6519 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
<> 144:ef7eb2e8f9f7 6520 #define SIM_SCGC6_I2S_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 6521 #define SIM_SCGC6_I2S_SHIFT (15U)
<> 144:ef7eb2e8f9f7 6522 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
<> 144:ef7eb2e8f9f7 6523 #define SIM_SCGC6_PIT_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 6524 #define SIM_SCGC6_PIT_SHIFT (23U)
<> 144:ef7eb2e8f9f7 6525 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
<> 144:ef7eb2e8f9f7 6526 #define SIM_SCGC6_TPM0_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 6527 #define SIM_SCGC6_TPM0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6528 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
<> 144:ef7eb2e8f9f7 6529 #define SIM_SCGC6_TPM1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 6530 #define SIM_SCGC6_TPM1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 6531 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
<> 144:ef7eb2e8f9f7 6532 #define SIM_SCGC6_TPM2_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 6533 #define SIM_SCGC6_TPM2_SHIFT (26U)
<> 144:ef7eb2e8f9f7 6534 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
<> 144:ef7eb2e8f9f7 6535 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 6536 #define SIM_SCGC6_ADC0_SHIFT (27U)
<> 144:ef7eb2e8f9f7 6537 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
<> 144:ef7eb2e8f9f7 6538 #define SIM_SCGC6_RTC_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 6539 #define SIM_SCGC6_RTC_SHIFT (29U)
<> 144:ef7eb2e8f9f7 6540 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
<> 144:ef7eb2e8f9f7 6541 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 6542 #define SIM_SCGC6_DAC0_SHIFT (31U)
<> 144:ef7eb2e8f9f7 6543 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
<> 144:ef7eb2e8f9f7 6544
<> 144:ef7eb2e8f9f7 6545 /*! @name SCGC7 - System Clock Gating Control Register 7 */
<> 144:ef7eb2e8f9f7 6546 #define SIM_SCGC7_DMA_MASK (0x100U)
<> 144:ef7eb2e8f9f7 6547 #define SIM_SCGC7_DMA_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6548 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
<> 144:ef7eb2e8f9f7 6549
<> 144:ef7eb2e8f9f7 6550 /*! @name CLKDIV1 - System Clock Divider Register 1 */
<> 144:ef7eb2e8f9f7 6551 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
<> 144:ef7eb2e8f9f7 6552 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6553 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
<> 144:ef7eb2e8f9f7 6554 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 6555 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
<> 144:ef7eb2e8f9f7 6556 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
<> 144:ef7eb2e8f9f7 6557
<> 144:ef7eb2e8f9f7 6558 /*! @name FCFG1 - Flash Configuration Register 1 */
<> 144:ef7eb2e8f9f7 6559 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6560 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6561 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
<> 144:ef7eb2e8f9f7 6562 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6563 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6564 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
<> 144:ef7eb2e8f9f7 6565 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 6566 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6567 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
<> 144:ef7eb2e8f9f7 6568
<> 144:ef7eb2e8f9f7 6569 /*! @name FCFG2 - Flash Configuration Register 2 */
<> 144:ef7eb2e8f9f7 6570 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
<> 144:ef7eb2e8f9f7 6571 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6572 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
<> 144:ef7eb2e8f9f7 6573 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
<> 144:ef7eb2e8f9f7 6574 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6575 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
<> 144:ef7eb2e8f9f7 6576
<> 144:ef7eb2e8f9f7 6577 /*! @name UIDMH - Unique Identification Register Mid-High */
<> 144:ef7eb2e8f9f7 6578 #define SIM_UIDMH_UID_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6579 #define SIM_UIDMH_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6580 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
<> 144:ef7eb2e8f9f7 6581
<> 144:ef7eb2e8f9f7 6582 /*! @name UIDML - Unique Identification Register Mid Low */
<> 144:ef7eb2e8f9f7 6583 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6584 #define SIM_UIDML_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6585 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
<> 144:ef7eb2e8f9f7 6586
<> 144:ef7eb2e8f9f7 6587 /*! @name UIDL - Unique Identification Register Low */
<> 144:ef7eb2e8f9f7 6588 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6589 #define SIM_UIDL_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6590 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
<> 144:ef7eb2e8f9f7 6591
<> 144:ef7eb2e8f9f7 6592 /*! @name COPC - COP Control Register */
<> 144:ef7eb2e8f9f7 6593 #define SIM_COPC_COPW_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6594 #define SIM_COPC_COPW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6595 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
<> 144:ef7eb2e8f9f7 6596 #define SIM_COPC_COPCLKS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6597 #define SIM_COPC_COPCLKS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6598 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
<> 144:ef7eb2e8f9f7 6599 #define SIM_COPC_COPT_MASK (0xCU)
<> 144:ef7eb2e8f9f7 6600 #define SIM_COPC_COPT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6601 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
<> 144:ef7eb2e8f9f7 6602 #define SIM_COPC_COPSTPEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6603 #define SIM_COPC_COPSTPEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6604 #define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK)
<> 144:ef7eb2e8f9f7 6605 #define SIM_COPC_COPDBGEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6606 #define SIM_COPC_COPDBGEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6607 #define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK)
<> 144:ef7eb2e8f9f7 6608 #define SIM_COPC_COPCLKSEL_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 6609 #define SIM_COPC_COPCLKSEL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6610 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK)
<> 144:ef7eb2e8f9f7 6611
<> 144:ef7eb2e8f9f7 6612 /*! @name SRVCOP - Service COP */
<> 144:ef7eb2e8f9f7 6613 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6614 #define SIM_SRVCOP_SRVCOP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6615 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
<> 144:ef7eb2e8f9f7 6616
<> 144:ef7eb2e8f9f7 6617
<> 144:ef7eb2e8f9f7 6618 /*!
<> 144:ef7eb2e8f9f7 6619 * @}
<> 144:ef7eb2e8f9f7 6620 */ /* end of group SIM_Register_Masks */
<> 144:ef7eb2e8f9f7 6621
<> 144:ef7eb2e8f9f7 6622
<> 144:ef7eb2e8f9f7 6623 /* SIM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6624 /** Peripheral SIM base address */
<> 144:ef7eb2e8f9f7 6625 #define SIM_BASE (0x40047000u)
<> 144:ef7eb2e8f9f7 6626 /** Peripheral SIM base pointer */
<> 144:ef7eb2e8f9f7 6627 #define SIM ((SIM_Type *)SIM_BASE)
<> 144:ef7eb2e8f9f7 6628 /** Array initializer of SIM peripheral base addresses */
<> 144:ef7eb2e8f9f7 6629 #define SIM_BASE_ADDRS { SIM_BASE }
<> 144:ef7eb2e8f9f7 6630 /** Array initializer of SIM peripheral base pointers */
<> 144:ef7eb2e8f9f7 6631 #define SIM_BASE_PTRS { SIM }
<> 144:ef7eb2e8f9f7 6632
<> 144:ef7eb2e8f9f7 6633 /*!
<> 144:ef7eb2e8f9f7 6634 * @}
<> 144:ef7eb2e8f9f7 6635 */ /* end of group SIM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6636
<> 144:ef7eb2e8f9f7 6637
<> 144:ef7eb2e8f9f7 6638 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6639 -- SMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6640 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6641
<> 144:ef7eb2e8f9f7 6642 /*!
<> 144:ef7eb2e8f9f7 6643 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6644 * @{
<> 144:ef7eb2e8f9f7 6645 */
<> 144:ef7eb2e8f9f7 6646
<> 144:ef7eb2e8f9f7 6647 /** SMC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6648 typedef struct {
<> 144:ef7eb2e8f9f7 6649 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6650 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 6651 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 6652 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 6653 } SMC_Type;
<> 144:ef7eb2e8f9f7 6654
<> 144:ef7eb2e8f9f7 6655 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6656 -- SMC Register Masks
<> 144:ef7eb2e8f9f7 6657 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6658
<> 144:ef7eb2e8f9f7 6659 /*!
<> 144:ef7eb2e8f9f7 6660 * @addtogroup SMC_Register_Masks SMC Register Masks
<> 144:ef7eb2e8f9f7 6661 * @{
<> 144:ef7eb2e8f9f7 6662 */
<> 144:ef7eb2e8f9f7 6663
<> 144:ef7eb2e8f9f7 6664 /*! @name PMPROT - Power Mode Protection register */
<> 144:ef7eb2e8f9f7 6665 #define SMC_PMPROT_AVLLS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6666 #define SMC_PMPROT_AVLLS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6667 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
<> 144:ef7eb2e8f9f7 6668 #define SMC_PMPROT_ALLS_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6669 #define SMC_PMPROT_ALLS_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6670 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
<> 144:ef7eb2e8f9f7 6671 #define SMC_PMPROT_AVLP_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6672 #define SMC_PMPROT_AVLP_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6673 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
<> 144:ef7eb2e8f9f7 6674
<> 144:ef7eb2e8f9f7 6675 /*! @name PMCTRL - Power Mode Control register */
<> 144:ef7eb2e8f9f7 6676 #define SMC_PMCTRL_STOPM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 6677 #define SMC_PMCTRL_STOPM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6678 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
<> 144:ef7eb2e8f9f7 6679 #define SMC_PMCTRL_STOPA_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6680 #define SMC_PMCTRL_STOPA_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6681 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
<> 144:ef7eb2e8f9f7 6682 #define SMC_PMCTRL_RUNM_MASK (0x60U)
<> 144:ef7eb2e8f9f7 6683 #define SMC_PMCTRL_RUNM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6684 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
<> 144:ef7eb2e8f9f7 6685
<> 144:ef7eb2e8f9f7 6686 /*! @name STOPCTRL - Stop Control Register */
<> 144:ef7eb2e8f9f7 6687 #define SMC_STOPCTRL_VLLSM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 6688 #define SMC_STOPCTRL_VLLSM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6689 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
<> 144:ef7eb2e8f9f7 6690 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6691 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6692 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
<> 144:ef7eb2e8f9f7 6693 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 6694 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6695 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
<> 144:ef7eb2e8f9f7 6696
<> 144:ef7eb2e8f9f7 6697 /*! @name PMSTAT - Power Mode Status register */
<> 144:ef7eb2e8f9f7 6698 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6699 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6700 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
<> 144:ef7eb2e8f9f7 6701
<> 144:ef7eb2e8f9f7 6702
<> 144:ef7eb2e8f9f7 6703 /*!
<> 144:ef7eb2e8f9f7 6704 * @}
<> 144:ef7eb2e8f9f7 6705 */ /* end of group SMC_Register_Masks */
<> 144:ef7eb2e8f9f7 6706
<> 144:ef7eb2e8f9f7 6707
<> 144:ef7eb2e8f9f7 6708 /* SMC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6709 /** Peripheral SMC base address */
<> 144:ef7eb2e8f9f7 6710 #define SMC_BASE (0x4007E000u)
<> 144:ef7eb2e8f9f7 6711 /** Peripheral SMC base pointer */
<> 144:ef7eb2e8f9f7 6712 #define SMC ((SMC_Type *)SMC_BASE)
<> 144:ef7eb2e8f9f7 6713 /** Array initializer of SMC peripheral base addresses */
<> 144:ef7eb2e8f9f7 6714 #define SMC_BASE_ADDRS { SMC_BASE }
<> 144:ef7eb2e8f9f7 6715 /** Array initializer of SMC peripheral base pointers */
<> 144:ef7eb2e8f9f7 6716 #define SMC_BASE_PTRS { SMC }
<> 144:ef7eb2e8f9f7 6717
<> 144:ef7eb2e8f9f7 6718 /*!
<> 144:ef7eb2e8f9f7 6719 * @}
<> 144:ef7eb2e8f9f7 6720 */ /* end of group SMC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6721
<> 144:ef7eb2e8f9f7 6722
<> 144:ef7eb2e8f9f7 6723 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6724 -- SPI Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6725 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6726
<> 144:ef7eb2e8f9f7 6727 /*!
<> 144:ef7eb2e8f9f7 6728 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6729 * @{
<> 144:ef7eb2e8f9f7 6730 */
<> 144:ef7eb2e8f9f7 6731
<> 144:ef7eb2e8f9f7 6732 /** SPI - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6733 typedef struct {
<> 144:ef7eb2e8f9f7 6734 __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6735 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 6736 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
<> 144:ef7eb2e8f9f7 6737 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
<> 144:ef7eb2e8f9f7 6738 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6739 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
<> 144:ef7eb2e8f9f7 6740 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
<> 144:ef7eb2e8f9f7 6741 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
<> 144:ef7eb2e8f9f7 6742 uint8_t RESERVED_0[2];
<> 144:ef7eb2e8f9f7 6743 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
<> 144:ef7eb2e8f9f7 6744 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
<> 144:ef7eb2e8f9f7 6745 } SPI_Type;
<> 144:ef7eb2e8f9f7 6746
<> 144:ef7eb2e8f9f7 6747 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6748 -- SPI Register Masks
<> 144:ef7eb2e8f9f7 6749 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6750
<> 144:ef7eb2e8f9f7 6751 /*!
<> 144:ef7eb2e8f9f7 6752 * @addtogroup SPI_Register_Masks SPI Register Masks
<> 144:ef7eb2e8f9f7 6753 * @{
<> 144:ef7eb2e8f9f7 6754 */
<> 144:ef7eb2e8f9f7 6755
<> 144:ef7eb2e8f9f7 6756 /*! @name S - SPI Status Register */
<> 144:ef7eb2e8f9f7 6757 #define SPI_S_RFIFOEF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6758 #define SPI_S_RFIFOEF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6759 #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
<> 144:ef7eb2e8f9f7 6760 #define SPI_S_TXFULLF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6761 #define SPI_S_TXFULLF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6762 #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
<> 144:ef7eb2e8f9f7 6763 #define SPI_S_TNEAREF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6764 #define SPI_S_TNEAREF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6765 #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
<> 144:ef7eb2e8f9f7 6766 #define SPI_S_RNFULLF_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6767 #define SPI_S_RNFULLF_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6768 #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
<> 144:ef7eb2e8f9f7 6769 #define SPI_S_MODF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6770 #define SPI_S_MODF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6771 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
<> 144:ef7eb2e8f9f7 6772 #define SPI_S_SPTEF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6773 #define SPI_S_SPTEF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6774 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
<> 144:ef7eb2e8f9f7 6775 #define SPI_S_SPMF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6776 #define SPI_S_SPMF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6777 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
<> 144:ef7eb2e8f9f7 6778 #define SPI_S_SPRF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6779 #define SPI_S_SPRF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6780 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
<> 144:ef7eb2e8f9f7 6781
<> 144:ef7eb2e8f9f7 6782 /*! @name BR - SPI Baud Rate Register */
<> 144:ef7eb2e8f9f7 6783 #define SPI_BR_SPR_MASK (0xFU)
<> 144:ef7eb2e8f9f7 6784 #define SPI_BR_SPR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6785 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
<> 144:ef7eb2e8f9f7 6786 #define SPI_BR_SPPR_MASK (0x70U)
<> 144:ef7eb2e8f9f7 6787 #define SPI_BR_SPPR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6788 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
<> 144:ef7eb2e8f9f7 6789
<> 144:ef7eb2e8f9f7 6790 /*! @name C2 - SPI Control Register 2 */
<> 144:ef7eb2e8f9f7 6791 #define SPI_C2_SPC0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6792 #define SPI_C2_SPC0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6793 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
<> 144:ef7eb2e8f9f7 6794 #define SPI_C2_SPISWAI_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6795 #define SPI_C2_SPISWAI_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6796 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
<> 144:ef7eb2e8f9f7 6797 #define SPI_C2_RXDMAE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6798 #define SPI_C2_RXDMAE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6799 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
<> 144:ef7eb2e8f9f7 6800 #define SPI_C2_BIDIROE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6801 #define SPI_C2_BIDIROE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6802 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
<> 144:ef7eb2e8f9f7 6803 #define SPI_C2_MODFEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6804 #define SPI_C2_MODFEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6805 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
<> 144:ef7eb2e8f9f7 6806 #define SPI_C2_TXDMAE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6807 #define SPI_C2_TXDMAE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6808 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
<> 144:ef7eb2e8f9f7 6809 #define SPI_C2_SPIMODE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6810 #define SPI_C2_SPIMODE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6811 #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
<> 144:ef7eb2e8f9f7 6812 #define SPI_C2_SPMIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6813 #define SPI_C2_SPMIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6814 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
<> 144:ef7eb2e8f9f7 6815
<> 144:ef7eb2e8f9f7 6816 /*! @name C1 - SPI Control Register 1 */
<> 144:ef7eb2e8f9f7 6817 #define SPI_C1_LSBFE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6818 #define SPI_C1_LSBFE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6819 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
<> 144:ef7eb2e8f9f7 6820 #define SPI_C1_SSOE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6821 #define SPI_C1_SSOE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6822 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
<> 144:ef7eb2e8f9f7 6823 #define SPI_C1_CPHA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6824 #define SPI_C1_CPHA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6825 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
<> 144:ef7eb2e8f9f7 6826 #define SPI_C1_CPOL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6827 #define SPI_C1_CPOL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6828 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
<> 144:ef7eb2e8f9f7 6829 #define SPI_C1_MSTR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6830 #define SPI_C1_MSTR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6831 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
<> 144:ef7eb2e8f9f7 6832 #define SPI_C1_SPTIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6833 #define SPI_C1_SPTIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6834 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
<> 144:ef7eb2e8f9f7 6835 #define SPI_C1_SPE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6836 #define SPI_C1_SPE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6837 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
<> 144:ef7eb2e8f9f7 6838 #define SPI_C1_SPIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6839 #define SPI_C1_SPIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6840 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
<> 144:ef7eb2e8f9f7 6841
<> 144:ef7eb2e8f9f7 6842 /*! @name ML - SPI Match Register low */
<> 144:ef7eb2e8f9f7 6843 #define SPI_ML_Bits_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6844 #define SPI_ML_Bits_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6845 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
<> 144:ef7eb2e8f9f7 6846
<> 144:ef7eb2e8f9f7 6847 /*! @name MH - SPI match register high */
<> 144:ef7eb2e8f9f7 6848 #define SPI_MH_Bits_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6849 #define SPI_MH_Bits_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6850 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
<> 144:ef7eb2e8f9f7 6851
<> 144:ef7eb2e8f9f7 6852 /*! @name DL - SPI Data Register low */
<> 144:ef7eb2e8f9f7 6853 #define SPI_DL_Bits_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6854 #define SPI_DL_Bits_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6855 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
<> 144:ef7eb2e8f9f7 6856
<> 144:ef7eb2e8f9f7 6857 /*! @name DH - SPI data register high */
<> 144:ef7eb2e8f9f7 6858 #define SPI_DH_Bits_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6859 #define SPI_DH_Bits_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6860 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
<> 144:ef7eb2e8f9f7 6861
<> 144:ef7eb2e8f9f7 6862 /*! @name CI - SPI clear interrupt register */
<> 144:ef7eb2e8f9f7 6863 #define SPI_CI_SPRFCI_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6864 #define SPI_CI_SPRFCI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6865 #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
<> 144:ef7eb2e8f9f7 6866 #define SPI_CI_SPTEFCI_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6867 #define SPI_CI_SPTEFCI_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6868 #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
<> 144:ef7eb2e8f9f7 6869 #define SPI_CI_RNFULLFCI_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6870 #define SPI_CI_RNFULLFCI_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6871 #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
<> 144:ef7eb2e8f9f7 6872 #define SPI_CI_TNEAREFCI_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6873 #define SPI_CI_TNEAREFCI_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6874 #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
<> 144:ef7eb2e8f9f7 6875 #define SPI_CI_RXFOF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6876 #define SPI_CI_RXFOF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6877 #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
<> 144:ef7eb2e8f9f7 6878 #define SPI_CI_TXFOF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6879 #define SPI_CI_TXFOF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6880 #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
<> 144:ef7eb2e8f9f7 6881 #define SPI_CI_RXFERR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6882 #define SPI_CI_RXFERR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6883 #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
<> 144:ef7eb2e8f9f7 6884 #define SPI_CI_TXFERR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6885 #define SPI_CI_TXFERR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6886 #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
<> 144:ef7eb2e8f9f7 6887
<> 144:ef7eb2e8f9f7 6888 /*! @name C3 - SPI control register 3 */
<> 144:ef7eb2e8f9f7 6889 #define SPI_C3_FIFOMODE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6890 #define SPI_C3_FIFOMODE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6891 #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
<> 144:ef7eb2e8f9f7 6892 #define SPI_C3_RNFULLIEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6893 #define SPI_C3_RNFULLIEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6894 #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
<> 144:ef7eb2e8f9f7 6895 #define SPI_C3_TNEARIEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6896 #define SPI_C3_TNEARIEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6897 #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
<> 144:ef7eb2e8f9f7 6898 #define SPI_C3_INTCLR_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6899 #define SPI_C3_INTCLR_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6900 #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
<> 144:ef7eb2e8f9f7 6901 #define SPI_C3_RNFULLF_MARK_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6902 #define SPI_C3_RNFULLF_MARK_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6903 #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
<> 144:ef7eb2e8f9f7 6904 #define SPI_C3_TNEAREF_MARK_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6905 #define SPI_C3_TNEAREF_MARK_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6906 #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
<> 144:ef7eb2e8f9f7 6907
<> 144:ef7eb2e8f9f7 6908
<> 144:ef7eb2e8f9f7 6909 /*!
<> 144:ef7eb2e8f9f7 6910 * @}
<> 144:ef7eb2e8f9f7 6911 */ /* end of group SPI_Register_Masks */
<> 144:ef7eb2e8f9f7 6912
<> 144:ef7eb2e8f9f7 6913
<> 144:ef7eb2e8f9f7 6914 /* SPI - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6915 /** Peripheral SPI0 base address */
<> 144:ef7eb2e8f9f7 6916 #define SPI0_BASE (0x40076000u)
<> 144:ef7eb2e8f9f7 6917 /** Peripheral SPI0 base pointer */
<> 144:ef7eb2e8f9f7 6918 #define SPI0 ((SPI_Type *)SPI0_BASE)
<> 144:ef7eb2e8f9f7 6919 /** Peripheral SPI1 base address */
<> 144:ef7eb2e8f9f7 6920 #define SPI1_BASE (0x40077000u)
<> 144:ef7eb2e8f9f7 6921 /** Peripheral SPI1 base pointer */
<> 144:ef7eb2e8f9f7 6922 #define SPI1 ((SPI_Type *)SPI1_BASE)
<> 144:ef7eb2e8f9f7 6923 /** Array initializer of SPI peripheral base addresses */
<> 144:ef7eb2e8f9f7 6924 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
<> 144:ef7eb2e8f9f7 6925 /** Array initializer of SPI peripheral base pointers */
<> 144:ef7eb2e8f9f7 6926 #define SPI_BASE_PTRS { SPI0, SPI1 }
<> 144:ef7eb2e8f9f7 6927 /** Interrupt vectors for the SPI peripheral type */
<> 144:ef7eb2e8f9f7 6928 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
<> 144:ef7eb2e8f9f7 6929
<> 144:ef7eb2e8f9f7 6930 /*!
<> 144:ef7eb2e8f9f7 6931 * @}
<> 144:ef7eb2e8f9f7 6932 */ /* end of group SPI_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6933
<> 144:ef7eb2e8f9f7 6934
<> 144:ef7eb2e8f9f7 6935 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6936 -- TPM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6937 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6938
<> 144:ef7eb2e8f9f7 6939 /*!
<> 144:ef7eb2e8f9f7 6940 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6941 * @{
<> 144:ef7eb2e8f9f7 6942 */
<> 144:ef7eb2e8f9f7 6943
<> 144:ef7eb2e8f9f7 6944 /** TPM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6945 typedef struct {
<> 144:ef7eb2e8f9f7 6946 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6947 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6948 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
<> 144:ef7eb2e8f9f7 6949 struct { /* offset: 0xC, array step: 0x8 */
<> 144:ef7eb2e8f9f7 6950 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
<> 144:ef7eb2e8f9f7 6951 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
<> 144:ef7eb2e8f9f7 6952 } CONTROLS[6];
<> 144:ef7eb2e8f9f7 6953 uint8_t RESERVED_0[20];
<> 144:ef7eb2e8f9f7 6954 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
<> 144:ef7eb2e8f9f7 6955 uint8_t RESERVED_1[28];
<> 144:ef7eb2e8f9f7 6956 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
<> 144:ef7eb2e8f9f7 6957 uint8_t RESERVED_2[16];
<> 144:ef7eb2e8f9f7 6958 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
<> 144:ef7eb2e8f9f7 6959 } TPM_Type;
<> 144:ef7eb2e8f9f7 6960
<> 144:ef7eb2e8f9f7 6961 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6962 -- TPM Register Masks
<> 144:ef7eb2e8f9f7 6963 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6964
<> 144:ef7eb2e8f9f7 6965 /*!
<> 144:ef7eb2e8f9f7 6966 * @addtogroup TPM_Register_Masks TPM Register Masks
<> 144:ef7eb2e8f9f7 6967 * @{
<> 144:ef7eb2e8f9f7 6968 */
<> 144:ef7eb2e8f9f7 6969
<> 144:ef7eb2e8f9f7 6970 /*! @name SC - Status and Control */
<> 144:ef7eb2e8f9f7 6971 #define TPM_SC_PS_MASK (0x7U)
<> 144:ef7eb2e8f9f7 6972 #define TPM_SC_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6973 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
<> 144:ef7eb2e8f9f7 6974 #define TPM_SC_CMOD_MASK (0x18U)
<> 144:ef7eb2e8f9f7 6975 #define TPM_SC_CMOD_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6976 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
<> 144:ef7eb2e8f9f7 6977 #define TPM_SC_CPWMS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6978 #define TPM_SC_CPWMS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6979 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
<> 144:ef7eb2e8f9f7 6980 #define TPM_SC_TOIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6981 #define TPM_SC_TOIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6982 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
<> 144:ef7eb2e8f9f7 6983 #define TPM_SC_TOF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6984 #define TPM_SC_TOF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6985 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
<> 144:ef7eb2e8f9f7 6986 #define TPM_SC_DMA_MASK (0x100U)
<> 144:ef7eb2e8f9f7 6987 #define TPM_SC_DMA_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6988 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
<> 144:ef7eb2e8f9f7 6989
<> 144:ef7eb2e8f9f7 6990 /*! @name CNT - Counter */
<> 144:ef7eb2e8f9f7 6991 #define TPM_CNT_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6992 #define TPM_CNT_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6993 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6994
<> 144:ef7eb2e8f9f7 6995 /*! @name MOD - Modulo */
<> 144:ef7eb2e8f9f7 6996 #define TPM_MOD_MOD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6997 #define TPM_MOD_MOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6998 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
<> 144:ef7eb2e8f9f7 6999
<> 144:ef7eb2e8f9f7 7000 /*! @name CnSC - Channel (n) Status and Control */
<> 144:ef7eb2e8f9f7 7001 #define TPM_CnSC_DMA_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7002 #define TPM_CnSC_DMA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7003 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
<> 144:ef7eb2e8f9f7 7004 #define TPM_CnSC_ELSA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7005 #define TPM_CnSC_ELSA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7006 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
<> 144:ef7eb2e8f9f7 7007 #define TPM_CnSC_ELSB_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7008 #define TPM_CnSC_ELSB_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7009 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
<> 144:ef7eb2e8f9f7 7010 #define TPM_CnSC_MSA_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7011 #define TPM_CnSC_MSA_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7012 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
<> 144:ef7eb2e8f9f7 7013 #define TPM_CnSC_MSB_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7014 #define TPM_CnSC_MSB_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7015 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
<> 144:ef7eb2e8f9f7 7016 #define TPM_CnSC_CHIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7017 #define TPM_CnSC_CHIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7018 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
<> 144:ef7eb2e8f9f7 7019 #define TPM_CnSC_CHF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7020 #define TPM_CnSC_CHF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7021 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
<> 144:ef7eb2e8f9f7 7022
<> 144:ef7eb2e8f9f7 7023 /* The count of TPM_CnSC */
<> 144:ef7eb2e8f9f7 7024 #define TPM_CnSC_COUNT (6U)
<> 144:ef7eb2e8f9f7 7025
<> 144:ef7eb2e8f9f7 7026 /*! @name CnV - Channel (n) Value */
<> 144:ef7eb2e8f9f7 7027 #define TPM_CnV_VAL_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 7028 #define TPM_CnV_VAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7029 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
<> 144:ef7eb2e8f9f7 7030
<> 144:ef7eb2e8f9f7 7031 /* The count of TPM_CnV */
<> 144:ef7eb2e8f9f7 7032 #define TPM_CnV_COUNT (6U)
<> 144:ef7eb2e8f9f7 7033
<> 144:ef7eb2e8f9f7 7034 /*! @name STATUS - Capture and Compare Status */
<> 144:ef7eb2e8f9f7 7035 #define TPM_STATUS_CH0F_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7036 #define TPM_STATUS_CH0F_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7037 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
<> 144:ef7eb2e8f9f7 7038 #define TPM_STATUS_CH1F_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7039 #define TPM_STATUS_CH1F_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7040 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
<> 144:ef7eb2e8f9f7 7041 #define TPM_STATUS_CH2F_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7042 #define TPM_STATUS_CH2F_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7043 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
<> 144:ef7eb2e8f9f7 7044 #define TPM_STATUS_CH3F_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7045 #define TPM_STATUS_CH3F_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7046 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
<> 144:ef7eb2e8f9f7 7047 #define TPM_STATUS_CH4F_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7048 #define TPM_STATUS_CH4F_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7049 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
<> 144:ef7eb2e8f9f7 7050 #define TPM_STATUS_CH5F_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7051 #define TPM_STATUS_CH5F_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7052 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
<> 144:ef7eb2e8f9f7 7053 #define TPM_STATUS_TOF_MASK (0x100U)
<> 144:ef7eb2e8f9f7 7054 #define TPM_STATUS_TOF_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7055 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
<> 144:ef7eb2e8f9f7 7056
<> 144:ef7eb2e8f9f7 7057 /*! @name POL - Channel Polarity */
<> 144:ef7eb2e8f9f7 7058 #define TPM_POL_POL0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7059 #define TPM_POL_POL0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7060 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
<> 144:ef7eb2e8f9f7 7061 #define TPM_POL_POL1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7062 #define TPM_POL_POL1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7063 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
<> 144:ef7eb2e8f9f7 7064 #define TPM_POL_POL2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7065 #define TPM_POL_POL2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7066 #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
<> 144:ef7eb2e8f9f7 7067 #define TPM_POL_POL3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7068 #define TPM_POL_POL3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7069 #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
<> 144:ef7eb2e8f9f7 7070 #define TPM_POL_POL4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7071 #define TPM_POL_POL4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7072 #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
<> 144:ef7eb2e8f9f7 7073 #define TPM_POL_POL5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7074 #define TPM_POL_POL5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7075 #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
<> 144:ef7eb2e8f9f7 7076
<> 144:ef7eb2e8f9f7 7077 /*! @name CONF - Configuration */
<> 144:ef7eb2e8f9f7 7078 #define TPM_CONF_DOZEEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7079 #define TPM_CONF_DOZEEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7080 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
<> 144:ef7eb2e8f9f7 7081 #define TPM_CONF_DBGMODE_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 7082 #define TPM_CONF_DBGMODE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7083 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
<> 144:ef7eb2e8f9f7 7084 #define TPM_CONF_GTBSYNC_MASK (0x100U)
<> 144:ef7eb2e8f9f7 7085 #define TPM_CONF_GTBSYNC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7086 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
<> 144:ef7eb2e8f9f7 7087 #define TPM_CONF_GTBEEN_MASK (0x200U)
<> 144:ef7eb2e8f9f7 7088 #define TPM_CONF_GTBEEN_SHIFT (9U)
<> 144:ef7eb2e8f9f7 7089 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
<> 144:ef7eb2e8f9f7 7090 #define TPM_CONF_CSOT_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 7091 #define TPM_CONF_CSOT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 7092 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
<> 144:ef7eb2e8f9f7 7093 #define TPM_CONF_CSOO_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 7094 #define TPM_CONF_CSOO_SHIFT (17U)
<> 144:ef7eb2e8f9f7 7095 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
<> 144:ef7eb2e8f9f7 7096 #define TPM_CONF_CROT_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 7097 #define TPM_CONF_CROT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 7098 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
<> 144:ef7eb2e8f9f7 7099 #define TPM_CONF_CPOT_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 7100 #define TPM_CONF_CPOT_SHIFT (19U)
<> 144:ef7eb2e8f9f7 7101 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
<> 144:ef7eb2e8f9f7 7102 #define TPM_CONF_TRGPOL_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 7103 #define TPM_CONF_TRGPOL_SHIFT (22U)
<> 144:ef7eb2e8f9f7 7104 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
<> 144:ef7eb2e8f9f7 7105 #define TPM_CONF_TRGSRC_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 7106 #define TPM_CONF_TRGSRC_SHIFT (23U)
<> 144:ef7eb2e8f9f7 7107 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
<> 144:ef7eb2e8f9f7 7108 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 7109 #define TPM_CONF_TRGSEL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 7110 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 7111
<> 144:ef7eb2e8f9f7 7112
<> 144:ef7eb2e8f9f7 7113 /*!
<> 144:ef7eb2e8f9f7 7114 * @}
<> 144:ef7eb2e8f9f7 7115 */ /* end of group TPM_Register_Masks */
<> 144:ef7eb2e8f9f7 7116
<> 144:ef7eb2e8f9f7 7117
<> 144:ef7eb2e8f9f7 7118 /* TPM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7119 /** Peripheral TPM0 base address */
<> 144:ef7eb2e8f9f7 7120 #define TPM0_BASE (0x40038000u)
<> 144:ef7eb2e8f9f7 7121 /** Peripheral TPM0 base pointer */
<> 144:ef7eb2e8f9f7 7122 #define TPM0 ((TPM_Type *)TPM0_BASE)
<> 144:ef7eb2e8f9f7 7123 /** Peripheral TPM1 base address */
<> 144:ef7eb2e8f9f7 7124 #define TPM1_BASE (0x40039000u)
<> 144:ef7eb2e8f9f7 7125 /** Peripheral TPM1 base pointer */
<> 144:ef7eb2e8f9f7 7126 #define TPM1 ((TPM_Type *)TPM1_BASE)
<> 144:ef7eb2e8f9f7 7127 /** Peripheral TPM2 base address */
<> 144:ef7eb2e8f9f7 7128 #define TPM2_BASE (0x4003A000u)
<> 144:ef7eb2e8f9f7 7129 /** Peripheral TPM2 base pointer */
<> 144:ef7eb2e8f9f7 7130 #define TPM2 ((TPM_Type *)TPM2_BASE)
<> 144:ef7eb2e8f9f7 7131 /** Array initializer of TPM peripheral base addresses */
<> 144:ef7eb2e8f9f7 7132 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
<> 144:ef7eb2e8f9f7 7133 /** Array initializer of TPM peripheral base pointers */
<> 144:ef7eb2e8f9f7 7134 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
<> 144:ef7eb2e8f9f7 7135 /** Interrupt vectors for the TPM peripheral type */
<> 144:ef7eb2e8f9f7 7136 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
<> 144:ef7eb2e8f9f7 7137
<> 144:ef7eb2e8f9f7 7138 /*!
<> 144:ef7eb2e8f9f7 7139 * @}
<> 144:ef7eb2e8f9f7 7140 */ /* end of group TPM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7141
<> 144:ef7eb2e8f9f7 7142
<> 144:ef7eb2e8f9f7 7143 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7144 -- UART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7145 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7146
<> 144:ef7eb2e8f9f7 7147 /*!
<> 144:ef7eb2e8f9f7 7148 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7149 * @{
<> 144:ef7eb2e8f9f7 7150 */
<> 144:ef7eb2e8f9f7 7151
<> 144:ef7eb2e8f9f7 7152 /** UART - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 7153 typedef struct {
<> 144:ef7eb2e8f9f7 7154 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
<> 144:ef7eb2e8f9f7 7155 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
<> 144:ef7eb2e8f9f7 7156 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
<> 144:ef7eb2e8f9f7 7157 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
<> 144:ef7eb2e8f9f7 7158 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
<> 144:ef7eb2e8f9f7 7159 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
<> 144:ef7eb2e8f9f7 7160 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
<> 144:ef7eb2e8f9f7 7161 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 7162 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
<> 144:ef7eb2e8f9f7 7163 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
<> 144:ef7eb2e8f9f7 7164 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
<> 144:ef7eb2e8f9f7 7165 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
<> 144:ef7eb2e8f9f7 7166 uint8_t RESERVED_0[12];
<> 144:ef7eb2e8f9f7 7167 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 7168 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
<> 144:ef7eb2e8f9f7 7169 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
<> 144:ef7eb2e8f9f7 7170 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
<> 144:ef7eb2e8f9f7 7171 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 7172 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
<> 144:ef7eb2e8f9f7 7173 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
<> 144:ef7eb2e8f9f7 7174 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
<> 144:ef7eb2e8f9f7 7175 uint8_t RESERVED_1[26];
<> 144:ef7eb2e8f9f7 7176 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
<> 144:ef7eb2e8f9f7 7177 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
<> 144:ef7eb2e8f9f7 7178 union { /* offset: 0x3C */
<> 144:ef7eb2e8f9f7 7179 struct { /* offset: 0x3C */
<> 144:ef7eb2e8f9f7 7180 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
<> 144:ef7eb2e8f9f7 7181 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
<> 144:ef7eb2e8f9f7 7182 } TYPE0;
<> 144:ef7eb2e8f9f7 7183 struct { /* offset: 0x3C */
<> 144:ef7eb2e8f9f7 7184 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
<> 144:ef7eb2e8f9f7 7185 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
<> 144:ef7eb2e8f9f7 7186 } TYPE1;
<> 144:ef7eb2e8f9f7 7187 };
<> 144:ef7eb2e8f9f7 7188 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
<> 144:ef7eb2e8f9f7 7189 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
<> 144:ef7eb2e8f9f7 7190 } UART_Type;
<> 144:ef7eb2e8f9f7 7191
<> 144:ef7eb2e8f9f7 7192 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7193 -- UART Register Masks
<> 144:ef7eb2e8f9f7 7194 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7195
<> 144:ef7eb2e8f9f7 7196 /*!
<> 144:ef7eb2e8f9f7 7197 * @addtogroup UART_Register_Masks UART Register Masks
<> 144:ef7eb2e8f9f7 7198 * @{
<> 144:ef7eb2e8f9f7 7199 */
<> 144:ef7eb2e8f9f7 7200
<> 144:ef7eb2e8f9f7 7201 /*! @name BDH - UART Baud Rate Registers: High */
<> 144:ef7eb2e8f9f7 7202 #define UART_BDH_SBR_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 7203 #define UART_BDH_SBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7204 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
<> 144:ef7eb2e8f9f7 7205 #define UART_BDH_RXEDGIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7206 #define UART_BDH_RXEDGIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7207 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
<> 144:ef7eb2e8f9f7 7208
<> 144:ef7eb2e8f9f7 7209 /*! @name BDL - UART Baud Rate Registers: Low */
<> 144:ef7eb2e8f9f7 7210 #define UART_BDL_SBR_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7211 #define UART_BDL_SBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7212 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
<> 144:ef7eb2e8f9f7 7213
<> 144:ef7eb2e8f9f7 7214 /*! @name C1 - UART Control Register 1 */
<> 144:ef7eb2e8f9f7 7215 #define UART_C1_PT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7216 #define UART_C1_PT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7217 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
<> 144:ef7eb2e8f9f7 7218 #define UART_C1_PE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7219 #define UART_C1_PE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7220 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
<> 144:ef7eb2e8f9f7 7221 #define UART_C1_ILT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7222 #define UART_C1_ILT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7223 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
<> 144:ef7eb2e8f9f7 7224 #define UART_C1_WAKE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7225 #define UART_C1_WAKE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7226 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
<> 144:ef7eb2e8f9f7 7227 #define UART_C1_M_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7228 #define UART_C1_M_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7229 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
<> 144:ef7eb2e8f9f7 7230 #define UART_C1_RSRC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7231 #define UART_C1_RSRC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7232 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
<> 144:ef7eb2e8f9f7 7233 #define UART_C1_LOOPS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7234 #define UART_C1_LOOPS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7235 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
<> 144:ef7eb2e8f9f7 7236
<> 144:ef7eb2e8f9f7 7237 /*! @name C2 - UART Control Register 2 */
<> 144:ef7eb2e8f9f7 7238 #define UART_C2_SBK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7239 #define UART_C2_SBK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7240 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
<> 144:ef7eb2e8f9f7 7241 #define UART_C2_RWU_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7242 #define UART_C2_RWU_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7243 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
<> 144:ef7eb2e8f9f7 7244 #define UART_C2_RE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7245 #define UART_C2_RE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7246 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
<> 144:ef7eb2e8f9f7 7247 #define UART_C2_TE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7248 #define UART_C2_TE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7249 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
<> 144:ef7eb2e8f9f7 7250 #define UART_C2_ILIE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7251 #define UART_C2_ILIE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7252 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
<> 144:ef7eb2e8f9f7 7253 #define UART_C2_RIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7254 #define UART_C2_RIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7255 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
<> 144:ef7eb2e8f9f7 7256 #define UART_C2_TCIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7257 #define UART_C2_TCIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7258 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
<> 144:ef7eb2e8f9f7 7259 #define UART_C2_TIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7260 #define UART_C2_TIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7261 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
<> 144:ef7eb2e8f9f7 7262
<> 144:ef7eb2e8f9f7 7263 /*! @name S1 - UART Status Register 1 */
<> 144:ef7eb2e8f9f7 7264 #define UART_S1_PF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7265 #define UART_S1_PF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7266 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
<> 144:ef7eb2e8f9f7 7267 #define UART_S1_FE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7268 #define UART_S1_FE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7269 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
<> 144:ef7eb2e8f9f7 7270 #define UART_S1_NF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7271 #define UART_S1_NF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7272 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
<> 144:ef7eb2e8f9f7 7273 #define UART_S1_OR_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7274 #define UART_S1_OR_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7275 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
<> 144:ef7eb2e8f9f7 7276 #define UART_S1_IDLE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7277 #define UART_S1_IDLE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7278 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
<> 144:ef7eb2e8f9f7 7279 #define UART_S1_RDRF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7280 #define UART_S1_RDRF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7281 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
<> 144:ef7eb2e8f9f7 7282 #define UART_S1_TC_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7283 #define UART_S1_TC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7284 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
<> 144:ef7eb2e8f9f7 7285 #define UART_S1_TDRE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7286 #define UART_S1_TDRE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7287 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
<> 144:ef7eb2e8f9f7 7288
<> 144:ef7eb2e8f9f7 7289 /*! @name S2 - UART Status Register 2 */
<> 144:ef7eb2e8f9f7 7290 #define UART_S2_RAF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7291 #define UART_S2_RAF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7292 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
<> 144:ef7eb2e8f9f7 7293 #define UART_S2_BRK13_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7294 #define UART_S2_BRK13_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7295 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
<> 144:ef7eb2e8f9f7 7296 #define UART_S2_RWUID_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7297 #define UART_S2_RWUID_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7298 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
<> 144:ef7eb2e8f9f7 7299 #define UART_S2_RXINV_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7300 #define UART_S2_RXINV_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7301 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
<> 144:ef7eb2e8f9f7 7302 #define UART_S2_MSBF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7303 #define UART_S2_MSBF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7304 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
<> 144:ef7eb2e8f9f7 7305 #define UART_S2_RXEDGIF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7306 #define UART_S2_RXEDGIF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7307 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
<> 144:ef7eb2e8f9f7 7308
<> 144:ef7eb2e8f9f7 7309 /*! @name C3 - UART Control Register 3 */
<> 144:ef7eb2e8f9f7 7310 #define UART_C3_PEIE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7311 #define UART_C3_PEIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7312 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
<> 144:ef7eb2e8f9f7 7313 #define UART_C3_FEIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7314 #define UART_C3_FEIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7315 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
<> 144:ef7eb2e8f9f7 7316 #define UART_C3_NEIE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7317 #define UART_C3_NEIE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7318 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
<> 144:ef7eb2e8f9f7 7319 #define UART_C3_ORIE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7320 #define UART_C3_ORIE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7321 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
<> 144:ef7eb2e8f9f7 7322 #define UART_C3_TXINV_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7323 #define UART_C3_TXINV_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7324 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
<> 144:ef7eb2e8f9f7 7325 #define UART_C3_TXDIR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7326 #define UART_C3_TXDIR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7327 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
<> 144:ef7eb2e8f9f7 7328 #define UART_C3_T8_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7329 #define UART_C3_T8_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7330 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
<> 144:ef7eb2e8f9f7 7331 #define UART_C3_R8_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7332 #define UART_C3_R8_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7333 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
<> 144:ef7eb2e8f9f7 7334
<> 144:ef7eb2e8f9f7 7335 /*! @name D - UART Data Register */
<> 144:ef7eb2e8f9f7 7336 #define UART_D_RT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7337 #define UART_D_RT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7338 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
<> 144:ef7eb2e8f9f7 7339
<> 144:ef7eb2e8f9f7 7340 /*! @name MA1 - UART Match Address Registers 1 */
<> 144:ef7eb2e8f9f7 7341 #define UART_MA1_MA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7342 #define UART_MA1_MA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7343 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
<> 144:ef7eb2e8f9f7 7344
<> 144:ef7eb2e8f9f7 7345 /*! @name MA2 - UART Match Address Registers 2 */
<> 144:ef7eb2e8f9f7 7346 #define UART_MA2_MA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7347 #define UART_MA2_MA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7348 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
<> 144:ef7eb2e8f9f7 7349
<> 144:ef7eb2e8f9f7 7350 /*! @name C4 - UART Control Register 4 */
<> 144:ef7eb2e8f9f7 7351 #define UART_C4_BRFA_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 7352 #define UART_C4_BRFA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7353 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
<> 144:ef7eb2e8f9f7 7354 #define UART_C4_M10_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7355 #define UART_C4_M10_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7356 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
<> 144:ef7eb2e8f9f7 7357 #define UART_C4_MAEN2_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7358 #define UART_C4_MAEN2_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7359 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
<> 144:ef7eb2e8f9f7 7360 #define UART_C4_MAEN1_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7361 #define UART_C4_MAEN1_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7362 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
<> 144:ef7eb2e8f9f7 7363
<> 144:ef7eb2e8f9f7 7364 /*! @name C5 - UART Control Register 5 */
<> 144:ef7eb2e8f9f7 7365 #define UART_C5_RDMAS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7366 #define UART_C5_RDMAS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7367 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
<> 144:ef7eb2e8f9f7 7368 #define UART_C5_TDMAS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7369 #define UART_C5_TDMAS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7370 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
<> 144:ef7eb2e8f9f7 7371
<> 144:ef7eb2e8f9f7 7372 /*! @name C7816 - UART 7816 Control Register */
<> 144:ef7eb2e8f9f7 7373 #define UART_C7816_ISO_7816E_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7374 #define UART_C7816_ISO_7816E_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7375 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
<> 144:ef7eb2e8f9f7 7376 #define UART_C7816_TTYPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7377 #define UART_C7816_TTYPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7378 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
<> 144:ef7eb2e8f9f7 7379 #define UART_C7816_INIT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7380 #define UART_C7816_INIT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7381 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
<> 144:ef7eb2e8f9f7 7382 #define UART_C7816_ANACK_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7383 #define UART_C7816_ANACK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7384 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
<> 144:ef7eb2e8f9f7 7385 #define UART_C7816_ONACK_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7386 #define UART_C7816_ONACK_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7387 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
<> 144:ef7eb2e8f9f7 7388
<> 144:ef7eb2e8f9f7 7389 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 7390 #define UART_IE7816_RXTE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7391 #define UART_IE7816_RXTE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7392 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
<> 144:ef7eb2e8f9f7 7393 #define UART_IE7816_TXTE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7394 #define UART_IE7816_TXTE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7395 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
<> 144:ef7eb2e8f9f7 7396 #define UART_IE7816_GTVE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7397 #define UART_IE7816_GTVE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7398 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
<> 144:ef7eb2e8f9f7 7399 #define UART_IE7816_ADTE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7400 #define UART_IE7816_ADTE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7401 #define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
<> 144:ef7eb2e8f9f7 7402 #define UART_IE7816_INITDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7403 #define UART_IE7816_INITDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7404 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
<> 144:ef7eb2e8f9f7 7405 #define UART_IE7816_BWTE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7406 #define UART_IE7816_BWTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7407 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
<> 144:ef7eb2e8f9f7 7408 #define UART_IE7816_CWTE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7409 #define UART_IE7816_CWTE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7410 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
<> 144:ef7eb2e8f9f7 7411 #define UART_IE7816_WTE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7412 #define UART_IE7816_WTE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7413 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
<> 144:ef7eb2e8f9f7 7414
<> 144:ef7eb2e8f9f7 7415 /*! @name IS7816 - UART 7816 Interrupt Status Register */
<> 144:ef7eb2e8f9f7 7416 #define UART_IS7816_RXT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7417 #define UART_IS7816_RXT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7418 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
<> 144:ef7eb2e8f9f7 7419 #define UART_IS7816_TXT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7420 #define UART_IS7816_TXT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7421 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
<> 144:ef7eb2e8f9f7 7422 #define UART_IS7816_GTV_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7423 #define UART_IS7816_GTV_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7424 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
<> 144:ef7eb2e8f9f7 7425 #define UART_IS7816_ADT_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7426 #define UART_IS7816_ADT_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7427 #define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
<> 144:ef7eb2e8f9f7 7428 #define UART_IS7816_INITD_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7429 #define UART_IS7816_INITD_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7430 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
<> 144:ef7eb2e8f9f7 7431 #define UART_IS7816_BWT_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7432 #define UART_IS7816_BWT_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7433 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
<> 144:ef7eb2e8f9f7 7434 #define UART_IS7816_CWT_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7435 #define UART_IS7816_CWT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7436 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
<> 144:ef7eb2e8f9f7 7437 #define UART_IS7816_WT_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7438 #define UART_IS7816_WT_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7439 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
<> 144:ef7eb2e8f9f7 7440
<> 144:ef7eb2e8f9f7 7441 /*! @name WP7816 - UART 7816 Wait Parameter Register */
<> 144:ef7eb2e8f9f7 7442 #define UART_WP7816_WTX_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7443 #define UART_WP7816_WTX_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7444 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
<> 144:ef7eb2e8f9f7 7445
<> 144:ef7eb2e8f9f7 7446 /*! @name WN7816 - UART 7816 Wait N Register */
<> 144:ef7eb2e8f9f7 7447 #define UART_WN7816_GTN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7448 #define UART_WN7816_GTN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7449 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
<> 144:ef7eb2e8f9f7 7450
<> 144:ef7eb2e8f9f7 7451 /*! @name WF7816 - UART 7816 Wait FD Register */
<> 144:ef7eb2e8f9f7 7452 #define UART_WF7816_GTFD_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7453 #define UART_WF7816_GTFD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7454 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
<> 144:ef7eb2e8f9f7 7455
<> 144:ef7eb2e8f9f7 7456 /*! @name ET7816 - UART 7816 Error Threshold Register */
<> 144:ef7eb2e8f9f7 7457 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
<> 144:ef7eb2e8f9f7 7458 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7459 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
<> 144:ef7eb2e8f9f7 7460 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 7461 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7462 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
<> 144:ef7eb2e8f9f7 7463
<> 144:ef7eb2e8f9f7 7464 /*! @name TL7816 - UART 7816 Transmit Length Register */
<> 144:ef7eb2e8f9f7 7465 #define UART_TL7816_TLEN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7466 #define UART_TL7816_TLEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7467 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
<> 144:ef7eb2e8f9f7 7468
<> 144:ef7eb2e8f9f7 7469 /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
<> 144:ef7eb2e8f9f7 7470 #define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7471 #define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7472 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
<> 144:ef7eb2e8f9f7 7473
<> 144:ef7eb2e8f9f7 7474 /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
<> 144:ef7eb2e8f9f7 7475 #define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7476 #define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7477 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
<> 144:ef7eb2e8f9f7 7478
<> 144:ef7eb2e8f9f7 7479 /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
<> 144:ef7eb2e8f9f7 7480 #define UART_WP7816A_T0_WI_H_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7481 #define UART_WP7816A_T0_WI_H_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7482 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
<> 144:ef7eb2e8f9f7 7483
<> 144:ef7eb2e8f9f7 7484 /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
<> 144:ef7eb2e8f9f7 7485 #define UART_WP7816B_T0_WI_L_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7486 #define UART_WP7816B_T0_WI_L_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7487 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
<> 144:ef7eb2e8f9f7 7488
<> 144:ef7eb2e8f9f7 7489 /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
<> 144:ef7eb2e8f9f7 7490 #define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7491 #define UART_WP7816A_T1_BWI_H_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7492 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
<> 144:ef7eb2e8f9f7 7493
<> 144:ef7eb2e8f9f7 7494 /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
<> 144:ef7eb2e8f9f7 7495 #define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7496 #define UART_WP7816B_T1_BWI_L_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7497 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
<> 144:ef7eb2e8f9f7 7498
<> 144:ef7eb2e8f9f7 7499 /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
<> 144:ef7eb2e8f9f7 7500 #define UART_WGP7816_T1_BGI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 7501 #define UART_WGP7816_T1_BGI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7502 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
<> 144:ef7eb2e8f9f7 7503 #define UART_WGP7816_T1_CWI1_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 7504 #define UART_WGP7816_T1_CWI1_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7505 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
<> 144:ef7eb2e8f9f7 7506
<> 144:ef7eb2e8f9f7 7507 /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
<> 144:ef7eb2e8f9f7 7508 #define UART_WP7816C_T1_CWI2_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 7509 #define UART_WP7816C_T1_CWI2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7510 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
<> 144:ef7eb2e8f9f7 7511
<> 144:ef7eb2e8f9f7 7512
<> 144:ef7eb2e8f9f7 7513 /*!
<> 144:ef7eb2e8f9f7 7514 * @}
<> 144:ef7eb2e8f9f7 7515 */ /* end of group UART_Register_Masks */
<> 144:ef7eb2e8f9f7 7516
<> 144:ef7eb2e8f9f7 7517
<> 144:ef7eb2e8f9f7 7518 /* UART - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7519 /** Peripheral UART2 base address */
<> 144:ef7eb2e8f9f7 7520 #define UART2_BASE (0x4006C000u)
<> 144:ef7eb2e8f9f7 7521 /** Peripheral UART2 base pointer */
<> 144:ef7eb2e8f9f7 7522 #define UART2 ((UART_Type *)UART2_BASE)
<> 144:ef7eb2e8f9f7 7523 /** Array initializer of UART peripheral base addresses */
<> 144:ef7eb2e8f9f7 7524 #define UART_BASE_ADDRS { 0u, 0u, UART2_BASE }
<> 144:ef7eb2e8f9f7 7525 /** Array initializer of UART peripheral base pointers */
<> 144:ef7eb2e8f9f7 7526 #define UART_BASE_PTRS { (UART_Type *)0u, (UART_Type *)0u, UART2 }
<> 144:ef7eb2e8f9f7 7527 /** Interrupt vectors for the UART peripheral type */
<> 144:ef7eb2e8f9f7 7528 #define UART_RX_TX_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
<> 144:ef7eb2e8f9f7 7529 #define UART_ERR_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
<> 144:ef7eb2e8f9f7 7530
<> 144:ef7eb2e8f9f7 7531 /*!
<> 144:ef7eb2e8f9f7 7532 * @}
<> 144:ef7eb2e8f9f7 7533 */ /* end of group UART_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7534
<> 144:ef7eb2e8f9f7 7535
<> 144:ef7eb2e8f9f7 7536 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7537 -- USB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7538 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7539
<> 144:ef7eb2e8f9f7 7540 /*!
<> 144:ef7eb2e8f9f7 7541 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7542 * @{
<> 144:ef7eb2e8f9f7 7543 */
<> 144:ef7eb2e8f9f7 7544
<> 144:ef7eb2e8f9f7 7545 /** USB - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 7546 typedef struct {
<> 144:ef7eb2e8f9f7 7547 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 7548 uint8_t RESERVED_0[3];
<> 144:ef7eb2e8f9f7 7549 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 7550 uint8_t RESERVED_1[3];
<> 144:ef7eb2e8f9f7 7551 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 7552 uint8_t RESERVED_2[3];
<> 144:ef7eb2e8f9f7 7553 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
<> 144:ef7eb2e8f9f7 7554 uint8_t RESERVED_3[15];
<> 144:ef7eb2e8f9f7 7555 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 7556 uint8_t RESERVED_4[99];
<> 144:ef7eb2e8f9f7 7557 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 7558 uint8_t RESERVED_5[3];
<> 144:ef7eb2e8f9f7 7559 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 7560 uint8_t RESERVED_6[3];
<> 144:ef7eb2e8f9f7 7561 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
<> 144:ef7eb2e8f9f7 7562 uint8_t RESERVED_7[3];
<> 144:ef7eb2e8f9f7 7563 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
<> 144:ef7eb2e8f9f7 7564 uint8_t RESERVED_8[3];
<> 144:ef7eb2e8f9f7 7565 __I uint8_t STAT; /**< Status register, offset: 0x90 */
<> 144:ef7eb2e8f9f7 7566 uint8_t RESERVED_9[3];
<> 144:ef7eb2e8f9f7 7567 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
<> 144:ef7eb2e8f9f7 7568 uint8_t RESERVED_10[3];
<> 144:ef7eb2e8f9f7 7569 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
<> 144:ef7eb2e8f9f7 7570 uint8_t RESERVED_11[3];
<> 144:ef7eb2e8f9f7 7571 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
<> 144:ef7eb2e8f9f7 7572 uint8_t RESERVED_12[3];
<> 144:ef7eb2e8f9f7 7573 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
<> 144:ef7eb2e8f9f7 7574 uint8_t RESERVED_13[3];
<> 144:ef7eb2e8f9f7 7575 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
<> 144:ef7eb2e8f9f7 7576 uint8_t RESERVED_14[11];
<> 144:ef7eb2e8f9f7 7577 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
<> 144:ef7eb2e8f9f7 7578 uint8_t RESERVED_15[3];
<> 144:ef7eb2e8f9f7 7579 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
<> 144:ef7eb2e8f9f7 7580 uint8_t RESERVED_16[11];
<> 144:ef7eb2e8f9f7 7581 struct { /* offset: 0xC0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 7582 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 7583 uint8_t RESERVED_0[3];
<> 144:ef7eb2e8f9f7 7584 } ENDPOINT[16];
<> 144:ef7eb2e8f9f7 7585 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 7586 uint8_t RESERVED_17[3];
<> 144:ef7eb2e8f9f7 7587 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
<> 144:ef7eb2e8f9f7 7588 uint8_t RESERVED_18[3];
<> 144:ef7eb2e8f9f7 7589 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
<> 144:ef7eb2e8f9f7 7590 uint8_t RESERVED_19[3];
<> 144:ef7eb2e8f9f7 7591 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
<> 144:ef7eb2e8f9f7 7592 uint8_t RESERVED_20[7];
<> 144:ef7eb2e8f9f7 7593 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
<> 144:ef7eb2e8f9f7 7594 uint8_t RESERVED_21[43];
<> 144:ef7eb2e8f9f7 7595 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
<> 144:ef7eb2e8f9f7 7596 uint8_t RESERVED_22[3];
<> 144:ef7eb2e8f9f7 7597 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
<> 144:ef7eb2e8f9f7 7598 uint8_t RESERVED_23[15];
<> 144:ef7eb2e8f9f7 7599 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
<> 144:ef7eb2e8f9f7 7600 uint8_t RESERVED_24[7];
<> 144:ef7eb2e8f9f7 7601 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
<> 144:ef7eb2e8f9f7 7602 } USB_Type;
<> 144:ef7eb2e8f9f7 7603
<> 144:ef7eb2e8f9f7 7604 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7605 -- USB Register Masks
<> 144:ef7eb2e8f9f7 7606 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7607
<> 144:ef7eb2e8f9f7 7608 /*!
<> 144:ef7eb2e8f9f7 7609 * @addtogroup USB_Register_Masks USB Register Masks
<> 144:ef7eb2e8f9f7 7610 * @{
<> 144:ef7eb2e8f9f7 7611 */
<> 144:ef7eb2e8f9f7 7612
<> 144:ef7eb2e8f9f7 7613 /*! @name PERID - Peripheral ID register */
<> 144:ef7eb2e8f9f7 7614 #define USB_PERID_ID_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 7615 #define USB_PERID_ID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7616 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
<> 144:ef7eb2e8f9f7 7617
<> 144:ef7eb2e8f9f7 7618 /*! @name IDCOMP - Peripheral ID Complement register */
<> 144:ef7eb2e8f9f7 7619 #define USB_IDCOMP_NID_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 7620 #define USB_IDCOMP_NID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7621 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
<> 144:ef7eb2e8f9f7 7622
<> 144:ef7eb2e8f9f7 7623 /*! @name REV - Peripheral Revision register */
<> 144:ef7eb2e8f9f7 7624 #define USB_REV_REV_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7625 #define USB_REV_REV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7626 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
<> 144:ef7eb2e8f9f7 7627
<> 144:ef7eb2e8f9f7 7628 /*! @name ADDINFO - Peripheral Additional Info register */
<> 144:ef7eb2e8f9f7 7629 #define USB_ADDINFO_IEHOST_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7630 #define USB_ADDINFO_IEHOST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7631 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
<> 144:ef7eb2e8f9f7 7632
<> 144:ef7eb2e8f9f7 7633 /*! @name OTGCTL - OTG Control register */
<> 144:ef7eb2e8f9f7 7634 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7635 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7636 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
<> 144:ef7eb2e8f9f7 7637
<> 144:ef7eb2e8f9f7 7638 /*! @name ISTAT - Interrupt Status register */
<> 144:ef7eb2e8f9f7 7639 #define USB_ISTAT_USBRST_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7640 #define USB_ISTAT_USBRST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7641 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
<> 144:ef7eb2e8f9f7 7642 #define USB_ISTAT_ERROR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7643 #define USB_ISTAT_ERROR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7644 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
<> 144:ef7eb2e8f9f7 7645 #define USB_ISTAT_SOFTOK_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7646 #define USB_ISTAT_SOFTOK_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7647 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
<> 144:ef7eb2e8f9f7 7648 #define USB_ISTAT_TOKDNE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7649 #define USB_ISTAT_TOKDNE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7650 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
<> 144:ef7eb2e8f9f7 7651 #define USB_ISTAT_SLEEP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7652 #define USB_ISTAT_SLEEP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7653 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
<> 144:ef7eb2e8f9f7 7654 #define USB_ISTAT_RESUME_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7655 #define USB_ISTAT_RESUME_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7656 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
<> 144:ef7eb2e8f9f7 7657 #define USB_ISTAT_STALL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7658 #define USB_ISTAT_STALL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7659 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
<> 144:ef7eb2e8f9f7 7660
<> 144:ef7eb2e8f9f7 7661 /*! @name INTEN - Interrupt Enable register */
<> 144:ef7eb2e8f9f7 7662 #define USB_INTEN_USBRSTEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7663 #define USB_INTEN_USBRSTEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7664 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
<> 144:ef7eb2e8f9f7 7665 #define USB_INTEN_ERROREN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7666 #define USB_INTEN_ERROREN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7667 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
<> 144:ef7eb2e8f9f7 7668 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7669 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7670 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
<> 144:ef7eb2e8f9f7 7671 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7672 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7673 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
<> 144:ef7eb2e8f9f7 7674 #define USB_INTEN_SLEEPEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7675 #define USB_INTEN_SLEEPEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7676 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
<> 144:ef7eb2e8f9f7 7677 #define USB_INTEN_RESUMEEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7678 #define USB_INTEN_RESUMEEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7679 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
<> 144:ef7eb2e8f9f7 7680 #define USB_INTEN_STALLEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7681 #define USB_INTEN_STALLEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7682 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
<> 144:ef7eb2e8f9f7 7683
<> 144:ef7eb2e8f9f7 7684 /*! @name ERRSTAT - Error Interrupt Status register */
<> 144:ef7eb2e8f9f7 7685 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7686 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7687 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
<> 144:ef7eb2e8f9f7 7688 #define USB_ERRSTAT_CRC5_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7689 #define USB_ERRSTAT_CRC5_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7690 #define USB_ERRSTAT_CRC5(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5_SHIFT)) & USB_ERRSTAT_CRC5_MASK)
<> 144:ef7eb2e8f9f7 7691 #define USB_ERRSTAT_CRC16_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7692 #define USB_ERRSTAT_CRC16_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7693 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
<> 144:ef7eb2e8f9f7 7694 #define USB_ERRSTAT_DFN8_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7695 #define USB_ERRSTAT_DFN8_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7696 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
<> 144:ef7eb2e8f9f7 7697 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7698 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7699 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
<> 144:ef7eb2e8f9f7 7700 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7701 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7702 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
<> 144:ef7eb2e8f9f7 7703 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7704 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7705 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
<> 144:ef7eb2e8f9f7 7706
<> 144:ef7eb2e8f9f7 7707 /*! @name ERREN - Error Interrupt Enable register */
<> 144:ef7eb2e8f9f7 7708 #define USB_ERREN_PIDERREN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7709 #define USB_ERREN_PIDERREN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7710 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
<> 144:ef7eb2e8f9f7 7711 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7712 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7713 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
<> 144:ef7eb2e8f9f7 7714 #define USB_ERREN_CRC16EN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7715 #define USB_ERREN_CRC16EN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7716 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
<> 144:ef7eb2e8f9f7 7717 #define USB_ERREN_DFN8EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7718 #define USB_ERREN_DFN8EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7719 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
<> 144:ef7eb2e8f9f7 7720 #define USB_ERREN_BTOERREN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7721 #define USB_ERREN_BTOERREN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7722 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
<> 144:ef7eb2e8f9f7 7723 #define USB_ERREN_DMAERREN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7724 #define USB_ERREN_DMAERREN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7725 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
<> 144:ef7eb2e8f9f7 7726 #define USB_ERREN_BTSERREN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7727 #define USB_ERREN_BTSERREN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7728 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
<> 144:ef7eb2e8f9f7 7729
<> 144:ef7eb2e8f9f7 7730 /*! @name STAT - Status register */
<> 144:ef7eb2e8f9f7 7731 #define USB_STAT_ODD_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7732 #define USB_STAT_ODD_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7733 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
<> 144:ef7eb2e8f9f7 7734 #define USB_STAT_TX_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7735 #define USB_STAT_TX_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7736 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
<> 144:ef7eb2e8f9f7 7737 #define USB_STAT_ENDP_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 7738 #define USB_STAT_ENDP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7739 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
<> 144:ef7eb2e8f9f7 7740
<> 144:ef7eb2e8f9f7 7741 /*! @name CTL - Control register */
<> 144:ef7eb2e8f9f7 7742 #define USB_CTL_USBENSOFEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7743 #define USB_CTL_USBENSOFEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7744 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
<> 144:ef7eb2e8f9f7 7745 #define USB_CTL_ODDRST_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7746 #define USB_CTL_ODDRST_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7747 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
<> 144:ef7eb2e8f9f7 7748 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7749 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7750 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
<> 144:ef7eb2e8f9f7 7751 #define USB_CTL_SE0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7752 #define USB_CTL_SE0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7753 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
<> 144:ef7eb2e8f9f7 7754 #define USB_CTL_JSTATE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7755 #define USB_CTL_JSTATE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7756 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
<> 144:ef7eb2e8f9f7 7757
<> 144:ef7eb2e8f9f7 7758 /*! @name ADDR - Address register */
<> 144:ef7eb2e8f9f7 7759 #define USB_ADDR_ADDR_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 7760 #define USB_ADDR_ADDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7761 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
<> 144:ef7eb2e8f9f7 7762
<> 144:ef7eb2e8f9f7 7763 /*! @name BDTPAGE1 - BDT Page register 1 */
<> 144:ef7eb2e8f9f7 7764 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 7765 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7766 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
<> 144:ef7eb2e8f9f7 7767
<> 144:ef7eb2e8f9f7 7768 /*! @name FRMNUML - Frame Number register Low */
<> 144:ef7eb2e8f9f7 7769 #define USB_FRMNUML_FRM_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7770 #define USB_FRMNUML_FRM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7771 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
<> 144:ef7eb2e8f9f7 7772
<> 144:ef7eb2e8f9f7 7773 /*! @name FRMNUMH - Frame Number register High */
<> 144:ef7eb2e8f9f7 7774 #define USB_FRMNUMH_FRM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 7775 #define USB_FRMNUMH_FRM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7776 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
<> 144:ef7eb2e8f9f7 7777
<> 144:ef7eb2e8f9f7 7778 /*! @name BDTPAGE2 - BDT Page Register 2 */
<> 144:ef7eb2e8f9f7 7779 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7780 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7781 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
<> 144:ef7eb2e8f9f7 7782
<> 144:ef7eb2e8f9f7 7783 /*! @name BDTPAGE3 - BDT Page Register 3 */
<> 144:ef7eb2e8f9f7 7784 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7785 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7786 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
<> 144:ef7eb2e8f9f7 7787
<> 144:ef7eb2e8f9f7 7788 /*! @name ENDPT - Endpoint Control register */
<> 144:ef7eb2e8f9f7 7789 #define USB_ENDPT_EPHSHK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7790 #define USB_ENDPT_EPHSHK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7791 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
<> 144:ef7eb2e8f9f7 7792 #define USB_ENDPT_EPSTALL_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7793 #define USB_ENDPT_EPSTALL_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7794 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
<> 144:ef7eb2e8f9f7 7795 #define USB_ENDPT_EPTXEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7796 #define USB_ENDPT_EPTXEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7797 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
<> 144:ef7eb2e8f9f7 7798 #define USB_ENDPT_EPRXEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7799 #define USB_ENDPT_EPRXEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7800 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
<> 144:ef7eb2e8f9f7 7801 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7802 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7803 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
<> 144:ef7eb2e8f9f7 7804
<> 144:ef7eb2e8f9f7 7805 /* The count of USB_ENDPT */
<> 144:ef7eb2e8f9f7 7806 #define USB_ENDPT_COUNT (16U)
<> 144:ef7eb2e8f9f7 7807
<> 144:ef7eb2e8f9f7 7808 /*! @name USBCTRL - USB Control register */
<> 144:ef7eb2e8f9f7 7809 #define USB_USBCTRL_PDE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7810 #define USB_USBCTRL_PDE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7811 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
<> 144:ef7eb2e8f9f7 7812 #define USB_USBCTRL_SUSP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7813 #define USB_USBCTRL_SUSP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7814 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
<> 144:ef7eb2e8f9f7 7815
<> 144:ef7eb2e8f9f7 7816 /*! @name OBSERVE - USB OTG Observe register */
<> 144:ef7eb2e8f9f7 7817 #define USB_OBSERVE_DMPD_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7818 #define USB_OBSERVE_DMPD_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7819 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
<> 144:ef7eb2e8f9f7 7820 #define USB_OBSERVE_DPPD_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7821 #define USB_OBSERVE_DPPD_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7822 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
<> 144:ef7eb2e8f9f7 7823 #define USB_OBSERVE_DPPU_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7824 #define USB_OBSERVE_DPPU_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7825 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
<> 144:ef7eb2e8f9f7 7826
<> 144:ef7eb2e8f9f7 7827 /*! @name CONTROL - USB OTG Control register */
<> 144:ef7eb2e8f9f7 7828 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7829 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7830 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
<> 144:ef7eb2e8f9f7 7831
<> 144:ef7eb2e8f9f7 7832 /*! @name USBTRC0 - USB Transceiver Control register 0 */
<> 144:ef7eb2e8f9f7 7833 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7834 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7835 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
<> 144:ef7eb2e8f9f7 7836 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7837 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7838 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
<> 144:ef7eb2e8f9f7 7839 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7840 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7841 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
<> 144:ef7eb2e8f9f7 7842 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7843 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7844 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
<> 144:ef7eb2e8f9f7 7845 #define USB_USBTRC0_USBRESET_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7846 #define USB_USBTRC0_USBRESET_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7847 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
<> 144:ef7eb2e8f9f7 7848
<> 144:ef7eb2e8f9f7 7849 /*! @name USBFRMADJUST - Frame Adjust Register */
<> 144:ef7eb2e8f9f7 7850 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7851 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7852 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
<> 144:ef7eb2e8f9f7 7853
<> 144:ef7eb2e8f9f7 7854 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
<> 144:ef7eb2e8f9f7 7855 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7856 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7857 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
<> 144:ef7eb2e8f9f7 7858 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7859 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7860 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
<> 144:ef7eb2e8f9f7 7861 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7862 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7863 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
<> 144:ef7eb2e8f9f7 7864
<> 144:ef7eb2e8f9f7 7865 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
<> 144:ef7eb2e8f9f7 7866 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7867 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7868 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
<> 144:ef7eb2e8f9f7 7869
<> 144:ef7eb2e8f9f7 7870 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
<> 144:ef7eb2e8f9f7 7871 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7872 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7873 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
<> 144:ef7eb2e8f9f7 7874
<> 144:ef7eb2e8f9f7 7875 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
<> 144:ef7eb2e8f9f7 7876 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7877 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7878 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
<> 144:ef7eb2e8f9f7 7879
<> 144:ef7eb2e8f9f7 7880
<> 144:ef7eb2e8f9f7 7881 /*!
<> 144:ef7eb2e8f9f7 7882 * @}
<> 144:ef7eb2e8f9f7 7883 */ /* end of group USB_Register_Masks */
<> 144:ef7eb2e8f9f7 7884
<> 144:ef7eb2e8f9f7 7885
<> 144:ef7eb2e8f9f7 7886 /* USB - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7887 /** Peripheral USB0 base address */
<> 144:ef7eb2e8f9f7 7888 #define USB0_BASE (0x40072000u)
<> 144:ef7eb2e8f9f7 7889 /** Peripheral USB0 base pointer */
<> 144:ef7eb2e8f9f7 7890 #define USB0 ((USB_Type *)USB0_BASE)
<> 144:ef7eb2e8f9f7 7891 /** Array initializer of USB peripheral base addresses */
<> 144:ef7eb2e8f9f7 7892 #define USB_BASE_ADDRS { USB0_BASE }
<> 144:ef7eb2e8f9f7 7893 /** Array initializer of USB peripheral base pointers */
<> 144:ef7eb2e8f9f7 7894 #define USB_BASE_PTRS { USB0 }
<> 144:ef7eb2e8f9f7 7895 /** Interrupt vectors for the USB peripheral type */
<> 144:ef7eb2e8f9f7 7896 #define USB_IRQS { USB0_IRQn }
<> 144:ef7eb2e8f9f7 7897
<> 144:ef7eb2e8f9f7 7898 /*!
<> 144:ef7eb2e8f9f7 7899 * @}
<> 144:ef7eb2e8f9f7 7900 */ /* end of group USB_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7901
<> 144:ef7eb2e8f9f7 7902
<> 144:ef7eb2e8f9f7 7903 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7904 -- VREF Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7905 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7906
<> 144:ef7eb2e8f9f7 7907 /*!
<> 144:ef7eb2e8f9f7 7908 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7909 * @{
<> 144:ef7eb2e8f9f7 7910 */
<> 144:ef7eb2e8f9f7 7911
<> 144:ef7eb2e8f9f7 7912 /** VREF - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 7913 typedef struct {
<> 144:ef7eb2e8f9f7 7914 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 7915 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 7916 } VREF_Type;
<> 144:ef7eb2e8f9f7 7917
<> 144:ef7eb2e8f9f7 7918 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7919 -- VREF Register Masks
<> 144:ef7eb2e8f9f7 7920 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7921
<> 144:ef7eb2e8f9f7 7922 /*!
<> 144:ef7eb2e8f9f7 7923 * @addtogroup VREF_Register_Masks VREF Register Masks
<> 144:ef7eb2e8f9f7 7924 * @{
<> 144:ef7eb2e8f9f7 7925 */
<> 144:ef7eb2e8f9f7 7926
<> 144:ef7eb2e8f9f7 7927 /*! @name TRM - VREF Trim Register */
<> 144:ef7eb2e8f9f7 7928 #define VREF_TRM_TRIM_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 7929 #define VREF_TRM_TRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7930 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
<> 144:ef7eb2e8f9f7 7931 #define VREF_TRM_CHOPEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7932 #define VREF_TRM_CHOPEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7933 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
<> 144:ef7eb2e8f9f7 7934
<> 144:ef7eb2e8f9f7 7935 /*! @name SC - VREF Status and Control Register */
<> 144:ef7eb2e8f9f7 7936 #define VREF_SC_MODE_LV_MASK (0x3U)
<> 144:ef7eb2e8f9f7 7937 #define VREF_SC_MODE_LV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7938 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
<> 144:ef7eb2e8f9f7 7939 #define VREF_SC_VREFST_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7940 #define VREF_SC_VREFST_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7941 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
<> 144:ef7eb2e8f9f7 7942 #define VREF_SC_ICOMPEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7943 #define VREF_SC_ICOMPEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7944 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
<> 144:ef7eb2e8f9f7 7945 #define VREF_SC_REGEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7946 #define VREF_SC_REGEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7947 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
<> 144:ef7eb2e8f9f7 7948 #define VREF_SC_VREFEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7949 #define VREF_SC_VREFEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7950 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
<> 144:ef7eb2e8f9f7 7951
<> 144:ef7eb2e8f9f7 7952
<> 144:ef7eb2e8f9f7 7953 /*!
<> 144:ef7eb2e8f9f7 7954 * @}
<> 144:ef7eb2e8f9f7 7955 */ /* end of group VREF_Register_Masks */
<> 144:ef7eb2e8f9f7 7956
<> 144:ef7eb2e8f9f7 7957
<> 144:ef7eb2e8f9f7 7958 /* VREF - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7959 /** Peripheral VREF base address */
<> 144:ef7eb2e8f9f7 7960 #define VREF_BASE (0x40074000u)
<> 144:ef7eb2e8f9f7 7961 /** Peripheral VREF base pointer */
<> 144:ef7eb2e8f9f7 7962 #define VREF ((VREF_Type *)VREF_BASE)
<> 144:ef7eb2e8f9f7 7963 /** Array initializer of VREF peripheral base addresses */
<> 144:ef7eb2e8f9f7 7964 #define VREF_BASE_ADDRS { VREF_BASE }
<> 144:ef7eb2e8f9f7 7965 /** Array initializer of VREF peripheral base pointers */
<> 144:ef7eb2e8f9f7 7966 #define VREF_BASE_PTRS { VREF }
<> 144:ef7eb2e8f9f7 7967
<> 144:ef7eb2e8f9f7 7968 /*!
<> 144:ef7eb2e8f9f7 7969 * @}
<> 144:ef7eb2e8f9f7 7970 */ /* end of group VREF_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7971
<> 144:ef7eb2e8f9f7 7972
<> 144:ef7eb2e8f9f7 7973 /*
<> 144:ef7eb2e8f9f7 7974 ** End of section using anonymous unions
<> 144:ef7eb2e8f9f7 7975 */
<> 144:ef7eb2e8f9f7 7976
<> 144:ef7eb2e8f9f7 7977 #if defined(__ARMCC_VERSION)
<> 144:ef7eb2e8f9f7 7978 #pragma pop
<> 144:ef7eb2e8f9f7 7979 #elif defined(__CWCC__)
<> 144:ef7eb2e8f9f7 7980 #pragma pop
<> 144:ef7eb2e8f9f7 7981 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 7982 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 7983 #elif defined(__IAR_SYSTEMS_ICC__)
<> 144:ef7eb2e8f9f7 7984 #pragma language=default
<> 144:ef7eb2e8f9f7 7985 #else
<> 144:ef7eb2e8f9f7 7986 #error Not supported compiler type
<> 144:ef7eb2e8f9f7 7987 #endif
<> 144:ef7eb2e8f9f7 7988
<> 144:ef7eb2e8f9f7 7989 /*!
<> 144:ef7eb2e8f9f7 7990 * @}
<> 144:ef7eb2e8f9f7 7991 */ /* end of group Peripheral_access_layer */
<> 144:ef7eb2e8f9f7 7992
<> 144:ef7eb2e8f9f7 7993
<> 144:ef7eb2e8f9f7 7994 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7995 -- SDK Compatibility
<> 144:ef7eb2e8f9f7 7996 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7997
<> 144:ef7eb2e8f9f7 7998 /*!
<> 144:ef7eb2e8f9f7 7999 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
<> 144:ef7eb2e8f9f7 8000 * @{
<> 144:ef7eb2e8f9f7 8001 */
<> 144:ef7eb2e8f9f7 8002
<> 144:ef7eb2e8f9f7 8003 #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
<> 144:ef7eb2e8f9f7 8004 #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
<> 144:ef7eb2e8f9f7 8005 #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
<> 144:ef7eb2e8f9f7 8006 #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
<> 144:ef7eb2e8f9f7 8007 #define I2C_S1_SRW_MASK I2C_S_SRW_MASK
<> 144:ef7eb2e8f9f7 8008 #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
<> 144:ef7eb2e8f9f7 8009 #define I2C_S1_RAM_MASK I2C_S_RAM_MASK
<> 144:ef7eb2e8f9f7 8010 #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
<> 144:ef7eb2e8f9f7 8011 #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
<> 144:ef7eb2e8f9f7 8012 #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
<> 144:ef7eb2e8f9f7 8013 #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
<> 144:ef7eb2e8f9f7 8014 #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
<> 144:ef7eb2e8f9f7 8015 #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
<> 144:ef7eb2e8f9f7 8016 #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
<> 144:ef7eb2e8f9f7 8017 #define I2C_S1_TCF_MASK I2C_S_TCF_MASK
<> 144:ef7eb2e8f9f7 8018 #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
<> 144:ef7eb2e8f9f7 8019 #define I2C_S1_REG(base) I2C_S_REG(base)
<> 144:ef7eb2e8f9f7 8020 #define I2C0_S1 I2C0_S
<> 144:ef7eb2e8f9f7 8021 #define I2C1_S1 I2C1_S
<> 144:ef7eb2e8f9f7 8022 #define PTA_BASE GPIOA_BASE
<> 144:ef7eb2e8f9f7 8023 #define PTB_BASE GPIOB_BASE
<> 144:ef7eb2e8f9f7 8024 #define PTC_BASE GPIOC_BASE
<> 144:ef7eb2e8f9f7 8025 #define PTD_BASE GPIOD_BASE
<> 144:ef7eb2e8f9f7 8026 #define PTE_BASE GPIOE_BASE
<> 144:ef7eb2e8f9f7 8027 #define PTA GPIOA
<> 144:ef7eb2e8f9f7 8028 #define PTB GPIOB
<> 144:ef7eb2e8f9f7 8029 #define PTC GPIOC
<> 144:ef7eb2e8f9f7 8030 #define PTD GPIOD
<> 144:ef7eb2e8f9f7 8031 #define PTE GPIOE
<> 144:ef7eb2e8f9f7 8032 #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
<> 144:ef7eb2e8f9f7 8033 #define UART0_FLEXIO_IRQHandler UART2_FLEXIO_IRQHandler
<> 144:ef7eb2e8f9f7 8034 #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
<> 144:ef7eb2e8f9f7 8035 #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
<> 144:ef7eb2e8f9f7 8036 #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
<> 144:ef7eb2e8f9f7 8037 #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
<> 144:ef7eb2e8f9f7 8038 #define UART0_BASE UART2_BASE
<> 144:ef7eb2e8f9f7 8039 #define UART0_BDH UART2_BDH
<> 144:ef7eb2e8f9f7 8040 #define UART0_BDL UART2_BDL
<> 144:ef7eb2e8f9f7 8041 #define UART0_C1 UART2_C1
<> 144:ef7eb2e8f9f7 8042 #define UART0_C2 UART2_C2
<> 144:ef7eb2e8f9f7 8043 #define UART0_S1 UART2_S1
<> 144:ef7eb2e8f9f7 8044 #define UART0_S2 UART2_S2
<> 144:ef7eb2e8f9f7 8045 #define UART0_C3 UART2_C3
<> 144:ef7eb2e8f9f7 8046 #define UART0_D UART2_D
<> 144:ef7eb2e8f9f7 8047 #define UART0_MA1 UART2_MA1
<> 144:ef7eb2e8f9f7 8048 #define UART0_MA2 UART2_MA2
<> 144:ef7eb2e8f9f7 8049 #define UART0_C4 UART2_C4
<> 144:ef7eb2e8f9f7 8050 #define UART0_C5 UART2_C5
<> 144:ef7eb2e8f9f7 8051 #define UART0_ED UART2_ED
<> 144:ef7eb2e8f9f7 8052 #define UART0_MODEM UART2_MODEM
<> 144:ef7eb2e8f9f7 8053 #define UART0_IR UART2_IR
<> 144:ef7eb2e8f9f7 8054 #define UART0_PFIFO UART2_PFIFO
<> 144:ef7eb2e8f9f7 8055 #define UART0_CFIFO UART2_CFIFO
<> 144:ef7eb2e8f9f7 8056 #define UART0_SFIFO UART2_SFIFO
<> 144:ef7eb2e8f9f7 8057 #define UART0_TWFIFO UART2_TWFIFO
<> 144:ef7eb2e8f9f7 8058 #define UART0_TCFIFO UART2_TCFIFO
<> 144:ef7eb2e8f9f7 8059 #define UART0_RWFIFO UART2_RWFIFO
<> 144:ef7eb2e8f9f7 8060 #define UART0_RCFIFO UART2_RCFIFO
<> 144:ef7eb2e8f9f7 8061 #define UART0_C7816 UART2_C7816
<> 144:ef7eb2e8f9f7 8062 #define UART0_IE7816 UART2_IE7816
<> 144:ef7eb2e8f9f7 8063 #define UART0_IS7816 UART2_IS7816
<> 144:ef7eb2e8f9f7 8064 #define UART0_WP7816 UART2_WP7816
<> 144:ef7eb2e8f9f7 8065 #define UART0_WN7816 UART2_WN7816
<> 144:ef7eb2e8f9f7 8066 #define UART0_WF7816 UART2_WF7816
<> 144:ef7eb2e8f9f7 8067 #define UART0_ET7816 UART2_ET7816
<> 144:ef7eb2e8f9f7 8068 #define UART0_TL7816 UART2_TL7816
<> 144:ef7eb2e8f9f7 8069 #define UART0_AP7816A_T0 UART2_AP7816A_T0
<> 144:ef7eb2e8f9f7 8070 #define UART0_AP7816B_T0 UART2_AP7816B_T0
<> 144:ef7eb2e8f9f7 8071 #define UART0_WP7816A_T0 UART2_WP7816A_T0
<> 144:ef7eb2e8f9f7 8072 #define UART0_WP7816A_T1 UART2_WP7816A_T1
<> 144:ef7eb2e8f9f7 8073 #define UART0_WP7816B_T0 UART2_WP7816B_T0
<> 144:ef7eb2e8f9f7 8074 #define UART0_WP7816B_T1 UART2_WP7816B_T1
<> 144:ef7eb2e8f9f7 8075 #define UART0_WGP7816_T1 UART2_WGP7816_T1
<> 144:ef7eb2e8f9f7 8076 #define UART0_WP7816C_T1 UART2_WP7816C_T1
<> 144:ef7eb2e8f9f7 8077 #define I2S0_MDR This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8078 #define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8079 #define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8080 #define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8081 #define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8082 #define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8083 #define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8084 #define I2S_MDR_REG(base) This_symb_has_been_deprecated
<> 144:ef7eb2e8f9f7 8085 #define CTL0 OTGCTL
<> 144:ef7eb2e8f9f7 8086 #define USB0_CTL0 USB0_OTGCTL
<> 144:ef7eb2e8f9f7 8087 #define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
<> 144:ef7eb2e8f9f7 8088 #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
<> 144:ef7eb2e8f9f7 8089 #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
<> 144:ef7eb2e8f9f7 8090 #define CTL1 CTL
<> 144:ef7eb2e8f9f7 8091 #define USB0_CTL1 USB0_CTL
<> 144:ef7eb2e8f9f7 8092 #define USB_CTL1_REG(base) USB_CTL_REG(base)
<> 144:ef7eb2e8f9f7 8093 #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
<> 144:ef7eb2e8f9f7 8094 #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
<> 144:ef7eb2e8f9f7 8095 #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
<> 144:ef7eb2e8f9f7 8096 #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
<> 144:ef7eb2e8f9f7 8097 #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
<> 144:ef7eb2e8f9f7 8098 #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
<> 144:ef7eb2e8f9f7 8099 #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
<> 144:ef7eb2e8f9f7 8100 #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
<> 144:ef7eb2e8f9f7 8101 #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
<> 144:ef7eb2e8f9f7 8102 #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
<> 144:ef7eb2e8f9f7 8103 #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
<> 144:ef7eb2e8f9f7 8104 #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
<> 144:ef7eb2e8f9f7 8105
<> 144:ef7eb2e8f9f7 8106 /*!
<> 144:ef7eb2e8f9f7 8107 * @}
<> 144:ef7eb2e8f9f7 8108 */ /* end of group SDK_Compatibility_Symbols */
<> 144:ef7eb2e8f9f7 8109
<> 144:ef7eb2e8f9f7 8110
<> 144:ef7eb2e8f9f7 8111 #endif /* _MKL43Z4_H_ */
<> 144:ef7eb2e8f9f7 8112