Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K66F/system_MK66F18.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MK66FN2M0VLQ18
<> 144:ef7eb2e8f9f7 4 ** MK66FN2M0VMD18
<> 144:ef7eb2e8f9f7 5 ** MK66FX1M0VLQ18
<> 144:ef7eb2e8f9f7 6 ** MK66FX1M0VMD18
<> 144:ef7eb2e8f9f7 7 **
<> 144:ef7eb2e8f9f7 8 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 9 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 10 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 11 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 12 **
<> 144:ef7eb2e8f9f7 13 ** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
<> 144:ef7eb2e8f9f7 14 ** Version: rev. 3.0, 2015-03-25
<> 144:ef7eb2e8f9f7 15 ** Build: b151216
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Abstract:
<> 144:ef7eb2e8f9f7 18 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 19 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 20 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 21 **
<> 144:ef7eb2e8f9f7 22 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 23 ** All rights reserved.
<> 144:ef7eb2e8f9f7 24 **
<> 144:ef7eb2e8f9f7 25 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 26 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 27 **
<> 144:ef7eb2e8f9f7 28 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 29 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 30 **
<> 144:ef7eb2e8f9f7 31 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 32 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 33 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 34 **
<> 144:ef7eb2e8f9f7 35 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 36 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 37 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 38 **
<> 144:ef7eb2e8f9f7 39 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 40 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 41 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 42 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 43 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 44 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 45 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 46 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 47 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 48 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 49 **
<> 144:ef7eb2e8f9f7 50 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 51 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 52 **
<> 144:ef7eb2e8f9f7 53 ** Revisions:
<> 144:ef7eb2e8f9f7 54 ** - rev. 1.0 (2013-09-02)
<> 144:ef7eb2e8f9f7 55 ** Initial version.
<> 144:ef7eb2e8f9f7 56 ** - rev. 2.0 (2014-02-17)
<> 144:ef7eb2e8f9f7 57 ** Register accessor macros added to the memory map.
<> 144:ef7eb2e8f9f7 58 ** Symbols for Processor Expert memory map compatibility added to the memory map.
<> 144:ef7eb2e8f9f7 59 ** Startup file for gcc has been updated according to CMSIS 3.2.
<> 144:ef7eb2e8f9f7 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
<> 144:ef7eb2e8f9f7 61 ** Update according to reference manual rev. 2
<> 144:ef7eb2e8f9f7 62 ** - rev. 2.1 (2014-04-16)
<> 144:ef7eb2e8f9f7 63 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
<> 144:ef7eb2e8f9f7 64 ** - rev. 2.2 (2014-10-14)
<> 144:ef7eb2e8f9f7 65 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
<> 144:ef7eb2e8f9f7 66 ** - rev. 2.3 (2014-11-20)
<> 144:ef7eb2e8f9f7 67 ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
<> 144:ef7eb2e8f9f7 68 ** Update of SystemInit() to use 16MHz external crystal.
<> 144:ef7eb2e8f9f7 69 ** - rev. 2.4 (2015-02-19)
<> 144:ef7eb2e8f9f7 70 ** Renamed interrupt vector LLW to LLWU.
<> 144:ef7eb2e8f9f7 71 ** - rev. 3.0 (2015-03-25)
<> 144:ef7eb2e8f9f7 72 ** Registers updated according to the reference manual revision 1, March 2015
<> 144:ef7eb2e8f9f7 73 **
<> 144:ef7eb2e8f9f7 74 ** ###################################################################
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /*!
<> 144:ef7eb2e8f9f7 78 * @file MK66F18
<> 144:ef7eb2e8f9f7 79 * @version 3.0
<> 144:ef7eb2e8f9f7 80 * @date 2015-03-25
<> 144:ef7eb2e8f9f7 81 * @brief Device specific configuration file for MK66F18 (implementation file)
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 84 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 85 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #include <stdint.h>
<> 144:ef7eb2e8f9f7 89 #include "fsl_device_registers.h"
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 94 -- Core clock
<> 144:ef7eb2e8f9f7 95 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 100 -- SystemInit()
<> 144:ef7eb2e8f9f7 101 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 104 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
<> 144:ef7eb2e8f9f7 105 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
<> 144:ef7eb2e8f9f7 106 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
<> 144:ef7eb2e8f9f7 107 /* Watchdog disable */
<> 144:ef7eb2e8f9f7 108 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 109 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
<> 144:ef7eb2e8f9f7 110 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
<> 144:ef7eb2e8f9f7 111 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
<> 144:ef7eb2e8f9f7 112 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
<> 144:ef7eb2e8f9f7 113 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
<> 144:ef7eb2e8f9f7 114 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
<> 144:ef7eb2e8f9f7 115 WDOG_STCTRLH_WAITEN_MASK |
<> 144:ef7eb2e8f9f7 116 WDOG_STCTRLH_STOPEN_MASK |
<> 144:ef7eb2e8f9f7 117 WDOG_STCTRLH_ALLOWUPDATE_MASK |
<> 144:ef7eb2e8f9f7 118 WDOG_STCTRLH_CLKSRC_MASK |
<> 144:ef7eb2e8f9f7 119 0x0100U;
<> 144:ef7eb2e8f9f7 120 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 125 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 126 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 129 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 130 uint16_t Divider;
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 133 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 134 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 135 /* FLL is selected */
<> 144:ef7eb2e8f9f7 136 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 137 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 138 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
<> 144:ef7eb2e8f9f7 139 case 0x00U:
<> 144:ef7eb2e8f9f7 140 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 141 break;
<> 144:ef7eb2e8f9f7 142 case 0x01U:
<> 144:ef7eb2e8f9f7 143 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 144 break;
<> 144:ef7eb2e8f9f7 145 case 0x02U:
<> 144:ef7eb2e8f9f7 146 default:
<> 144:ef7eb2e8f9f7 147 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 148 break;
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
<> 144:ef7eb2e8f9f7 151 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
<> 144:ef7eb2e8f9f7 152 case 0x38U:
<> 144:ef7eb2e8f9f7 153 Divider = 1536U;
<> 144:ef7eb2e8f9f7 154 break;
<> 144:ef7eb2e8f9f7 155 case 0x30U:
<> 144:ef7eb2e8f9f7 156 Divider = 1280U;
<> 144:ef7eb2e8f9f7 157 break;
<> 144:ef7eb2e8f9f7 158 default:
<> 144:ef7eb2e8f9f7 159 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 160 break;
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
<> 144:ef7eb2e8f9f7 163 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 166 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 167 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 168 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 169 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 170 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 171 case 0x00U:
<> 144:ef7eb2e8f9f7 172 MCGOUTClock *= 640U;
<> 144:ef7eb2e8f9f7 173 break;
<> 144:ef7eb2e8f9f7 174 case 0x20U:
<> 144:ef7eb2e8f9f7 175 MCGOUTClock *= 1280U;
<> 144:ef7eb2e8f9f7 176 break;
<> 144:ef7eb2e8f9f7 177 case 0x40U:
<> 144:ef7eb2e8f9f7 178 MCGOUTClock *= 1920U;
<> 144:ef7eb2e8f9f7 179 break;
<> 144:ef7eb2e8f9f7 180 case 0x60U:
<> 144:ef7eb2e8f9f7 181 MCGOUTClock *= 2560U;
<> 144:ef7eb2e8f9f7 182 break;
<> 144:ef7eb2e8f9f7 183 case 0x80U:
<> 144:ef7eb2e8f9f7 184 MCGOUTClock *= 732U;
<> 144:ef7eb2e8f9f7 185 break;
<> 144:ef7eb2e8f9f7 186 case 0xA0U:
<> 144:ef7eb2e8f9f7 187 MCGOUTClock *= 1464U;
<> 144:ef7eb2e8f9f7 188 break;
<> 144:ef7eb2e8f9f7 189 case 0xC0U:
<> 144:ef7eb2e8f9f7 190 MCGOUTClock *= 2197U;
<> 144:ef7eb2e8f9f7 191 break;
<> 144:ef7eb2e8f9f7 192 case 0xE0U:
<> 144:ef7eb2e8f9f7 193 MCGOUTClock *= 2929U;
<> 144:ef7eb2e8f9f7 194 break;
<> 144:ef7eb2e8f9f7 195 default:
<> 144:ef7eb2e8f9f7 196 break;
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 199 if ((MCG->C11 & MCG_C11_PLLCS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 200 /* PLL is selected */
<> 144:ef7eb2e8f9f7 201 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
<> 144:ef7eb2e8f9f7 202 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 203 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
<> 144:ef7eb2e8f9f7 204 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
<> 144:ef7eb2e8f9f7 205 MCGOUTClock /= 2; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 206 } else {
<> 144:ef7eb2e8f9f7 207 /* External PLL is selected */
<> 144:ef7eb2e8f9f7 208 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 209 MCGOUTClock = CPU_XTAL_CLK_HZ;
<> 144:ef7eb2e8f9f7 210 } else {
<> 144:ef7eb2e8f9f7 211 Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4);
<> 144:ef7eb2e8f9f7 212 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) {
<> 144:ef7eb2e8f9f7 213 Divider *= 0x04U;
<> 144:ef7eb2e8f9f7 214 } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
<> 144:ef7eb2e8f9f7 215 Divider *= 0x02U;
<> 144:ef7eb2e8f9f7 216 } else {
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218 MCGOUTClock = (uint32_t)(480000000 / Divider);
<> 144:ef7eb2e8f9f7 219 MCGOUTClock *= 18;
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 223 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
<> 144:ef7eb2e8f9f7 224 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 225 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 226 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 227 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 228 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 229 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 230 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 231 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
<> 144:ef7eb2e8f9f7 232 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 233 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
<> 144:ef7eb2e8f9f7 234 case 0x00U:
<> 144:ef7eb2e8f9f7 235 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 236 break;
<> 144:ef7eb2e8f9f7 237 case 0x01U:
<> 144:ef7eb2e8f9f7 238 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 239 break;
<> 144:ef7eb2e8f9f7 240 case 0x02U:
<> 144:ef7eb2e8f9f7 241 default:
<> 144:ef7eb2e8f9f7 242 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 243 break;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 246 /* Reserved value */
<> 144:ef7eb2e8f9f7 247 return;
<> 144:ef7eb2e8f9f7 248 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 249 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 250 }