Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K66F/MK66F18.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MK66FN2M0VLQ18
<> 144:ef7eb2e8f9f7 4 ** MK66FN2M0VMD18
<> 144:ef7eb2e8f9f7 5 ** MK66FX1M0VLQ18
<> 144:ef7eb2e8f9f7 6 ** MK66FX1M0VMD18
<> 144:ef7eb2e8f9f7 7 **
<> 144:ef7eb2e8f9f7 8 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 9 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 10 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 11 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 12 **
<> 144:ef7eb2e8f9f7 13 ** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
<> 144:ef7eb2e8f9f7 14 ** Version: rev. 3.0, 2015-03-25
<> 144:ef7eb2e8f9f7 15 ** Build: b151218
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Abstract:
<> 144:ef7eb2e8f9f7 18 ** CMSIS Peripheral Access Layer for MK66F18
<> 144:ef7eb2e8f9f7 19 **
<> 144:ef7eb2e8f9f7 20 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 21 ** All rights reserved.
<> 144:ef7eb2e8f9f7 22 **
<> 144:ef7eb2e8f9f7 23 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 24 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 27 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 28 **
<> 144:ef7eb2e8f9f7 29 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 30 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 31 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 32 **
<> 144:ef7eb2e8f9f7 33 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 34 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 35 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 36 **
<> 144:ef7eb2e8f9f7 37 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 38 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 39 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 40 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 41 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 42 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 43 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 44 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 45 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 46 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 47 **
<> 144:ef7eb2e8f9f7 48 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 49 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 50 **
<> 144:ef7eb2e8f9f7 51 ** Revisions:
<> 144:ef7eb2e8f9f7 52 ** - rev. 1.0 (2013-09-02)
<> 144:ef7eb2e8f9f7 53 ** Initial version.
<> 144:ef7eb2e8f9f7 54 ** - rev. 2.0 (2014-02-17)
<> 144:ef7eb2e8f9f7 55 ** Register accessor macros added to the memory map.
<> 144:ef7eb2e8f9f7 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
<> 144:ef7eb2e8f9f7 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
<> 144:ef7eb2e8f9f7 58 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
<> 144:ef7eb2e8f9f7 59 ** Update according to reference manual rev. 2
<> 144:ef7eb2e8f9f7 60 ** - rev. 2.1 (2014-04-16)
<> 144:ef7eb2e8f9f7 61 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
<> 144:ef7eb2e8f9f7 62 ** - rev. 2.2 (2014-10-14)
<> 144:ef7eb2e8f9f7 63 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
<> 144:ef7eb2e8f9f7 64 ** - rev. 2.3 (2014-11-20)
<> 144:ef7eb2e8f9f7 65 ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
<> 144:ef7eb2e8f9f7 66 ** Update of SystemInit() to use 16MHz external crystal.
<> 144:ef7eb2e8f9f7 67 ** - rev. 2.4 (2015-02-19)
<> 144:ef7eb2e8f9f7 68 ** Renamed interrupt vector LLW to LLWU.
<> 144:ef7eb2e8f9f7 69 ** - rev. 3.0 (2015-03-25)
<> 144:ef7eb2e8f9f7 70 ** Registers updated according to the reference manual revision 1, March 2015
<> 144:ef7eb2e8f9f7 71 **
<> 144:ef7eb2e8f9f7 72 ** ###################################################################
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /*!
<> 144:ef7eb2e8f9f7 76 * @file MK66F18.h
<> 144:ef7eb2e8f9f7 77 * @version 3.0
<> 144:ef7eb2e8f9f7 78 * @date 2015-03-25
<> 144:ef7eb2e8f9f7 79 * @brief CMSIS Peripheral Access Layer for MK66F18
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * CMSIS Peripheral Access Layer for MK66F18
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #ifndef _MK66F18_H_
<> 144:ef7eb2e8f9f7 85 #define _MK66F18_H_ /**< Symbol preventing repeated inclusion */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** Memory map major version (memory maps with equal major version number are
<> 144:ef7eb2e8f9f7 88 * compatible) */
<> 144:ef7eb2e8f9f7 89 #define MCU_MEM_MAP_VERSION 0x0300U
<> 144:ef7eb2e8f9f7 90 /** Memory map minor version */
<> 144:ef7eb2e8f9f7 91 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief Macro to calculate address of an aliased word in the peripheral
<> 144:ef7eb2e8f9f7 95 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
<> 144:ef7eb2e8f9f7 96 * 0x400FFFFF).
<> 144:ef7eb2e8f9f7 97 * @param Reg Register to access.
<> 144:ef7eb2e8f9f7 98 * @param Bit Bit number to access.
<> 144:ef7eb2e8f9f7 99 * @return Address of the aliased word in the peripheral bitband area.
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @brief Macro to access a single bit of a peripheral register (bit band region
<> 144:ef7eb2e8f9f7 104 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
<> 144:ef7eb2e8f9f7 105 * be used for peripherals with 32bit access allowed.
<> 144:ef7eb2e8f9f7 106 * @param Reg Register to access.
<> 144:ef7eb2e8f9f7 107 * @param Bit Bit number to access.
<> 144:ef7eb2e8f9f7 108 * @return Value of the targeted bit in the bit band region.
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
<> 144:ef7eb2e8f9f7 111 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
<> 144:ef7eb2e8f9f7 112 /**
<> 144:ef7eb2e8f9f7 113 * @brief Macro to access a single bit of a peripheral register (bit band region
<> 144:ef7eb2e8f9f7 114 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
<> 144:ef7eb2e8f9f7 115 * be used for peripherals with 16bit access allowed.
<> 144:ef7eb2e8f9f7 116 * @param Reg Register to access.
<> 144:ef7eb2e8f9f7 117 * @param Bit Bit number to access.
<> 144:ef7eb2e8f9f7 118 * @return Value of the targeted bit in the bit band region.
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @brief Macro to access a single bit of a peripheral register (bit band region
<> 144:ef7eb2e8f9f7 123 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
<> 144:ef7eb2e8f9f7 124 * be used for peripherals with 8bit access allowed.
<> 144:ef7eb2e8f9f7 125 * @param Reg Register to access.
<> 144:ef7eb2e8f9f7 126 * @param Bit Bit number to access.
<> 144:ef7eb2e8f9f7 127 * @return Value of the targeted bit in the bit band region.
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 132 -- Interrupt vector numbers
<> 144:ef7eb2e8f9f7 133 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /*!
<> 144:ef7eb2e8f9f7 136 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** Interrupt Number Definitions */
<> 144:ef7eb2e8f9f7 141 #define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 typedef enum IRQn {
<> 144:ef7eb2e8f9f7 144 /* Auxiliary constants */
<> 144:ef7eb2e8f9f7 145 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Core interrupts */
<> 144:ef7eb2e8f9f7 148 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 149 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 150 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 151 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 152 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 153 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 154 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 155 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 156 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Device specific interrupts */
<> 144:ef7eb2e8f9f7 159 DMA0_DMA16_IRQn = 0, /**< DMA Channel 0, 16 Transfer Complete */
<> 144:ef7eb2e8f9f7 160 DMA1_DMA17_IRQn = 1, /**< DMA Channel 1, 17 Transfer Complete */
<> 144:ef7eb2e8f9f7 161 DMA2_DMA18_IRQn = 2, /**< DMA Channel 2, 18 Transfer Complete */
<> 144:ef7eb2e8f9f7 162 DMA3_DMA19_IRQn = 3, /**< DMA Channel 3, 19 Transfer Complete */
<> 144:ef7eb2e8f9f7 163 DMA4_DMA20_IRQn = 4, /**< DMA Channel 4, 20 Transfer Complete */
<> 144:ef7eb2e8f9f7 164 DMA5_DMA21_IRQn = 5, /**< DMA Channel 5, 21 Transfer Complete */
<> 144:ef7eb2e8f9f7 165 DMA6_DMA22_IRQn = 6, /**< DMA Channel 6, 22 Transfer Complete */
<> 144:ef7eb2e8f9f7 166 DMA7_DMA23_IRQn = 7, /**< DMA Channel 7, 23 Transfer Complete */
<> 144:ef7eb2e8f9f7 167 DMA8_DMA24_IRQn = 8, /**< DMA Channel 8, 24 Transfer Complete */
<> 144:ef7eb2e8f9f7 168 DMA9_DMA25_IRQn = 9, /**< DMA Channel 9, 25 Transfer Complete */
<> 144:ef7eb2e8f9f7 169 DMA10_DMA26_IRQn = 10, /**< DMA Channel 10, 26 Transfer Complete */
<> 144:ef7eb2e8f9f7 170 DMA11_DMA27_IRQn = 11, /**< DMA Channel 11, 27 Transfer Complete */
<> 144:ef7eb2e8f9f7 171 DMA12_DMA28_IRQn = 12, /**< DMA Channel 12, 28 Transfer Complete */
<> 144:ef7eb2e8f9f7 172 DMA13_DMA29_IRQn = 13, /**< DMA Channel 13, 29 Transfer Complete */
<> 144:ef7eb2e8f9f7 173 DMA14_DMA30_IRQn = 14, /**< DMA Channel 14, 30 Transfer Complete */
<> 144:ef7eb2e8f9f7 174 DMA15_DMA31_IRQn = 15, /**< DMA Channel 15, 31 Transfer Complete */
<> 144:ef7eb2e8f9f7 175 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
<> 144:ef7eb2e8f9f7 176 MCM_IRQn = 17, /**< Normal Interrupt */
<> 144:ef7eb2e8f9f7 177 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
<> 144:ef7eb2e8f9f7 178 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
<> 144:ef7eb2e8f9f7 179 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
<> 144:ef7eb2e8f9f7 180 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
<> 144:ef7eb2e8f9f7 181 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
<> 144:ef7eb2e8f9f7 182 RNG_IRQn = 23, /**< RNG Interrupt */
<> 144:ef7eb2e8f9f7 183 I2C0_IRQn = 24, /**< I2C0 interrupt */
<> 144:ef7eb2e8f9f7 184 I2C1_IRQn = 25, /**< I2C1 interrupt */
<> 144:ef7eb2e8f9f7 185 SPI0_IRQn = 26, /**< SPI0 Interrupt */
<> 144:ef7eb2e8f9f7 186 SPI1_IRQn = 27, /**< SPI1 Interrupt */
<> 144:ef7eb2e8f9f7 187 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
<> 144:ef7eb2e8f9f7 188 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
<> 144:ef7eb2e8f9f7 189 Reserved46_IRQn = 30, /**< Reserved interrupt 46 */
<> 144:ef7eb2e8f9f7 190 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
<> 144:ef7eb2e8f9f7 191 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
<> 144:ef7eb2e8f9f7 192 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
<> 144:ef7eb2e8f9f7 193 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
<> 144:ef7eb2e8f9f7 194 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
<> 144:ef7eb2e8f9f7 195 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
<> 144:ef7eb2e8f9f7 196 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
<> 144:ef7eb2e8f9f7 197 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
<> 144:ef7eb2e8f9f7 198 ADC0_IRQn = 39, /**< ADC0 interrupt */
<> 144:ef7eb2e8f9f7 199 CMP0_IRQn = 40, /**< CMP0 interrupt */
<> 144:ef7eb2e8f9f7 200 CMP1_IRQn = 41, /**< CMP1 interrupt */
<> 144:ef7eb2e8f9f7 201 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
<> 144:ef7eb2e8f9f7 202 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
<> 144:ef7eb2e8f9f7 203 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
<> 144:ef7eb2e8f9f7 204 CMT_IRQn = 45, /**< CMT interrupt */
<> 144:ef7eb2e8f9f7 205 RTC_IRQn = 46, /**< RTC interrupt */
<> 144:ef7eb2e8f9f7 206 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
<> 144:ef7eb2e8f9f7 207 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
<> 144:ef7eb2e8f9f7 208 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
<> 144:ef7eb2e8f9f7 209 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
<> 144:ef7eb2e8f9f7 210 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
<> 144:ef7eb2e8f9f7 211 PDB0_IRQn = 52, /**< PDB0 Interrupt */
<> 144:ef7eb2e8f9f7 212 USB0_IRQn = 53, /**< USB0 interrupt */
<> 144:ef7eb2e8f9f7 213 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
<> 144:ef7eb2e8f9f7 214 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
<> 144:ef7eb2e8f9f7 215 DAC0_IRQn = 56, /**< DAC0 interrupt */
<> 144:ef7eb2e8f9f7 216 MCG_IRQn = 57, /**< MCG Interrupt */
<> 144:ef7eb2e8f9f7 217 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
<> 144:ef7eb2e8f9f7 218 PORTA_IRQn = 59, /**< Port A interrupt */
<> 144:ef7eb2e8f9f7 219 PORTB_IRQn = 60, /**< Port B interrupt */
<> 144:ef7eb2e8f9f7 220 PORTC_IRQn = 61, /**< Port C interrupt */
<> 144:ef7eb2e8f9f7 221 PORTD_IRQn = 62, /**< Port D interrupt */
<> 144:ef7eb2e8f9f7 222 PORTE_IRQn = 63, /**< Port E interrupt */
<> 144:ef7eb2e8f9f7 223 SWI_IRQn = 64, /**< Software interrupt */
<> 144:ef7eb2e8f9f7 224 SPI2_IRQn = 65, /**< SPI2 Interrupt */
<> 144:ef7eb2e8f9f7 225 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
<> 144:ef7eb2e8f9f7 226 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
<> 144:ef7eb2e8f9f7 227 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
<> 144:ef7eb2e8f9f7 228 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
<> 144:ef7eb2e8f9f7 229 CMP2_IRQn = 70, /**< CMP2 interrupt */
<> 144:ef7eb2e8f9f7 230 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
<> 144:ef7eb2e8f9f7 231 DAC1_IRQn = 72, /**< DAC1 interrupt */
<> 144:ef7eb2e8f9f7 232 ADC1_IRQn = 73, /**< ADC1 interrupt */
<> 144:ef7eb2e8f9f7 233 I2C2_IRQn = 74, /**< I2C2 interrupt */
<> 144:ef7eb2e8f9f7 234 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
<> 144:ef7eb2e8f9f7 235 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
<> 144:ef7eb2e8f9f7 236 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
<> 144:ef7eb2e8f9f7 237 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
<> 144:ef7eb2e8f9f7 238 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
<> 144:ef7eb2e8f9f7 239 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
<> 144:ef7eb2e8f9f7 240 SDHC_IRQn = 81, /**< SDHC interrupt */
<> 144:ef7eb2e8f9f7 241 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
<> 144:ef7eb2e8f9f7 242 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
<> 144:ef7eb2e8f9f7 243 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
<> 144:ef7eb2e8f9f7 244 ENET_Error_IRQn = 85, /**< Ethernet MAC Error and miscelaneous Interrupt */
<> 144:ef7eb2e8f9f7 245 LPUART0_IRQn = 86, /**< LPUART0 status/error interrupt */
<> 144:ef7eb2e8f9f7 246 TSI0_IRQn = 87, /**< TSI0 interrupt */
<> 144:ef7eb2e8f9f7 247 TPM1_IRQn = 88, /**< TPM1 fault, overflow and channels interrupt */
<> 144:ef7eb2e8f9f7 248 TPM2_IRQn = 89, /**< TPM2 fault, overflow and channels interrupt */
<> 144:ef7eb2e8f9f7 249 USBHSDCD_IRQn = 90, /**< USBHSDCD, USBHS Phy Interrupt */
<> 144:ef7eb2e8f9f7 250 I2C3_IRQn = 91, /**< I2C3 interrupt */
<> 144:ef7eb2e8f9f7 251 CMP3_IRQn = 92, /**< CMP3 interrupt */
<> 144:ef7eb2e8f9f7 252 USBHS_IRQn = 93, /**< USB high speed OTG interrupt */
<> 144:ef7eb2e8f9f7 253 CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN1 OR'd message buffers interrupt */
<> 144:ef7eb2e8f9f7 254 CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */
<> 144:ef7eb2e8f9f7 255 CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */
<> 144:ef7eb2e8f9f7 256 CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */
<> 144:ef7eb2e8f9f7 257 CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */
<> 144:ef7eb2e8f9f7 258 CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */
<> 144:ef7eb2e8f9f7 259 } IRQn_Type;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /*!
<> 144:ef7eb2e8f9f7 262 * @}
<> 144:ef7eb2e8f9f7 263 */ /* end of group Interrupt_vector_numbers */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 267 -- Cortex M4 Core Configuration
<> 144:ef7eb2e8f9f7 268 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /*!
<> 144:ef7eb2e8f9f7 271 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
<> 144:ef7eb2e8f9f7 276 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
<> 144:ef7eb2e8f9f7 277 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
<> 144:ef7eb2e8f9f7 278 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 #include "core_cm4.h" /* Core Peripheral Access Layer */
<> 144:ef7eb2e8f9f7 281 #include "system_MK66F18.h" /* Device specific configuration file */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /*!
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */ /* end of group Cortex_Core_Configuration */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 289 -- Mapping Information
<> 144:ef7eb2e8f9f7 290 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /*!
<> 144:ef7eb2e8f9f7 293 * @addtogroup Mapping_Information Mapping Information
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** Mapping Information */
<> 144:ef7eb2e8f9f7 298 /*!
<> 144:ef7eb2e8f9f7 299 * @addtogroup edma_request
<> 144:ef7eb2e8f9f7 300 * @{
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /*******************************************************************************
<> 144:ef7eb2e8f9f7 304 * Definitions
<> 144:ef7eb2e8f9f7 305 ******************************************************************************/
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /*!
<> 144:ef7eb2e8f9f7 308 * @brief Structure for the DMA hardware request
<> 144:ef7eb2e8f9f7 309 *
<> 144:ef7eb2e8f9f7 310 * Defines the structure for the DMA hardware request collections. The user can configure the
<> 144:ef7eb2e8f9f7 311 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
<> 144:ef7eb2e8f9f7 312 * of the hardware request varies according to the to SoC.
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 typedef enum _dma_request_source
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
<> 144:ef7eb2e8f9f7 317 kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
<> 144:ef7eb2e8f9f7 318 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
<> 144:ef7eb2e8f9f7 319 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
<> 144:ef7eb2e8f9f7 320 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
<> 144:ef7eb2e8f9f7 321 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
<> 144:ef7eb2e8f9f7 322 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
<> 144:ef7eb2e8f9f7 323 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
<> 144:ef7eb2e8f9f7 324 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
<> 144:ef7eb2e8f9f7 325 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
<> 144:ef7eb2e8f9f7 326 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
<> 144:ef7eb2e8f9f7 327 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
<> 144:ef7eb2e8f9f7 328 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
<> 144:ef7eb2e8f9f7 329 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
<> 144:ef7eb2e8f9f7 330 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
<> 144:ef7eb2e8f9f7 331 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
<> 144:ef7eb2e8f9f7 332 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
<> 144:ef7eb2e8f9f7 333 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
<> 144:ef7eb2e8f9f7 334 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
<> 144:ef7eb2e8f9f7 335 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
<> 144:ef7eb2e8f9f7 336 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
<> 144:ef7eb2e8f9f7 337 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
<> 144:ef7eb2e8f9f7 338 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
<> 144:ef7eb2e8f9f7 339 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
<> 144:ef7eb2e8f9f7 340 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
<> 144:ef7eb2e8f9f7 341 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
<> 144:ef7eb2e8f9f7 342 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
<> 144:ef7eb2e8f9f7 343 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
<> 144:ef7eb2e8f9f7 344 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
<> 144:ef7eb2e8f9f7 345 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
<> 144:ef7eb2e8f9f7 346 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
<> 144:ef7eb2e8f9f7 347 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
<> 144:ef7eb2e8f9f7 348 kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
<> 144:ef7eb2e8f9f7 349 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
<> 144:ef7eb2e8f9f7 350 kDmaRequestMux0TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
<> 144:ef7eb2e8f9f7 351 kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
<> 144:ef7eb2e8f9f7 352 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
<> 144:ef7eb2e8f9f7 353 kDmaRequestMux0TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
<> 144:ef7eb2e8f9f7 354 kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
<> 144:ef7eb2e8f9f7 355 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
<> 144:ef7eb2e8f9f7 356 kDmaRequestMux0TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
<> 144:ef7eb2e8f9f7 357 kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
<> 144:ef7eb2e8f9f7 358 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
<> 144:ef7eb2e8f9f7 359 kDmaRequestMux0TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
<> 144:ef7eb2e8f9f7 360 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
<> 144:ef7eb2e8f9f7 361 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
<> 144:ef7eb2e8f9f7 362 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
<> 144:ef7eb2e8f9f7 363 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
<> 144:ef7eb2e8f9f7 364 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
<> 144:ef7eb2e8f9f7 365 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
<> 144:ef7eb2e8f9f7 366 kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
<> 144:ef7eb2e8f9f7 367 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
<> 144:ef7eb2e8f9f7 368 kDmaRequestMux0SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
<> 144:ef7eb2e8f9f7 369 kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
<> 144:ef7eb2e8f9f7 370 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
<> 144:ef7eb2e8f9f7 371 kDmaRequestMux0SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
<> 144:ef7eb2e8f9f7 372 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
<> 144:ef7eb2e8f9f7 373 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
<> 144:ef7eb2e8f9f7 374 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
<> 144:ef7eb2e8f9f7 375 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
<> 144:ef7eb2e8f9f7 376 kDmaRequestMux0CMP2CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
<> 144:ef7eb2e8f9f7 377 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 and CMP3. */
<> 144:ef7eb2e8f9f7 378 kDmaRequestMux0CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
<> 144:ef7eb2e8f9f7 379 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
<> 144:ef7eb2e8f9f7 380 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
<> 144:ef7eb2e8f9f7 381 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
<> 144:ef7eb2e8f9f7 382 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
<> 144:ef7eb2e8f9f7 383 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
<> 144:ef7eb2e8f9f7 384 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
<> 144:ef7eb2e8f9f7 385 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
<> 144:ef7eb2e8f9f7 386 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
<> 144:ef7eb2e8f9f7 387 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
<> 144:ef7eb2e8f9f7 388 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */
<> 144:ef7eb2e8f9f7 389 kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
<> 144:ef7eb2e8f9f7 390 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
<> 144:ef7eb2e8f9f7 391 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
<> 144:ef7eb2e8f9f7 392 kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
<> 144:ef7eb2e8f9f7 393 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
<> 144:ef7eb2e8f9f7 394 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
<> 144:ef7eb2e8f9f7 395 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */
<> 144:ef7eb2e8f9f7 396 kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
<> 144:ef7eb2e8f9f7 397 kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
<> 144:ef7eb2e8f9f7 398 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
<> 144:ef7eb2e8f9f7 399 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
<> 144:ef7eb2e8f9f7 400 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
<> 144:ef7eb2e8f9f7 401 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
<> 144:ef7eb2e8f9f7 402 } dma_request_source_t;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* @} */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*!
<> 144:ef7eb2e8f9f7 408 * @}
<> 144:ef7eb2e8f9f7 409 */ /* end of group Mapping_Information */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 413 -- Device Peripheral Access Layer
<> 144:ef7eb2e8f9f7 414 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /*!
<> 144:ef7eb2e8f9f7 417 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
<> 144:ef7eb2e8f9f7 418 * @{
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /*
<> 144:ef7eb2e8f9f7 423 ** Start of section using anonymous unions
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #if defined(__ARMCC_VERSION)
<> 144:ef7eb2e8f9f7 427 #pragma push
<> 144:ef7eb2e8f9f7 428 #pragma anon_unions
<> 144:ef7eb2e8f9f7 429 #elif defined(__CWCC__)
<> 144:ef7eb2e8f9f7 430 #pragma push
<> 144:ef7eb2e8f9f7 431 #pragma cpp_extensions on
<> 144:ef7eb2e8f9f7 432 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 433 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 434 #elif defined(__IAR_SYSTEMS_ICC__)
<> 144:ef7eb2e8f9f7 435 #pragma language=extended
<> 144:ef7eb2e8f9f7 436 #else
<> 144:ef7eb2e8f9f7 437 #error Not supported compiler type
<> 144:ef7eb2e8f9f7 438 #endif
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 441 -- ADC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 442 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /*!
<> 144:ef7eb2e8f9f7 445 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 446 * @{
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /** ADC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 450 typedef struct {
<> 144:ef7eb2e8f9f7 451 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 452 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
<> 144:ef7eb2e8f9f7 453 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
<> 144:ef7eb2e8f9f7 454 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
<> 144:ef7eb2e8f9f7 455 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
<> 144:ef7eb2e8f9f7 456 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
<> 144:ef7eb2e8f9f7 457 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
<> 144:ef7eb2e8f9f7 458 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 460 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 462 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
<> 144:ef7eb2e8f9f7 464 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
<> 144:ef7eb2e8f9f7 465 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 466 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 467 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
<> 144:ef7eb2e8f9f7 468 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
<> 144:ef7eb2e8f9f7 469 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 470 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
<> 144:ef7eb2e8f9f7 471 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
<> 144:ef7eb2e8f9f7 472 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
<> 144:ef7eb2e8f9f7 473 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
<> 144:ef7eb2e8f9f7 474 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
<> 144:ef7eb2e8f9f7 476 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
<> 144:ef7eb2e8f9f7 477 } ADC_Type;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 480 -- ADC Register Masks
<> 144:ef7eb2e8f9f7 481 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /*!
<> 144:ef7eb2e8f9f7 484 * @addtogroup ADC_Register_Masks ADC Register Masks
<> 144:ef7eb2e8f9f7 485 * @{
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /*! @name SC1 - ADC Status and Control Registers 1 */
<> 144:ef7eb2e8f9f7 489 #define ADC_SC1_ADCH_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 490 #define ADC_SC1_ADCH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 491 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
<> 144:ef7eb2e8f9f7 492 #define ADC_SC1_DIFF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 493 #define ADC_SC1_DIFF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 494 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
<> 144:ef7eb2e8f9f7 495 #define ADC_SC1_AIEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 496 #define ADC_SC1_AIEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 497 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
<> 144:ef7eb2e8f9f7 498 #define ADC_SC1_COCO_MASK (0x80U)
<> 144:ef7eb2e8f9f7 499 #define ADC_SC1_COCO_SHIFT (7U)
<> 144:ef7eb2e8f9f7 500 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* The count of ADC_SC1 */
<> 144:ef7eb2e8f9f7 503 #define ADC_SC1_COUNT (2U)
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /*! @name CFG1 - ADC Configuration Register 1 */
<> 144:ef7eb2e8f9f7 506 #define ADC_CFG1_ADICLK_MASK (0x3U)
<> 144:ef7eb2e8f9f7 507 #define ADC_CFG1_ADICLK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 508 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
<> 144:ef7eb2e8f9f7 509 #define ADC_CFG1_MODE_MASK (0xCU)
<> 144:ef7eb2e8f9f7 510 #define ADC_CFG1_MODE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 511 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
<> 144:ef7eb2e8f9f7 512 #define ADC_CFG1_ADLSMP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 513 #define ADC_CFG1_ADLSMP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 514 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
<> 144:ef7eb2e8f9f7 515 #define ADC_CFG1_ADIV_MASK (0x60U)
<> 144:ef7eb2e8f9f7 516 #define ADC_CFG1_ADIV_SHIFT (5U)
<> 144:ef7eb2e8f9f7 517 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
<> 144:ef7eb2e8f9f7 518 #define ADC_CFG1_ADLPC_MASK (0x80U)
<> 144:ef7eb2e8f9f7 519 #define ADC_CFG1_ADLPC_SHIFT (7U)
<> 144:ef7eb2e8f9f7 520 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /*! @name CFG2 - ADC Configuration Register 2 */
<> 144:ef7eb2e8f9f7 523 #define ADC_CFG2_ADLSTS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 524 #define ADC_CFG2_ADLSTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 525 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
<> 144:ef7eb2e8f9f7 526 #define ADC_CFG2_ADHSC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 527 #define ADC_CFG2_ADHSC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 528 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
<> 144:ef7eb2e8f9f7 529 #define ADC_CFG2_ADACKEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 530 #define ADC_CFG2_ADACKEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 531 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
<> 144:ef7eb2e8f9f7 532 #define ADC_CFG2_MUXSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 533 #define ADC_CFG2_MUXSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 534 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /*! @name R - ADC Data Result Register */
<> 144:ef7eb2e8f9f7 537 #define ADC_R_D_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 538 #define ADC_R_D_SHIFT (0U)
<> 144:ef7eb2e8f9f7 539 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* The count of ADC_R */
<> 144:ef7eb2e8f9f7 542 #define ADC_R_COUNT (2U)
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /*! @name CV1 - Compare Value Registers */
<> 144:ef7eb2e8f9f7 545 #define ADC_CV1_CV_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 546 #define ADC_CV1_CV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 547 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /*! @name CV2 - Compare Value Registers */
<> 144:ef7eb2e8f9f7 550 #define ADC_CV2_CV_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 551 #define ADC_CV2_CV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 552 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /*! @name SC2 - Status and Control Register 2 */
<> 144:ef7eb2e8f9f7 555 #define ADC_SC2_REFSEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 556 #define ADC_SC2_REFSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 557 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
<> 144:ef7eb2e8f9f7 558 #define ADC_SC2_DMAEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 559 #define ADC_SC2_DMAEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 560 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 561 #define ADC_SC2_ACREN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 562 #define ADC_SC2_ACREN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 563 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
<> 144:ef7eb2e8f9f7 564 #define ADC_SC2_ACFGT_MASK (0x10U)
<> 144:ef7eb2e8f9f7 565 #define ADC_SC2_ACFGT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 566 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
<> 144:ef7eb2e8f9f7 567 #define ADC_SC2_ACFE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 568 #define ADC_SC2_ACFE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 569 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
<> 144:ef7eb2e8f9f7 570 #define ADC_SC2_ADTRG_MASK (0x40U)
<> 144:ef7eb2e8f9f7 571 #define ADC_SC2_ADTRG_SHIFT (6U)
<> 144:ef7eb2e8f9f7 572 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
<> 144:ef7eb2e8f9f7 573 #define ADC_SC2_ADACT_MASK (0x80U)
<> 144:ef7eb2e8f9f7 574 #define ADC_SC2_ADACT_SHIFT (7U)
<> 144:ef7eb2e8f9f7 575 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /*! @name SC3 - Status and Control Register 3 */
<> 144:ef7eb2e8f9f7 578 #define ADC_SC3_AVGS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 579 #define ADC_SC3_AVGS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 580 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
<> 144:ef7eb2e8f9f7 581 #define ADC_SC3_AVGE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 582 #define ADC_SC3_AVGE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 583 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
<> 144:ef7eb2e8f9f7 584 #define ADC_SC3_ADCO_MASK (0x8U)
<> 144:ef7eb2e8f9f7 585 #define ADC_SC3_ADCO_SHIFT (3U)
<> 144:ef7eb2e8f9f7 586 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
<> 144:ef7eb2e8f9f7 587 #define ADC_SC3_CALF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 588 #define ADC_SC3_CALF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 589 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
<> 144:ef7eb2e8f9f7 590 #define ADC_SC3_CAL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 591 #define ADC_SC3_CAL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 592 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /*! @name OFS - ADC Offset Correction Register */
<> 144:ef7eb2e8f9f7 595 #define ADC_OFS_OFS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 596 #define ADC_OFS_OFS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 597 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /*! @name PG - ADC Plus-Side Gain Register */
<> 144:ef7eb2e8f9f7 600 #define ADC_PG_PG_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 601 #define ADC_PG_PG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 602 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /*! @name MG - ADC Minus-Side Gain Register */
<> 144:ef7eb2e8f9f7 605 #define ADC_MG_MG_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 606 #define ADC_MG_MG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 607 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 610 #define ADC_CLPD_CLPD_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 611 #define ADC_CLPD_CLPD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 612 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 615 #define ADC_CLPS_CLPS_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 616 #define ADC_CLPS_CLPS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 617 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 620 #define ADC_CLP4_CLP4_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 621 #define ADC_CLP4_CLP4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 622 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 625 #define ADC_CLP3_CLP3_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 626 #define ADC_CLP3_CLP3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 627 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 630 #define ADC_CLP2_CLP2_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 631 #define ADC_CLP2_CLP2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 632 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 635 #define ADC_CLP1_CLP1_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 636 #define ADC_CLP1_CLP1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 637 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 640 #define ADC_CLP0_CLP0_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 641 #define ADC_CLP0_CLP0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 642 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 645 #define ADC_CLMD_CLMD_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 646 #define ADC_CLMD_CLMD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 647 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 650 #define ADC_CLMS_CLMS_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 651 #define ADC_CLMS_CLMS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 652 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 655 #define ADC_CLM4_CLM4_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 656 #define ADC_CLM4_CLM4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 657 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 660 #define ADC_CLM3_CLM3_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 661 #define ADC_CLM3_CLM3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 662 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 665 #define ADC_CLM2_CLM2_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 666 #define ADC_CLM2_CLM2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 667 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 670 #define ADC_CLM1_CLM1_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 671 #define ADC_CLM1_CLM1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 672 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
<> 144:ef7eb2e8f9f7 675 #define ADC_CLM0_CLM0_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 676 #define ADC_CLM0_CLM0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 677 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /*!
<> 144:ef7eb2e8f9f7 681 * @}
<> 144:ef7eb2e8f9f7 682 */ /* end of group ADC_Register_Masks */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* ADC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 686 /** Peripheral ADC0 base address */
<> 144:ef7eb2e8f9f7 687 #define ADC0_BASE (0x4003B000u)
<> 144:ef7eb2e8f9f7 688 /** Peripheral ADC0 base pointer */
<> 144:ef7eb2e8f9f7 689 #define ADC0 ((ADC_Type *)ADC0_BASE)
<> 144:ef7eb2e8f9f7 690 /** Peripheral ADC1 base address */
<> 144:ef7eb2e8f9f7 691 #define ADC1_BASE (0x400BB000u)
<> 144:ef7eb2e8f9f7 692 /** Peripheral ADC1 base pointer */
<> 144:ef7eb2e8f9f7 693 #define ADC1 ((ADC_Type *)ADC1_BASE)
<> 144:ef7eb2e8f9f7 694 /** Array initializer of ADC peripheral base addresses */
<> 144:ef7eb2e8f9f7 695 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
<> 144:ef7eb2e8f9f7 696 /** Array initializer of ADC peripheral base pointers */
<> 144:ef7eb2e8f9f7 697 #define ADC_BASE_PTRS { ADC0, ADC1 }
<> 144:ef7eb2e8f9f7 698 /** Interrupt vectors for the ADC peripheral type */
<> 144:ef7eb2e8f9f7 699 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /*!
<> 144:ef7eb2e8f9f7 702 * @}
<> 144:ef7eb2e8f9f7 703 */ /* end of group ADC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 707 -- AIPS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 708 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /*!
<> 144:ef7eb2e8f9f7 711 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 712 * @{
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /** AIPS - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 716 typedef struct {
<> 144:ef7eb2e8f9f7 717 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
<> 144:ef7eb2e8f9f7 718 uint8_t RESERVED_0[28];
<> 144:ef7eb2e8f9f7 719 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 720 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 721 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 722 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 723 uint8_t RESERVED_1[16];
<> 144:ef7eb2e8f9f7 724 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 725 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 726 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
<> 144:ef7eb2e8f9f7 727 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
<> 144:ef7eb2e8f9f7 728 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
<> 144:ef7eb2e8f9f7 729 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
<> 144:ef7eb2e8f9f7 730 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
<> 144:ef7eb2e8f9f7 731 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
<> 144:ef7eb2e8f9f7 732 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
<> 144:ef7eb2e8f9f7 733 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
<> 144:ef7eb2e8f9f7 734 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
<> 144:ef7eb2e8f9f7 735 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
<> 144:ef7eb2e8f9f7 736 } AIPS_Type;
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 739 -- AIPS Register Masks
<> 144:ef7eb2e8f9f7 740 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /*!
<> 144:ef7eb2e8f9f7 743 * @addtogroup AIPS_Register_Masks AIPS Register Masks
<> 144:ef7eb2e8f9f7 744 * @{
<> 144:ef7eb2e8f9f7 745 */
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /*! @name MPRA - Master Privilege Register A */
<> 144:ef7eb2e8f9f7 748 #define AIPS_MPRA_MPL6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 749 #define AIPS_MPRA_MPL6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 750 #define AIPS_MPRA_MPL6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
<> 144:ef7eb2e8f9f7 751 #define AIPS_MPRA_MTW6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 752 #define AIPS_MPRA_MTW6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 753 #define AIPS_MPRA_MTW6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
<> 144:ef7eb2e8f9f7 754 #define AIPS_MPRA_MTR6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 755 #define AIPS_MPRA_MTR6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 756 #define AIPS_MPRA_MTR6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
<> 144:ef7eb2e8f9f7 757 #define AIPS_MPRA_MPL5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 758 #define AIPS_MPRA_MPL5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 759 #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
<> 144:ef7eb2e8f9f7 760 #define AIPS_MPRA_MTW5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 761 #define AIPS_MPRA_MTW5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 762 #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
<> 144:ef7eb2e8f9f7 763 #define AIPS_MPRA_MTR5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 764 #define AIPS_MPRA_MTR5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 765 #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
<> 144:ef7eb2e8f9f7 766 #define AIPS_MPRA_MPL4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 767 #define AIPS_MPRA_MPL4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 768 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
<> 144:ef7eb2e8f9f7 769 #define AIPS_MPRA_MTW4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 770 #define AIPS_MPRA_MTW4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 771 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
<> 144:ef7eb2e8f9f7 772 #define AIPS_MPRA_MTR4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 773 #define AIPS_MPRA_MTR4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 774 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
<> 144:ef7eb2e8f9f7 775 #define AIPS_MPRA_MPL3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 776 #define AIPS_MPRA_MPL3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 777 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
<> 144:ef7eb2e8f9f7 778 #define AIPS_MPRA_MTW3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 779 #define AIPS_MPRA_MTW3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 780 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
<> 144:ef7eb2e8f9f7 781 #define AIPS_MPRA_MTR3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 782 #define AIPS_MPRA_MTR3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 783 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
<> 144:ef7eb2e8f9f7 784 #define AIPS_MPRA_MPL2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 785 #define AIPS_MPRA_MPL2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 786 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
<> 144:ef7eb2e8f9f7 787 #define AIPS_MPRA_MTW2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 788 #define AIPS_MPRA_MTW2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 789 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
<> 144:ef7eb2e8f9f7 790 #define AIPS_MPRA_MTR2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 791 #define AIPS_MPRA_MTR2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 792 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
<> 144:ef7eb2e8f9f7 793 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 794 #define AIPS_MPRA_MPL1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 795 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
<> 144:ef7eb2e8f9f7 796 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 797 #define AIPS_MPRA_MTW1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 798 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
<> 144:ef7eb2e8f9f7 799 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 800 #define AIPS_MPRA_MTR1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 801 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
<> 144:ef7eb2e8f9f7 802 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 803 #define AIPS_MPRA_MPL0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 804 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
<> 144:ef7eb2e8f9f7 805 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 806 #define AIPS_MPRA_MTW0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 807 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
<> 144:ef7eb2e8f9f7 808 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 809 #define AIPS_MPRA_MTR0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 810 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /*! @name PACRA - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 813 #define AIPS_PACRA_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 814 #define AIPS_PACRA_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 815 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
<> 144:ef7eb2e8f9f7 816 #define AIPS_PACRA_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 817 #define AIPS_PACRA_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 818 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
<> 144:ef7eb2e8f9f7 819 #define AIPS_PACRA_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 820 #define AIPS_PACRA_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 821 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
<> 144:ef7eb2e8f9f7 822 #define AIPS_PACRA_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 823 #define AIPS_PACRA_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 824 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
<> 144:ef7eb2e8f9f7 825 #define AIPS_PACRA_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 826 #define AIPS_PACRA_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 827 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
<> 144:ef7eb2e8f9f7 828 #define AIPS_PACRA_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 829 #define AIPS_PACRA_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 830 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
<> 144:ef7eb2e8f9f7 831 #define AIPS_PACRA_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 832 #define AIPS_PACRA_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 833 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
<> 144:ef7eb2e8f9f7 834 #define AIPS_PACRA_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 835 #define AIPS_PACRA_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 836 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
<> 144:ef7eb2e8f9f7 837 #define AIPS_PACRA_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 838 #define AIPS_PACRA_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 839 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
<> 144:ef7eb2e8f9f7 840 #define AIPS_PACRA_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 841 #define AIPS_PACRA_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 842 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
<> 144:ef7eb2e8f9f7 843 #define AIPS_PACRA_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 844 #define AIPS_PACRA_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 845 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
<> 144:ef7eb2e8f9f7 846 #define AIPS_PACRA_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 847 #define AIPS_PACRA_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 848 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
<> 144:ef7eb2e8f9f7 849 #define AIPS_PACRA_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 850 #define AIPS_PACRA_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 851 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
<> 144:ef7eb2e8f9f7 852 #define AIPS_PACRA_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 853 #define AIPS_PACRA_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 854 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
<> 144:ef7eb2e8f9f7 855 #define AIPS_PACRA_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 856 #define AIPS_PACRA_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 857 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
<> 144:ef7eb2e8f9f7 858 #define AIPS_PACRA_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 859 #define AIPS_PACRA_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 860 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
<> 144:ef7eb2e8f9f7 861 #define AIPS_PACRA_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 862 #define AIPS_PACRA_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 863 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
<> 144:ef7eb2e8f9f7 864 #define AIPS_PACRA_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 865 #define AIPS_PACRA_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 866 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
<> 144:ef7eb2e8f9f7 867 #define AIPS_PACRA_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 868 #define AIPS_PACRA_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 869 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
<> 144:ef7eb2e8f9f7 870 #define AIPS_PACRA_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 871 #define AIPS_PACRA_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 872 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
<> 144:ef7eb2e8f9f7 873 #define AIPS_PACRA_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 874 #define AIPS_PACRA_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 875 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
<> 144:ef7eb2e8f9f7 876 #define AIPS_PACRA_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 877 #define AIPS_PACRA_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 878 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
<> 144:ef7eb2e8f9f7 879 #define AIPS_PACRA_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 880 #define AIPS_PACRA_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 881 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
<> 144:ef7eb2e8f9f7 882 #define AIPS_PACRA_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 883 #define AIPS_PACRA_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 884 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /*! @name PACRB - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 887 #define AIPS_PACRB_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 888 #define AIPS_PACRB_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 889 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
<> 144:ef7eb2e8f9f7 890 #define AIPS_PACRB_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 891 #define AIPS_PACRB_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 892 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
<> 144:ef7eb2e8f9f7 893 #define AIPS_PACRB_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 894 #define AIPS_PACRB_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 895 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
<> 144:ef7eb2e8f9f7 896 #define AIPS_PACRB_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 897 #define AIPS_PACRB_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 898 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
<> 144:ef7eb2e8f9f7 899 #define AIPS_PACRB_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 900 #define AIPS_PACRB_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 901 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
<> 144:ef7eb2e8f9f7 902 #define AIPS_PACRB_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 903 #define AIPS_PACRB_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 904 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
<> 144:ef7eb2e8f9f7 905 #define AIPS_PACRB_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 906 #define AIPS_PACRB_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 907 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
<> 144:ef7eb2e8f9f7 908 #define AIPS_PACRB_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 909 #define AIPS_PACRB_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 910 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
<> 144:ef7eb2e8f9f7 911 #define AIPS_PACRB_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 912 #define AIPS_PACRB_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 913 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
<> 144:ef7eb2e8f9f7 914 #define AIPS_PACRB_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 915 #define AIPS_PACRB_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 916 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
<> 144:ef7eb2e8f9f7 917 #define AIPS_PACRB_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 918 #define AIPS_PACRB_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 919 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
<> 144:ef7eb2e8f9f7 920 #define AIPS_PACRB_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 921 #define AIPS_PACRB_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 922 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
<> 144:ef7eb2e8f9f7 923 #define AIPS_PACRB_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 924 #define AIPS_PACRB_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 925 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
<> 144:ef7eb2e8f9f7 926 #define AIPS_PACRB_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 927 #define AIPS_PACRB_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 928 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
<> 144:ef7eb2e8f9f7 929 #define AIPS_PACRB_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 930 #define AIPS_PACRB_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 931 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
<> 144:ef7eb2e8f9f7 932 #define AIPS_PACRB_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 933 #define AIPS_PACRB_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 934 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
<> 144:ef7eb2e8f9f7 935 #define AIPS_PACRB_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 936 #define AIPS_PACRB_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 937 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
<> 144:ef7eb2e8f9f7 938 #define AIPS_PACRB_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 939 #define AIPS_PACRB_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 940 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
<> 144:ef7eb2e8f9f7 941 #define AIPS_PACRB_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 942 #define AIPS_PACRB_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 943 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
<> 144:ef7eb2e8f9f7 944 #define AIPS_PACRB_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 945 #define AIPS_PACRB_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 946 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
<> 144:ef7eb2e8f9f7 947 #define AIPS_PACRB_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 948 #define AIPS_PACRB_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 949 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
<> 144:ef7eb2e8f9f7 950 #define AIPS_PACRB_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 951 #define AIPS_PACRB_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 952 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
<> 144:ef7eb2e8f9f7 953 #define AIPS_PACRB_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 954 #define AIPS_PACRB_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 955 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
<> 144:ef7eb2e8f9f7 956 #define AIPS_PACRB_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 957 #define AIPS_PACRB_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 958 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /*! @name PACRC - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 961 #define AIPS_PACRC_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 962 #define AIPS_PACRC_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 963 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
<> 144:ef7eb2e8f9f7 964 #define AIPS_PACRC_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 965 #define AIPS_PACRC_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 966 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
<> 144:ef7eb2e8f9f7 967 #define AIPS_PACRC_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 968 #define AIPS_PACRC_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 969 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
<> 144:ef7eb2e8f9f7 970 #define AIPS_PACRC_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 971 #define AIPS_PACRC_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 972 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
<> 144:ef7eb2e8f9f7 973 #define AIPS_PACRC_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 974 #define AIPS_PACRC_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 975 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
<> 144:ef7eb2e8f9f7 976 #define AIPS_PACRC_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 977 #define AIPS_PACRC_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 978 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
<> 144:ef7eb2e8f9f7 979 #define AIPS_PACRC_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 980 #define AIPS_PACRC_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 981 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
<> 144:ef7eb2e8f9f7 982 #define AIPS_PACRC_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 983 #define AIPS_PACRC_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 984 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
<> 144:ef7eb2e8f9f7 985 #define AIPS_PACRC_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 986 #define AIPS_PACRC_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 987 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
<> 144:ef7eb2e8f9f7 988 #define AIPS_PACRC_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 989 #define AIPS_PACRC_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 990 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
<> 144:ef7eb2e8f9f7 991 #define AIPS_PACRC_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 992 #define AIPS_PACRC_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 993 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
<> 144:ef7eb2e8f9f7 994 #define AIPS_PACRC_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 995 #define AIPS_PACRC_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 996 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
<> 144:ef7eb2e8f9f7 997 #define AIPS_PACRC_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 998 #define AIPS_PACRC_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 999 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
<> 144:ef7eb2e8f9f7 1000 #define AIPS_PACRC_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1001 #define AIPS_PACRC_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1002 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
<> 144:ef7eb2e8f9f7 1003 #define AIPS_PACRC_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1004 #define AIPS_PACRC_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1005 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
<> 144:ef7eb2e8f9f7 1006 #define AIPS_PACRC_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1007 #define AIPS_PACRC_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1008 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
<> 144:ef7eb2e8f9f7 1009 #define AIPS_PACRC_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1010 #define AIPS_PACRC_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1011 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
<> 144:ef7eb2e8f9f7 1012 #define AIPS_PACRC_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1013 #define AIPS_PACRC_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1014 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
<> 144:ef7eb2e8f9f7 1015 #define AIPS_PACRC_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1016 #define AIPS_PACRC_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1017 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
<> 144:ef7eb2e8f9f7 1018 #define AIPS_PACRC_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1019 #define AIPS_PACRC_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1020 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
<> 144:ef7eb2e8f9f7 1021 #define AIPS_PACRC_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1022 #define AIPS_PACRC_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1023 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
<> 144:ef7eb2e8f9f7 1024 #define AIPS_PACRC_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1025 #define AIPS_PACRC_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1026 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
<> 144:ef7eb2e8f9f7 1027 #define AIPS_PACRC_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1028 #define AIPS_PACRC_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1029 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
<> 144:ef7eb2e8f9f7 1030 #define AIPS_PACRC_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1031 #define AIPS_PACRC_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1032 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /*! @name PACRD - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1035 #define AIPS_PACRD_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1036 #define AIPS_PACRD_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1037 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
<> 144:ef7eb2e8f9f7 1038 #define AIPS_PACRD_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1039 #define AIPS_PACRD_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1040 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
<> 144:ef7eb2e8f9f7 1041 #define AIPS_PACRD_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1042 #define AIPS_PACRD_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1043 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
<> 144:ef7eb2e8f9f7 1044 #define AIPS_PACRD_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1045 #define AIPS_PACRD_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1046 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
<> 144:ef7eb2e8f9f7 1047 #define AIPS_PACRD_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1048 #define AIPS_PACRD_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1049 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
<> 144:ef7eb2e8f9f7 1050 #define AIPS_PACRD_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1051 #define AIPS_PACRD_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1052 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
<> 144:ef7eb2e8f9f7 1053 #define AIPS_PACRD_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1054 #define AIPS_PACRD_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1055 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
<> 144:ef7eb2e8f9f7 1056 #define AIPS_PACRD_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1057 #define AIPS_PACRD_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1058 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
<> 144:ef7eb2e8f9f7 1059 #define AIPS_PACRD_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1060 #define AIPS_PACRD_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1061 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
<> 144:ef7eb2e8f9f7 1062 #define AIPS_PACRD_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1063 #define AIPS_PACRD_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1064 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
<> 144:ef7eb2e8f9f7 1065 #define AIPS_PACRD_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1066 #define AIPS_PACRD_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1067 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
<> 144:ef7eb2e8f9f7 1068 #define AIPS_PACRD_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1069 #define AIPS_PACRD_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1070 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
<> 144:ef7eb2e8f9f7 1071 #define AIPS_PACRD_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1072 #define AIPS_PACRD_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1073 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
<> 144:ef7eb2e8f9f7 1074 #define AIPS_PACRD_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1075 #define AIPS_PACRD_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1076 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
<> 144:ef7eb2e8f9f7 1077 #define AIPS_PACRD_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1078 #define AIPS_PACRD_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1079 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
<> 144:ef7eb2e8f9f7 1080 #define AIPS_PACRD_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1081 #define AIPS_PACRD_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1082 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
<> 144:ef7eb2e8f9f7 1083 #define AIPS_PACRD_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1084 #define AIPS_PACRD_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1085 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
<> 144:ef7eb2e8f9f7 1086 #define AIPS_PACRD_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1087 #define AIPS_PACRD_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1088 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
<> 144:ef7eb2e8f9f7 1089 #define AIPS_PACRD_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1090 #define AIPS_PACRD_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1091 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
<> 144:ef7eb2e8f9f7 1092 #define AIPS_PACRD_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1093 #define AIPS_PACRD_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1094 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
<> 144:ef7eb2e8f9f7 1095 #define AIPS_PACRD_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1096 #define AIPS_PACRD_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1097 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
<> 144:ef7eb2e8f9f7 1098 #define AIPS_PACRD_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1099 #define AIPS_PACRD_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1100 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
<> 144:ef7eb2e8f9f7 1101 #define AIPS_PACRD_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1102 #define AIPS_PACRD_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1103 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
<> 144:ef7eb2e8f9f7 1104 #define AIPS_PACRD_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1105 #define AIPS_PACRD_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1106 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /*! @name PACRE - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1109 #define AIPS_PACRE_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1110 #define AIPS_PACRE_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1111 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
<> 144:ef7eb2e8f9f7 1112 #define AIPS_PACRE_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1113 #define AIPS_PACRE_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1114 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
<> 144:ef7eb2e8f9f7 1115 #define AIPS_PACRE_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1116 #define AIPS_PACRE_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1117 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
<> 144:ef7eb2e8f9f7 1118 #define AIPS_PACRE_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1119 #define AIPS_PACRE_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1120 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
<> 144:ef7eb2e8f9f7 1121 #define AIPS_PACRE_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1122 #define AIPS_PACRE_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1123 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
<> 144:ef7eb2e8f9f7 1124 #define AIPS_PACRE_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1125 #define AIPS_PACRE_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1126 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
<> 144:ef7eb2e8f9f7 1127 #define AIPS_PACRE_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1128 #define AIPS_PACRE_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1129 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
<> 144:ef7eb2e8f9f7 1130 #define AIPS_PACRE_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1131 #define AIPS_PACRE_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1132 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
<> 144:ef7eb2e8f9f7 1133 #define AIPS_PACRE_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1134 #define AIPS_PACRE_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1135 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
<> 144:ef7eb2e8f9f7 1136 #define AIPS_PACRE_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1137 #define AIPS_PACRE_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1138 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
<> 144:ef7eb2e8f9f7 1139 #define AIPS_PACRE_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1140 #define AIPS_PACRE_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1141 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
<> 144:ef7eb2e8f9f7 1142 #define AIPS_PACRE_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1143 #define AIPS_PACRE_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1144 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
<> 144:ef7eb2e8f9f7 1145 #define AIPS_PACRE_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1146 #define AIPS_PACRE_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1147 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
<> 144:ef7eb2e8f9f7 1148 #define AIPS_PACRE_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1149 #define AIPS_PACRE_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1150 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
<> 144:ef7eb2e8f9f7 1151 #define AIPS_PACRE_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1152 #define AIPS_PACRE_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1153 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
<> 144:ef7eb2e8f9f7 1154 #define AIPS_PACRE_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1155 #define AIPS_PACRE_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1156 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
<> 144:ef7eb2e8f9f7 1157 #define AIPS_PACRE_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1158 #define AIPS_PACRE_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1159 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
<> 144:ef7eb2e8f9f7 1160 #define AIPS_PACRE_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1161 #define AIPS_PACRE_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1162 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
<> 144:ef7eb2e8f9f7 1163 #define AIPS_PACRE_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1164 #define AIPS_PACRE_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1165 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
<> 144:ef7eb2e8f9f7 1166 #define AIPS_PACRE_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1167 #define AIPS_PACRE_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1168 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
<> 144:ef7eb2e8f9f7 1169 #define AIPS_PACRE_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1170 #define AIPS_PACRE_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1171 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
<> 144:ef7eb2e8f9f7 1172 #define AIPS_PACRE_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1173 #define AIPS_PACRE_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1174 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
<> 144:ef7eb2e8f9f7 1175 #define AIPS_PACRE_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1176 #define AIPS_PACRE_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1177 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
<> 144:ef7eb2e8f9f7 1178 #define AIPS_PACRE_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1179 #define AIPS_PACRE_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1180 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /*! @name PACRF - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1183 #define AIPS_PACRF_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1184 #define AIPS_PACRF_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1185 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
<> 144:ef7eb2e8f9f7 1186 #define AIPS_PACRF_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1187 #define AIPS_PACRF_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1188 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
<> 144:ef7eb2e8f9f7 1189 #define AIPS_PACRF_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1190 #define AIPS_PACRF_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1191 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
<> 144:ef7eb2e8f9f7 1192 #define AIPS_PACRF_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1193 #define AIPS_PACRF_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1194 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
<> 144:ef7eb2e8f9f7 1195 #define AIPS_PACRF_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1196 #define AIPS_PACRF_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1197 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
<> 144:ef7eb2e8f9f7 1198 #define AIPS_PACRF_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1199 #define AIPS_PACRF_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1200 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
<> 144:ef7eb2e8f9f7 1201 #define AIPS_PACRF_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1202 #define AIPS_PACRF_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1203 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
<> 144:ef7eb2e8f9f7 1204 #define AIPS_PACRF_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1205 #define AIPS_PACRF_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1206 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
<> 144:ef7eb2e8f9f7 1207 #define AIPS_PACRF_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1208 #define AIPS_PACRF_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1209 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
<> 144:ef7eb2e8f9f7 1210 #define AIPS_PACRF_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1211 #define AIPS_PACRF_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1212 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
<> 144:ef7eb2e8f9f7 1213 #define AIPS_PACRF_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1214 #define AIPS_PACRF_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1215 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
<> 144:ef7eb2e8f9f7 1216 #define AIPS_PACRF_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1217 #define AIPS_PACRF_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1218 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
<> 144:ef7eb2e8f9f7 1219 #define AIPS_PACRF_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1220 #define AIPS_PACRF_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1221 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
<> 144:ef7eb2e8f9f7 1222 #define AIPS_PACRF_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1223 #define AIPS_PACRF_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1224 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
<> 144:ef7eb2e8f9f7 1225 #define AIPS_PACRF_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1226 #define AIPS_PACRF_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1227 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
<> 144:ef7eb2e8f9f7 1228 #define AIPS_PACRF_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1229 #define AIPS_PACRF_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1230 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
<> 144:ef7eb2e8f9f7 1231 #define AIPS_PACRF_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1232 #define AIPS_PACRF_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1233 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
<> 144:ef7eb2e8f9f7 1234 #define AIPS_PACRF_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1235 #define AIPS_PACRF_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1236 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
<> 144:ef7eb2e8f9f7 1237 #define AIPS_PACRF_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1238 #define AIPS_PACRF_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1239 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
<> 144:ef7eb2e8f9f7 1240 #define AIPS_PACRF_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1241 #define AIPS_PACRF_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1242 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
<> 144:ef7eb2e8f9f7 1243 #define AIPS_PACRF_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1244 #define AIPS_PACRF_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1245 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
<> 144:ef7eb2e8f9f7 1246 #define AIPS_PACRF_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1247 #define AIPS_PACRF_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1248 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
<> 144:ef7eb2e8f9f7 1249 #define AIPS_PACRF_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1250 #define AIPS_PACRF_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1251 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
<> 144:ef7eb2e8f9f7 1252 #define AIPS_PACRF_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1253 #define AIPS_PACRF_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1254 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 /*! @name PACRG - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1257 #define AIPS_PACRG_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1258 #define AIPS_PACRG_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1259 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
<> 144:ef7eb2e8f9f7 1260 #define AIPS_PACRG_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1261 #define AIPS_PACRG_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1262 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
<> 144:ef7eb2e8f9f7 1263 #define AIPS_PACRG_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1264 #define AIPS_PACRG_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1265 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
<> 144:ef7eb2e8f9f7 1266 #define AIPS_PACRG_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1267 #define AIPS_PACRG_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1268 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
<> 144:ef7eb2e8f9f7 1269 #define AIPS_PACRG_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1270 #define AIPS_PACRG_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1271 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
<> 144:ef7eb2e8f9f7 1272 #define AIPS_PACRG_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1273 #define AIPS_PACRG_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1274 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
<> 144:ef7eb2e8f9f7 1275 #define AIPS_PACRG_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1276 #define AIPS_PACRG_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1277 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
<> 144:ef7eb2e8f9f7 1278 #define AIPS_PACRG_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1279 #define AIPS_PACRG_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1280 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
<> 144:ef7eb2e8f9f7 1281 #define AIPS_PACRG_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1282 #define AIPS_PACRG_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1283 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
<> 144:ef7eb2e8f9f7 1284 #define AIPS_PACRG_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1285 #define AIPS_PACRG_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1286 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
<> 144:ef7eb2e8f9f7 1287 #define AIPS_PACRG_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1288 #define AIPS_PACRG_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1289 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
<> 144:ef7eb2e8f9f7 1290 #define AIPS_PACRG_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1291 #define AIPS_PACRG_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1292 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
<> 144:ef7eb2e8f9f7 1293 #define AIPS_PACRG_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1294 #define AIPS_PACRG_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1295 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
<> 144:ef7eb2e8f9f7 1296 #define AIPS_PACRG_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1297 #define AIPS_PACRG_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1298 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
<> 144:ef7eb2e8f9f7 1299 #define AIPS_PACRG_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1300 #define AIPS_PACRG_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1301 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
<> 144:ef7eb2e8f9f7 1302 #define AIPS_PACRG_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1303 #define AIPS_PACRG_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1304 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
<> 144:ef7eb2e8f9f7 1305 #define AIPS_PACRG_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1306 #define AIPS_PACRG_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1307 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
<> 144:ef7eb2e8f9f7 1308 #define AIPS_PACRG_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1309 #define AIPS_PACRG_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1310 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
<> 144:ef7eb2e8f9f7 1311 #define AIPS_PACRG_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1312 #define AIPS_PACRG_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1313 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
<> 144:ef7eb2e8f9f7 1314 #define AIPS_PACRG_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1315 #define AIPS_PACRG_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1316 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
<> 144:ef7eb2e8f9f7 1317 #define AIPS_PACRG_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1318 #define AIPS_PACRG_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1319 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
<> 144:ef7eb2e8f9f7 1320 #define AIPS_PACRG_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1321 #define AIPS_PACRG_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1322 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
<> 144:ef7eb2e8f9f7 1323 #define AIPS_PACRG_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1324 #define AIPS_PACRG_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1325 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
<> 144:ef7eb2e8f9f7 1326 #define AIPS_PACRG_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1327 #define AIPS_PACRG_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1328 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /*! @name PACRH - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1331 #define AIPS_PACRH_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1332 #define AIPS_PACRH_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1333 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
<> 144:ef7eb2e8f9f7 1334 #define AIPS_PACRH_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1335 #define AIPS_PACRH_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1336 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
<> 144:ef7eb2e8f9f7 1337 #define AIPS_PACRH_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1338 #define AIPS_PACRH_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1339 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
<> 144:ef7eb2e8f9f7 1340 #define AIPS_PACRH_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1341 #define AIPS_PACRH_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1342 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
<> 144:ef7eb2e8f9f7 1343 #define AIPS_PACRH_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1344 #define AIPS_PACRH_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1345 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
<> 144:ef7eb2e8f9f7 1346 #define AIPS_PACRH_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1347 #define AIPS_PACRH_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1348 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
<> 144:ef7eb2e8f9f7 1349 #define AIPS_PACRH_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1350 #define AIPS_PACRH_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1351 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
<> 144:ef7eb2e8f9f7 1352 #define AIPS_PACRH_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1353 #define AIPS_PACRH_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1354 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
<> 144:ef7eb2e8f9f7 1355 #define AIPS_PACRH_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1356 #define AIPS_PACRH_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1357 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
<> 144:ef7eb2e8f9f7 1358 #define AIPS_PACRH_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1359 #define AIPS_PACRH_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1360 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
<> 144:ef7eb2e8f9f7 1361 #define AIPS_PACRH_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1362 #define AIPS_PACRH_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1363 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
<> 144:ef7eb2e8f9f7 1364 #define AIPS_PACRH_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1365 #define AIPS_PACRH_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1366 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
<> 144:ef7eb2e8f9f7 1367 #define AIPS_PACRH_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1368 #define AIPS_PACRH_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1369 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
<> 144:ef7eb2e8f9f7 1370 #define AIPS_PACRH_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1371 #define AIPS_PACRH_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1372 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
<> 144:ef7eb2e8f9f7 1373 #define AIPS_PACRH_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1374 #define AIPS_PACRH_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1375 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
<> 144:ef7eb2e8f9f7 1376 #define AIPS_PACRH_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1377 #define AIPS_PACRH_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1378 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
<> 144:ef7eb2e8f9f7 1379 #define AIPS_PACRH_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1380 #define AIPS_PACRH_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1381 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
<> 144:ef7eb2e8f9f7 1382 #define AIPS_PACRH_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1383 #define AIPS_PACRH_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1384 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
<> 144:ef7eb2e8f9f7 1385 #define AIPS_PACRH_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1386 #define AIPS_PACRH_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1387 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
<> 144:ef7eb2e8f9f7 1388 #define AIPS_PACRH_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1389 #define AIPS_PACRH_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1390 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
<> 144:ef7eb2e8f9f7 1391 #define AIPS_PACRH_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1392 #define AIPS_PACRH_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1393 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
<> 144:ef7eb2e8f9f7 1394 #define AIPS_PACRH_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1395 #define AIPS_PACRH_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1396 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
<> 144:ef7eb2e8f9f7 1397 #define AIPS_PACRH_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1398 #define AIPS_PACRH_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1399 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
<> 144:ef7eb2e8f9f7 1400 #define AIPS_PACRH_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1401 #define AIPS_PACRH_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1402 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
<> 144:ef7eb2e8f9f7 1403
<> 144:ef7eb2e8f9f7 1404 /*! @name PACRI - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1405 #define AIPS_PACRI_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1406 #define AIPS_PACRI_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1407 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
<> 144:ef7eb2e8f9f7 1408 #define AIPS_PACRI_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1409 #define AIPS_PACRI_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1410 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
<> 144:ef7eb2e8f9f7 1411 #define AIPS_PACRI_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1412 #define AIPS_PACRI_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1413 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
<> 144:ef7eb2e8f9f7 1414 #define AIPS_PACRI_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1415 #define AIPS_PACRI_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1416 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
<> 144:ef7eb2e8f9f7 1417 #define AIPS_PACRI_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1418 #define AIPS_PACRI_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1419 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
<> 144:ef7eb2e8f9f7 1420 #define AIPS_PACRI_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1421 #define AIPS_PACRI_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1422 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
<> 144:ef7eb2e8f9f7 1423 #define AIPS_PACRI_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1424 #define AIPS_PACRI_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1425 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
<> 144:ef7eb2e8f9f7 1426 #define AIPS_PACRI_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1427 #define AIPS_PACRI_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1428 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
<> 144:ef7eb2e8f9f7 1429 #define AIPS_PACRI_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1430 #define AIPS_PACRI_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1431 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
<> 144:ef7eb2e8f9f7 1432 #define AIPS_PACRI_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1433 #define AIPS_PACRI_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1434 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
<> 144:ef7eb2e8f9f7 1435 #define AIPS_PACRI_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1436 #define AIPS_PACRI_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1437 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
<> 144:ef7eb2e8f9f7 1438 #define AIPS_PACRI_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1439 #define AIPS_PACRI_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1440 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
<> 144:ef7eb2e8f9f7 1441 #define AIPS_PACRI_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1442 #define AIPS_PACRI_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1443 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
<> 144:ef7eb2e8f9f7 1444 #define AIPS_PACRI_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1445 #define AIPS_PACRI_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1446 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
<> 144:ef7eb2e8f9f7 1447 #define AIPS_PACRI_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1448 #define AIPS_PACRI_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1449 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
<> 144:ef7eb2e8f9f7 1450 #define AIPS_PACRI_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1451 #define AIPS_PACRI_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1452 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
<> 144:ef7eb2e8f9f7 1453 #define AIPS_PACRI_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1454 #define AIPS_PACRI_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1455 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
<> 144:ef7eb2e8f9f7 1456 #define AIPS_PACRI_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1457 #define AIPS_PACRI_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1458 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
<> 144:ef7eb2e8f9f7 1459 #define AIPS_PACRI_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1460 #define AIPS_PACRI_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1461 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
<> 144:ef7eb2e8f9f7 1462 #define AIPS_PACRI_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1463 #define AIPS_PACRI_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1464 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
<> 144:ef7eb2e8f9f7 1465 #define AIPS_PACRI_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1466 #define AIPS_PACRI_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1467 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
<> 144:ef7eb2e8f9f7 1468 #define AIPS_PACRI_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1469 #define AIPS_PACRI_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1470 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
<> 144:ef7eb2e8f9f7 1471 #define AIPS_PACRI_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1472 #define AIPS_PACRI_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1473 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
<> 144:ef7eb2e8f9f7 1474 #define AIPS_PACRI_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1475 #define AIPS_PACRI_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1476 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /*! @name PACRJ - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1479 #define AIPS_PACRJ_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1480 #define AIPS_PACRJ_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1481 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
<> 144:ef7eb2e8f9f7 1482 #define AIPS_PACRJ_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1483 #define AIPS_PACRJ_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1484 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
<> 144:ef7eb2e8f9f7 1485 #define AIPS_PACRJ_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1486 #define AIPS_PACRJ_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1487 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
<> 144:ef7eb2e8f9f7 1488 #define AIPS_PACRJ_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1489 #define AIPS_PACRJ_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1490 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
<> 144:ef7eb2e8f9f7 1491 #define AIPS_PACRJ_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1492 #define AIPS_PACRJ_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1493 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
<> 144:ef7eb2e8f9f7 1494 #define AIPS_PACRJ_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1495 #define AIPS_PACRJ_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1496 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
<> 144:ef7eb2e8f9f7 1497 #define AIPS_PACRJ_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1498 #define AIPS_PACRJ_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1499 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
<> 144:ef7eb2e8f9f7 1500 #define AIPS_PACRJ_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1501 #define AIPS_PACRJ_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1502 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
<> 144:ef7eb2e8f9f7 1503 #define AIPS_PACRJ_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1504 #define AIPS_PACRJ_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1505 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
<> 144:ef7eb2e8f9f7 1506 #define AIPS_PACRJ_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1507 #define AIPS_PACRJ_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1508 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
<> 144:ef7eb2e8f9f7 1509 #define AIPS_PACRJ_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1510 #define AIPS_PACRJ_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1511 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
<> 144:ef7eb2e8f9f7 1512 #define AIPS_PACRJ_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1513 #define AIPS_PACRJ_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1514 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
<> 144:ef7eb2e8f9f7 1515 #define AIPS_PACRJ_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1516 #define AIPS_PACRJ_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1517 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
<> 144:ef7eb2e8f9f7 1518 #define AIPS_PACRJ_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1519 #define AIPS_PACRJ_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1520 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
<> 144:ef7eb2e8f9f7 1521 #define AIPS_PACRJ_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1522 #define AIPS_PACRJ_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1523 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
<> 144:ef7eb2e8f9f7 1524 #define AIPS_PACRJ_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1525 #define AIPS_PACRJ_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1526 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
<> 144:ef7eb2e8f9f7 1527 #define AIPS_PACRJ_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1528 #define AIPS_PACRJ_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1529 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
<> 144:ef7eb2e8f9f7 1530 #define AIPS_PACRJ_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1531 #define AIPS_PACRJ_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1532 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
<> 144:ef7eb2e8f9f7 1533 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1534 #define AIPS_PACRJ_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1535 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
<> 144:ef7eb2e8f9f7 1536 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1537 #define AIPS_PACRJ_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1538 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
<> 144:ef7eb2e8f9f7 1539 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1540 #define AIPS_PACRJ_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1541 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
<> 144:ef7eb2e8f9f7 1542 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1543 #define AIPS_PACRJ_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1544 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
<> 144:ef7eb2e8f9f7 1545 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1546 #define AIPS_PACRJ_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1547 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
<> 144:ef7eb2e8f9f7 1548 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1549 #define AIPS_PACRJ_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1550 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 /*! @name PACRK - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1553 #define AIPS_PACRK_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1554 #define AIPS_PACRK_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1555 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
<> 144:ef7eb2e8f9f7 1556 #define AIPS_PACRK_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1557 #define AIPS_PACRK_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1558 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
<> 144:ef7eb2e8f9f7 1559 #define AIPS_PACRK_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1560 #define AIPS_PACRK_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1561 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
<> 144:ef7eb2e8f9f7 1562 #define AIPS_PACRK_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1563 #define AIPS_PACRK_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1564 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
<> 144:ef7eb2e8f9f7 1565 #define AIPS_PACRK_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1566 #define AIPS_PACRK_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1567 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
<> 144:ef7eb2e8f9f7 1568 #define AIPS_PACRK_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1569 #define AIPS_PACRK_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1570 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
<> 144:ef7eb2e8f9f7 1571 #define AIPS_PACRK_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1572 #define AIPS_PACRK_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1573 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
<> 144:ef7eb2e8f9f7 1574 #define AIPS_PACRK_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1575 #define AIPS_PACRK_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1576 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
<> 144:ef7eb2e8f9f7 1577 #define AIPS_PACRK_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1578 #define AIPS_PACRK_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1579 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
<> 144:ef7eb2e8f9f7 1580 #define AIPS_PACRK_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1581 #define AIPS_PACRK_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1582 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
<> 144:ef7eb2e8f9f7 1583 #define AIPS_PACRK_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1584 #define AIPS_PACRK_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1585 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
<> 144:ef7eb2e8f9f7 1586 #define AIPS_PACRK_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1587 #define AIPS_PACRK_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1588 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
<> 144:ef7eb2e8f9f7 1589 #define AIPS_PACRK_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1590 #define AIPS_PACRK_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1591 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
<> 144:ef7eb2e8f9f7 1592 #define AIPS_PACRK_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1593 #define AIPS_PACRK_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1594 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
<> 144:ef7eb2e8f9f7 1595 #define AIPS_PACRK_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1596 #define AIPS_PACRK_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1597 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
<> 144:ef7eb2e8f9f7 1598 #define AIPS_PACRK_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1599 #define AIPS_PACRK_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1600 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
<> 144:ef7eb2e8f9f7 1601 #define AIPS_PACRK_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1602 #define AIPS_PACRK_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1603 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
<> 144:ef7eb2e8f9f7 1604 #define AIPS_PACRK_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1605 #define AIPS_PACRK_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1606 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
<> 144:ef7eb2e8f9f7 1607 #define AIPS_PACRK_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1608 #define AIPS_PACRK_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1609 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
<> 144:ef7eb2e8f9f7 1610 #define AIPS_PACRK_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1611 #define AIPS_PACRK_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1612 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
<> 144:ef7eb2e8f9f7 1613 #define AIPS_PACRK_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1614 #define AIPS_PACRK_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1615 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
<> 144:ef7eb2e8f9f7 1616 #define AIPS_PACRK_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1617 #define AIPS_PACRK_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1618 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
<> 144:ef7eb2e8f9f7 1619 #define AIPS_PACRK_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1620 #define AIPS_PACRK_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1621 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
<> 144:ef7eb2e8f9f7 1622 #define AIPS_PACRK_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1623 #define AIPS_PACRK_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1624 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 /*! @name PACRL - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1627 #define AIPS_PACRL_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1628 #define AIPS_PACRL_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1629 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
<> 144:ef7eb2e8f9f7 1630 #define AIPS_PACRL_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1631 #define AIPS_PACRL_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1632 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
<> 144:ef7eb2e8f9f7 1633 #define AIPS_PACRL_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1634 #define AIPS_PACRL_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1635 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
<> 144:ef7eb2e8f9f7 1636 #define AIPS_PACRL_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1637 #define AIPS_PACRL_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1638 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
<> 144:ef7eb2e8f9f7 1639 #define AIPS_PACRL_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1640 #define AIPS_PACRL_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1641 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
<> 144:ef7eb2e8f9f7 1642 #define AIPS_PACRL_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1643 #define AIPS_PACRL_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1644 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
<> 144:ef7eb2e8f9f7 1645 #define AIPS_PACRL_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1646 #define AIPS_PACRL_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1647 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
<> 144:ef7eb2e8f9f7 1648 #define AIPS_PACRL_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1649 #define AIPS_PACRL_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1650 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
<> 144:ef7eb2e8f9f7 1651 #define AIPS_PACRL_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1652 #define AIPS_PACRL_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1653 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
<> 144:ef7eb2e8f9f7 1654 #define AIPS_PACRL_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1655 #define AIPS_PACRL_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1656 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
<> 144:ef7eb2e8f9f7 1657 #define AIPS_PACRL_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1658 #define AIPS_PACRL_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1659 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
<> 144:ef7eb2e8f9f7 1660 #define AIPS_PACRL_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1661 #define AIPS_PACRL_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1662 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
<> 144:ef7eb2e8f9f7 1663 #define AIPS_PACRL_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1664 #define AIPS_PACRL_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1665 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
<> 144:ef7eb2e8f9f7 1666 #define AIPS_PACRL_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1667 #define AIPS_PACRL_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1668 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
<> 144:ef7eb2e8f9f7 1669 #define AIPS_PACRL_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1670 #define AIPS_PACRL_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1671 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
<> 144:ef7eb2e8f9f7 1672 #define AIPS_PACRL_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1673 #define AIPS_PACRL_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1674 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
<> 144:ef7eb2e8f9f7 1675 #define AIPS_PACRL_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1676 #define AIPS_PACRL_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1677 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
<> 144:ef7eb2e8f9f7 1678 #define AIPS_PACRL_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1679 #define AIPS_PACRL_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1680 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
<> 144:ef7eb2e8f9f7 1681 #define AIPS_PACRL_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1682 #define AIPS_PACRL_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1683 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
<> 144:ef7eb2e8f9f7 1684 #define AIPS_PACRL_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1685 #define AIPS_PACRL_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1686 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
<> 144:ef7eb2e8f9f7 1687 #define AIPS_PACRL_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1688 #define AIPS_PACRL_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1689 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
<> 144:ef7eb2e8f9f7 1690 #define AIPS_PACRL_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1691 #define AIPS_PACRL_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1692 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
<> 144:ef7eb2e8f9f7 1693 #define AIPS_PACRL_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1694 #define AIPS_PACRL_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1695 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
<> 144:ef7eb2e8f9f7 1696 #define AIPS_PACRL_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1697 #define AIPS_PACRL_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1698 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /*! @name PACRM - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1701 #define AIPS_PACRM_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1702 #define AIPS_PACRM_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1703 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
<> 144:ef7eb2e8f9f7 1704 #define AIPS_PACRM_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1705 #define AIPS_PACRM_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1706 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
<> 144:ef7eb2e8f9f7 1707 #define AIPS_PACRM_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1708 #define AIPS_PACRM_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1709 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
<> 144:ef7eb2e8f9f7 1710 #define AIPS_PACRM_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1711 #define AIPS_PACRM_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1712 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
<> 144:ef7eb2e8f9f7 1713 #define AIPS_PACRM_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1714 #define AIPS_PACRM_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1715 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
<> 144:ef7eb2e8f9f7 1716 #define AIPS_PACRM_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1717 #define AIPS_PACRM_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1718 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
<> 144:ef7eb2e8f9f7 1719 #define AIPS_PACRM_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1720 #define AIPS_PACRM_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1721 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
<> 144:ef7eb2e8f9f7 1722 #define AIPS_PACRM_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1723 #define AIPS_PACRM_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1724 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
<> 144:ef7eb2e8f9f7 1725 #define AIPS_PACRM_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1726 #define AIPS_PACRM_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1727 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
<> 144:ef7eb2e8f9f7 1728 #define AIPS_PACRM_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1729 #define AIPS_PACRM_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1730 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
<> 144:ef7eb2e8f9f7 1731 #define AIPS_PACRM_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1732 #define AIPS_PACRM_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1733 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
<> 144:ef7eb2e8f9f7 1734 #define AIPS_PACRM_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1735 #define AIPS_PACRM_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1736 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
<> 144:ef7eb2e8f9f7 1737 #define AIPS_PACRM_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1738 #define AIPS_PACRM_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1739 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
<> 144:ef7eb2e8f9f7 1740 #define AIPS_PACRM_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1741 #define AIPS_PACRM_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1742 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
<> 144:ef7eb2e8f9f7 1743 #define AIPS_PACRM_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1744 #define AIPS_PACRM_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1745 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
<> 144:ef7eb2e8f9f7 1746 #define AIPS_PACRM_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1747 #define AIPS_PACRM_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1748 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
<> 144:ef7eb2e8f9f7 1749 #define AIPS_PACRM_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1750 #define AIPS_PACRM_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1751 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
<> 144:ef7eb2e8f9f7 1752 #define AIPS_PACRM_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1753 #define AIPS_PACRM_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1754 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
<> 144:ef7eb2e8f9f7 1755 #define AIPS_PACRM_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1756 #define AIPS_PACRM_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1757 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
<> 144:ef7eb2e8f9f7 1758 #define AIPS_PACRM_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1759 #define AIPS_PACRM_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1760 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
<> 144:ef7eb2e8f9f7 1761 #define AIPS_PACRM_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1762 #define AIPS_PACRM_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1763 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
<> 144:ef7eb2e8f9f7 1764 #define AIPS_PACRM_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1765 #define AIPS_PACRM_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1766 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
<> 144:ef7eb2e8f9f7 1767 #define AIPS_PACRM_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1768 #define AIPS_PACRM_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1769 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
<> 144:ef7eb2e8f9f7 1770 #define AIPS_PACRM_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1771 #define AIPS_PACRM_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1772 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
<> 144:ef7eb2e8f9f7 1773
<> 144:ef7eb2e8f9f7 1774 /*! @name PACRN - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1775 #define AIPS_PACRN_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1776 #define AIPS_PACRN_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1777 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
<> 144:ef7eb2e8f9f7 1778 #define AIPS_PACRN_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1779 #define AIPS_PACRN_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1780 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
<> 144:ef7eb2e8f9f7 1781 #define AIPS_PACRN_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1782 #define AIPS_PACRN_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1783 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
<> 144:ef7eb2e8f9f7 1784 #define AIPS_PACRN_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1785 #define AIPS_PACRN_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1786 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
<> 144:ef7eb2e8f9f7 1787 #define AIPS_PACRN_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1788 #define AIPS_PACRN_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1789 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
<> 144:ef7eb2e8f9f7 1790 #define AIPS_PACRN_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1791 #define AIPS_PACRN_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1792 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
<> 144:ef7eb2e8f9f7 1793 #define AIPS_PACRN_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1794 #define AIPS_PACRN_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1795 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
<> 144:ef7eb2e8f9f7 1796 #define AIPS_PACRN_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1797 #define AIPS_PACRN_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1798 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
<> 144:ef7eb2e8f9f7 1799 #define AIPS_PACRN_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1800 #define AIPS_PACRN_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1801 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
<> 144:ef7eb2e8f9f7 1802 #define AIPS_PACRN_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1803 #define AIPS_PACRN_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1804 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
<> 144:ef7eb2e8f9f7 1805 #define AIPS_PACRN_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1806 #define AIPS_PACRN_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1807 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
<> 144:ef7eb2e8f9f7 1808 #define AIPS_PACRN_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1809 #define AIPS_PACRN_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1810 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
<> 144:ef7eb2e8f9f7 1811 #define AIPS_PACRN_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1812 #define AIPS_PACRN_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1813 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
<> 144:ef7eb2e8f9f7 1814 #define AIPS_PACRN_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1815 #define AIPS_PACRN_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1816 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
<> 144:ef7eb2e8f9f7 1817 #define AIPS_PACRN_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1818 #define AIPS_PACRN_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1819 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
<> 144:ef7eb2e8f9f7 1820 #define AIPS_PACRN_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1821 #define AIPS_PACRN_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1822 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
<> 144:ef7eb2e8f9f7 1823 #define AIPS_PACRN_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1824 #define AIPS_PACRN_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1825 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
<> 144:ef7eb2e8f9f7 1826 #define AIPS_PACRN_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1827 #define AIPS_PACRN_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1828 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
<> 144:ef7eb2e8f9f7 1829 #define AIPS_PACRN_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1830 #define AIPS_PACRN_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1831 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
<> 144:ef7eb2e8f9f7 1832 #define AIPS_PACRN_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1833 #define AIPS_PACRN_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1834 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
<> 144:ef7eb2e8f9f7 1835 #define AIPS_PACRN_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1836 #define AIPS_PACRN_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1837 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
<> 144:ef7eb2e8f9f7 1838 #define AIPS_PACRN_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1839 #define AIPS_PACRN_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1840 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
<> 144:ef7eb2e8f9f7 1841 #define AIPS_PACRN_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1842 #define AIPS_PACRN_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1843 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
<> 144:ef7eb2e8f9f7 1844 #define AIPS_PACRN_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1845 #define AIPS_PACRN_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1846 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /*! @name PACRO - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1849 #define AIPS_PACRO_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1850 #define AIPS_PACRO_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1851 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
<> 144:ef7eb2e8f9f7 1852 #define AIPS_PACRO_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1853 #define AIPS_PACRO_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1854 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
<> 144:ef7eb2e8f9f7 1855 #define AIPS_PACRO_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1856 #define AIPS_PACRO_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1857 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
<> 144:ef7eb2e8f9f7 1858 #define AIPS_PACRO_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1859 #define AIPS_PACRO_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1860 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
<> 144:ef7eb2e8f9f7 1861 #define AIPS_PACRO_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1862 #define AIPS_PACRO_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1863 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
<> 144:ef7eb2e8f9f7 1864 #define AIPS_PACRO_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1865 #define AIPS_PACRO_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1866 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
<> 144:ef7eb2e8f9f7 1867 #define AIPS_PACRO_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1868 #define AIPS_PACRO_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1869 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
<> 144:ef7eb2e8f9f7 1870 #define AIPS_PACRO_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1871 #define AIPS_PACRO_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1872 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
<> 144:ef7eb2e8f9f7 1873 #define AIPS_PACRO_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1874 #define AIPS_PACRO_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1875 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
<> 144:ef7eb2e8f9f7 1876 #define AIPS_PACRO_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1877 #define AIPS_PACRO_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1878 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
<> 144:ef7eb2e8f9f7 1879 #define AIPS_PACRO_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1880 #define AIPS_PACRO_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1881 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
<> 144:ef7eb2e8f9f7 1882 #define AIPS_PACRO_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1883 #define AIPS_PACRO_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1884 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
<> 144:ef7eb2e8f9f7 1885 #define AIPS_PACRO_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1886 #define AIPS_PACRO_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1887 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
<> 144:ef7eb2e8f9f7 1888 #define AIPS_PACRO_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1889 #define AIPS_PACRO_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1890 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
<> 144:ef7eb2e8f9f7 1891 #define AIPS_PACRO_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1892 #define AIPS_PACRO_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1893 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
<> 144:ef7eb2e8f9f7 1894 #define AIPS_PACRO_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1895 #define AIPS_PACRO_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1896 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
<> 144:ef7eb2e8f9f7 1897 #define AIPS_PACRO_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1898 #define AIPS_PACRO_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1899 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
<> 144:ef7eb2e8f9f7 1900 #define AIPS_PACRO_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1901 #define AIPS_PACRO_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1902 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
<> 144:ef7eb2e8f9f7 1903 #define AIPS_PACRO_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1904 #define AIPS_PACRO_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1905 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
<> 144:ef7eb2e8f9f7 1906 #define AIPS_PACRO_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1907 #define AIPS_PACRO_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1908 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
<> 144:ef7eb2e8f9f7 1909 #define AIPS_PACRO_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1910 #define AIPS_PACRO_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1911 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
<> 144:ef7eb2e8f9f7 1912 #define AIPS_PACRO_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1913 #define AIPS_PACRO_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1914 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
<> 144:ef7eb2e8f9f7 1915 #define AIPS_PACRO_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1916 #define AIPS_PACRO_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1917 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
<> 144:ef7eb2e8f9f7 1918 #define AIPS_PACRO_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1919 #define AIPS_PACRO_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1920 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /*! @name PACRP - Peripheral Access Control Register */
<> 144:ef7eb2e8f9f7 1923 #define AIPS_PACRP_TP7_MASK (0x1U)
<> 144:ef7eb2e8f9f7 1924 #define AIPS_PACRP_TP7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 1925 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
<> 144:ef7eb2e8f9f7 1926 #define AIPS_PACRP_WP7_MASK (0x2U)
<> 144:ef7eb2e8f9f7 1927 #define AIPS_PACRP_WP7_SHIFT (1U)
<> 144:ef7eb2e8f9f7 1928 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
<> 144:ef7eb2e8f9f7 1929 #define AIPS_PACRP_SP7_MASK (0x4U)
<> 144:ef7eb2e8f9f7 1930 #define AIPS_PACRP_SP7_SHIFT (2U)
<> 144:ef7eb2e8f9f7 1931 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
<> 144:ef7eb2e8f9f7 1932 #define AIPS_PACRP_TP6_MASK (0x10U)
<> 144:ef7eb2e8f9f7 1933 #define AIPS_PACRP_TP6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 1934 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
<> 144:ef7eb2e8f9f7 1935 #define AIPS_PACRP_WP6_MASK (0x20U)
<> 144:ef7eb2e8f9f7 1936 #define AIPS_PACRP_WP6_SHIFT (5U)
<> 144:ef7eb2e8f9f7 1937 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
<> 144:ef7eb2e8f9f7 1938 #define AIPS_PACRP_SP6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 1939 #define AIPS_PACRP_SP6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 1940 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
<> 144:ef7eb2e8f9f7 1941 #define AIPS_PACRP_TP5_MASK (0x100U)
<> 144:ef7eb2e8f9f7 1942 #define AIPS_PACRP_TP5_SHIFT (8U)
<> 144:ef7eb2e8f9f7 1943 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
<> 144:ef7eb2e8f9f7 1944 #define AIPS_PACRP_WP5_MASK (0x200U)
<> 144:ef7eb2e8f9f7 1945 #define AIPS_PACRP_WP5_SHIFT (9U)
<> 144:ef7eb2e8f9f7 1946 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
<> 144:ef7eb2e8f9f7 1947 #define AIPS_PACRP_SP5_MASK (0x400U)
<> 144:ef7eb2e8f9f7 1948 #define AIPS_PACRP_SP5_SHIFT (10U)
<> 144:ef7eb2e8f9f7 1949 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
<> 144:ef7eb2e8f9f7 1950 #define AIPS_PACRP_TP4_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 1951 #define AIPS_PACRP_TP4_SHIFT (12U)
<> 144:ef7eb2e8f9f7 1952 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
<> 144:ef7eb2e8f9f7 1953 #define AIPS_PACRP_WP4_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 1954 #define AIPS_PACRP_WP4_SHIFT (13U)
<> 144:ef7eb2e8f9f7 1955 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
<> 144:ef7eb2e8f9f7 1956 #define AIPS_PACRP_SP4_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 1957 #define AIPS_PACRP_SP4_SHIFT (14U)
<> 144:ef7eb2e8f9f7 1958 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
<> 144:ef7eb2e8f9f7 1959 #define AIPS_PACRP_TP3_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 1960 #define AIPS_PACRP_TP3_SHIFT (16U)
<> 144:ef7eb2e8f9f7 1961 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
<> 144:ef7eb2e8f9f7 1962 #define AIPS_PACRP_WP3_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 1963 #define AIPS_PACRP_WP3_SHIFT (17U)
<> 144:ef7eb2e8f9f7 1964 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
<> 144:ef7eb2e8f9f7 1965 #define AIPS_PACRP_SP3_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 1966 #define AIPS_PACRP_SP3_SHIFT (18U)
<> 144:ef7eb2e8f9f7 1967 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
<> 144:ef7eb2e8f9f7 1968 #define AIPS_PACRP_TP2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 1969 #define AIPS_PACRP_TP2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 1970 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
<> 144:ef7eb2e8f9f7 1971 #define AIPS_PACRP_WP2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 1972 #define AIPS_PACRP_WP2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 1973 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
<> 144:ef7eb2e8f9f7 1974 #define AIPS_PACRP_SP2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 1975 #define AIPS_PACRP_SP2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 1976 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
<> 144:ef7eb2e8f9f7 1977 #define AIPS_PACRP_TP1_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 1978 #define AIPS_PACRP_TP1_SHIFT (24U)
<> 144:ef7eb2e8f9f7 1979 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
<> 144:ef7eb2e8f9f7 1980 #define AIPS_PACRP_WP1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 1981 #define AIPS_PACRP_WP1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 1982 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
<> 144:ef7eb2e8f9f7 1983 #define AIPS_PACRP_SP1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 1984 #define AIPS_PACRP_SP1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 1985 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
<> 144:ef7eb2e8f9f7 1986 #define AIPS_PACRP_TP0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 1987 #define AIPS_PACRP_TP0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 1988 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
<> 144:ef7eb2e8f9f7 1989 #define AIPS_PACRP_WP0_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 1990 #define AIPS_PACRP_WP0_SHIFT (29U)
<> 144:ef7eb2e8f9f7 1991 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
<> 144:ef7eb2e8f9f7 1992 #define AIPS_PACRP_SP0_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 1993 #define AIPS_PACRP_SP0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 1994 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
<> 144:ef7eb2e8f9f7 1995
<> 144:ef7eb2e8f9f7 1996
<> 144:ef7eb2e8f9f7 1997 /*!
<> 144:ef7eb2e8f9f7 1998 * @}
<> 144:ef7eb2e8f9f7 1999 */ /* end of group AIPS_Register_Masks */
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /* AIPS - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 2003 /** Peripheral AIPS0 base address */
<> 144:ef7eb2e8f9f7 2004 #define AIPS0_BASE (0x40000000u)
<> 144:ef7eb2e8f9f7 2005 /** Peripheral AIPS0 base pointer */
<> 144:ef7eb2e8f9f7 2006 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
<> 144:ef7eb2e8f9f7 2007 /** Peripheral AIPS1 base address */
<> 144:ef7eb2e8f9f7 2008 #define AIPS1_BASE (0x40080000u)
<> 144:ef7eb2e8f9f7 2009 /** Peripheral AIPS1 base pointer */
<> 144:ef7eb2e8f9f7 2010 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
<> 144:ef7eb2e8f9f7 2011 /** Array initializer of AIPS peripheral base addresses */
<> 144:ef7eb2e8f9f7 2012 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
<> 144:ef7eb2e8f9f7 2013 /** Array initializer of AIPS peripheral base pointers */
<> 144:ef7eb2e8f9f7 2014 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
<> 144:ef7eb2e8f9f7 2015
<> 144:ef7eb2e8f9f7 2016 /*!
<> 144:ef7eb2e8f9f7 2017 * @}
<> 144:ef7eb2e8f9f7 2018 */ /* end of group AIPS_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 2019
<> 144:ef7eb2e8f9f7 2020
<> 144:ef7eb2e8f9f7 2021 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2022 -- AXBS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2023 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2024
<> 144:ef7eb2e8f9f7 2025 /*!
<> 144:ef7eb2e8f9f7 2026 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2027 * @{
<> 144:ef7eb2e8f9f7 2028 */
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /** AXBS - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 2031 typedef struct {
<> 144:ef7eb2e8f9f7 2032 struct { /* offset: 0x0, array step: 0x100 */
<> 144:ef7eb2e8f9f7 2033 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
<> 144:ef7eb2e8f9f7 2034 uint8_t RESERVED_0[12];
<> 144:ef7eb2e8f9f7 2035 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
<> 144:ef7eb2e8f9f7 2036 uint8_t RESERVED_1[236];
<> 144:ef7eb2e8f9f7 2037 } SLAVE[5];
<> 144:ef7eb2e8f9f7 2038 uint8_t RESERVED_0[768];
<> 144:ef7eb2e8f9f7 2039 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
<> 144:ef7eb2e8f9f7 2040 uint8_t RESERVED_1[252];
<> 144:ef7eb2e8f9f7 2041 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
<> 144:ef7eb2e8f9f7 2042 uint8_t RESERVED_2[252];
<> 144:ef7eb2e8f9f7 2043 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
<> 144:ef7eb2e8f9f7 2044 uint8_t RESERVED_3[252];
<> 144:ef7eb2e8f9f7 2045 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
<> 144:ef7eb2e8f9f7 2046 uint8_t RESERVED_4[252];
<> 144:ef7eb2e8f9f7 2047 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
<> 144:ef7eb2e8f9f7 2048 uint8_t RESERVED_5[252];
<> 144:ef7eb2e8f9f7 2049 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
<> 144:ef7eb2e8f9f7 2050 uint8_t RESERVED_6[252];
<> 144:ef7eb2e8f9f7 2051 __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
<> 144:ef7eb2e8f9f7 2052 } AXBS_Type;
<> 144:ef7eb2e8f9f7 2053
<> 144:ef7eb2e8f9f7 2054 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2055 -- AXBS Register Masks
<> 144:ef7eb2e8f9f7 2056 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2057
<> 144:ef7eb2e8f9f7 2058 /*!
<> 144:ef7eb2e8f9f7 2059 * @addtogroup AXBS_Register_Masks AXBS Register Masks
<> 144:ef7eb2e8f9f7 2060 * @{
<> 144:ef7eb2e8f9f7 2061 */
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 /*! @name PRS - Priority Registers Slave */
<> 144:ef7eb2e8f9f7 2064 #define AXBS_PRS_M0_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2065 #define AXBS_PRS_M0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2066 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
<> 144:ef7eb2e8f9f7 2067 #define AXBS_PRS_M1_MASK (0x70U)
<> 144:ef7eb2e8f9f7 2068 #define AXBS_PRS_M1_SHIFT (4U)
<> 144:ef7eb2e8f9f7 2069 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
<> 144:ef7eb2e8f9f7 2070 #define AXBS_PRS_M2_MASK (0x700U)
<> 144:ef7eb2e8f9f7 2071 #define AXBS_PRS_M2_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2072 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
<> 144:ef7eb2e8f9f7 2073 #define AXBS_PRS_M3_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 2074 #define AXBS_PRS_M3_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2075 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
<> 144:ef7eb2e8f9f7 2076 #define AXBS_PRS_M4_MASK (0x70000U)
<> 144:ef7eb2e8f9f7 2077 #define AXBS_PRS_M4_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2078 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
<> 144:ef7eb2e8f9f7 2079 #define AXBS_PRS_M5_MASK (0x700000U)
<> 144:ef7eb2e8f9f7 2080 #define AXBS_PRS_M5_SHIFT (20U)
<> 144:ef7eb2e8f9f7 2081 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
<> 144:ef7eb2e8f9f7 2082 #define AXBS_PRS_M6_MASK (0x7000000U)
<> 144:ef7eb2e8f9f7 2083 #define AXBS_PRS_M6_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2084 #define AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
<> 144:ef7eb2e8f9f7 2085
<> 144:ef7eb2e8f9f7 2086 /* The count of AXBS_PRS */
<> 144:ef7eb2e8f9f7 2087 #define AXBS_PRS_COUNT (5U)
<> 144:ef7eb2e8f9f7 2088
<> 144:ef7eb2e8f9f7 2089 /*! @name CRS - Control Register */
<> 144:ef7eb2e8f9f7 2090 #define AXBS_CRS_PARK_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2091 #define AXBS_CRS_PARK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2092 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
<> 144:ef7eb2e8f9f7 2093 #define AXBS_CRS_PCTL_MASK (0x30U)
<> 144:ef7eb2e8f9f7 2094 #define AXBS_CRS_PCTL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 2095 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
<> 144:ef7eb2e8f9f7 2096 #define AXBS_CRS_ARB_MASK (0x300U)
<> 144:ef7eb2e8f9f7 2097 #define AXBS_CRS_ARB_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2098 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
<> 144:ef7eb2e8f9f7 2099 #define AXBS_CRS_HLP_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 2100 #define AXBS_CRS_HLP_SHIFT (30U)
<> 144:ef7eb2e8f9f7 2101 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
<> 144:ef7eb2e8f9f7 2102 #define AXBS_CRS_RO_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 2103 #define AXBS_CRS_RO_SHIFT (31U)
<> 144:ef7eb2e8f9f7 2104 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
<> 144:ef7eb2e8f9f7 2105
<> 144:ef7eb2e8f9f7 2106 /* The count of AXBS_CRS */
<> 144:ef7eb2e8f9f7 2107 #define AXBS_CRS_COUNT (5U)
<> 144:ef7eb2e8f9f7 2108
<> 144:ef7eb2e8f9f7 2109 /*! @name MGPCR0 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2110 #define AXBS_MGPCR0_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2111 #define AXBS_MGPCR0_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2112 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
<> 144:ef7eb2e8f9f7 2113
<> 144:ef7eb2e8f9f7 2114 /*! @name MGPCR1 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2115 #define AXBS_MGPCR1_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2116 #define AXBS_MGPCR1_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2117 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
<> 144:ef7eb2e8f9f7 2118
<> 144:ef7eb2e8f9f7 2119 /*! @name MGPCR2 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2120 #define AXBS_MGPCR2_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2121 #define AXBS_MGPCR2_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2122 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
<> 144:ef7eb2e8f9f7 2123
<> 144:ef7eb2e8f9f7 2124 /*! @name MGPCR3 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2125 #define AXBS_MGPCR3_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2126 #define AXBS_MGPCR3_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2127 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
<> 144:ef7eb2e8f9f7 2128
<> 144:ef7eb2e8f9f7 2129 /*! @name MGPCR4 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2130 #define AXBS_MGPCR4_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2131 #define AXBS_MGPCR4_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2132 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
<> 144:ef7eb2e8f9f7 2133
<> 144:ef7eb2e8f9f7 2134 /*! @name MGPCR5 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2135 #define AXBS_MGPCR5_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2136 #define AXBS_MGPCR5_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2137 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
<> 144:ef7eb2e8f9f7 2138
<> 144:ef7eb2e8f9f7 2139 /*! @name MGPCR6 - Master General Purpose Control Register */
<> 144:ef7eb2e8f9f7 2140 #define AXBS_MGPCR6_AULB_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2141 #define AXBS_MGPCR6_AULB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2142 #define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
<> 144:ef7eb2e8f9f7 2143
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /*!
<> 144:ef7eb2e8f9f7 2146 * @}
<> 144:ef7eb2e8f9f7 2147 */ /* end of group AXBS_Register_Masks */
<> 144:ef7eb2e8f9f7 2148
<> 144:ef7eb2e8f9f7 2149
<> 144:ef7eb2e8f9f7 2150 /* AXBS - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 2151 /** Peripheral AXBS base address */
<> 144:ef7eb2e8f9f7 2152 #define AXBS_BASE (0x40004000u)
<> 144:ef7eb2e8f9f7 2153 /** Peripheral AXBS base pointer */
<> 144:ef7eb2e8f9f7 2154 #define AXBS ((AXBS_Type *)AXBS_BASE)
<> 144:ef7eb2e8f9f7 2155 /** Array initializer of AXBS peripheral base addresses */
<> 144:ef7eb2e8f9f7 2156 #define AXBS_BASE_ADDRS { AXBS_BASE }
<> 144:ef7eb2e8f9f7 2157 /** Array initializer of AXBS peripheral base pointers */
<> 144:ef7eb2e8f9f7 2158 #define AXBS_BASE_PTRS { AXBS }
<> 144:ef7eb2e8f9f7 2159
<> 144:ef7eb2e8f9f7 2160 /*!
<> 144:ef7eb2e8f9f7 2161 * @}
<> 144:ef7eb2e8f9f7 2162 */ /* end of group AXBS_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2166 -- CAN Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2167 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2168
<> 144:ef7eb2e8f9f7 2169 /*!
<> 144:ef7eb2e8f9f7 2170 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2171 * @{
<> 144:ef7eb2e8f9f7 2172 */
<> 144:ef7eb2e8f9f7 2173
<> 144:ef7eb2e8f9f7 2174 /** CAN - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 2175 typedef struct {
<> 144:ef7eb2e8f9f7 2176 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 2177 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 2178 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
<> 144:ef7eb2e8f9f7 2179 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 2180 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 2181 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 2182 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 2183 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
<> 144:ef7eb2e8f9f7 2184 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 2185 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 2186 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 2187 uint8_t RESERVED_2[4];
<> 144:ef7eb2e8f9f7 2188 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 2189 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
<> 144:ef7eb2e8f9f7 2190 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
<> 144:ef7eb2e8f9f7 2191 uint8_t RESERVED_3[8];
<> 144:ef7eb2e8f9f7 2192 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 2193 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
<> 144:ef7eb2e8f9f7 2194 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
<> 144:ef7eb2e8f9f7 2195 uint8_t RESERVED_4[48];
<> 144:ef7eb2e8f9f7 2196 struct { /* offset: 0x80, array step: 0x10 */
<> 144:ef7eb2e8f9f7 2197 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
<> 144:ef7eb2e8f9f7 2198 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
<> 144:ef7eb2e8f9f7 2199 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
<> 144:ef7eb2e8f9f7 2200 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
<> 144:ef7eb2e8f9f7 2201 } MB[16];
<> 144:ef7eb2e8f9f7 2202 uint8_t RESERVED_5[1792];
<> 144:ef7eb2e8f9f7 2203 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2204 } CAN_Type;
<> 144:ef7eb2e8f9f7 2205
<> 144:ef7eb2e8f9f7 2206 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2207 -- CAN Register Masks
<> 144:ef7eb2e8f9f7 2208 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210 /*!
<> 144:ef7eb2e8f9f7 2211 * @addtogroup CAN_Register_Masks CAN Register Masks
<> 144:ef7eb2e8f9f7 2212 * @{
<> 144:ef7eb2e8f9f7 2213 */
<> 144:ef7eb2e8f9f7 2214
<> 144:ef7eb2e8f9f7 2215 /*! @name MCR - Module Configuration Register */
<> 144:ef7eb2e8f9f7 2216 #define CAN_MCR_MAXMB_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 2217 #define CAN_MCR_MAXMB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2218 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
<> 144:ef7eb2e8f9f7 2219 #define CAN_MCR_IDAM_MASK (0x300U)
<> 144:ef7eb2e8f9f7 2220 #define CAN_MCR_IDAM_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2221 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
<> 144:ef7eb2e8f9f7 2222 #define CAN_MCR_AEN_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 2223 #define CAN_MCR_AEN_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2224 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
<> 144:ef7eb2e8f9f7 2225 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 2226 #define CAN_MCR_LPRIOEN_SHIFT (13U)
<> 144:ef7eb2e8f9f7 2227 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
<> 144:ef7eb2e8f9f7 2228 #define CAN_MCR_IRMQ_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 2229 #define CAN_MCR_IRMQ_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2230 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
<> 144:ef7eb2e8f9f7 2231 #define CAN_MCR_SRXDIS_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 2232 #define CAN_MCR_SRXDIS_SHIFT (17U)
<> 144:ef7eb2e8f9f7 2233 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
<> 144:ef7eb2e8f9f7 2234 #define CAN_MCR_WAKSRC_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 2235 #define CAN_MCR_WAKSRC_SHIFT (19U)
<> 144:ef7eb2e8f9f7 2236 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
<> 144:ef7eb2e8f9f7 2237 #define CAN_MCR_LPMACK_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 2238 #define CAN_MCR_LPMACK_SHIFT (20U)
<> 144:ef7eb2e8f9f7 2239 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
<> 144:ef7eb2e8f9f7 2240 #define CAN_MCR_WRNEN_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 2241 #define CAN_MCR_WRNEN_SHIFT (21U)
<> 144:ef7eb2e8f9f7 2242 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
<> 144:ef7eb2e8f9f7 2243 #define CAN_MCR_SLFWAK_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 2244 #define CAN_MCR_SLFWAK_SHIFT (22U)
<> 144:ef7eb2e8f9f7 2245 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
<> 144:ef7eb2e8f9f7 2246 #define CAN_MCR_SUPV_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 2247 #define CAN_MCR_SUPV_SHIFT (23U)
<> 144:ef7eb2e8f9f7 2248 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
<> 144:ef7eb2e8f9f7 2249 #define CAN_MCR_FRZACK_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 2250 #define CAN_MCR_FRZACK_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2251 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
<> 144:ef7eb2e8f9f7 2252 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 2253 #define CAN_MCR_SOFTRST_SHIFT (25U)
<> 144:ef7eb2e8f9f7 2254 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
<> 144:ef7eb2e8f9f7 2255 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 2256 #define CAN_MCR_WAKMSK_SHIFT (26U)
<> 144:ef7eb2e8f9f7 2257 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
<> 144:ef7eb2e8f9f7 2258 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 2259 #define CAN_MCR_NOTRDY_SHIFT (27U)
<> 144:ef7eb2e8f9f7 2260 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
<> 144:ef7eb2e8f9f7 2261 #define CAN_MCR_HALT_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 2262 #define CAN_MCR_HALT_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2263 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
<> 144:ef7eb2e8f9f7 2264 #define CAN_MCR_RFEN_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 2265 #define CAN_MCR_RFEN_SHIFT (29U)
<> 144:ef7eb2e8f9f7 2266 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
<> 144:ef7eb2e8f9f7 2267 #define CAN_MCR_FRZ_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 2268 #define CAN_MCR_FRZ_SHIFT (30U)
<> 144:ef7eb2e8f9f7 2269 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
<> 144:ef7eb2e8f9f7 2270 #define CAN_MCR_MDIS_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 2271 #define CAN_MCR_MDIS_SHIFT (31U)
<> 144:ef7eb2e8f9f7 2272 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
<> 144:ef7eb2e8f9f7 2273
<> 144:ef7eb2e8f9f7 2274 /*! @name CTRL1 - Control 1 register */
<> 144:ef7eb2e8f9f7 2275 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
<> 144:ef7eb2e8f9f7 2276 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2277 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
<> 144:ef7eb2e8f9f7 2278 #define CAN_CTRL1_LOM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 2279 #define CAN_CTRL1_LOM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 2280 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
<> 144:ef7eb2e8f9f7 2281 #define CAN_CTRL1_LBUF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 2282 #define CAN_CTRL1_LBUF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 2283 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
<> 144:ef7eb2e8f9f7 2284 #define CAN_CTRL1_TSYN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 2285 #define CAN_CTRL1_TSYN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 2286 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
<> 144:ef7eb2e8f9f7 2287 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
<> 144:ef7eb2e8f9f7 2288 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 2289 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
<> 144:ef7eb2e8f9f7 2290 #define CAN_CTRL1_SMP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 2291 #define CAN_CTRL1_SMP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 2292 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
<> 144:ef7eb2e8f9f7 2293 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
<> 144:ef7eb2e8f9f7 2294 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
<> 144:ef7eb2e8f9f7 2295 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
<> 144:ef7eb2e8f9f7 2296 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
<> 144:ef7eb2e8f9f7 2297 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
<> 144:ef7eb2e8f9f7 2298 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
<> 144:ef7eb2e8f9f7 2299 #define CAN_CTRL1_LPB_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 2300 #define CAN_CTRL1_LPB_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2301 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
<> 144:ef7eb2e8f9f7 2302 #define CAN_CTRL1_CLKSRC_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 2303 #define CAN_CTRL1_CLKSRC_SHIFT (13U)
<> 144:ef7eb2e8f9f7 2304 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
<> 144:ef7eb2e8f9f7 2305 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 2306 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
<> 144:ef7eb2e8f9f7 2307 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
<> 144:ef7eb2e8f9f7 2308 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 2309 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
<> 144:ef7eb2e8f9f7 2310 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
<> 144:ef7eb2e8f9f7 2311 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
<> 144:ef7eb2e8f9f7 2312 #define CAN_CTRL1_PSEG2_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2313 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
<> 144:ef7eb2e8f9f7 2314 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
<> 144:ef7eb2e8f9f7 2315 #define CAN_CTRL1_PSEG1_SHIFT (19U)
<> 144:ef7eb2e8f9f7 2316 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
<> 144:ef7eb2e8f9f7 2317 #define CAN_CTRL1_RJW_MASK (0xC00000U)
<> 144:ef7eb2e8f9f7 2318 #define CAN_CTRL1_RJW_SHIFT (22U)
<> 144:ef7eb2e8f9f7 2319 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
<> 144:ef7eb2e8f9f7 2320 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2321 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2322 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 /*! @name TIMER - Free Running Timer */
<> 144:ef7eb2e8f9f7 2325 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 2326 #define CAN_TIMER_TIMER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2327 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
<> 144:ef7eb2e8f9f7 2328
<> 144:ef7eb2e8f9f7 2329 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
<> 144:ef7eb2e8f9f7 2330 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2331 #define CAN_RXMGMASK_MG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2332 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334 /*! @name RX14MASK - Rx 14 Mask register */
<> 144:ef7eb2e8f9f7 2335 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2336 #define CAN_RX14MASK_RX14M_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2337 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
<> 144:ef7eb2e8f9f7 2338
<> 144:ef7eb2e8f9f7 2339 /*! @name RX15MASK - Rx 15 Mask register */
<> 144:ef7eb2e8f9f7 2340 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2341 #define CAN_RX15MASK_RX15M_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2342 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
<> 144:ef7eb2e8f9f7 2343
<> 144:ef7eb2e8f9f7 2344 /*! @name ECR - Error Counter */
<> 144:ef7eb2e8f9f7 2345 #define CAN_ECR_TXERRCNT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2346 #define CAN_ECR_TXERRCNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2347 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
<> 144:ef7eb2e8f9f7 2348 #define CAN_ECR_RXERRCNT_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2349 #define CAN_ECR_RXERRCNT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2350 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 /*! @name ESR1 - Error and Status 1 register */
<> 144:ef7eb2e8f9f7 2353 #define CAN_ESR1_WAKINT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2354 #define CAN_ESR1_WAKINT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2355 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
<> 144:ef7eb2e8f9f7 2356 #define CAN_ESR1_ERRINT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2357 #define CAN_ESR1_ERRINT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2358 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
<> 144:ef7eb2e8f9f7 2359 #define CAN_ESR1_BOFFINT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 2360 #define CAN_ESR1_BOFFINT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 2361 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
<> 144:ef7eb2e8f9f7 2362 #define CAN_ESR1_RX_MASK (0x8U)
<> 144:ef7eb2e8f9f7 2363 #define CAN_ESR1_RX_SHIFT (3U)
<> 144:ef7eb2e8f9f7 2364 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
<> 144:ef7eb2e8f9f7 2365 #define CAN_ESR1_FLTCONF_MASK (0x30U)
<> 144:ef7eb2e8f9f7 2366 #define CAN_ESR1_FLTCONF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 2367 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
<> 144:ef7eb2e8f9f7 2368 #define CAN_ESR1_TX_MASK (0x40U)
<> 144:ef7eb2e8f9f7 2369 #define CAN_ESR1_TX_SHIFT (6U)
<> 144:ef7eb2e8f9f7 2370 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
<> 144:ef7eb2e8f9f7 2371 #define CAN_ESR1_IDLE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 2372 #define CAN_ESR1_IDLE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 2373 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
<> 144:ef7eb2e8f9f7 2374 #define CAN_ESR1_RXWRN_MASK (0x100U)
<> 144:ef7eb2e8f9f7 2375 #define CAN_ESR1_RXWRN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2376 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
<> 144:ef7eb2e8f9f7 2377 #define CAN_ESR1_TXWRN_MASK (0x200U)
<> 144:ef7eb2e8f9f7 2378 #define CAN_ESR1_TXWRN_SHIFT (9U)
<> 144:ef7eb2e8f9f7 2379 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
<> 144:ef7eb2e8f9f7 2380 #define CAN_ESR1_STFERR_MASK (0x400U)
<> 144:ef7eb2e8f9f7 2381 #define CAN_ESR1_STFERR_SHIFT (10U)
<> 144:ef7eb2e8f9f7 2382 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
<> 144:ef7eb2e8f9f7 2383 #define CAN_ESR1_FRMERR_MASK (0x800U)
<> 144:ef7eb2e8f9f7 2384 #define CAN_ESR1_FRMERR_SHIFT (11U)
<> 144:ef7eb2e8f9f7 2385 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
<> 144:ef7eb2e8f9f7 2386 #define CAN_ESR1_CRCERR_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 2387 #define CAN_ESR1_CRCERR_SHIFT (12U)
<> 144:ef7eb2e8f9f7 2388 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
<> 144:ef7eb2e8f9f7 2389 #define CAN_ESR1_ACKERR_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 2390 #define CAN_ESR1_ACKERR_SHIFT (13U)
<> 144:ef7eb2e8f9f7 2391 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
<> 144:ef7eb2e8f9f7 2392 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 2393 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
<> 144:ef7eb2e8f9f7 2394 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
<> 144:ef7eb2e8f9f7 2395 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 2396 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
<> 144:ef7eb2e8f9f7 2397 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
<> 144:ef7eb2e8f9f7 2398 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 2399 #define CAN_ESR1_RWRNINT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2400 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
<> 144:ef7eb2e8f9f7 2401 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 2402 #define CAN_ESR1_TWRNINT_SHIFT (17U)
<> 144:ef7eb2e8f9f7 2403 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
<> 144:ef7eb2e8f9f7 2404 #define CAN_ESR1_SYNCH_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 2405 #define CAN_ESR1_SYNCH_SHIFT (18U)
<> 144:ef7eb2e8f9f7 2406 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
<> 144:ef7eb2e8f9f7 2407
<> 144:ef7eb2e8f9f7 2408 /*! @name IMASK1 - Interrupt Masks 1 register */
<> 144:ef7eb2e8f9f7 2409 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2410 #define CAN_IMASK1_BUFLM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2411 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
<> 144:ef7eb2e8f9f7 2412
<> 144:ef7eb2e8f9f7 2413 /*! @name IFLAG1 - Interrupt Flags 1 register */
<> 144:ef7eb2e8f9f7 2414 #define CAN_IFLAG1_BUF0I_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2415 #define CAN_IFLAG1_BUF0I_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2416 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
<> 144:ef7eb2e8f9f7 2417 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
<> 144:ef7eb2e8f9f7 2418 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2419 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
<> 144:ef7eb2e8f9f7 2420 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
<> 144:ef7eb2e8f9f7 2421 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
<> 144:ef7eb2e8f9f7 2422 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
<> 144:ef7eb2e8f9f7 2423 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
<> 144:ef7eb2e8f9f7 2424 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
<> 144:ef7eb2e8f9f7 2425 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
<> 144:ef7eb2e8f9f7 2426 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
<> 144:ef7eb2e8f9f7 2427 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
<> 144:ef7eb2e8f9f7 2428 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
<> 144:ef7eb2e8f9f7 2429 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
<> 144:ef7eb2e8f9f7 2430 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2431 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
<> 144:ef7eb2e8f9f7 2432
<> 144:ef7eb2e8f9f7 2433 /*! @name CTRL2 - Control 2 register */
<> 144:ef7eb2e8f9f7 2434 #define CAN_CTRL2_EACEN_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 2435 #define CAN_CTRL2_EACEN_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2436 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
<> 144:ef7eb2e8f9f7 2437 #define CAN_CTRL2_RRS_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 2438 #define CAN_CTRL2_RRS_SHIFT (17U)
<> 144:ef7eb2e8f9f7 2439 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
<> 144:ef7eb2e8f9f7 2440 #define CAN_CTRL2_MRP_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 2441 #define CAN_CTRL2_MRP_SHIFT (18U)
<> 144:ef7eb2e8f9f7 2442 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
<> 144:ef7eb2e8f9f7 2443 #define CAN_CTRL2_TASD_MASK (0xF80000U)
<> 144:ef7eb2e8f9f7 2444 #define CAN_CTRL2_TASD_SHIFT (19U)
<> 144:ef7eb2e8f9f7 2445 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
<> 144:ef7eb2e8f9f7 2446 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 2447 #define CAN_CTRL2_RFFN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2448 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
<> 144:ef7eb2e8f9f7 2449 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 2450 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2451 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
<> 144:ef7eb2e8f9f7 2452
<> 144:ef7eb2e8f9f7 2453 /*! @name ESR2 - Error and Status 2 register */
<> 144:ef7eb2e8f9f7 2454 #define CAN_ESR2_IMB_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 2455 #define CAN_ESR2_IMB_SHIFT (13U)
<> 144:ef7eb2e8f9f7 2456 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
<> 144:ef7eb2e8f9f7 2457 #define CAN_ESR2_VPS_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 2458 #define CAN_ESR2_VPS_SHIFT (14U)
<> 144:ef7eb2e8f9f7 2459 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
<> 144:ef7eb2e8f9f7 2460 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
<> 144:ef7eb2e8f9f7 2461 #define CAN_ESR2_LPTM_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2462 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
<> 144:ef7eb2e8f9f7 2463
<> 144:ef7eb2e8f9f7 2464 /*! @name CRCR - CRC Register */
<> 144:ef7eb2e8f9f7 2465 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
<> 144:ef7eb2e8f9f7 2466 #define CAN_CRCR_TXCRC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2467 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
<> 144:ef7eb2e8f9f7 2468 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
<> 144:ef7eb2e8f9f7 2469 #define CAN_CRCR_MBCRC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2470 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
<> 144:ef7eb2e8f9f7 2471
<> 144:ef7eb2e8f9f7 2472 /*! @name RXFGMASK - Rx FIFO Global Mask register */
<> 144:ef7eb2e8f9f7 2473 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2474 #define CAN_RXFGMASK_FGM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2475 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
<> 144:ef7eb2e8f9f7 2476
<> 144:ef7eb2e8f9f7 2477 /*! @name RXFIR - Rx FIFO Information Register */
<> 144:ef7eb2e8f9f7 2478 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 2479 #define CAN_RXFIR_IDHIT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2480 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
<> 144:ef7eb2e8f9f7 2481
<> 144:ef7eb2e8f9f7 2482 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
<> 144:ef7eb2e8f9f7 2483 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 2484 #define CAN_CS_TIME_STAMP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2485 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
<> 144:ef7eb2e8f9f7 2486 #define CAN_CS_DLC_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 2487 #define CAN_CS_DLC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2488 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
<> 144:ef7eb2e8f9f7 2489 #define CAN_CS_RTR_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 2490 #define CAN_CS_RTR_SHIFT (20U)
<> 144:ef7eb2e8f9f7 2491 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
<> 144:ef7eb2e8f9f7 2492 #define CAN_CS_IDE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 2493 #define CAN_CS_IDE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 2494 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
<> 144:ef7eb2e8f9f7 2495 #define CAN_CS_SRR_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 2496 #define CAN_CS_SRR_SHIFT (22U)
<> 144:ef7eb2e8f9f7 2497 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
<> 144:ef7eb2e8f9f7 2498 #define CAN_CS_CODE_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 2499 #define CAN_CS_CODE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2500 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
<> 144:ef7eb2e8f9f7 2501
<> 144:ef7eb2e8f9f7 2502 /* The count of CAN_CS */
<> 144:ef7eb2e8f9f7 2503 #define CAN_CS_COUNT (16U)
<> 144:ef7eb2e8f9f7 2504
<> 144:ef7eb2e8f9f7 2505 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
<> 144:ef7eb2e8f9f7 2506 #define CAN_ID_EXT_MASK (0x3FFFFU)
<> 144:ef7eb2e8f9f7 2507 #define CAN_ID_EXT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2508 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
<> 144:ef7eb2e8f9f7 2509 #define CAN_ID_STD_MASK (0x1FFC0000U)
<> 144:ef7eb2e8f9f7 2510 #define CAN_ID_STD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 2511 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
<> 144:ef7eb2e8f9f7 2512 #define CAN_ID_PRIO_MASK (0xE0000000U)
<> 144:ef7eb2e8f9f7 2513 #define CAN_ID_PRIO_SHIFT (29U)
<> 144:ef7eb2e8f9f7 2514 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
<> 144:ef7eb2e8f9f7 2515
<> 144:ef7eb2e8f9f7 2516 /* The count of CAN_ID */
<> 144:ef7eb2e8f9f7 2517 #define CAN_ID_COUNT (16U)
<> 144:ef7eb2e8f9f7 2518
<> 144:ef7eb2e8f9f7 2519 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
<> 144:ef7eb2e8f9f7 2520 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2521 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2522 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
<> 144:ef7eb2e8f9f7 2523 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2524 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2525 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
<> 144:ef7eb2e8f9f7 2526 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2527 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2528 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
<> 144:ef7eb2e8f9f7 2529 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2530 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2531 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
<> 144:ef7eb2e8f9f7 2532
<> 144:ef7eb2e8f9f7 2533 /* The count of CAN_WORD0 */
<> 144:ef7eb2e8f9f7 2534 #define CAN_WORD0_COUNT (16U)
<> 144:ef7eb2e8f9f7 2535
<> 144:ef7eb2e8f9f7 2536 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
<> 144:ef7eb2e8f9f7 2537 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 2538 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2539 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
<> 144:ef7eb2e8f9f7 2540 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 2541 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
<> 144:ef7eb2e8f9f7 2542 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
<> 144:ef7eb2e8f9f7 2543 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 2544 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
<> 144:ef7eb2e8f9f7 2545 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
<> 144:ef7eb2e8f9f7 2546 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 2547 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
<> 144:ef7eb2e8f9f7 2548 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
<> 144:ef7eb2e8f9f7 2549
<> 144:ef7eb2e8f9f7 2550 /* The count of CAN_WORD1 */
<> 144:ef7eb2e8f9f7 2551 #define CAN_WORD1_COUNT (16U)
<> 144:ef7eb2e8f9f7 2552
<> 144:ef7eb2e8f9f7 2553 /*! @name RXIMR - Rx Individual Mask Registers */
<> 144:ef7eb2e8f9f7 2554 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2555 #define CAN_RXIMR_MI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2556 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /* The count of CAN_RXIMR */
<> 144:ef7eb2e8f9f7 2559 #define CAN_RXIMR_COUNT (16U)
<> 144:ef7eb2e8f9f7 2560
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /*!
<> 144:ef7eb2e8f9f7 2563 * @}
<> 144:ef7eb2e8f9f7 2564 */ /* end of group CAN_Register_Masks */
<> 144:ef7eb2e8f9f7 2565
<> 144:ef7eb2e8f9f7 2566
<> 144:ef7eb2e8f9f7 2567 /* CAN - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 2568 /** Peripheral CAN0 base address */
<> 144:ef7eb2e8f9f7 2569 #define CAN0_BASE (0x40024000u)
<> 144:ef7eb2e8f9f7 2570 /** Peripheral CAN0 base pointer */
<> 144:ef7eb2e8f9f7 2571 #define CAN0 ((CAN_Type *)CAN0_BASE)
<> 144:ef7eb2e8f9f7 2572 /** Peripheral CAN1 base address */
<> 144:ef7eb2e8f9f7 2573 #define CAN1_BASE (0x400A4000u)
<> 144:ef7eb2e8f9f7 2574 /** Peripheral CAN1 base pointer */
<> 144:ef7eb2e8f9f7 2575 #define CAN1 ((CAN_Type *)CAN1_BASE)
<> 144:ef7eb2e8f9f7 2576 /** Array initializer of CAN peripheral base addresses */
<> 144:ef7eb2e8f9f7 2577 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
<> 144:ef7eb2e8f9f7 2578 /** Array initializer of CAN peripheral base pointers */
<> 144:ef7eb2e8f9f7 2579 #define CAN_BASE_PTRS { CAN0, CAN1 }
<> 144:ef7eb2e8f9f7 2580 /** Interrupt vectors for the CAN peripheral type */
<> 144:ef7eb2e8f9f7 2581 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
<> 144:ef7eb2e8f9f7 2582 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
<> 144:ef7eb2e8f9f7 2583 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
<> 144:ef7eb2e8f9f7 2584 #define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
<> 144:ef7eb2e8f9f7 2585 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
<> 144:ef7eb2e8f9f7 2586 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
<> 144:ef7eb2e8f9f7 2587
<> 144:ef7eb2e8f9f7 2588 /*!
<> 144:ef7eb2e8f9f7 2589 * @}
<> 144:ef7eb2e8f9f7 2590 */ /* end of group CAN_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 2591
<> 144:ef7eb2e8f9f7 2592
<> 144:ef7eb2e8f9f7 2593 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2594 -- CAU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2595 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2596
<> 144:ef7eb2e8f9f7 2597 /*!
<> 144:ef7eb2e8f9f7 2598 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 2599 * @{
<> 144:ef7eb2e8f9f7 2600 */
<> 144:ef7eb2e8f9f7 2601
<> 144:ef7eb2e8f9f7 2602 /** CAU - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 2603 typedef struct {
<> 144:ef7eb2e8f9f7 2604 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2605 uint8_t RESERVED_0[2048];
<> 144:ef7eb2e8f9f7 2606 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
<> 144:ef7eb2e8f9f7 2607 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
<> 144:ef7eb2e8f9f7 2608 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2609 uint8_t RESERVED_1[20];
<> 144:ef7eb2e8f9f7 2610 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
<> 144:ef7eb2e8f9f7 2611 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
<> 144:ef7eb2e8f9f7 2612 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2613 uint8_t RESERVED_2[20];
<> 144:ef7eb2e8f9f7 2614 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
<> 144:ef7eb2e8f9f7 2615 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
<> 144:ef7eb2e8f9f7 2616 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2617 uint8_t RESERVED_3[20];
<> 144:ef7eb2e8f9f7 2618 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
<> 144:ef7eb2e8f9f7 2619 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
<> 144:ef7eb2e8f9f7 2620 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2621 uint8_t RESERVED_4[84];
<> 144:ef7eb2e8f9f7 2622 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
<> 144:ef7eb2e8f9f7 2623 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
<> 144:ef7eb2e8f9f7 2624 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2625 uint8_t RESERVED_5[20];
<> 144:ef7eb2e8f9f7 2626 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
<> 144:ef7eb2e8f9f7 2627 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
<> 144:ef7eb2e8f9f7 2628 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2629 uint8_t RESERVED_6[276];
<> 144:ef7eb2e8f9f7 2630 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
<> 144:ef7eb2e8f9f7 2631 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
<> 144:ef7eb2e8f9f7 2632 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2633 uint8_t RESERVED_7[20];
<> 144:ef7eb2e8f9f7 2634 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
<> 144:ef7eb2e8f9f7 2635 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
<> 144:ef7eb2e8f9f7 2636 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
<> 144:ef7eb2e8f9f7 2637 } CAU_Type;
<> 144:ef7eb2e8f9f7 2638
<> 144:ef7eb2e8f9f7 2639 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2640 -- CAU Register Masks
<> 144:ef7eb2e8f9f7 2641 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 2642
<> 144:ef7eb2e8f9f7 2643 /*!
<> 144:ef7eb2e8f9f7 2644 * @addtogroup CAU_Register_Masks CAU Register Masks
<> 144:ef7eb2e8f9f7 2645 * @{
<> 144:ef7eb2e8f9f7 2646 */
<> 144:ef7eb2e8f9f7 2647
<> 144:ef7eb2e8f9f7 2648 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
<> 144:ef7eb2e8f9f7 2649 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2650 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2651 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
<> 144:ef7eb2e8f9f7 2652 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2653 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2654 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
<> 144:ef7eb2e8f9f7 2655 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2656 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2657 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
<> 144:ef7eb2e8f9f7 2658 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2659 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2660 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
<> 144:ef7eb2e8f9f7 2661 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2662 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2663 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
<> 144:ef7eb2e8f9f7 2664 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2665 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2666 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
<> 144:ef7eb2e8f9f7 2667 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2668 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2669 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
<> 144:ef7eb2e8f9f7 2670 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2671 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2672 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
<> 144:ef7eb2e8f9f7 2673 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2674 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2675 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
<> 144:ef7eb2e8f9f7 2676 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2677 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2678 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
<> 144:ef7eb2e8f9f7 2679 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2680 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2681 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
<> 144:ef7eb2e8f9f7 2682 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2683 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2684 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
<> 144:ef7eb2e8f9f7 2685 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2686 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2687 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
<> 144:ef7eb2e8f9f7 2688 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2689 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2690 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
<> 144:ef7eb2e8f9f7 2691 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2692 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2693 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
<> 144:ef7eb2e8f9f7 2694 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2695 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2696 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
<> 144:ef7eb2e8f9f7 2697
<> 144:ef7eb2e8f9f7 2698 /* The count of CAU_DIRECT */
<> 144:ef7eb2e8f9f7 2699 #define CAU_DIRECT_COUNT (16U)
<> 144:ef7eb2e8f9f7 2700
<> 144:ef7eb2e8f9f7 2701 /*! @name LDR_CASR - Status register - Load Register command */
<> 144:ef7eb2e8f9f7 2702 #define CAU_LDR_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2703 #define CAU_LDR_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2704 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2705 #define CAU_LDR_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2706 #define CAU_LDR_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2707 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2708 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2709 #define CAU_LDR_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2710 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2711
<> 144:ef7eb2e8f9f7 2712 /*! @name LDR_CAA - Accumulator register - Load Register command */
<> 144:ef7eb2e8f9f7 2713 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2714 #define CAU_LDR_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2715 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 2716
<> 144:ef7eb2e8f9f7 2717 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
<> 144:ef7eb2e8f9f7 2718 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2719 #define CAU_LDR_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2720 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 2721 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2722 #define CAU_LDR_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2723 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 2724 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2725 #define CAU_LDR_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2726 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 2727 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2728 #define CAU_LDR_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2729 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 2730 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2731 #define CAU_LDR_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2732 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 2733 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2734 #define CAU_LDR_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2735 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 2736 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2737 #define CAU_LDR_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2738 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 2739 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2740 #define CAU_LDR_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2741 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 2742 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2743 #define CAU_LDR_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2744 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 2745
<> 144:ef7eb2e8f9f7 2746 /* The count of CAU_LDR_CA */
<> 144:ef7eb2e8f9f7 2747 #define CAU_LDR_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 2748
<> 144:ef7eb2e8f9f7 2749 /*! @name STR_CASR - Status register - Store Register command */
<> 144:ef7eb2e8f9f7 2750 #define CAU_STR_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2751 #define CAU_STR_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2752 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2753 #define CAU_STR_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2754 #define CAU_STR_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2755 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2756 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2757 #define CAU_STR_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2758 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2759
<> 144:ef7eb2e8f9f7 2760 /*! @name STR_CAA - Accumulator register - Store Register command */
<> 144:ef7eb2e8f9f7 2761 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2762 #define CAU_STR_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2763 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 2764
<> 144:ef7eb2e8f9f7 2765 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
<> 144:ef7eb2e8f9f7 2766 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2767 #define CAU_STR_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2768 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 2769 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2770 #define CAU_STR_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2771 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 2772 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2773 #define CAU_STR_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2774 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 2775 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2776 #define CAU_STR_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2777 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 2778 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2779 #define CAU_STR_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2780 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 2781 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2782 #define CAU_STR_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2783 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 2784 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2785 #define CAU_STR_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2786 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 2787 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2788 #define CAU_STR_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2789 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 2790 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2791 #define CAU_STR_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2792 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 2793
<> 144:ef7eb2e8f9f7 2794 /* The count of CAU_STR_CA */
<> 144:ef7eb2e8f9f7 2795 #define CAU_STR_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 2796
<> 144:ef7eb2e8f9f7 2797 /*! @name ADR_CASR - Status register - Add Register command */
<> 144:ef7eb2e8f9f7 2798 #define CAU_ADR_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2799 #define CAU_ADR_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2800 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2801 #define CAU_ADR_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2802 #define CAU_ADR_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2803 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2804 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2805 #define CAU_ADR_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2806 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2807
<> 144:ef7eb2e8f9f7 2808 /*! @name ADR_CAA - Accumulator register - Add to register command */
<> 144:ef7eb2e8f9f7 2809 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2810 #define CAU_ADR_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2811 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 2812
<> 144:ef7eb2e8f9f7 2813 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
<> 144:ef7eb2e8f9f7 2814 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2815 #define CAU_ADR_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2816 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 2817 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2818 #define CAU_ADR_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2819 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 2820 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2821 #define CAU_ADR_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2822 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 2823 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2824 #define CAU_ADR_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2825 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 2826 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2827 #define CAU_ADR_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2828 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 2829 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2830 #define CAU_ADR_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2831 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 2832 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2833 #define CAU_ADR_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2834 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 2835 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2836 #define CAU_ADR_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2837 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 2838 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2839 #define CAU_ADR_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2840 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 2841
<> 144:ef7eb2e8f9f7 2842 /* The count of CAU_ADR_CA */
<> 144:ef7eb2e8f9f7 2843 #define CAU_ADR_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 2844
<> 144:ef7eb2e8f9f7 2845 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
<> 144:ef7eb2e8f9f7 2846 #define CAU_RADR_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2847 #define CAU_RADR_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2848 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2849 #define CAU_RADR_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2850 #define CAU_RADR_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2851 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2852 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2853 #define CAU_RADR_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2854 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2855
<> 144:ef7eb2e8f9f7 2856 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
<> 144:ef7eb2e8f9f7 2857 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2858 #define CAU_RADR_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2859 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 2860
<> 144:ef7eb2e8f9f7 2861 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
<> 144:ef7eb2e8f9f7 2862 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2863 #define CAU_RADR_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2864 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 2865 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2866 #define CAU_RADR_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2867 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 2868 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2869 #define CAU_RADR_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2870 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 2871 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2872 #define CAU_RADR_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2873 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 2874 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2875 #define CAU_RADR_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2876 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 2877 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2878 #define CAU_RADR_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2879 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 2880 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2881 #define CAU_RADR_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2882 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 2883 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2884 #define CAU_RADR_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2885 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 2886 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2887 #define CAU_RADR_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2888 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 2889
<> 144:ef7eb2e8f9f7 2890 /* The count of CAU_RADR_CA */
<> 144:ef7eb2e8f9f7 2891 #define CAU_RADR_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 2892
<> 144:ef7eb2e8f9f7 2893 /*! @name XOR_CASR - Status register - Exclusive Or command */
<> 144:ef7eb2e8f9f7 2894 #define CAU_XOR_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2895 #define CAU_XOR_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2896 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2897 #define CAU_XOR_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2898 #define CAU_XOR_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2899 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2900 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2901 #define CAU_XOR_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2902 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2903
<> 144:ef7eb2e8f9f7 2904 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
<> 144:ef7eb2e8f9f7 2905 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2906 #define CAU_XOR_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2907 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
<> 144:ef7eb2e8f9f7 2910 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2911 #define CAU_XOR_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2912 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 2913 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2914 #define CAU_XOR_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2915 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 2916 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2917 #define CAU_XOR_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2918 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 2919 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2920 #define CAU_XOR_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2921 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 2922 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2923 #define CAU_XOR_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2924 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 2925 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2926 #define CAU_XOR_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2927 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 2928 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2929 #define CAU_XOR_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2930 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 2931 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2932 #define CAU_XOR_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2933 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 2934 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2935 #define CAU_XOR_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2936 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 2937
<> 144:ef7eb2e8f9f7 2938 /* The count of CAU_XOR_CA */
<> 144:ef7eb2e8f9f7 2939 #define CAU_XOR_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 2940
<> 144:ef7eb2e8f9f7 2941 /*! @name ROTL_CASR - Status register - Rotate Left command */
<> 144:ef7eb2e8f9f7 2942 #define CAU_ROTL_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2943 #define CAU_ROTL_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2944 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2945 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2946 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2947 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2948 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2949 #define CAU_ROTL_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2950 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2951
<> 144:ef7eb2e8f9f7 2952 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
<> 144:ef7eb2e8f9f7 2953 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2954 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2955 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 2956
<> 144:ef7eb2e8f9f7 2957 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
<> 144:ef7eb2e8f9f7 2958 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2959 #define CAU_ROTL_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2960 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 2961 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2962 #define CAU_ROTL_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2963 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 2964 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2965 #define CAU_ROTL_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2966 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 2967 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2968 #define CAU_ROTL_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2969 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 2970 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2971 #define CAU_ROTL_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2972 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 2973 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2974 #define CAU_ROTL_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2975 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 2976 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2977 #define CAU_ROTL_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2978 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 2979 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2980 #define CAU_ROTL_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2981 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 2982 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 2983 #define CAU_ROTL_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2984 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 2985
<> 144:ef7eb2e8f9f7 2986 /* The count of CAU_ROTL_CA */
<> 144:ef7eb2e8f9f7 2987 #define CAU_ROTL_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 2988
<> 144:ef7eb2e8f9f7 2989 /*! @name AESC_CASR - Status register - AES Column Operation command */
<> 144:ef7eb2e8f9f7 2990 #define CAU_AESC_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 2991 #define CAU_AESC_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 2992 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 2993 #define CAU_AESC_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 2994 #define CAU_AESC_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 2995 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 2996 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 2997 #define CAU_AESC_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 2998 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 2999
<> 144:ef7eb2e8f9f7 3000 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
<> 144:ef7eb2e8f9f7 3001 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3002 #define CAU_AESC_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3003 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 3004
<> 144:ef7eb2e8f9f7 3005 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
<> 144:ef7eb2e8f9f7 3006 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3007 #define CAU_AESC_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3008 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 3009 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3010 #define CAU_AESC_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3011 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 3012 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3013 #define CAU_AESC_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3014 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 3015 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3016 #define CAU_AESC_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3017 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 3018 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3019 #define CAU_AESC_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3020 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 3021 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3022 #define CAU_AESC_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3023 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 3024 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3025 #define CAU_AESC_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3026 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 3027 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3028 #define CAU_AESC_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3029 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 3030 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3031 #define CAU_AESC_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3032 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 3033
<> 144:ef7eb2e8f9f7 3034 /* The count of CAU_AESC_CA */
<> 144:ef7eb2e8f9f7 3035 #define CAU_AESC_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 3036
<> 144:ef7eb2e8f9f7 3037 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
<> 144:ef7eb2e8f9f7 3038 #define CAU_AESIC_CASR_IC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3039 #define CAU_AESIC_CASR_IC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3040 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
<> 144:ef7eb2e8f9f7 3041 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3042 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3043 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
<> 144:ef7eb2e8f9f7 3044 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 3045 #define CAU_AESIC_CASR_VER_SHIFT (28U)
<> 144:ef7eb2e8f9f7 3046 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
<> 144:ef7eb2e8f9f7 3047
<> 144:ef7eb2e8f9f7 3048 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
<> 144:ef7eb2e8f9f7 3049 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3050 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3051 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
<> 144:ef7eb2e8f9f7 3052
<> 144:ef7eb2e8f9f7 3053 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
<> 144:ef7eb2e8f9f7 3054 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3055 #define CAU_AESIC_CA_CA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3056 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
<> 144:ef7eb2e8f9f7 3057 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3058 #define CAU_AESIC_CA_CA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3059 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
<> 144:ef7eb2e8f9f7 3060 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3061 #define CAU_AESIC_CA_CA2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3062 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
<> 144:ef7eb2e8f9f7 3063 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3064 #define CAU_AESIC_CA_CA3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3065 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
<> 144:ef7eb2e8f9f7 3066 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3067 #define CAU_AESIC_CA_CA4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3068 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
<> 144:ef7eb2e8f9f7 3069 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3070 #define CAU_AESIC_CA_CA5_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3071 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
<> 144:ef7eb2e8f9f7 3072 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3073 #define CAU_AESIC_CA_CA6_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3074 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
<> 144:ef7eb2e8f9f7 3075 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3076 #define CAU_AESIC_CA_CA7_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3077 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
<> 144:ef7eb2e8f9f7 3078 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 3079 #define CAU_AESIC_CA_CA8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3080 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
<> 144:ef7eb2e8f9f7 3081
<> 144:ef7eb2e8f9f7 3082 /* The count of CAU_AESIC_CA */
<> 144:ef7eb2e8f9f7 3083 #define CAU_AESIC_CA_COUNT (9U)
<> 144:ef7eb2e8f9f7 3084
<> 144:ef7eb2e8f9f7 3085
<> 144:ef7eb2e8f9f7 3086 /*!
<> 144:ef7eb2e8f9f7 3087 * @}
<> 144:ef7eb2e8f9f7 3088 */ /* end of group CAU_Register_Masks */
<> 144:ef7eb2e8f9f7 3089
<> 144:ef7eb2e8f9f7 3090
<> 144:ef7eb2e8f9f7 3091 /* CAU - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 3092 /** Peripheral CAU base address */
<> 144:ef7eb2e8f9f7 3093 #define CAU_BASE (0xE0081000u)
<> 144:ef7eb2e8f9f7 3094 /** Peripheral CAU base pointer */
<> 144:ef7eb2e8f9f7 3095 #define CAU ((CAU_Type *)CAU_BASE)
<> 144:ef7eb2e8f9f7 3096 /** Array initializer of CAU peripheral base addresses */
<> 144:ef7eb2e8f9f7 3097 #define CAU_BASE_ADDRS { CAU_BASE }
<> 144:ef7eb2e8f9f7 3098 /** Array initializer of CAU peripheral base pointers */
<> 144:ef7eb2e8f9f7 3099 #define CAU_BASE_PTRS { CAU }
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 /*!
<> 144:ef7eb2e8f9f7 3102 * @}
<> 144:ef7eb2e8f9f7 3103 */ /* end of group CAU_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 3104
<> 144:ef7eb2e8f9f7 3105
<> 144:ef7eb2e8f9f7 3106 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3107 -- CMP Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3108 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3109
<> 144:ef7eb2e8f9f7 3110 /*!
<> 144:ef7eb2e8f9f7 3111 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3112 * @{
<> 144:ef7eb2e8f9f7 3113 */
<> 144:ef7eb2e8f9f7 3114
<> 144:ef7eb2e8f9f7 3115 /** CMP - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 3116 typedef struct {
<> 144:ef7eb2e8f9f7 3117 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
<> 144:ef7eb2e8f9f7 3118 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
<> 144:ef7eb2e8f9f7 3119 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 3120 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 3121 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 3122 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 3123 } CMP_Type;
<> 144:ef7eb2e8f9f7 3124
<> 144:ef7eb2e8f9f7 3125 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3126 -- CMP Register Masks
<> 144:ef7eb2e8f9f7 3127 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3128
<> 144:ef7eb2e8f9f7 3129 /*!
<> 144:ef7eb2e8f9f7 3130 * @addtogroup CMP_Register_Masks CMP Register Masks
<> 144:ef7eb2e8f9f7 3131 * @{
<> 144:ef7eb2e8f9f7 3132 */
<> 144:ef7eb2e8f9f7 3133
<> 144:ef7eb2e8f9f7 3134 /*! @name CR0 - CMP Control Register 0 */
<> 144:ef7eb2e8f9f7 3135 #define CMP_CR0_HYSTCTR_MASK (0x3U)
<> 144:ef7eb2e8f9f7 3136 #define CMP_CR0_HYSTCTR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3137 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
<> 144:ef7eb2e8f9f7 3138 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
<> 144:ef7eb2e8f9f7 3139 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3140 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
<> 144:ef7eb2e8f9f7 3141
<> 144:ef7eb2e8f9f7 3142 /*! @name CR1 - CMP Control Register 1 */
<> 144:ef7eb2e8f9f7 3143 #define CMP_CR1_EN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3144 #define CMP_CR1_EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3145 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
<> 144:ef7eb2e8f9f7 3146 #define CMP_CR1_OPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3147 #define CMP_CR1_OPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3148 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
<> 144:ef7eb2e8f9f7 3149 #define CMP_CR1_COS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3150 #define CMP_CR1_COS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3151 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
<> 144:ef7eb2e8f9f7 3152 #define CMP_CR1_INV_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3153 #define CMP_CR1_INV_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3154 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
<> 144:ef7eb2e8f9f7 3155 #define CMP_CR1_PMODE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3156 #define CMP_CR1_PMODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3157 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
<> 144:ef7eb2e8f9f7 3158 #define CMP_CR1_TRIGM_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3159 #define CMP_CR1_TRIGM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3160 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
<> 144:ef7eb2e8f9f7 3161 #define CMP_CR1_WE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3162 #define CMP_CR1_WE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3163 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
<> 144:ef7eb2e8f9f7 3164 #define CMP_CR1_SE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3165 #define CMP_CR1_SE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3166 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
<> 144:ef7eb2e8f9f7 3167
<> 144:ef7eb2e8f9f7 3168 /*! @name FPR - CMP Filter Period Register */
<> 144:ef7eb2e8f9f7 3169 #define CMP_FPR_FILT_PER_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3170 #define CMP_FPR_FILT_PER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3171 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
<> 144:ef7eb2e8f9f7 3172
<> 144:ef7eb2e8f9f7 3173 /*! @name SCR - CMP Status and Control Register */
<> 144:ef7eb2e8f9f7 3174 #define CMP_SCR_COUT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3175 #define CMP_SCR_COUT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3176 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
<> 144:ef7eb2e8f9f7 3177 #define CMP_SCR_CFF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3178 #define CMP_SCR_CFF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3179 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
<> 144:ef7eb2e8f9f7 3180 #define CMP_SCR_CFR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3181 #define CMP_SCR_CFR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3182 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
<> 144:ef7eb2e8f9f7 3183 #define CMP_SCR_IEF_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3184 #define CMP_SCR_IEF_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3185 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
<> 144:ef7eb2e8f9f7 3186 #define CMP_SCR_IER_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3187 #define CMP_SCR_IER_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3188 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
<> 144:ef7eb2e8f9f7 3189 #define CMP_SCR_DMAEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3190 #define CMP_SCR_DMAEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3191 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 3192
<> 144:ef7eb2e8f9f7 3193 /*! @name DACCR - DAC Control Register */
<> 144:ef7eb2e8f9f7 3194 #define CMP_DACCR_VOSEL_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 3195 #define CMP_DACCR_VOSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3196 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
<> 144:ef7eb2e8f9f7 3197 #define CMP_DACCR_VRSEL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3198 #define CMP_DACCR_VRSEL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3199 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
<> 144:ef7eb2e8f9f7 3200 #define CMP_DACCR_DACEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3201 #define CMP_DACCR_DACEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3202 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
<> 144:ef7eb2e8f9f7 3203
<> 144:ef7eb2e8f9f7 3204 /*! @name MUXCR - MUX Control Register */
<> 144:ef7eb2e8f9f7 3205 #define CMP_MUXCR_MSEL_MASK (0x7U)
<> 144:ef7eb2e8f9f7 3206 #define CMP_MUXCR_MSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3207 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
<> 144:ef7eb2e8f9f7 3208 #define CMP_MUXCR_PSEL_MASK (0x38U)
<> 144:ef7eb2e8f9f7 3209 #define CMP_MUXCR_PSEL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3210 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
<> 144:ef7eb2e8f9f7 3211 #define CMP_MUXCR_PSTM_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3212 #define CMP_MUXCR_PSTM_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3213 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
<> 144:ef7eb2e8f9f7 3214
<> 144:ef7eb2e8f9f7 3215
<> 144:ef7eb2e8f9f7 3216 /*!
<> 144:ef7eb2e8f9f7 3217 * @}
<> 144:ef7eb2e8f9f7 3218 */ /* end of group CMP_Register_Masks */
<> 144:ef7eb2e8f9f7 3219
<> 144:ef7eb2e8f9f7 3220
<> 144:ef7eb2e8f9f7 3221 /* CMP - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 3222 /** Peripheral CMP0 base address */
<> 144:ef7eb2e8f9f7 3223 #define CMP0_BASE (0x40073000u)
<> 144:ef7eb2e8f9f7 3224 /** Peripheral CMP0 base pointer */
<> 144:ef7eb2e8f9f7 3225 #define CMP0 ((CMP_Type *)CMP0_BASE)
<> 144:ef7eb2e8f9f7 3226 /** Peripheral CMP1 base address */
<> 144:ef7eb2e8f9f7 3227 #define CMP1_BASE (0x40073008u)
<> 144:ef7eb2e8f9f7 3228 /** Peripheral CMP1 base pointer */
<> 144:ef7eb2e8f9f7 3229 #define CMP1 ((CMP_Type *)CMP1_BASE)
<> 144:ef7eb2e8f9f7 3230 /** Peripheral CMP2 base address */
<> 144:ef7eb2e8f9f7 3231 #define CMP2_BASE (0x40073010u)
<> 144:ef7eb2e8f9f7 3232 /** Peripheral CMP2 base pointer */
<> 144:ef7eb2e8f9f7 3233 #define CMP2 ((CMP_Type *)CMP2_BASE)
<> 144:ef7eb2e8f9f7 3234 /** Peripheral CMP3 base address */
<> 144:ef7eb2e8f9f7 3235 #define CMP3_BASE (0x40073018u)
<> 144:ef7eb2e8f9f7 3236 /** Peripheral CMP3 base pointer */
<> 144:ef7eb2e8f9f7 3237 #define CMP3 ((CMP_Type *)CMP3_BASE)
<> 144:ef7eb2e8f9f7 3238 /** Array initializer of CMP peripheral base addresses */
<> 144:ef7eb2e8f9f7 3239 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
<> 144:ef7eb2e8f9f7 3240 /** Array initializer of CMP peripheral base pointers */
<> 144:ef7eb2e8f9f7 3241 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
<> 144:ef7eb2e8f9f7 3242 /** Interrupt vectors for the CMP peripheral type */
<> 144:ef7eb2e8f9f7 3243 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
<> 144:ef7eb2e8f9f7 3244
<> 144:ef7eb2e8f9f7 3245 /*!
<> 144:ef7eb2e8f9f7 3246 * @}
<> 144:ef7eb2e8f9f7 3247 */ /* end of group CMP_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 3248
<> 144:ef7eb2e8f9f7 3249
<> 144:ef7eb2e8f9f7 3250 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3251 -- CMT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3252 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3253
<> 144:ef7eb2e8f9f7 3254 /*!
<> 144:ef7eb2e8f9f7 3255 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3256 * @{
<> 144:ef7eb2e8f9f7 3257 */
<> 144:ef7eb2e8f9f7 3258
<> 144:ef7eb2e8f9f7 3259 /** CMT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 3260 typedef struct {
<> 144:ef7eb2e8f9f7 3261 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
<> 144:ef7eb2e8f9f7 3262 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
<> 144:ef7eb2e8f9f7 3263 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
<> 144:ef7eb2e8f9f7 3264 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
<> 144:ef7eb2e8f9f7 3265 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 3266 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 3267 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
<> 144:ef7eb2e8f9f7 3268 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
<> 144:ef7eb2e8f9f7 3269 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
<> 144:ef7eb2e8f9f7 3270 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
<> 144:ef7eb2e8f9f7 3271 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
<> 144:ef7eb2e8f9f7 3272 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
<> 144:ef7eb2e8f9f7 3273 } CMT_Type;
<> 144:ef7eb2e8f9f7 3274
<> 144:ef7eb2e8f9f7 3275 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3276 -- CMT Register Masks
<> 144:ef7eb2e8f9f7 3277 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3278
<> 144:ef7eb2e8f9f7 3279 /*!
<> 144:ef7eb2e8f9f7 3280 * @addtogroup CMT_Register_Masks CMT Register Masks
<> 144:ef7eb2e8f9f7 3281 * @{
<> 144:ef7eb2e8f9f7 3282 */
<> 144:ef7eb2e8f9f7 3283
<> 144:ef7eb2e8f9f7 3284 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
<> 144:ef7eb2e8f9f7 3285 #define CMT_CGH1_PH_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3286 #define CMT_CGH1_PH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3287 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
<> 144:ef7eb2e8f9f7 3288
<> 144:ef7eb2e8f9f7 3289 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
<> 144:ef7eb2e8f9f7 3290 #define CMT_CGL1_PL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3291 #define CMT_CGL1_PL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3292 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
<> 144:ef7eb2e8f9f7 3293
<> 144:ef7eb2e8f9f7 3294 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
<> 144:ef7eb2e8f9f7 3295 #define CMT_CGH2_SH_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3296 #define CMT_CGH2_SH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3297 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
<> 144:ef7eb2e8f9f7 3298
<> 144:ef7eb2e8f9f7 3299 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
<> 144:ef7eb2e8f9f7 3300 #define CMT_CGL2_SL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3301 #define CMT_CGL2_SL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3302 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
<> 144:ef7eb2e8f9f7 3303
<> 144:ef7eb2e8f9f7 3304 /*! @name OC - CMT Output Control Register */
<> 144:ef7eb2e8f9f7 3305 #define CMT_OC_IROPEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3306 #define CMT_OC_IROPEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3307 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
<> 144:ef7eb2e8f9f7 3308 #define CMT_OC_CMTPOL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3309 #define CMT_OC_CMTPOL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3310 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
<> 144:ef7eb2e8f9f7 3311 #define CMT_OC_IROL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3312 #define CMT_OC_IROL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3313 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
<> 144:ef7eb2e8f9f7 3314
<> 144:ef7eb2e8f9f7 3315 /*! @name MSC - CMT Modulator Status and Control Register */
<> 144:ef7eb2e8f9f7 3316 #define CMT_MSC_MCGEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3317 #define CMT_MSC_MCGEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3318 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
<> 144:ef7eb2e8f9f7 3319 #define CMT_MSC_EOCIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3320 #define CMT_MSC_EOCIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3321 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
<> 144:ef7eb2e8f9f7 3322 #define CMT_MSC_FSK_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3323 #define CMT_MSC_FSK_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3324 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
<> 144:ef7eb2e8f9f7 3325 #define CMT_MSC_BASE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3326 #define CMT_MSC_BASE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3327 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
<> 144:ef7eb2e8f9f7 3328 #define CMT_MSC_EXSPC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3329 #define CMT_MSC_EXSPC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3330 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
<> 144:ef7eb2e8f9f7 3331 #define CMT_MSC_CMTDIV_MASK (0x60U)
<> 144:ef7eb2e8f9f7 3332 #define CMT_MSC_CMTDIV_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3333 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
<> 144:ef7eb2e8f9f7 3334 #define CMT_MSC_EOCF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3335 #define CMT_MSC_EOCF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3336 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
<> 144:ef7eb2e8f9f7 3337
<> 144:ef7eb2e8f9f7 3338 /*! @name CMD1 - CMT Modulator Data Register Mark High */
<> 144:ef7eb2e8f9f7 3339 #define CMT_CMD1_MB_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3340 #define CMT_CMD1_MB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3341 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
<> 144:ef7eb2e8f9f7 3342
<> 144:ef7eb2e8f9f7 3343 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
<> 144:ef7eb2e8f9f7 3344 #define CMT_CMD2_MB_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3345 #define CMT_CMD2_MB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3346 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
<> 144:ef7eb2e8f9f7 3347
<> 144:ef7eb2e8f9f7 3348 /*! @name CMD3 - CMT Modulator Data Register Space High */
<> 144:ef7eb2e8f9f7 3349 #define CMT_CMD3_SB_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3350 #define CMT_CMD3_SB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3351 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
<> 144:ef7eb2e8f9f7 3352
<> 144:ef7eb2e8f9f7 3353 /*! @name CMD4 - CMT Modulator Data Register Space Low */
<> 144:ef7eb2e8f9f7 3354 #define CMT_CMD4_SB_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3355 #define CMT_CMD4_SB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3356 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
<> 144:ef7eb2e8f9f7 3357
<> 144:ef7eb2e8f9f7 3358 /*! @name PPS - CMT Primary Prescaler Register */
<> 144:ef7eb2e8f9f7 3359 #define CMT_PPS_PPSDIV_MASK (0xFU)
<> 144:ef7eb2e8f9f7 3360 #define CMT_PPS_PPSDIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3361 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
<> 144:ef7eb2e8f9f7 3362
<> 144:ef7eb2e8f9f7 3363 /*! @name DMA - CMT Direct Memory Access Register */
<> 144:ef7eb2e8f9f7 3364 #define CMT_DMA_DMA_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3365 #define CMT_DMA_DMA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3366 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
<> 144:ef7eb2e8f9f7 3367
<> 144:ef7eb2e8f9f7 3368
<> 144:ef7eb2e8f9f7 3369 /*!
<> 144:ef7eb2e8f9f7 3370 * @}
<> 144:ef7eb2e8f9f7 3371 */ /* end of group CMT_Register_Masks */
<> 144:ef7eb2e8f9f7 3372
<> 144:ef7eb2e8f9f7 3373
<> 144:ef7eb2e8f9f7 3374 /* CMT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 3375 /** Peripheral CMT base address */
<> 144:ef7eb2e8f9f7 3376 #define CMT_BASE (0x40062000u)
<> 144:ef7eb2e8f9f7 3377 /** Peripheral CMT base pointer */
<> 144:ef7eb2e8f9f7 3378 #define CMT ((CMT_Type *)CMT_BASE)
<> 144:ef7eb2e8f9f7 3379 /** Array initializer of CMT peripheral base addresses */
<> 144:ef7eb2e8f9f7 3380 #define CMT_BASE_ADDRS { CMT_BASE }
<> 144:ef7eb2e8f9f7 3381 /** Array initializer of CMT peripheral base pointers */
<> 144:ef7eb2e8f9f7 3382 #define CMT_BASE_PTRS { CMT }
<> 144:ef7eb2e8f9f7 3383 /** Interrupt vectors for the CMT peripheral type */
<> 144:ef7eb2e8f9f7 3384 #define CMT_IRQS { CMT_IRQn }
<> 144:ef7eb2e8f9f7 3385
<> 144:ef7eb2e8f9f7 3386 /*!
<> 144:ef7eb2e8f9f7 3387 * @}
<> 144:ef7eb2e8f9f7 3388 */ /* end of group CMT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 3389
<> 144:ef7eb2e8f9f7 3390
<> 144:ef7eb2e8f9f7 3391 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3392 -- CRC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3393 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3394
<> 144:ef7eb2e8f9f7 3395 /*!
<> 144:ef7eb2e8f9f7 3396 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3397 * @{
<> 144:ef7eb2e8f9f7 3398 */
<> 144:ef7eb2e8f9f7 3399
<> 144:ef7eb2e8f9f7 3400 /** CRC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 3401 typedef struct {
<> 144:ef7eb2e8f9f7 3402 union { /* offset: 0x0 */
<> 144:ef7eb2e8f9f7 3403 struct { /* offset: 0x0 */
<> 144:ef7eb2e8f9f7 3404 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
<> 144:ef7eb2e8f9f7 3405 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
<> 144:ef7eb2e8f9f7 3406 } ACCESS16BIT;
<> 144:ef7eb2e8f9f7 3407 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 3408 struct { /* offset: 0x0 */
<> 144:ef7eb2e8f9f7 3409 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
<> 144:ef7eb2e8f9f7 3410 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
<> 144:ef7eb2e8f9f7 3411 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
<> 144:ef7eb2e8f9f7 3412 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
<> 144:ef7eb2e8f9f7 3413 } ACCESS8BIT;
<> 144:ef7eb2e8f9f7 3414 };
<> 144:ef7eb2e8f9f7 3415 union { /* offset: 0x4 */
<> 144:ef7eb2e8f9f7 3416 struct { /* offset: 0x4 */
<> 144:ef7eb2e8f9f7 3417 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
<> 144:ef7eb2e8f9f7 3418 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
<> 144:ef7eb2e8f9f7 3419 } GPOLY_ACCESS16BIT;
<> 144:ef7eb2e8f9f7 3420 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 3421 struct { /* offset: 0x4 */
<> 144:ef7eb2e8f9f7 3422 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
<> 144:ef7eb2e8f9f7 3423 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
<> 144:ef7eb2e8f9f7 3424 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
<> 144:ef7eb2e8f9f7 3425 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
<> 144:ef7eb2e8f9f7 3426 } GPOLY_ACCESS8BIT;
<> 144:ef7eb2e8f9f7 3427 };
<> 144:ef7eb2e8f9f7 3428 union { /* offset: 0x8 */
<> 144:ef7eb2e8f9f7 3429 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 3430 struct { /* offset: 0x8 */
<> 144:ef7eb2e8f9f7 3431 uint8_t RESERVED_0[3];
<> 144:ef7eb2e8f9f7 3432 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
<> 144:ef7eb2e8f9f7 3433 } CTRL_ACCESS8BIT;
<> 144:ef7eb2e8f9f7 3434 };
<> 144:ef7eb2e8f9f7 3435 } CRC_Type;
<> 144:ef7eb2e8f9f7 3436
<> 144:ef7eb2e8f9f7 3437 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3438 -- CRC Register Masks
<> 144:ef7eb2e8f9f7 3439 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3440
<> 144:ef7eb2e8f9f7 3441 /*!
<> 144:ef7eb2e8f9f7 3442 * @addtogroup CRC_Register_Masks CRC Register Masks
<> 144:ef7eb2e8f9f7 3443 * @{
<> 144:ef7eb2e8f9f7 3444 */
<> 144:ef7eb2e8f9f7 3445
<> 144:ef7eb2e8f9f7 3446 /*! @name DATAL - CRC_DATAL register. */
<> 144:ef7eb2e8f9f7 3447 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 3448 #define CRC_DATAL_DATAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3449 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
<> 144:ef7eb2e8f9f7 3450
<> 144:ef7eb2e8f9f7 3451 /*! @name DATAH - CRC_DATAH register. */
<> 144:ef7eb2e8f9f7 3452 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 3453 #define CRC_DATAH_DATAH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3454 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
<> 144:ef7eb2e8f9f7 3455
<> 144:ef7eb2e8f9f7 3456 /*! @name DATA - CRC Data register */
<> 144:ef7eb2e8f9f7 3457 #define CRC_DATA_LL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3458 #define CRC_DATA_LL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3459 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
<> 144:ef7eb2e8f9f7 3460 #define CRC_DATA_LU_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 3461 #define CRC_DATA_LU_SHIFT (8U)
<> 144:ef7eb2e8f9f7 3462 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
<> 144:ef7eb2e8f9f7 3463 #define CRC_DATA_HL_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 3464 #define CRC_DATA_HL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 3465 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
<> 144:ef7eb2e8f9f7 3466 #define CRC_DATA_HU_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 3467 #define CRC_DATA_HU_SHIFT (24U)
<> 144:ef7eb2e8f9f7 3468 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
<> 144:ef7eb2e8f9f7 3469
<> 144:ef7eb2e8f9f7 3470 /*! @name DATALL - CRC_DATALL register. */
<> 144:ef7eb2e8f9f7 3471 #define CRC_DATALL_DATALL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3472 #define CRC_DATALL_DATALL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3473 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
<> 144:ef7eb2e8f9f7 3474
<> 144:ef7eb2e8f9f7 3475 /*! @name DATALU - CRC_DATALU register. */
<> 144:ef7eb2e8f9f7 3476 #define CRC_DATALU_DATALU_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3477 #define CRC_DATALU_DATALU_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3478 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
<> 144:ef7eb2e8f9f7 3479
<> 144:ef7eb2e8f9f7 3480 /*! @name DATAHL - CRC_DATAHL register. */
<> 144:ef7eb2e8f9f7 3481 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3482 #define CRC_DATAHL_DATAHL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3483 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
<> 144:ef7eb2e8f9f7 3484
<> 144:ef7eb2e8f9f7 3485 /*! @name DATAHU - CRC_DATAHU register. */
<> 144:ef7eb2e8f9f7 3486 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3487 #define CRC_DATAHU_DATAHU_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3488 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
<> 144:ef7eb2e8f9f7 3489
<> 144:ef7eb2e8f9f7 3490 /*! @name GPOLYL - CRC_GPOLYL register. */
<> 144:ef7eb2e8f9f7 3491 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 3492 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3493 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
<> 144:ef7eb2e8f9f7 3494
<> 144:ef7eb2e8f9f7 3495 /*! @name GPOLYH - CRC_GPOLYH register. */
<> 144:ef7eb2e8f9f7 3496 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 3497 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3498 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
<> 144:ef7eb2e8f9f7 3499
<> 144:ef7eb2e8f9f7 3500 /*! @name GPOLY - CRC Polynomial register */
<> 144:ef7eb2e8f9f7 3501 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 3502 #define CRC_GPOLY_LOW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3503 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
<> 144:ef7eb2e8f9f7 3504 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 3505 #define CRC_GPOLY_HIGH_SHIFT (16U)
<> 144:ef7eb2e8f9f7 3506 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
<> 144:ef7eb2e8f9f7 3507
<> 144:ef7eb2e8f9f7 3508 /*! @name GPOLYLL - CRC_GPOLYLL register. */
<> 144:ef7eb2e8f9f7 3509 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3510 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3511 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
<> 144:ef7eb2e8f9f7 3512
<> 144:ef7eb2e8f9f7 3513 /*! @name GPOLYLU - CRC_GPOLYLU register. */
<> 144:ef7eb2e8f9f7 3514 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3515 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3516 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
<> 144:ef7eb2e8f9f7 3517
<> 144:ef7eb2e8f9f7 3518 /*! @name GPOLYHL - CRC_GPOLYHL register. */
<> 144:ef7eb2e8f9f7 3519 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3520 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3521 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
<> 144:ef7eb2e8f9f7 3522
<> 144:ef7eb2e8f9f7 3523 /*! @name GPOLYHU - CRC_GPOLYHU register. */
<> 144:ef7eb2e8f9f7 3524 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3525 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3526 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
<> 144:ef7eb2e8f9f7 3527
<> 144:ef7eb2e8f9f7 3528 /*! @name CTRL - CRC Control register */
<> 144:ef7eb2e8f9f7 3529 #define CRC_CTRL_TCRC_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 3530 #define CRC_CTRL_TCRC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 3531 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
<> 144:ef7eb2e8f9f7 3532 #define CRC_CTRL_WAS_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 3533 #define CRC_CTRL_WAS_SHIFT (25U)
<> 144:ef7eb2e8f9f7 3534 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
<> 144:ef7eb2e8f9f7 3535 #define CRC_CTRL_FXOR_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 3536 #define CRC_CTRL_FXOR_SHIFT (26U)
<> 144:ef7eb2e8f9f7 3537 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
<> 144:ef7eb2e8f9f7 3538 #define CRC_CTRL_TOTR_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 3539 #define CRC_CTRL_TOTR_SHIFT (28U)
<> 144:ef7eb2e8f9f7 3540 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
<> 144:ef7eb2e8f9f7 3541 #define CRC_CTRL_TOT_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 3542 #define CRC_CTRL_TOT_SHIFT (30U)
<> 144:ef7eb2e8f9f7 3543 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
<> 144:ef7eb2e8f9f7 3544
<> 144:ef7eb2e8f9f7 3545 /*! @name CTRLHU - CRC_CTRLHU register. */
<> 144:ef7eb2e8f9f7 3546 #define CRC_CTRLHU_TCRC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3547 #define CRC_CTRLHU_TCRC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3548 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
<> 144:ef7eb2e8f9f7 3549 #define CRC_CTRLHU_WAS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3550 #define CRC_CTRLHU_WAS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3551 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
<> 144:ef7eb2e8f9f7 3552 #define CRC_CTRLHU_FXOR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3553 #define CRC_CTRLHU_FXOR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3554 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
<> 144:ef7eb2e8f9f7 3555 #define CRC_CTRLHU_TOTR_MASK (0x30U)
<> 144:ef7eb2e8f9f7 3556 #define CRC_CTRLHU_TOTR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3557 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
<> 144:ef7eb2e8f9f7 3558 #define CRC_CTRLHU_TOT_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 3559 #define CRC_CTRLHU_TOT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3560 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
<> 144:ef7eb2e8f9f7 3561
<> 144:ef7eb2e8f9f7 3562
<> 144:ef7eb2e8f9f7 3563 /*!
<> 144:ef7eb2e8f9f7 3564 * @}
<> 144:ef7eb2e8f9f7 3565 */ /* end of group CRC_Register_Masks */
<> 144:ef7eb2e8f9f7 3566
<> 144:ef7eb2e8f9f7 3567
<> 144:ef7eb2e8f9f7 3568 /* CRC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 3569 /** Peripheral CRC base address */
<> 144:ef7eb2e8f9f7 3570 #define CRC_BASE (0x40032000u)
<> 144:ef7eb2e8f9f7 3571 /** Peripheral CRC base pointer */
<> 144:ef7eb2e8f9f7 3572 #define CRC0 ((CRC_Type *)CRC_BASE)
<> 144:ef7eb2e8f9f7 3573 /** Array initializer of CRC peripheral base addresses */
<> 144:ef7eb2e8f9f7 3574 #define CRC_BASE_ADDRS { CRC_BASE }
<> 144:ef7eb2e8f9f7 3575 /** Array initializer of CRC peripheral base pointers */
<> 144:ef7eb2e8f9f7 3576 #define CRC_BASE_PTRS { CRC0 }
<> 144:ef7eb2e8f9f7 3577
<> 144:ef7eb2e8f9f7 3578 /*!
<> 144:ef7eb2e8f9f7 3579 * @}
<> 144:ef7eb2e8f9f7 3580 */ /* end of group CRC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 3581
<> 144:ef7eb2e8f9f7 3582
<> 144:ef7eb2e8f9f7 3583 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3584 -- DAC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3585 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3586
<> 144:ef7eb2e8f9f7 3587 /*!
<> 144:ef7eb2e8f9f7 3588 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3589 * @{
<> 144:ef7eb2e8f9f7 3590 */
<> 144:ef7eb2e8f9f7 3591
<> 144:ef7eb2e8f9f7 3592 /** DAC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 3593 typedef struct {
<> 144:ef7eb2e8f9f7 3594 struct { /* offset: 0x0, array step: 0x2 */
<> 144:ef7eb2e8f9f7 3595 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
<> 144:ef7eb2e8f9f7 3596 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
<> 144:ef7eb2e8f9f7 3597 } DAT[16];
<> 144:ef7eb2e8f9f7 3598 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 3599 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
<> 144:ef7eb2e8f9f7 3600 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
<> 144:ef7eb2e8f9f7 3601 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
<> 144:ef7eb2e8f9f7 3602 } DAC_Type;
<> 144:ef7eb2e8f9f7 3603
<> 144:ef7eb2e8f9f7 3604 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3605 -- DAC Register Masks
<> 144:ef7eb2e8f9f7 3606 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3607
<> 144:ef7eb2e8f9f7 3608 /*!
<> 144:ef7eb2e8f9f7 3609 * @addtogroup DAC_Register_Masks DAC Register Masks
<> 144:ef7eb2e8f9f7 3610 * @{
<> 144:ef7eb2e8f9f7 3611 */
<> 144:ef7eb2e8f9f7 3612
<> 144:ef7eb2e8f9f7 3613 /*! @name DATL - DAC Data Low Register */
<> 144:ef7eb2e8f9f7 3614 #define DAC_DATL_DATA0_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 3615 #define DAC_DATL_DATA0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3616 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
<> 144:ef7eb2e8f9f7 3617
<> 144:ef7eb2e8f9f7 3618 /* The count of DAC_DATL */
<> 144:ef7eb2e8f9f7 3619 #define DAC_DATL_COUNT (16U)
<> 144:ef7eb2e8f9f7 3620
<> 144:ef7eb2e8f9f7 3621 /*! @name DATH - DAC Data High Register */
<> 144:ef7eb2e8f9f7 3622 #define DAC_DATH_DATA1_MASK (0xFU)
<> 144:ef7eb2e8f9f7 3623 #define DAC_DATH_DATA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3624 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
<> 144:ef7eb2e8f9f7 3625
<> 144:ef7eb2e8f9f7 3626 /* The count of DAC_DATH */
<> 144:ef7eb2e8f9f7 3627 #define DAC_DATH_COUNT (16U)
<> 144:ef7eb2e8f9f7 3628
<> 144:ef7eb2e8f9f7 3629 /*! @name SR - DAC Status Register */
<> 144:ef7eb2e8f9f7 3630 #define DAC_SR_DACBFRPBF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3631 #define DAC_SR_DACBFRPBF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3632 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
<> 144:ef7eb2e8f9f7 3633 #define DAC_SR_DACBFRPTF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3634 #define DAC_SR_DACBFRPTF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3635 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
<> 144:ef7eb2e8f9f7 3636 #define DAC_SR_DACBFWMF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3637 #define DAC_SR_DACBFWMF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3638 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
<> 144:ef7eb2e8f9f7 3639
<> 144:ef7eb2e8f9f7 3640 /*! @name C0 - DAC Control Register */
<> 144:ef7eb2e8f9f7 3641 #define DAC_C0_DACBBIEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3642 #define DAC_C0_DACBBIEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3643 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
<> 144:ef7eb2e8f9f7 3644 #define DAC_C0_DACBTIEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3645 #define DAC_C0_DACBTIEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3646 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
<> 144:ef7eb2e8f9f7 3647 #define DAC_C0_DACBWIEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3648 #define DAC_C0_DACBWIEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3649 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
<> 144:ef7eb2e8f9f7 3650 #define DAC_C0_LPEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3651 #define DAC_C0_LPEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3652 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
<> 144:ef7eb2e8f9f7 3653 #define DAC_C0_DACSWTRG_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3654 #define DAC_C0_DACSWTRG_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3655 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
<> 144:ef7eb2e8f9f7 3656 #define DAC_C0_DACTRGSEL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3657 #define DAC_C0_DACTRGSEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3658 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
<> 144:ef7eb2e8f9f7 3659 #define DAC_C0_DACRFS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3660 #define DAC_C0_DACRFS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3661 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
<> 144:ef7eb2e8f9f7 3662 #define DAC_C0_DACEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3663 #define DAC_C0_DACEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3664 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
<> 144:ef7eb2e8f9f7 3665
<> 144:ef7eb2e8f9f7 3666 /*! @name C1 - DAC Control Register 1 */
<> 144:ef7eb2e8f9f7 3667 #define DAC_C1_DACBFEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3668 #define DAC_C1_DACBFEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3669 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
<> 144:ef7eb2e8f9f7 3670 #define DAC_C1_DACBFMD_MASK (0x6U)
<> 144:ef7eb2e8f9f7 3671 #define DAC_C1_DACBFMD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3672 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
<> 144:ef7eb2e8f9f7 3673 #define DAC_C1_DACBFWM_MASK (0x18U)
<> 144:ef7eb2e8f9f7 3674 #define DAC_C1_DACBFWM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3675 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
<> 144:ef7eb2e8f9f7 3676 #define DAC_C1_DMAEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3677 #define DAC_C1_DMAEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3678 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 3679
<> 144:ef7eb2e8f9f7 3680 /*! @name C2 - DAC Control Register 2 */
<> 144:ef7eb2e8f9f7 3681 #define DAC_C2_DACBFUP_MASK (0xFU)
<> 144:ef7eb2e8f9f7 3682 #define DAC_C2_DACBFUP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3683 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
<> 144:ef7eb2e8f9f7 3684 #define DAC_C2_DACBFRP_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 3685 #define DAC_C2_DACBFRP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3686 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
<> 144:ef7eb2e8f9f7 3687
<> 144:ef7eb2e8f9f7 3688
<> 144:ef7eb2e8f9f7 3689 /*!
<> 144:ef7eb2e8f9f7 3690 * @}
<> 144:ef7eb2e8f9f7 3691 */ /* end of group DAC_Register_Masks */
<> 144:ef7eb2e8f9f7 3692
<> 144:ef7eb2e8f9f7 3693
<> 144:ef7eb2e8f9f7 3694 /* DAC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 3695 /** Peripheral DAC0 base address */
<> 144:ef7eb2e8f9f7 3696 #define DAC0_BASE (0x400CC000u)
<> 144:ef7eb2e8f9f7 3697 /** Peripheral DAC0 base pointer */
<> 144:ef7eb2e8f9f7 3698 #define DAC0 ((DAC_Type *)DAC0_BASE)
<> 144:ef7eb2e8f9f7 3699 /** Peripheral DAC1 base address */
<> 144:ef7eb2e8f9f7 3700 #define DAC1_BASE (0x400CD000u)
<> 144:ef7eb2e8f9f7 3701 /** Peripheral DAC1 base pointer */
<> 144:ef7eb2e8f9f7 3702 #define DAC1 ((DAC_Type *)DAC1_BASE)
<> 144:ef7eb2e8f9f7 3703 /** Array initializer of DAC peripheral base addresses */
<> 144:ef7eb2e8f9f7 3704 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
<> 144:ef7eb2e8f9f7 3705 /** Array initializer of DAC peripheral base pointers */
<> 144:ef7eb2e8f9f7 3706 #define DAC_BASE_PTRS { DAC0, DAC1 }
<> 144:ef7eb2e8f9f7 3707 /** Interrupt vectors for the DAC peripheral type */
<> 144:ef7eb2e8f9f7 3708 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
<> 144:ef7eb2e8f9f7 3709
<> 144:ef7eb2e8f9f7 3710 /*!
<> 144:ef7eb2e8f9f7 3711 * @}
<> 144:ef7eb2e8f9f7 3712 */ /* end of group DAC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 3713
<> 144:ef7eb2e8f9f7 3714
<> 144:ef7eb2e8f9f7 3715 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3716 -- DMA Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3717 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3718
<> 144:ef7eb2e8f9f7 3719 /*!
<> 144:ef7eb2e8f9f7 3720 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
<> 144:ef7eb2e8f9f7 3721 * @{
<> 144:ef7eb2e8f9f7 3722 */
<> 144:ef7eb2e8f9f7 3723
<> 144:ef7eb2e8f9f7 3724 /** DMA - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 3725 typedef struct {
<> 144:ef7eb2e8f9f7 3726 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 3727 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 3728 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 3729 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 3730 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 3731 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 3732 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 3733 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
<> 144:ef7eb2e8f9f7 3734 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
<> 144:ef7eb2e8f9f7 3735 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
<> 144:ef7eb2e8f9f7 3736 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 3737 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
<> 144:ef7eb2e8f9f7 3738 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
<> 144:ef7eb2e8f9f7 3739 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
<> 144:ef7eb2e8f9f7 3740 uint8_t RESERVED_2[4];
<> 144:ef7eb2e8f9f7 3741 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 3742 uint8_t RESERVED_3[4];
<> 144:ef7eb2e8f9f7 3743 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 3744 uint8_t RESERVED_4[4];
<> 144:ef7eb2e8f9f7 3745 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
<> 144:ef7eb2e8f9f7 3746 uint8_t RESERVED_5[12];
<> 144:ef7eb2e8f9f7 3747 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 3748 uint8_t RESERVED_6[184];
<> 144:ef7eb2e8f9f7 3749 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 3750 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
<> 144:ef7eb2e8f9f7 3751 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
<> 144:ef7eb2e8f9f7 3752 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
<> 144:ef7eb2e8f9f7 3753 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
<> 144:ef7eb2e8f9f7 3754 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
<> 144:ef7eb2e8f9f7 3755 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
<> 144:ef7eb2e8f9f7 3756 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
<> 144:ef7eb2e8f9f7 3757 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
<> 144:ef7eb2e8f9f7 3758 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
<> 144:ef7eb2e8f9f7 3759 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
<> 144:ef7eb2e8f9f7 3760 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
<> 144:ef7eb2e8f9f7 3761 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
<> 144:ef7eb2e8f9f7 3762 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
<> 144:ef7eb2e8f9f7 3763 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
<> 144:ef7eb2e8f9f7 3764 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
<> 144:ef7eb2e8f9f7 3765 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
<> 144:ef7eb2e8f9f7 3766 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
<> 144:ef7eb2e8f9f7 3767 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
<> 144:ef7eb2e8f9f7 3768 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
<> 144:ef7eb2e8f9f7 3769 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
<> 144:ef7eb2e8f9f7 3770 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
<> 144:ef7eb2e8f9f7 3771 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
<> 144:ef7eb2e8f9f7 3772 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
<> 144:ef7eb2e8f9f7 3773 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
<> 144:ef7eb2e8f9f7 3774 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
<> 144:ef7eb2e8f9f7 3775 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
<> 144:ef7eb2e8f9f7 3776 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
<> 144:ef7eb2e8f9f7 3777 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
<> 144:ef7eb2e8f9f7 3778 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
<> 144:ef7eb2e8f9f7 3779 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
<> 144:ef7eb2e8f9f7 3780 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
<> 144:ef7eb2e8f9f7 3781 uint8_t RESERVED_7[3808];
<> 144:ef7eb2e8f9f7 3782 struct { /* offset: 0x1000, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3783 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3784 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3785 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3786 union { /* offset: 0x1008, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3787 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3788 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3789 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3790 };
<> 144:ef7eb2e8f9f7 3791 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3792 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3793 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3794 union { /* offset: 0x1016, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3795 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3796 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3797 };
<> 144:ef7eb2e8f9f7 3798 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3799 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3800 union { /* offset: 0x101E, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3801 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3802 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
<> 144:ef7eb2e8f9f7 3803 };
<> 144:ef7eb2e8f9f7 3804 } TCD[32];
<> 144:ef7eb2e8f9f7 3805 } DMA_Type;
<> 144:ef7eb2e8f9f7 3806
<> 144:ef7eb2e8f9f7 3807 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3808 -- DMA Register Masks
<> 144:ef7eb2e8f9f7 3809 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 3810
<> 144:ef7eb2e8f9f7 3811 /*!
<> 144:ef7eb2e8f9f7 3812 * @addtogroup DMA_Register_Masks DMA Register Masks
<> 144:ef7eb2e8f9f7 3813 * @{
<> 144:ef7eb2e8f9f7 3814 */
<> 144:ef7eb2e8f9f7 3815
<> 144:ef7eb2e8f9f7 3816 /*! @name CR - Control Register */
<> 144:ef7eb2e8f9f7 3817 #define DMA_CR_EDBG_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3818 #define DMA_CR_EDBG_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3819 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
<> 144:ef7eb2e8f9f7 3820 #define DMA_CR_ERCA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3821 #define DMA_CR_ERCA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3822 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
<> 144:ef7eb2e8f9f7 3823 #define DMA_CR_ERGA_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3824 #define DMA_CR_ERGA_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3825 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
<> 144:ef7eb2e8f9f7 3826 #define DMA_CR_HOE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3827 #define DMA_CR_HOE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3828 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
<> 144:ef7eb2e8f9f7 3829 #define DMA_CR_HALT_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3830 #define DMA_CR_HALT_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3831 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
<> 144:ef7eb2e8f9f7 3832 #define DMA_CR_CLM_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3833 #define DMA_CR_CLM_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3834 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
<> 144:ef7eb2e8f9f7 3835 #define DMA_CR_EMLM_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3836 #define DMA_CR_EMLM_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3837 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
<> 144:ef7eb2e8f9f7 3838 #define DMA_CR_GRP0PRI_MASK (0x100U)
<> 144:ef7eb2e8f9f7 3839 #define DMA_CR_GRP0PRI_SHIFT (8U)
<> 144:ef7eb2e8f9f7 3840 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
<> 144:ef7eb2e8f9f7 3841 #define DMA_CR_GRP1PRI_MASK (0x400U)
<> 144:ef7eb2e8f9f7 3842 #define DMA_CR_GRP1PRI_SHIFT (10U)
<> 144:ef7eb2e8f9f7 3843 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
<> 144:ef7eb2e8f9f7 3844 #define DMA_CR_ECX_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 3845 #define DMA_CR_ECX_SHIFT (16U)
<> 144:ef7eb2e8f9f7 3846 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
<> 144:ef7eb2e8f9f7 3847 #define DMA_CR_CX_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 3848 #define DMA_CR_CX_SHIFT (17U)
<> 144:ef7eb2e8f9f7 3849 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
<> 144:ef7eb2e8f9f7 3850
<> 144:ef7eb2e8f9f7 3851 /*! @name ES - Error Status Register */
<> 144:ef7eb2e8f9f7 3852 #define DMA_ES_DBE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3853 #define DMA_ES_DBE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3854 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
<> 144:ef7eb2e8f9f7 3855 #define DMA_ES_SBE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3856 #define DMA_ES_SBE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3857 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
<> 144:ef7eb2e8f9f7 3858 #define DMA_ES_SGE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3859 #define DMA_ES_SGE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3860 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
<> 144:ef7eb2e8f9f7 3861 #define DMA_ES_NCE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3862 #define DMA_ES_NCE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3863 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
<> 144:ef7eb2e8f9f7 3864 #define DMA_ES_DOE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3865 #define DMA_ES_DOE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3866 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
<> 144:ef7eb2e8f9f7 3867 #define DMA_ES_DAE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3868 #define DMA_ES_DAE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3869 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
<> 144:ef7eb2e8f9f7 3870 #define DMA_ES_SOE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3871 #define DMA_ES_SOE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3872 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
<> 144:ef7eb2e8f9f7 3873 #define DMA_ES_SAE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3874 #define DMA_ES_SAE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3875 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
<> 144:ef7eb2e8f9f7 3876 #define DMA_ES_ERRCHN_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 3877 #define DMA_ES_ERRCHN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 3878 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
<> 144:ef7eb2e8f9f7 3879 #define DMA_ES_CPE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 3880 #define DMA_ES_CPE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 3881 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
<> 144:ef7eb2e8f9f7 3882 #define DMA_ES_GPE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 3883 #define DMA_ES_GPE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 3884 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
<> 144:ef7eb2e8f9f7 3885 #define DMA_ES_ECX_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 3886 #define DMA_ES_ECX_SHIFT (16U)
<> 144:ef7eb2e8f9f7 3887 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
<> 144:ef7eb2e8f9f7 3888 #define DMA_ES_VLD_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 3889 #define DMA_ES_VLD_SHIFT (31U)
<> 144:ef7eb2e8f9f7 3890 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
<> 144:ef7eb2e8f9f7 3891
<> 144:ef7eb2e8f9f7 3892 /*! @name ERQ - Enable Request Register */
<> 144:ef7eb2e8f9f7 3893 #define DMA_ERQ_ERQ0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3894 #define DMA_ERQ_ERQ0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3895 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
<> 144:ef7eb2e8f9f7 3896 #define DMA_ERQ_ERQ1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3897 #define DMA_ERQ_ERQ1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3898 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
<> 144:ef7eb2e8f9f7 3899 #define DMA_ERQ_ERQ2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3900 #define DMA_ERQ_ERQ2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3901 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
<> 144:ef7eb2e8f9f7 3902 #define DMA_ERQ_ERQ3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 3903 #define DMA_ERQ_ERQ3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 3904 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
<> 144:ef7eb2e8f9f7 3905 #define DMA_ERQ_ERQ4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 3906 #define DMA_ERQ_ERQ4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 3907 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
<> 144:ef7eb2e8f9f7 3908 #define DMA_ERQ_ERQ5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 3909 #define DMA_ERQ_ERQ5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 3910 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
<> 144:ef7eb2e8f9f7 3911 #define DMA_ERQ_ERQ6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 3912 #define DMA_ERQ_ERQ6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 3913 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
<> 144:ef7eb2e8f9f7 3914 #define DMA_ERQ_ERQ7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 3915 #define DMA_ERQ_ERQ7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 3916 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
<> 144:ef7eb2e8f9f7 3917 #define DMA_ERQ_ERQ8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 3918 #define DMA_ERQ_ERQ8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 3919 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
<> 144:ef7eb2e8f9f7 3920 #define DMA_ERQ_ERQ9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 3921 #define DMA_ERQ_ERQ9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 3922 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
<> 144:ef7eb2e8f9f7 3923 #define DMA_ERQ_ERQ10_MASK (0x400U)
<> 144:ef7eb2e8f9f7 3924 #define DMA_ERQ_ERQ10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 3925 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
<> 144:ef7eb2e8f9f7 3926 #define DMA_ERQ_ERQ11_MASK (0x800U)
<> 144:ef7eb2e8f9f7 3927 #define DMA_ERQ_ERQ11_SHIFT (11U)
<> 144:ef7eb2e8f9f7 3928 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
<> 144:ef7eb2e8f9f7 3929 #define DMA_ERQ_ERQ12_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 3930 #define DMA_ERQ_ERQ12_SHIFT (12U)
<> 144:ef7eb2e8f9f7 3931 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
<> 144:ef7eb2e8f9f7 3932 #define DMA_ERQ_ERQ13_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 3933 #define DMA_ERQ_ERQ13_SHIFT (13U)
<> 144:ef7eb2e8f9f7 3934 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
<> 144:ef7eb2e8f9f7 3935 #define DMA_ERQ_ERQ14_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 3936 #define DMA_ERQ_ERQ14_SHIFT (14U)
<> 144:ef7eb2e8f9f7 3937 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
<> 144:ef7eb2e8f9f7 3938 #define DMA_ERQ_ERQ15_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 3939 #define DMA_ERQ_ERQ15_SHIFT (15U)
<> 144:ef7eb2e8f9f7 3940 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
<> 144:ef7eb2e8f9f7 3941 #define DMA_ERQ_ERQ16_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 3942 #define DMA_ERQ_ERQ16_SHIFT (16U)
<> 144:ef7eb2e8f9f7 3943 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
<> 144:ef7eb2e8f9f7 3944 #define DMA_ERQ_ERQ17_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 3945 #define DMA_ERQ_ERQ17_SHIFT (17U)
<> 144:ef7eb2e8f9f7 3946 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
<> 144:ef7eb2e8f9f7 3947 #define DMA_ERQ_ERQ18_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 3948 #define DMA_ERQ_ERQ18_SHIFT (18U)
<> 144:ef7eb2e8f9f7 3949 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
<> 144:ef7eb2e8f9f7 3950 #define DMA_ERQ_ERQ19_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 3951 #define DMA_ERQ_ERQ19_SHIFT (19U)
<> 144:ef7eb2e8f9f7 3952 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
<> 144:ef7eb2e8f9f7 3953 #define DMA_ERQ_ERQ20_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 3954 #define DMA_ERQ_ERQ20_SHIFT (20U)
<> 144:ef7eb2e8f9f7 3955 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
<> 144:ef7eb2e8f9f7 3956 #define DMA_ERQ_ERQ21_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 3957 #define DMA_ERQ_ERQ21_SHIFT (21U)
<> 144:ef7eb2e8f9f7 3958 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
<> 144:ef7eb2e8f9f7 3959 #define DMA_ERQ_ERQ22_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 3960 #define DMA_ERQ_ERQ22_SHIFT (22U)
<> 144:ef7eb2e8f9f7 3961 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
<> 144:ef7eb2e8f9f7 3962 #define DMA_ERQ_ERQ23_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 3963 #define DMA_ERQ_ERQ23_SHIFT (23U)
<> 144:ef7eb2e8f9f7 3964 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
<> 144:ef7eb2e8f9f7 3965 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 3966 #define DMA_ERQ_ERQ24_SHIFT (24U)
<> 144:ef7eb2e8f9f7 3967 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
<> 144:ef7eb2e8f9f7 3968 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 3969 #define DMA_ERQ_ERQ25_SHIFT (25U)
<> 144:ef7eb2e8f9f7 3970 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
<> 144:ef7eb2e8f9f7 3971 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 3972 #define DMA_ERQ_ERQ26_SHIFT (26U)
<> 144:ef7eb2e8f9f7 3973 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
<> 144:ef7eb2e8f9f7 3974 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 3975 #define DMA_ERQ_ERQ27_SHIFT (27U)
<> 144:ef7eb2e8f9f7 3976 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
<> 144:ef7eb2e8f9f7 3977 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 3978 #define DMA_ERQ_ERQ28_SHIFT (28U)
<> 144:ef7eb2e8f9f7 3979 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
<> 144:ef7eb2e8f9f7 3980 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 3981 #define DMA_ERQ_ERQ29_SHIFT (29U)
<> 144:ef7eb2e8f9f7 3982 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
<> 144:ef7eb2e8f9f7 3983 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 3984 #define DMA_ERQ_ERQ30_SHIFT (30U)
<> 144:ef7eb2e8f9f7 3985 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
<> 144:ef7eb2e8f9f7 3986 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 3987 #define DMA_ERQ_ERQ31_SHIFT (31U)
<> 144:ef7eb2e8f9f7 3988 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
<> 144:ef7eb2e8f9f7 3989
<> 144:ef7eb2e8f9f7 3990 /*! @name EEI - Enable Error Interrupt Register */
<> 144:ef7eb2e8f9f7 3991 #define DMA_EEI_EEI0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 3992 #define DMA_EEI_EEI0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 3993 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
<> 144:ef7eb2e8f9f7 3994 #define DMA_EEI_EEI1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 3995 #define DMA_EEI_EEI1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 3996 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
<> 144:ef7eb2e8f9f7 3997 #define DMA_EEI_EEI2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 3998 #define DMA_EEI_EEI2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 3999 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
<> 144:ef7eb2e8f9f7 4000 #define DMA_EEI_EEI3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4001 #define DMA_EEI_EEI3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4002 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
<> 144:ef7eb2e8f9f7 4003 #define DMA_EEI_EEI4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4004 #define DMA_EEI_EEI4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4005 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
<> 144:ef7eb2e8f9f7 4006 #define DMA_EEI_EEI5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4007 #define DMA_EEI_EEI5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4008 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
<> 144:ef7eb2e8f9f7 4009 #define DMA_EEI_EEI6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4010 #define DMA_EEI_EEI6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4011 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
<> 144:ef7eb2e8f9f7 4012 #define DMA_EEI_EEI7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4013 #define DMA_EEI_EEI7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4014 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
<> 144:ef7eb2e8f9f7 4015 #define DMA_EEI_EEI8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 4016 #define DMA_EEI_EEI8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4017 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
<> 144:ef7eb2e8f9f7 4018 #define DMA_EEI_EEI9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4019 #define DMA_EEI_EEI9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4020 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
<> 144:ef7eb2e8f9f7 4021 #define DMA_EEI_EEI10_MASK (0x400U)
<> 144:ef7eb2e8f9f7 4022 #define DMA_EEI_EEI10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 4023 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
<> 144:ef7eb2e8f9f7 4024 #define DMA_EEI_EEI11_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4025 #define DMA_EEI_EEI11_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4026 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
<> 144:ef7eb2e8f9f7 4027 #define DMA_EEI_EEI12_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4028 #define DMA_EEI_EEI12_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4029 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
<> 144:ef7eb2e8f9f7 4030 #define DMA_EEI_EEI13_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4031 #define DMA_EEI_EEI13_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4032 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
<> 144:ef7eb2e8f9f7 4033 #define DMA_EEI_EEI14_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4034 #define DMA_EEI_EEI14_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4035 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
<> 144:ef7eb2e8f9f7 4036 #define DMA_EEI_EEI15_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4037 #define DMA_EEI_EEI15_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4038 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
<> 144:ef7eb2e8f9f7 4039 #define DMA_EEI_EEI16_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4040 #define DMA_EEI_EEI16_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4041 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
<> 144:ef7eb2e8f9f7 4042 #define DMA_EEI_EEI17_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4043 #define DMA_EEI_EEI17_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4044 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
<> 144:ef7eb2e8f9f7 4045 #define DMA_EEI_EEI18_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4046 #define DMA_EEI_EEI18_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4047 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
<> 144:ef7eb2e8f9f7 4048 #define DMA_EEI_EEI19_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4049 #define DMA_EEI_EEI19_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4050 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
<> 144:ef7eb2e8f9f7 4051 #define DMA_EEI_EEI20_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4052 #define DMA_EEI_EEI20_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4053 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
<> 144:ef7eb2e8f9f7 4054 #define DMA_EEI_EEI21_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4055 #define DMA_EEI_EEI21_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4056 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
<> 144:ef7eb2e8f9f7 4057 #define DMA_EEI_EEI22_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4058 #define DMA_EEI_EEI22_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4059 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
<> 144:ef7eb2e8f9f7 4060 #define DMA_EEI_EEI23_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4061 #define DMA_EEI_EEI23_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4062 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
<> 144:ef7eb2e8f9f7 4063 #define DMA_EEI_EEI24_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4064 #define DMA_EEI_EEI24_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4065 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
<> 144:ef7eb2e8f9f7 4066 #define DMA_EEI_EEI25_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4067 #define DMA_EEI_EEI25_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4068 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
<> 144:ef7eb2e8f9f7 4069 #define DMA_EEI_EEI26_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4070 #define DMA_EEI_EEI26_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4071 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
<> 144:ef7eb2e8f9f7 4072 #define DMA_EEI_EEI27_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4073 #define DMA_EEI_EEI27_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4074 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
<> 144:ef7eb2e8f9f7 4075 #define DMA_EEI_EEI28_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4076 #define DMA_EEI_EEI28_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4077 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
<> 144:ef7eb2e8f9f7 4078 #define DMA_EEI_EEI29_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4079 #define DMA_EEI_EEI29_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4080 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
<> 144:ef7eb2e8f9f7 4081 #define DMA_EEI_EEI30_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4082 #define DMA_EEI_EEI30_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4083 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
<> 144:ef7eb2e8f9f7 4084 #define DMA_EEI_EEI31_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4085 #define DMA_EEI_EEI31_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4086 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
<> 144:ef7eb2e8f9f7 4087
<> 144:ef7eb2e8f9f7 4088 /*! @name CEEI - Clear Enable Error Interrupt Register */
<> 144:ef7eb2e8f9f7 4089 #define DMA_CEEI_CEEI_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4090 #define DMA_CEEI_CEEI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4091 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
<> 144:ef7eb2e8f9f7 4092 #define DMA_CEEI_CAEE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4093 #define DMA_CEEI_CAEE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4094 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
<> 144:ef7eb2e8f9f7 4095 #define DMA_CEEI_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4096 #define DMA_CEEI_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4097 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
<> 144:ef7eb2e8f9f7 4098
<> 144:ef7eb2e8f9f7 4099 /*! @name SEEI - Set Enable Error Interrupt Register */
<> 144:ef7eb2e8f9f7 4100 #define DMA_SEEI_SEEI_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4101 #define DMA_SEEI_SEEI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4102 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
<> 144:ef7eb2e8f9f7 4103 #define DMA_SEEI_SAEE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4104 #define DMA_SEEI_SAEE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4105 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
<> 144:ef7eb2e8f9f7 4106 #define DMA_SEEI_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4107 #define DMA_SEEI_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4108 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
<> 144:ef7eb2e8f9f7 4109
<> 144:ef7eb2e8f9f7 4110 /*! @name CERQ - Clear Enable Request Register */
<> 144:ef7eb2e8f9f7 4111 #define DMA_CERQ_CERQ_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4112 #define DMA_CERQ_CERQ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4113 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
<> 144:ef7eb2e8f9f7 4114 #define DMA_CERQ_CAER_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4115 #define DMA_CERQ_CAER_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4116 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
<> 144:ef7eb2e8f9f7 4117 #define DMA_CERQ_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4118 #define DMA_CERQ_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4119 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
<> 144:ef7eb2e8f9f7 4120
<> 144:ef7eb2e8f9f7 4121 /*! @name SERQ - Set Enable Request Register */
<> 144:ef7eb2e8f9f7 4122 #define DMA_SERQ_SERQ_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4123 #define DMA_SERQ_SERQ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4124 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
<> 144:ef7eb2e8f9f7 4125 #define DMA_SERQ_SAER_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4126 #define DMA_SERQ_SAER_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4127 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
<> 144:ef7eb2e8f9f7 4128 #define DMA_SERQ_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4129 #define DMA_SERQ_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4130 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
<> 144:ef7eb2e8f9f7 4131
<> 144:ef7eb2e8f9f7 4132 /*! @name CDNE - Clear DONE Status Bit Register */
<> 144:ef7eb2e8f9f7 4133 #define DMA_CDNE_CDNE_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4134 #define DMA_CDNE_CDNE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4135 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
<> 144:ef7eb2e8f9f7 4136 #define DMA_CDNE_CADN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4137 #define DMA_CDNE_CADN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4138 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
<> 144:ef7eb2e8f9f7 4139 #define DMA_CDNE_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4140 #define DMA_CDNE_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4141 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
<> 144:ef7eb2e8f9f7 4142
<> 144:ef7eb2e8f9f7 4143 /*! @name SSRT - Set START Bit Register */
<> 144:ef7eb2e8f9f7 4144 #define DMA_SSRT_SSRT_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4145 #define DMA_SSRT_SSRT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4146 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
<> 144:ef7eb2e8f9f7 4147 #define DMA_SSRT_SAST_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4148 #define DMA_SSRT_SAST_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4149 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
<> 144:ef7eb2e8f9f7 4150 #define DMA_SSRT_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4151 #define DMA_SSRT_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4152 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
<> 144:ef7eb2e8f9f7 4153
<> 144:ef7eb2e8f9f7 4154 /*! @name CERR - Clear Error Register */
<> 144:ef7eb2e8f9f7 4155 #define DMA_CERR_CERR_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4156 #define DMA_CERR_CERR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4157 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
<> 144:ef7eb2e8f9f7 4158 #define DMA_CERR_CAEI_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4159 #define DMA_CERR_CAEI_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4160 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
<> 144:ef7eb2e8f9f7 4161 #define DMA_CERR_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4162 #define DMA_CERR_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4163 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
<> 144:ef7eb2e8f9f7 4164
<> 144:ef7eb2e8f9f7 4165 /*! @name CINT - Clear Interrupt Request Register */
<> 144:ef7eb2e8f9f7 4166 #define DMA_CINT_CINT_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 4167 #define DMA_CINT_CINT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4168 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
<> 144:ef7eb2e8f9f7 4169 #define DMA_CINT_CAIR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4170 #define DMA_CINT_CAIR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4171 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
<> 144:ef7eb2e8f9f7 4172 #define DMA_CINT_NOP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4173 #define DMA_CINT_NOP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4174 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
<> 144:ef7eb2e8f9f7 4175
<> 144:ef7eb2e8f9f7 4176 /*! @name INT - Interrupt Request Register */
<> 144:ef7eb2e8f9f7 4177 #define DMA_INT_INT0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4178 #define DMA_INT_INT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4179 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
<> 144:ef7eb2e8f9f7 4180 #define DMA_INT_INT1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4181 #define DMA_INT_INT1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4182 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
<> 144:ef7eb2e8f9f7 4183 #define DMA_INT_INT2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4184 #define DMA_INT_INT2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4185 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
<> 144:ef7eb2e8f9f7 4186 #define DMA_INT_INT3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4187 #define DMA_INT_INT3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4188 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
<> 144:ef7eb2e8f9f7 4189 #define DMA_INT_INT4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4190 #define DMA_INT_INT4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4191 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
<> 144:ef7eb2e8f9f7 4192 #define DMA_INT_INT5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4193 #define DMA_INT_INT5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4194 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
<> 144:ef7eb2e8f9f7 4195 #define DMA_INT_INT6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4196 #define DMA_INT_INT6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4197 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
<> 144:ef7eb2e8f9f7 4198 #define DMA_INT_INT7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4199 #define DMA_INT_INT7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4200 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
<> 144:ef7eb2e8f9f7 4201 #define DMA_INT_INT8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 4202 #define DMA_INT_INT8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4203 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
<> 144:ef7eb2e8f9f7 4204 #define DMA_INT_INT9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4205 #define DMA_INT_INT9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4206 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
<> 144:ef7eb2e8f9f7 4207 #define DMA_INT_INT10_MASK (0x400U)
<> 144:ef7eb2e8f9f7 4208 #define DMA_INT_INT10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 4209 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
<> 144:ef7eb2e8f9f7 4210 #define DMA_INT_INT11_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4211 #define DMA_INT_INT11_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4212 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
<> 144:ef7eb2e8f9f7 4213 #define DMA_INT_INT12_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4214 #define DMA_INT_INT12_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4215 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
<> 144:ef7eb2e8f9f7 4216 #define DMA_INT_INT13_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4217 #define DMA_INT_INT13_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4218 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
<> 144:ef7eb2e8f9f7 4219 #define DMA_INT_INT14_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4220 #define DMA_INT_INT14_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4221 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
<> 144:ef7eb2e8f9f7 4222 #define DMA_INT_INT15_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4223 #define DMA_INT_INT15_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4224 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
<> 144:ef7eb2e8f9f7 4225 #define DMA_INT_INT16_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4226 #define DMA_INT_INT16_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4227 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
<> 144:ef7eb2e8f9f7 4228 #define DMA_INT_INT17_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4229 #define DMA_INT_INT17_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4230 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
<> 144:ef7eb2e8f9f7 4231 #define DMA_INT_INT18_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4232 #define DMA_INT_INT18_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4233 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
<> 144:ef7eb2e8f9f7 4234 #define DMA_INT_INT19_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4235 #define DMA_INT_INT19_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4236 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
<> 144:ef7eb2e8f9f7 4237 #define DMA_INT_INT20_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4238 #define DMA_INT_INT20_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4239 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
<> 144:ef7eb2e8f9f7 4240 #define DMA_INT_INT21_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4241 #define DMA_INT_INT21_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4242 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
<> 144:ef7eb2e8f9f7 4243 #define DMA_INT_INT22_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4244 #define DMA_INT_INT22_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4245 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
<> 144:ef7eb2e8f9f7 4246 #define DMA_INT_INT23_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4247 #define DMA_INT_INT23_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4248 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
<> 144:ef7eb2e8f9f7 4249 #define DMA_INT_INT24_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4250 #define DMA_INT_INT24_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4251 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
<> 144:ef7eb2e8f9f7 4252 #define DMA_INT_INT25_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4253 #define DMA_INT_INT25_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4254 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
<> 144:ef7eb2e8f9f7 4255 #define DMA_INT_INT26_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4256 #define DMA_INT_INT26_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4257 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
<> 144:ef7eb2e8f9f7 4258 #define DMA_INT_INT27_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4259 #define DMA_INT_INT27_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4260 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
<> 144:ef7eb2e8f9f7 4261 #define DMA_INT_INT28_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4262 #define DMA_INT_INT28_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4263 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
<> 144:ef7eb2e8f9f7 4264 #define DMA_INT_INT29_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4265 #define DMA_INT_INT29_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4266 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
<> 144:ef7eb2e8f9f7 4267 #define DMA_INT_INT30_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4268 #define DMA_INT_INT30_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4269 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
<> 144:ef7eb2e8f9f7 4270 #define DMA_INT_INT31_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4271 #define DMA_INT_INT31_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4272 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
<> 144:ef7eb2e8f9f7 4273
<> 144:ef7eb2e8f9f7 4274 /*! @name ERR - Error Register */
<> 144:ef7eb2e8f9f7 4275 #define DMA_ERR_ERR0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4276 #define DMA_ERR_ERR0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4277 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
<> 144:ef7eb2e8f9f7 4278 #define DMA_ERR_ERR1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4279 #define DMA_ERR_ERR1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4280 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
<> 144:ef7eb2e8f9f7 4281 #define DMA_ERR_ERR2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4282 #define DMA_ERR_ERR2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4283 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
<> 144:ef7eb2e8f9f7 4284 #define DMA_ERR_ERR3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4285 #define DMA_ERR_ERR3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4286 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
<> 144:ef7eb2e8f9f7 4287 #define DMA_ERR_ERR4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4288 #define DMA_ERR_ERR4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4289 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
<> 144:ef7eb2e8f9f7 4290 #define DMA_ERR_ERR5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4291 #define DMA_ERR_ERR5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4292 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
<> 144:ef7eb2e8f9f7 4293 #define DMA_ERR_ERR6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4294 #define DMA_ERR_ERR6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4295 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
<> 144:ef7eb2e8f9f7 4296 #define DMA_ERR_ERR7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4297 #define DMA_ERR_ERR7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4298 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
<> 144:ef7eb2e8f9f7 4299 #define DMA_ERR_ERR8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 4300 #define DMA_ERR_ERR8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4301 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
<> 144:ef7eb2e8f9f7 4302 #define DMA_ERR_ERR9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4303 #define DMA_ERR_ERR9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4304 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
<> 144:ef7eb2e8f9f7 4305 #define DMA_ERR_ERR10_MASK (0x400U)
<> 144:ef7eb2e8f9f7 4306 #define DMA_ERR_ERR10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 4307 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
<> 144:ef7eb2e8f9f7 4308 #define DMA_ERR_ERR11_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4309 #define DMA_ERR_ERR11_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4310 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
<> 144:ef7eb2e8f9f7 4311 #define DMA_ERR_ERR12_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4312 #define DMA_ERR_ERR12_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4313 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
<> 144:ef7eb2e8f9f7 4314 #define DMA_ERR_ERR13_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4315 #define DMA_ERR_ERR13_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4316 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
<> 144:ef7eb2e8f9f7 4317 #define DMA_ERR_ERR14_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4318 #define DMA_ERR_ERR14_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4319 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
<> 144:ef7eb2e8f9f7 4320 #define DMA_ERR_ERR15_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4321 #define DMA_ERR_ERR15_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4322 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
<> 144:ef7eb2e8f9f7 4323 #define DMA_ERR_ERR16_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4324 #define DMA_ERR_ERR16_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4325 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
<> 144:ef7eb2e8f9f7 4326 #define DMA_ERR_ERR17_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4327 #define DMA_ERR_ERR17_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4328 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
<> 144:ef7eb2e8f9f7 4329 #define DMA_ERR_ERR18_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4330 #define DMA_ERR_ERR18_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4331 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
<> 144:ef7eb2e8f9f7 4332 #define DMA_ERR_ERR19_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4333 #define DMA_ERR_ERR19_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4334 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
<> 144:ef7eb2e8f9f7 4335 #define DMA_ERR_ERR20_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4336 #define DMA_ERR_ERR20_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4337 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
<> 144:ef7eb2e8f9f7 4338 #define DMA_ERR_ERR21_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4339 #define DMA_ERR_ERR21_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4340 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
<> 144:ef7eb2e8f9f7 4341 #define DMA_ERR_ERR22_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4342 #define DMA_ERR_ERR22_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4343 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
<> 144:ef7eb2e8f9f7 4344 #define DMA_ERR_ERR23_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4345 #define DMA_ERR_ERR23_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4346 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
<> 144:ef7eb2e8f9f7 4347 #define DMA_ERR_ERR24_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4348 #define DMA_ERR_ERR24_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4349 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
<> 144:ef7eb2e8f9f7 4350 #define DMA_ERR_ERR25_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4351 #define DMA_ERR_ERR25_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4352 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
<> 144:ef7eb2e8f9f7 4353 #define DMA_ERR_ERR26_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4354 #define DMA_ERR_ERR26_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4355 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
<> 144:ef7eb2e8f9f7 4356 #define DMA_ERR_ERR27_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4357 #define DMA_ERR_ERR27_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4358 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
<> 144:ef7eb2e8f9f7 4359 #define DMA_ERR_ERR28_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4360 #define DMA_ERR_ERR28_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4361 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
<> 144:ef7eb2e8f9f7 4362 #define DMA_ERR_ERR29_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4363 #define DMA_ERR_ERR29_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4364 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
<> 144:ef7eb2e8f9f7 4365 #define DMA_ERR_ERR30_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4366 #define DMA_ERR_ERR30_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4367 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
<> 144:ef7eb2e8f9f7 4368 #define DMA_ERR_ERR31_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4369 #define DMA_ERR_ERR31_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4370 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
<> 144:ef7eb2e8f9f7 4371
<> 144:ef7eb2e8f9f7 4372 /*! @name HRS - Hardware Request Status Register */
<> 144:ef7eb2e8f9f7 4373 #define DMA_HRS_HRS0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4374 #define DMA_HRS_HRS0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4375 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
<> 144:ef7eb2e8f9f7 4376 #define DMA_HRS_HRS1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4377 #define DMA_HRS_HRS1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4378 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
<> 144:ef7eb2e8f9f7 4379 #define DMA_HRS_HRS2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4380 #define DMA_HRS_HRS2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4381 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
<> 144:ef7eb2e8f9f7 4382 #define DMA_HRS_HRS3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4383 #define DMA_HRS_HRS3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4384 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
<> 144:ef7eb2e8f9f7 4385 #define DMA_HRS_HRS4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4386 #define DMA_HRS_HRS4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4387 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
<> 144:ef7eb2e8f9f7 4388 #define DMA_HRS_HRS5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4389 #define DMA_HRS_HRS5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4390 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
<> 144:ef7eb2e8f9f7 4391 #define DMA_HRS_HRS6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4392 #define DMA_HRS_HRS6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4393 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
<> 144:ef7eb2e8f9f7 4394 #define DMA_HRS_HRS7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4395 #define DMA_HRS_HRS7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4396 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
<> 144:ef7eb2e8f9f7 4397 #define DMA_HRS_HRS8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 4398 #define DMA_HRS_HRS8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4399 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
<> 144:ef7eb2e8f9f7 4400 #define DMA_HRS_HRS9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4401 #define DMA_HRS_HRS9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4402 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
<> 144:ef7eb2e8f9f7 4403 #define DMA_HRS_HRS10_MASK (0x400U)
<> 144:ef7eb2e8f9f7 4404 #define DMA_HRS_HRS10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 4405 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
<> 144:ef7eb2e8f9f7 4406 #define DMA_HRS_HRS11_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4407 #define DMA_HRS_HRS11_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4408 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
<> 144:ef7eb2e8f9f7 4409 #define DMA_HRS_HRS12_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4410 #define DMA_HRS_HRS12_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4411 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
<> 144:ef7eb2e8f9f7 4412 #define DMA_HRS_HRS13_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4413 #define DMA_HRS_HRS13_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4414 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
<> 144:ef7eb2e8f9f7 4415 #define DMA_HRS_HRS14_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4416 #define DMA_HRS_HRS14_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4417 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
<> 144:ef7eb2e8f9f7 4418 #define DMA_HRS_HRS15_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4419 #define DMA_HRS_HRS15_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4420 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
<> 144:ef7eb2e8f9f7 4421 #define DMA_HRS_HRS16_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4422 #define DMA_HRS_HRS16_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4423 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
<> 144:ef7eb2e8f9f7 4424 #define DMA_HRS_HRS17_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4425 #define DMA_HRS_HRS17_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4426 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
<> 144:ef7eb2e8f9f7 4427 #define DMA_HRS_HRS18_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4428 #define DMA_HRS_HRS18_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4429 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
<> 144:ef7eb2e8f9f7 4430 #define DMA_HRS_HRS19_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4431 #define DMA_HRS_HRS19_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4432 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
<> 144:ef7eb2e8f9f7 4433 #define DMA_HRS_HRS20_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4434 #define DMA_HRS_HRS20_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4435 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
<> 144:ef7eb2e8f9f7 4436 #define DMA_HRS_HRS21_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4437 #define DMA_HRS_HRS21_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4438 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
<> 144:ef7eb2e8f9f7 4439 #define DMA_HRS_HRS22_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4440 #define DMA_HRS_HRS22_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4441 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
<> 144:ef7eb2e8f9f7 4442 #define DMA_HRS_HRS23_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4443 #define DMA_HRS_HRS23_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4444 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
<> 144:ef7eb2e8f9f7 4445 #define DMA_HRS_HRS24_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4446 #define DMA_HRS_HRS24_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4447 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
<> 144:ef7eb2e8f9f7 4448 #define DMA_HRS_HRS25_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4449 #define DMA_HRS_HRS25_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4450 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
<> 144:ef7eb2e8f9f7 4451 #define DMA_HRS_HRS26_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4452 #define DMA_HRS_HRS26_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4453 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
<> 144:ef7eb2e8f9f7 4454 #define DMA_HRS_HRS27_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4455 #define DMA_HRS_HRS27_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4456 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
<> 144:ef7eb2e8f9f7 4457 #define DMA_HRS_HRS28_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4458 #define DMA_HRS_HRS28_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4459 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
<> 144:ef7eb2e8f9f7 4460 #define DMA_HRS_HRS29_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4461 #define DMA_HRS_HRS29_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4462 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
<> 144:ef7eb2e8f9f7 4463 #define DMA_HRS_HRS30_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4464 #define DMA_HRS_HRS30_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4465 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
<> 144:ef7eb2e8f9f7 4466 #define DMA_HRS_HRS31_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4467 #define DMA_HRS_HRS31_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4468 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
<> 144:ef7eb2e8f9f7 4469
<> 144:ef7eb2e8f9f7 4470 /*! @name EARS - Enable Asynchronous Request in Stop Register */
<> 144:ef7eb2e8f9f7 4471 #define DMA_EARS_EDREQ_0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 4472 #define DMA_EARS_EDREQ_0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4473 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
<> 144:ef7eb2e8f9f7 4474 #define DMA_EARS_EDREQ_1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 4475 #define DMA_EARS_EDREQ_1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 4476 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
<> 144:ef7eb2e8f9f7 4477 #define DMA_EARS_EDREQ_2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 4478 #define DMA_EARS_EDREQ_2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 4479 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
<> 144:ef7eb2e8f9f7 4480 #define DMA_EARS_EDREQ_3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 4481 #define DMA_EARS_EDREQ_3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 4482 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
<> 144:ef7eb2e8f9f7 4483 #define DMA_EARS_EDREQ_4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 4484 #define DMA_EARS_EDREQ_4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4485 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
<> 144:ef7eb2e8f9f7 4486 #define DMA_EARS_EDREQ_5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 4487 #define DMA_EARS_EDREQ_5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 4488 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
<> 144:ef7eb2e8f9f7 4489 #define DMA_EARS_EDREQ_6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4490 #define DMA_EARS_EDREQ_6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4491 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
<> 144:ef7eb2e8f9f7 4492 #define DMA_EARS_EDREQ_7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4493 #define DMA_EARS_EDREQ_7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4494 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
<> 144:ef7eb2e8f9f7 4495 #define DMA_EARS_EDREQ_8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 4496 #define DMA_EARS_EDREQ_8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 4497 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
<> 144:ef7eb2e8f9f7 4498 #define DMA_EARS_EDREQ_9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 4499 #define DMA_EARS_EDREQ_9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 4500 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
<> 144:ef7eb2e8f9f7 4501 #define DMA_EARS_EDREQ_10_MASK (0x400U)
<> 144:ef7eb2e8f9f7 4502 #define DMA_EARS_EDREQ_10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 4503 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
<> 144:ef7eb2e8f9f7 4504 #define DMA_EARS_EDREQ_11_MASK (0x800U)
<> 144:ef7eb2e8f9f7 4505 #define DMA_EARS_EDREQ_11_SHIFT (11U)
<> 144:ef7eb2e8f9f7 4506 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
<> 144:ef7eb2e8f9f7 4507 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 4508 #define DMA_EARS_EDREQ_12_SHIFT (12U)
<> 144:ef7eb2e8f9f7 4509 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
<> 144:ef7eb2e8f9f7 4510 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 4511 #define DMA_EARS_EDREQ_13_SHIFT (13U)
<> 144:ef7eb2e8f9f7 4512 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
<> 144:ef7eb2e8f9f7 4513 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 4514 #define DMA_EARS_EDREQ_14_SHIFT (14U)
<> 144:ef7eb2e8f9f7 4515 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
<> 144:ef7eb2e8f9f7 4516 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 4517 #define DMA_EARS_EDREQ_15_SHIFT (15U)
<> 144:ef7eb2e8f9f7 4518 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
<> 144:ef7eb2e8f9f7 4519 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 4520 #define DMA_EARS_EDREQ_16_SHIFT (16U)
<> 144:ef7eb2e8f9f7 4521 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
<> 144:ef7eb2e8f9f7 4522 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 4523 #define DMA_EARS_EDREQ_17_SHIFT (17U)
<> 144:ef7eb2e8f9f7 4524 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
<> 144:ef7eb2e8f9f7 4525 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 4526 #define DMA_EARS_EDREQ_18_SHIFT (18U)
<> 144:ef7eb2e8f9f7 4527 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
<> 144:ef7eb2e8f9f7 4528 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 4529 #define DMA_EARS_EDREQ_19_SHIFT (19U)
<> 144:ef7eb2e8f9f7 4530 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
<> 144:ef7eb2e8f9f7 4531 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 4532 #define DMA_EARS_EDREQ_20_SHIFT (20U)
<> 144:ef7eb2e8f9f7 4533 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
<> 144:ef7eb2e8f9f7 4534 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 4535 #define DMA_EARS_EDREQ_21_SHIFT (21U)
<> 144:ef7eb2e8f9f7 4536 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
<> 144:ef7eb2e8f9f7 4537 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 4538 #define DMA_EARS_EDREQ_22_SHIFT (22U)
<> 144:ef7eb2e8f9f7 4539 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
<> 144:ef7eb2e8f9f7 4540 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 4541 #define DMA_EARS_EDREQ_23_SHIFT (23U)
<> 144:ef7eb2e8f9f7 4542 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
<> 144:ef7eb2e8f9f7 4543 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 4544 #define DMA_EARS_EDREQ_24_SHIFT (24U)
<> 144:ef7eb2e8f9f7 4545 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
<> 144:ef7eb2e8f9f7 4546 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 4547 #define DMA_EARS_EDREQ_25_SHIFT (25U)
<> 144:ef7eb2e8f9f7 4548 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
<> 144:ef7eb2e8f9f7 4549 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 4550 #define DMA_EARS_EDREQ_26_SHIFT (26U)
<> 144:ef7eb2e8f9f7 4551 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
<> 144:ef7eb2e8f9f7 4552 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 4553 #define DMA_EARS_EDREQ_27_SHIFT (27U)
<> 144:ef7eb2e8f9f7 4554 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
<> 144:ef7eb2e8f9f7 4555 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 4556 #define DMA_EARS_EDREQ_28_SHIFT (28U)
<> 144:ef7eb2e8f9f7 4557 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
<> 144:ef7eb2e8f9f7 4558 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 4559 #define DMA_EARS_EDREQ_29_SHIFT (29U)
<> 144:ef7eb2e8f9f7 4560 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
<> 144:ef7eb2e8f9f7 4561 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 4562 #define DMA_EARS_EDREQ_30_SHIFT (30U)
<> 144:ef7eb2e8f9f7 4563 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
<> 144:ef7eb2e8f9f7 4564 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 4565 #define DMA_EARS_EDREQ_31_SHIFT (31U)
<> 144:ef7eb2e8f9f7 4566 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
<> 144:ef7eb2e8f9f7 4567
<> 144:ef7eb2e8f9f7 4568 /*! @name DCHPRI3 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4569 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4570 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4571 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4572 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4573 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4574 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4575 #define DMA_DCHPRI3_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4576 #define DMA_DCHPRI3_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4577 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
<> 144:ef7eb2e8f9f7 4578 #define DMA_DCHPRI3_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4579 #define DMA_DCHPRI3_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4580 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
<> 144:ef7eb2e8f9f7 4581
<> 144:ef7eb2e8f9f7 4582 /*! @name DCHPRI2 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4583 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4584 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4585 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4586 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4587 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4588 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4589 #define DMA_DCHPRI2_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4590 #define DMA_DCHPRI2_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4591 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
<> 144:ef7eb2e8f9f7 4592 #define DMA_DCHPRI2_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4593 #define DMA_DCHPRI2_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4594 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
<> 144:ef7eb2e8f9f7 4595
<> 144:ef7eb2e8f9f7 4596 /*! @name DCHPRI1 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4597 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4598 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4599 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4600 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4601 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4602 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4603 #define DMA_DCHPRI1_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4604 #define DMA_DCHPRI1_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4605 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
<> 144:ef7eb2e8f9f7 4606 #define DMA_DCHPRI1_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4607 #define DMA_DCHPRI1_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4608 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
<> 144:ef7eb2e8f9f7 4609
<> 144:ef7eb2e8f9f7 4610 /*! @name DCHPRI0 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4611 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4612 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4613 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4614 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4615 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4616 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4617 #define DMA_DCHPRI0_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4618 #define DMA_DCHPRI0_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4619 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
<> 144:ef7eb2e8f9f7 4620 #define DMA_DCHPRI0_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4621 #define DMA_DCHPRI0_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4622 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
<> 144:ef7eb2e8f9f7 4623
<> 144:ef7eb2e8f9f7 4624 /*! @name DCHPRI7 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4625 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4626 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4627 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4628 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4629 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4630 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4631 #define DMA_DCHPRI7_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4632 #define DMA_DCHPRI7_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4633 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
<> 144:ef7eb2e8f9f7 4634 #define DMA_DCHPRI7_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4635 #define DMA_DCHPRI7_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4636 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
<> 144:ef7eb2e8f9f7 4637
<> 144:ef7eb2e8f9f7 4638 /*! @name DCHPRI6 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4639 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4640 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4641 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4642 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4643 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4644 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4645 #define DMA_DCHPRI6_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4646 #define DMA_DCHPRI6_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4647 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
<> 144:ef7eb2e8f9f7 4648 #define DMA_DCHPRI6_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4649 #define DMA_DCHPRI6_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4650 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
<> 144:ef7eb2e8f9f7 4651
<> 144:ef7eb2e8f9f7 4652 /*! @name DCHPRI5 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4653 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4654 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4655 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4656 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4657 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4658 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4659 #define DMA_DCHPRI5_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4660 #define DMA_DCHPRI5_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4661 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
<> 144:ef7eb2e8f9f7 4662 #define DMA_DCHPRI5_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4663 #define DMA_DCHPRI5_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4664 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
<> 144:ef7eb2e8f9f7 4665
<> 144:ef7eb2e8f9f7 4666 /*! @name DCHPRI4 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4667 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4668 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4669 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4670 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4671 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4672 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4673 #define DMA_DCHPRI4_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4674 #define DMA_DCHPRI4_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4675 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
<> 144:ef7eb2e8f9f7 4676 #define DMA_DCHPRI4_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4677 #define DMA_DCHPRI4_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4678 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
<> 144:ef7eb2e8f9f7 4679
<> 144:ef7eb2e8f9f7 4680 /*! @name DCHPRI11 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4681 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4682 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4683 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4684 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4685 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4686 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4687 #define DMA_DCHPRI11_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4688 #define DMA_DCHPRI11_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4689 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
<> 144:ef7eb2e8f9f7 4690 #define DMA_DCHPRI11_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4691 #define DMA_DCHPRI11_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4692 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
<> 144:ef7eb2e8f9f7 4693
<> 144:ef7eb2e8f9f7 4694 /*! @name DCHPRI10 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4695 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4696 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4697 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4698 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4699 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4700 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4701 #define DMA_DCHPRI10_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4702 #define DMA_DCHPRI10_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4703 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
<> 144:ef7eb2e8f9f7 4704 #define DMA_DCHPRI10_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4705 #define DMA_DCHPRI10_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4706 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
<> 144:ef7eb2e8f9f7 4707
<> 144:ef7eb2e8f9f7 4708 /*! @name DCHPRI9 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4709 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4710 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4711 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4712 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4713 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4714 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4715 #define DMA_DCHPRI9_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4716 #define DMA_DCHPRI9_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4717 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
<> 144:ef7eb2e8f9f7 4718 #define DMA_DCHPRI9_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4719 #define DMA_DCHPRI9_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4720 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
<> 144:ef7eb2e8f9f7 4721
<> 144:ef7eb2e8f9f7 4722 /*! @name DCHPRI8 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4723 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4724 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4725 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4726 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4727 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4728 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4729 #define DMA_DCHPRI8_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4730 #define DMA_DCHPRI8_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4731 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
<> 144:ef7eb2e8f9f7 4732 #define DMA_DCHPRI8_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4733 #define DMA_DCHPRI8_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4734 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
<> 144:ef7eb2e8f9f7 4735
<> 144:ef7eb2e8f9f7 4736 /*! @name DCHPRI15 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4737 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4738 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4739 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4740 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4741 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4742 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4743 #define DMA_DCHPRI15_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4744 #define DMA_DCHPRI15_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4745 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
<> 144:ef7eb2e8f9f7 4746 #define DMA_DCHPRI15_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4747 #define DMA_DCHPRI15_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4748 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
<> 144:ef7eb2e8f9f7 4749
<> 144:ef7eb2e8f9f7 4750 /*! @name DCHPRI14 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4751 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4752 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4753 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4754 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4755 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4756 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4757 #define DMA_DCHPRI14_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4758 #define DMA_DCHPRI14_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4759 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
<> 144:ef7eb2e8f9f7 4760 #define DMA_DCHPRI14_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4761 #define DMA_DCHPRI14_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4762 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
<> 144:ef7eb2e8f9f7 4763
<> 144:ef7eb2e8f9f7 4764 /*! @name DCHPRI13 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4765 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4766 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4767 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4768 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4769 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4770 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4771 #define DMA_DCHPRI13_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4772 #define DMA_DCHPRI13_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4773 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
<> 144:ef7eb2e8f9f7 4774 #define DMA_DCHPRI13_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4775 #define DMA_DCHPRI13_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4776 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
<> 144:ef7eb2e8f9f7 4777
<> 144:ef7eb2e8f9f7 4778 /*! @name DCHPRI12 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4779 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4780 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4781 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4782 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4783 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4784 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4785 #define DMA_DCHPRI12_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4786 #define DMA_DCHPRI12_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4787 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
<> 144:ef7eb2e8f9f7 4788 #define DMA_DCHPRI12_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4789 #define DMA_DCHPRI12_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4790 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
<> 144:ef7eb2e8f9f7 4791
<> 144:ef7eb2e8f9f7 4792 /*! @name DCHPRI19 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4793 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4794 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4795 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4796 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4797 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4798 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4799 #define DMA_DCHPRI19_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4800 #define DMA_DCHPRI19_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4801 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
<> 144:ef7eb2e8f9f7 4802 #define DMA_DCHPRI19_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4803 #define DMA_DCHPRI19_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4804 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
<> 144:ef7eb2e8f9f7 4805
<> 144:ef7eb2e8f9f7 4806 /*! @name DCHPRI18 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4807 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4808 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4809 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4810 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4811 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4812 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4813 #define DMA_DCHPRI18_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4814 #define DMA_DCHPRI18_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4815 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
<> 144:ef7eb2e8f9f7 4816 #define DMA_DCHPRI18_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4817 #define DMA_DCHPRI18_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4818 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
<> 144:ef7eb2e8f9f7 4819
<> 144:ef7eb2e8f9f7 4820 /*! @name DCHPRI17 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4821 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4822 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4823 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4824 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4825 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4826 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4827 #define DMA_DCHPRI17_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4828 #define DMA_DCHPRI17_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4829 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
<> 144:ef7eb2e8f9f7 4830 #define DMA_DCHPRI17_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4831 #define DMA_DCHPRI17_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4832 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
<> 144:ef7eb2e8f9f7 4833
<> 144:ef7eb2e8f9f7 4834 /*! @name DCHPRI16 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4835 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4836 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4837 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4838 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4839 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4840 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4841 #define DMA_DCHPRI16_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4842 #define DMA_DCHPRI16_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4843 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
<> 144:ef7eb2e8f9f7 4844 #define DMA_DCHPRI16_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4845 #define DMA_DCHPRI16_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4846 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
<> 144:ef7eb2e8f9f7 4847
<> 144:ef7eb2e8f9f7 4848 /*! @name DCHPRI23 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4849 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4850 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4851 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4852 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4853 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4854 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4855 #define DMA_DCHPRI23_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4856 #define DMA_DCHPRI23_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4857 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
<> 144:ef7eb2e8f9f7 4858 #define DMA_DCHPRI23_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4859 #define DMA_DCHPRI23_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4860 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
<> 144:ef7eb2e8f9f7 4861
<> 144:ef7eb2e8f9f7 4862 /*! @name DCHPRI22 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4863 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4864 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4865 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4866 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4867 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4868 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4869 #define DMA_DCHPRI22_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4870 #define DMA_DCHPRI22_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4871 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
<> 144:ef7eb2e8f9f7 4872 #define DMA_DCHPRI22_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4873 #define DMA_DCHPRI22_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4874 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
<> 144:ef7eb2e8f9f7 4875
<> 144:ef7eb2e8f9f7 4876 /*! @name DCHPRI21 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4877 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4878 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4879 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4880 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4881 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4882 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4883 #define DMA_DCHPRI21_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4884 #define DMA_DCHPRI21_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4885 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
<> 144:ef7eb2e8f9f7 4886 #define DMA_DCHPRI21_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4887 #define DMA_DCHPRI21_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4888 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
<> 144:ef7eb2e8f9f7 4889
<> 144:ef7eb2e8f9f7 4890 /*! @name DCHPRI20 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4891 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4892 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4893 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4894 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4895 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4896 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4897 #define DMA_DCHPRI20_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4898 #define DMA_DCHPRI20_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4899 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
<> 144:ef7eb2e8f9f7 4900 #define DMA_DCHPRI20_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4901 #define DMA_DCHPRI20_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4902 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
<> 144:ef7eb2e8f9f7 4903
<> 144:ef7eb2e8f9f7 4904 /*! @name DCHPRI27 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4905 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4906 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4907 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4908 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4909 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4910 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4911 #define DMA_DCHPRI27_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4912 #define DMA_DCHPRI27_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4913 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
<> 144:ef7eb2e8f9f7 4914 #define DMA_DCHPRI27_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4915 #define DMA_DCHPRI27_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4916 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
<> 144:ef7eb2e8f9f7 4917
<> 144:ef7eb2e8f9f7 4918 /*! @name DCHPRI26 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4919 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4920 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4921 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4922 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4923 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4924 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4925 #define DMA_DCHPRI26_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4926 #define DMA_DCHPRI26_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4927 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
<> 144:ef7eb2e8f9f7 4928 #define DMA_DCHPRI26_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4929 #define DMA_DCHPRI26_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4930 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
<> 144:ef7eb2e8f9f7 4931
<> 144:ef7eb2e8f9f7 4932 /*! @name DCHPRI25 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4933 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4934 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4935 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4936 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4937 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4938 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4939 #define DMA_DCHPRI25_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4940 #define DMA_DCHPRI25_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4941 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
<> 144:ef7eb2e8f9f7 4942 #define DMA_DCHPRI25_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4943 #define DMA_DCHPRI25_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4944 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
<> 144:ef7eb2e8f9f7 4945
<> 144:ef7eb2e8f9f7 4946 /*! @name DCHPRI24 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4947 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4948 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4949 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4950 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4951 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4952 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4953 #define DMA_DCHPRI24_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4954 #define DMA_DCHPRI24_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4955 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
<> 144:ef7eb2e8f9f7 4956 #define DMA_DCHPRI24_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4957 #define DMA_DCHPRI24_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4958 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
<> 144:ef7eb2e8f9f7 4959
<> 144:ef7eb2e8f9f7 4960 /*! @name DCHPRI31 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4961 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4962 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4963 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4964 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4965 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4966 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4967 #define DMA_DCHPRI31_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4968 #define DMA_DCHPRI31_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4969 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
<> 144:ef7eb2e8f9f7 4970 #define DMA_DCHPRI31_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4971 #define DMA_DCHPRI31_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4972 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
<> 144:ef7eb2e8f9f7 4973
<> 144:ef7eb2e8f9f7 4974 /*! @name DCHPRI30 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4975 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4976 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4977 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4978 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4979 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4980 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4981 #define DMA_DCHPRI30_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4982 #define DMA_DCHPRI30_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4983 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
<> 144:ef7eb2e8f9f7 4984 #define DMA_DCHPRI30_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4985 #define DMA_DCHPRI30_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 4986 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
<> 144:ef7eb2e8f9f7 4987
<> 144:ef7eb2e8f9f7 4988 /*! @name DCHPRI29 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 4989 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 4990 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 4991 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 4992 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 4993 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 4994 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 4995 #define DMA_DCHPRI29_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 4996 #define DMA_DCHPRI29_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 4997 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
<> 144:ef7eb2e8f9f7 4998 #define DMA_DCHPRI29_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 4999 #define DMA_DCHPRI29_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5000 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
<> 144:ef7eb2e8f9f7 5001
<> 144:ef7eb2e8f9f7 5002 /*! @name DCHPRI28 - Channel n Priority Register */
<> 144:ef7eb2e8f9f7 5003 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 5004 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5005 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
<> 144:ef7eb2e8f9f7 5006 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
<> 144:ef7eb2e8f9f7 5007 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5008 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
<> 144:ef7eb2e8f9f7 5009 #define DMA_DCHPRI28_DPA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5010 #define DMA_DCHPRI28_DPA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5011 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
<> 144:ef7eb2e8f9f7 5012 #define DMA_DCHPRI28_ECP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5013 #define DMA_DCHPRI28_ECP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5014 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
<> 144:ef7eb2e8f9f7 5015
<> 144:ef7eb2e8f9f7 5016 /*! @name SADDR - TCD Source Address */
<> 144:ef7eb2e8f9f7 5017 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5018 #define DMA_SADDR_SADDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5019 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
<> 144:ef7eb2e8f9f7 5020
<> 144:ef7eb2e8f9f7 5021 /* The count of DMA_SADDR */
<> 144:ef7eb2e8f9f7 5022 #define DMA_SADDR_COUNT (32U)
<> 144:ef7eb2e8f9f7 5023
<> 144:ef7eb2e8f9f7 5024 /*! @name SOFF - TCD Signed Source Address Offset */
<> 144:ef7eb2e8f9f7 5025 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5026 #define DMA_SOFF_SOFF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5027 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
<> 144:ef7eb2e8f9f7 5028
<> 144:ef7eb2e8f9f7 5029 /* The count of DMA_SOFF */
<> 144:ef7eb2e8f9f7 5030 #define DMA_SOFF_COUNT (32U)
<> 144:ef7eb2e8f9f7 5031
<> 144:ef7eb2e8f9f7 5032 /*! @name ATTR - TCD Transfer Attributes */
<> 144:ef7eb2e8f9f7 5033 #define DMA_ATTR_DSIZE_MASK (0x7U)
<> 144:ef7eb2e8f9f7 5034 #define DMA_ATTR_DSIZE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5035 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
<> 144:ef7eb2e8f9f7 5036 #define DMA_ATTR_DMOD_MASK (0xF8U)
<> 144:ef7eb2e8f9f7 5037 #define DMA_ATTR_DMOD_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5038 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
<> 144:ef7eb2e8f9f7 5039 #define DMA_ATTR_SSIZE_MASK (0x700U)
<> 144:ef7eb2e8f9f7 5040 #define DMA_ATTR_SSIZE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5041 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
<> 144:ef7eb2e8f9f7 5042 #define DMA_ATTR_SMOD_MASK (0xF800U)
<> 144:ef7eb2e8f9f7 5043 #define DMA_ATTR_SMOD_SHIFT (11U)
<> 144:ef7eb2e8f9f7 5044 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
<> 144:ef7eb2e8f9f7 5045
<> 144:ef7eb2e8f9f7 5046 /* The count of DMA_ATTR */
<> 144:ef7eb2e8f9f7 5047 #define DMA_ATTR_COUNT (32U)
<> 144:ef7eb2e8f9f7 5048
<> 144:ef7eb2e8f9f7 5049 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
<> 144:ef7eb2e8f9f7 5050 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5051 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5052 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
<> 144:ef7eb2e8f9f7 5053
<> 144:ef7eb2e8f9f7 5054 /* The count of DMA_NBYTES_MLNO */
<> 144:ef7eb2e8f9f7 5055 #define DMA_NBYTES_MLNO_COUNT (32U)
<> 144:ef7eb2e8f9f7 5056
<> 144:ef7eb2e8f9f7 5057 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
<> 144:ef7eb2e8f9f7 5058 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
<> 144:ef7eb2e8f9f7 5059 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5060 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
<> 144:ef7eb2e8f9f7 5061 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 5062 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5063 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
<> 144:ef7eb2e8f9f7 5064 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 5065 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 5066 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
<> 144:ef7eb2e8f9f7 5067
<> 144:ef7eb2e8f9f7 5068 /* The count of DMA_NBYTES_MLOFFNO */
<> 144:ef7eb2e8f9f7 5069 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
<> 144:ef7eb2e8f9f7 5072 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 5073 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5074 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
<> 144:ef7eb2e8f9f7 5075 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
<> 144:ef7eb2e8f9f7 5076 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
<> 144:ef7eb2e8f9f7 5077 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
<> 144:ef7eb2e8f9f7 5078 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 5079 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5080 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
<> 144:ef7eb2e8f9f7 5081 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 5082 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 5083 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
<> 144:ef7eb2e8f9f7 5084
<> 144:ef7eb2e8f9f7 5085 /* The count of DMA_NBYTES_MLOFFYES */
<> 144:ef7eb2e8f9f7 5086 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
<> 144:ef7eb2e8f9f7 5087
<> 144:ef7eb2e8f9f7 5088 /*! @name SLAST - TCD Last Source Address Adjustment */
<> 144:ef7eb2e8f9f7 5089 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5090 #define DMA_SLAST_SLAST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5091 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
<> 144:ef7eb2e8f9f7 5092
<> 144:ef7eb2e8f9f7 5093 /* The count of DMA_SLAST */
<> 144:ef7eb2e8f9f7 5094 #define DMA_SLAST_COUNT (32U)
<> 144:ef7eb2e8f9f7 5095
<> 144:ef7eb2e8f9f7 5096 /*! @name DADDR - TCD Destination Address */
<> 144:ef7eb2e8f9f7 5097 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5098 #define DMA_DADDR_DADDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5099 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
<> 144:ef7eb2e8f9f7 5100
<> 144:ef7eb2e8f9f7 5101 /* The count of DMA_DADDR */
<> 144:ef7eb2e8f9f7 5102 #define DMA_DADDR_COUNT (32U)
<> 144:ef7eb2e8f9f7 5103
<> 144:ef7eb2e8f9f7 5104 /*! @name DOFF - TCD Signed Destination Address Offset */
<> 144:ef7eb2e8f9f7 5105 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5106 #define DMA_DOFF_DOFF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5107 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
<> 144:ef7eb2e8f9f7 5108
<> 144:ef7eb2e8f9f7 5109 /* The count of DMA_DOFF */
<> 144:ef7eb2e8f9f7 5110 #define DMA_DOFF_COUNT (32U)
<> 144:ef7eb2e8f9f7 5111
<> 144:ef7eb2e8f9f7 5112 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
<> 144:ef7eb2e8f9f7 5113 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
<> 144:ef7eb2e8f9f7 5114 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5115 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
<> 144:ef7eb2e8f9f7 5116 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5117 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5118 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
<> 144:ef7eb2e8f9f7 5119
<> 144:ef7eb2e8f9f7 5120 /* The count of DMA_CITER_ELINKNO */
<> 144:ef7eb2e8f9f7 5121 #define DMA_CITER_ELINKNO_COUNT (32U)
<> 144:ef7eb2e8f9f7 5122
<> 144:ef7eb2e8f9f7 5123 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
<> 144:ef7eb2e8f9f7 5124 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 5125 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5126 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
<> 144:ef7eb2e8f9f7 5127 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
<> 144:ef7eb2e8f9f7 5128 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
<> 144:ef7eb2e8f9f7 5129 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
<> 144:ef7eb2e8f9f7 5130 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5131 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5132 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
<> 144:ef7eb2e8f9f7 5133
<> 144:ef7eb2e8f9f7 5134 /* The count of DMA_CITER_ELINKYES */
<> 144:ef7eb2e8f9f7 5135 #define DMA_CITER_ELINKYES_COUNT (32U)
<> 144:ef7eb2e8f9f7 5136
<> 144:ef7eb2e8f9f7 5137 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
<> 144:ef7eb2e8f9f7 5138 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5139 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5140 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
<> 144:ef7eb2e8f9f7 5141
<> 144:ef7eb2e8f9f7 5142 /* The count of DMA_DLAST_SGA */
<> 144:ef7eb2e8f9f7 5143 #define DMA_DLAST_SGA_COUNT (32U)
<> 144:ef7eb2e8f9f7 5144
<> 144:ef7eb2e8f9f7 5145 /*! @name CSR - TCD Control and Status */
<> 144:ef7eb2e8f9f7 5146 #define DMA_CSR_START_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5147 #define DMA_CSR_START_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5148 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
<> 144:ef7eb2e8f9f7 5149 #define DMA_CSR_INTMAJOR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5150 #define DMA_CSR_INTMAJOR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5151 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
<> 144:ef7eb2e8f9f7 5152 #define DMA_CSR_INTHALF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5153 #define DMA_CSR_INTHALF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5154 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
<> 144:ef7eb2e8f9f7 5155 #define DMA_CSR_DREQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5156 #define DMA_CSR_DREQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5157 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
<> 144:ef7eb2e8f9f7 5158 #define DMA_CSR_ESG_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5159 #define DMA_CSR_ESG_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5160 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
<> 144:ef7eb2e8f9f7 5161 #define DMA_CSR_MAJORELINK_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5162 #define DMA_CSR_MAJORELINK_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5163 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
<> 144:ef7eb2e8f9f7 5164 #define DMA_CSR_ACTIVE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5165 #define DMA_CSR_ACTIVE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5166 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
<> 144:ef7eb2e8f9f7 5167 #define DMA_CSR_DONE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5168 #define DMA_CSR_DONE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5169 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
<> 144:ef7eb2e8f9f7 5170 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 5171 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5172 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
<> 144:ef7eb2e8f9f7 5173 #define DMA_CSR_BWC_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 5174 #define DMA_CSR_BWC_SHIFT (14U)
<> 144:ef7eb2e8f9f7 5175 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
<> 144:ef7eb2e8f9f7 5176
<> 144:ef7eb2e8f9f7 5177 /* The count of DMA_CSR */
<> 144:ef7eb2e8f9f7 5178 #define DMA_CSR_COUNT (32U)
<> 144:ef7eb2e8f9f7 5179
<> 144:ef7eb2e8f9f7 5180 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
<> 144:ef7eb2e8f9f7 5181 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
<> 144:ef7eb2e8f9f7 5182 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5183 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
<> 144:ef7eb2e8f9f7 5184 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5185 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5186 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
<> 144:ef7eb2e8f9f7 5187
<> 144:ef7eb2e8f9f7 5188 /* The count of DMA_BITER_ELINKNO */
<> 144:ef7eb2e8f9f7 5189 #define DMA_BITER_ELINKNO_COUNT (32U)
<> 144:ef7eb2e8f9f7 5190
<> 144:ef7eb2e8f9f7 5191 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
<> 144:ef7eb2e8f9f7 5192 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 5193 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5194 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
<> 144:ef7eb2e8f9f7 5195 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
<> 144:ef7eb2e8f9f7 5196 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
<> 144:ef7eb2e8f9f7 5197 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
<> 144:ef7eb2e8f9f7 5198 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5199 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5200 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
<> 144:ef7eb2e8f9f7 5201
<> 144:ef7eb2e8f9f7 5202 /* The count of DMA_BITER_ELINKYES */
<> 144:ef7eb2e8f9f7 5203 #define DMA_BITER_ELINKYES_COUNT (32U)
<> 144:ef7eb2e8f9f7 5204
<> 144:ef7eb2e8f9f7 5205
<> 144:ef7eb2e8f9f7 5206 /*!
<> 144:ef7eb2e8f9f7 5207 * @}
<> 144:ef7eb2e8f9f7 5208 */ /* end of group DMA_Register_Masks */
<> 144:ef7eb2e8f9f7 5209
<> 144:ef7eb2e8f9f7 5210
<> 144:ef7eb2e8f9f7 5211 /* DMA - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5212 /** Peripheral DMA base address */
<> 144:ef7eb2e8f9f7 5213 #define DMA_BASE (0x40008000u)
<> 144:ef7eb2e8f9f7 5214 /** Peripheral DMA base pointer */
<> 144:ef7eb2e8f9f7 5215 #define DMA0 ((DMA_Type *)DMA_BASE)
<> 144:ef7eb2e8f9f7 5216 /** Array initializer of DMA peripheral base addresses */
<> 144:ef7eb2e8f9f7 5217 #define DMA_BASE_ADDRS { DMA_BASE }
<> 144:ef7eb2e8f9f7 5218 /** Array initializer of DMA peripheral base pointers */
<> 144:ef7eb2e8f9f7 5219 #define DMA_BASE_PTRS { DMA0 }
<> 144:ef7eb2e8f9f7 5220 /** Interrupt vectors for the DMA peripheral type */
<> 144:ef7eb2e8f9f7 5221 #define DMA_CHN_IRQS { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn }
<> 144:ef7eb2e8f9f7 5222 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
<> 144:ef7eb2e8f9f7 5223
<> 144:ef7eb2e8f9f7 5224 /*!
<> 144:ef7eb2e8f9f7 5225 * @}
<> 144:ef7eb2e8f9f7 5226 */ /* end of group DMA_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5227
<> 144:ef7eb2e8f9f7 5228
<> 144:ef7eb2e8f9f7 5229 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5230 -- DMAMUX Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5231 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5232
<> 144:ef7eb2e8f9f7 5233 /*!
<> 144:ef7eb2e8f9f7 5234 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5235 * @{
<> 144:ef7eb2e8f9f7 5236 */
<> 144:ef7eb2e8f9f7 5237
<> 144:ef7eb2e8f9f7 5238 /** DMAMUX - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5239 typedef struct {
<> 144:ef7eb2e8f9f7 5240 __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
<> 144:ef7eb2e8f9f7 5241 } DMAMUX_Type;
<> 144:ef7eb2e8f9f7 5242
<> 144:ef7eb2e8f9f7 5243 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5244 -- DMAMUX Register Masks
<> 144:ef7eb2e8f9f7 5245 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5246
<> 144:ef7eb2e8f9f7 5247 /*!
<> 144:ef7eb2e8f9f7 5248 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
<> 144:ef7eb2e8f9f7 5249 * @{
<> 144:ef7eb2e8f9f7 5250 */
<> 144:ef7eb2e8f9f7 5251
<> 144:ef7eb2e8f9f7 5252 /*! @name CHCFG - Channel Configuration register */
<> 144:ef7eb2e8f9f7 5253 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 5254 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5255 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
<> 144:ef7eb2e8f9f7 5256 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5257 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5258 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
<> 144:ef7eb2e8f9f7 5259 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5260 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5261 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
<> 144:ef7eb2e8f9f7 5262
<> 144:ef7eb2e8f9f7 5263 /* The count of DMAMUX_CHCFG */
<> 144:ef7eb2e8f9f7 5264 #define DMAMUX_CHCFG_COUNT (32U)
<> 144:ef7eb2e8f9f7 5265
<> 144:ef7eb2e8f9f7 5266
<> 144:ef7eb2e8f9f7 5267 /*!
<> 144:ef7eb2e8f9f7 5268 * @}
<> 144:ef7eb2e8f9f7 5269 */ /* end of group DMAMUX_Register_Masks */
<> 144:ef7eb2e8f9f7 5270
<> 144:ef7eb2e8f9f7 5271
<> 144:ef7eb2e8f9f7 5272 /* DMAMUX - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 5273 /** Peripheral DMAMUX base address */
<> 144:ef7eb2e8f9f7 5274 #define DMAMUX_BASE (0x40021000u)
<> 144:ef7eb2e8f9f7 5275 /** Peripheral DMAMUX base pointer */
<> 144:ef7eb2e8f9f7 5276 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
<> 144:ef7eb2e8f9f7 5277 /** Array initializer of DMAMUX peripheral base addresses */
<> 144:ef7eb2e8f9f7 5278 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
<> 144:ef7eb2e8f9f7 5279 /** Array initializer of DMAMUX peripheral base pointers */
<> 144:ef7eb2e8f9f7 5280 #define DMAMUX_BASE_PTRS { DMAMUX }
<> 144:ef7eb2e8f9f7 5281
<> 144:ef7eb2e8f9f7 5282 /*!
<> 144:ef7eb2e8f9f7 5283 * @}
<> 144:ef7eb2e8f9f7 5284 */ /* end of group DMAMUX_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 5285
<> 144:ef7eb2e8f9f7 5286
<> 144:ef7eb2e8f9f7 5287 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5288 -- ENET Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5289 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5290
<> 144:ef7eb2e8f9f7 5291 /*!
<> 144:ef7eb2e8f9f7 5292 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
<> 144:ef7eb2e8f9f7 5293 * @{
<> 144:ef7eb2e8f9f7 5294 */
<> 144:ef7eb2e8f9f7 5295
<> 144:ef7eb2e8f9f7 5296 /** ENET - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 5297 typedef struct {
<> 144:ef7eb2e8f9f7 5298 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 5299 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 5300 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 5301 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 5302 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 5303 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 5304 uint8_t RESERVED_2[12];
<> 144:ef7eb2e8f9f7 5305 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 5306 uint8_t RESERVED_3[24];
<> 144:ef7eb2e8f9f7 5307 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 5308 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 5309 uint8_t RESERVED_4[28];
<> 144:ef7eb2e8f9f7 5310 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
<> 144:ef7eb2e8f9f7 5311 uint8_t RESERVED_5[28];
<> 144:ef7eb2e8f9f7 5312 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 5313 uint8_t RESERVED_6[60];
<> 144:ef7eb2e8f9f7 5314 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
<> 144:ef7eb2e8f9f7 5315 uint8_t RESERVED_7[28];
<> 144:ef7eb2e8f9f7 5316 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
<> 144:ef7eb2e8f9f7 5317 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
<> 144:ef7eb2e8f9f7 5318 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
<> 144:ef7eb2e8f9f7 5319 uint8_t RESERVED_8[40];
<> 144:ef7eb2e8f9f7 5320 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
<> 144:ef7eb2e8f9f7 5321 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
<> 144:ef7eb2e8f9f7 5322 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
<> 144:ef7eb2e8f9f7 5323 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
<> 144:ef7eb2e8f9f7 5324 uint8_t RESERVED_9[28];
<> 144:ef7eb2e8f9f7 5325 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
<> 144:ef7eb2e8f9f7 5326 uint8_t RESERVED_10[56];
<> 144:ef7eb2e8f9f7 5327 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
<> 144:ef7eb2e8f9f7 5328 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
<> 144:ef7eb2e8f9f7 5329 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
<> 144:ef7eb2e8f9f7 5330 uint8_t RESERVED_11[4];
<> 144:ef7eb2e8f9f7 5331 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
<> 144:ef7eb2e8f9f7 5332 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
<> 144:ef7eb2e8f9f7 5333 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
<> 144:ef7eb2e8f9f7 5334 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
<> 144:ef7eb2e8f9f7 5335 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
<> 144:ef7eb2e8f9f7 5336 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
<> 144:ef7eb2e8f9f7 5337 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
<> 144:ef7eb2e8f9f7 5338 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
<> 144:ef7eb2e8f9f7 5339 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
<> 144:ef7eb2e8f9f7 5340 uint8_t RESERVED_12[12];
<> 144:ef7eb2e8f9f7 5341 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
<> 144:ef7eb2e8f9f7 5342 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
<> 144:ef7eb2e8f9f7 5343 uint8_t RESERVED_13[56];
<> 144:ef7eb2e8f9f7 5344 __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
<> 144:ef7eb2e8f9f7 5345 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
<> 144:ef7eb2e8f9f7 5346 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
<> 144:ef7eb2e8f9f7 5347 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
<> 144:ef7eb2e8f9f7 5348 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
<> 144:ef7eb2e8f9f7 5349 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
<> 144:ef7eb2e8f9f7 5350 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
<> 144:ef7eb2e8f9f7 5351 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
<> 144:ef7eb2e8f9f7 5352 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
<> 144:ef7eb2e8f9f7 5353 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
<> 144:ef7eb2e8f9f7 5354 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
<> 144:ef7eb2e8f9f7 5355 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
<> 144:ef7eb2e8f9f7 5356 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
<> 144:ef7eb2e8f9f7 5357 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
<> 144:ef7eb2e8f9f7 5358 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
<> 144:ef7eb2e8f9f7 5359 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
<> 144:ef7eb2e8f9f7 5360 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
<> 144:ef7eb2e8f9f7 5361 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
<> 144:ef7eb2e8f9f7 5362 __I uint32_t IEEE_T_DROP; /**< IEEE_T_DROP Reserved Statistic Register, offset: 0x248 */
<> 144:ef7eb2e8f9f7 5363 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
<> 144:ef7eb2e8f9f7 5364 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
<> 144:ef7eb2e8f9f7 5365 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
<> 144:ef7eb2e8f9f7 5366 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
<> 144:ef7eb2e8f9f7 5367 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
<> 144:ef7eb2e8f9f7 5368 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
<> 144:ef7eb2e8f9f7 5369 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
<> 144:ef7eb2e8f9f7 5370 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
<> 144:ef7eb2e8f9f7 5371 __I uint32_t IEEE_T_SQE; /**< , offset: 0x26C */
<> 144:ef7eb2e8f9f7 5372 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
<> 144:ef7eb2e8f9f7 5373 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
<> 144:ef7eb2e8f9f7 5374 uint8_t RESERVED_14[12];
<> 144:ef7eb2e8f9f7 5375 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
<> 144:ef7eb2e8f9f7 5376 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
<> 144:ef7eb2e8f9f7 5377 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
<> 144:ef7eb2e8f9f7 5378 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
<> 144:ef7eb2e8f9f7 5379 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
<> 144:ef7eb2e8f9f7 5380 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
<> 144:ef7eb2e8f9f7 5381 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
<> 144:ef7eb2e8f9f7 5382 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
<> 144:ef7eb2e8f9f7 5383 __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
<> 144:ef7eb2e8f9f7 5384 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
<> 144:ef7eb2e8f9f7 5385 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
<> 144:ef7eb2e8f9f7 5386 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
<> 144:ef7eb2e8f9f7 5387 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
<> 144:ef7eb2e8f9f7 5388 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
<> 144:ef7eb2e8f9f7 5389 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
<> 144:ef7eb2e8f9f7 5390 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
<> 144:ef7eb2e8f9f7 5391 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
<> 144:ef7eb2e8f9f7 5392 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
<> 144:ef7eb2e8f9f7 5393 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
<> 144:ef7eb2e8f9f7 5394 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
<> 144:ef7eb2e8f9f7 5395 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
<> 144:ef7eb2e8f9f7 5396 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
<> 144:ef7eb2e8f9f7 5397 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
<> 144:ef7eb2e8f9f7 5398 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
<> 144:ef7eb2e8f9f7 5399 uint8_t RESERVED_15[284];
<> 144:ef7eb2e8f9f7 5400 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
<> 144:ef7eb2e8f9f7 5401 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
<> 144:ef7eb2e8f9f7 5402 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
<> 144:ef7eb2e8f9f7 5403 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
<> 144:ef7eb2e8f9f7 5404 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
<> 144:ef7eb2e8f9f7 5405 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
<> 144:ef7eb2e8f9f7 5406 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
<> 144:ef7eb2e8f9f7 5407 uint8_t RESERVED_16[488];
<> 144:ef7eb2e8f9f7 5408 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
<> 144:ef7eb2e8f9f7 5409 struct { /* offset: 0x608, array step: 0x8 */
<> 144:ef7eb2e8f9f7 5410 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
<> 144:ef7eb2e8f9f7 5411 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
<> 144:ef7eb2e8f9f7 5412 } CHANNEL[4];
<> 144:ef7eb2e8f9f7 5413 } ENET_Type;
<> 144:ef7eb2e8f9f7 5414
<> 144:ef7eb2e8f9f7 5415 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5416 -- ENET Register Masks
<> 144:ef7eb2e8f9f7 5417 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 5418
<> 144:ef7eb2e8f9f7 5419 /*!
<> 144:ef7eb2e8f9f7 5420 * @addtogroup ENET_Register_Masks ENET Register Masks
<> 144:ef7eb2e8f9f7 5421 * @{
<> 144:ef7eb2e8f9f7 5422 */
<> 144:ef7eb2e8f9f7 5423
<> 144:ef7eb2e8f9f7 5424 /*! @name EIR - Interrupt Event Register */
<> 144:ef7eb2e8f9f7 5425 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5426 #define ENET_EIR_TS_TIMER_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5427 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
<> 144:ef7eb2e8f9f7 5428 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 5429 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5430 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
<> 144:ef7eb2e8f9f7 5431 #define ENET_EIR_WAKEUP_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 5432 #define ENET_EIR_WAKEUP_SHIFT (17U)
<> 144:ef7eb2e8f9f7 5433 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
<> 144:ef7eb2e8f9f7 5434 #define ENET_EIR_PLR_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 5435 #define ENET_EIR_PLR_SHIFT (18U)
<> 144:ef7eb2e8f9f7 5436 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
<> 144:ef7eb2e8f9f7 5437 #define ENET_EIR_UN_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 5438 #define ENET_EIR_UN_SHIFT (19U)
<> 144:ef7eb2e8f9f7 5439 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
<> 144:ef7eb2e8f9f7 5440 #define ENET_EIR_RL_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 5441 #define ENET_EIR_RL_SHIFT (20U)
<> 144:ef7eb2e8f9f7 5442 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
<> 144:ef7eb2e8f9f7 5443 #define ENET_EIR_LC_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 5444 #define ENET_EIR_LC_SHIFT (21U)
<> 144:ef7eb2e8f9f7 5445 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
<> 144:ef7eb2e8f9f7 5446 #define ENET_EIR_EBERR_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 5447 #define ENET_EIR_EBERR_SHIFT (22U)
<> 144:ef7eb2e8f9f7 5448 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
<> 144:ef7eb2e8f9f7 5449 #define ENET_EIR_MII_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 5450 #define ENET_EIR_MII_SHIFT (23U)
<> 144:ef7eb2e8f9f7 5451 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
<> 144:ef7eb2e8f9f7 5452 #define ENET_EIR_RXB_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 5453 #define ENET_EIR_RXB_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5454 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
<> 144:ef7eb2e8f9f7 5455 #define ENET_EIR_RXF_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 5456 #define ENET_EIR_RXF_SHIFT (25U)
<> 144:ef7eb2e8f9f7 5457 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
<> 144:ef7eb2e8f9f7 5458 #define ENET_EIR_TXB_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 5459 #define ENET_EIR_TXB_SHIFT (26U)
<> 144:ef7eb2e8f9f7 5460 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
<> 144:ef7eb2e8f9f7 5461 #define ENET_EIR_TXF_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 5462 #define ENET_EIR_TXF_SHIFT (27U)
<> 144:ef7eb2e8f9f7 5463 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
<> 144:ef7eb2e8f9f7 5464 #define ENET_EIR_GRA_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 5465 #define ENET_EIR_GRA_SHIFT (28U)
<> 144:ef7eb2e8f9f7 5466 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
<> 144:ef7eb2e8f9f7 5467 #define ENET_EIR_BABT_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 5468 #define ENET_EIR_BABT_SHIFT (29U)
<> 144:ef7eb2e8f9f7 5469 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
<> 144:ef7eb2e8f9f7 5470 #define ENET_EIR_BABR_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 5471 #define ENET_EIR_BABR_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5472 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
<> 144:ef7eb2e8f9f7 5473
<> 144:ef7eb2e8f9f7 5474 /*! @name EIMR - Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 5475 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5476 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5477 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
<> 144:ef7eb2e8f9f7 5478 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 5479 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5480 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
<> 144:ef7eb2e8f9f7 5481 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 5482 #define ENET_EIMR_WAKEUP_SHIFT (17U)
<> 144:ef7eb2e8f9f7 5483 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
<> 144:ef7eb2e8f9f7 5484 #define ENET_EIMR_PLR_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 5485 #define ENET_EIMR_PLR_SHIFT (18U)
<> 144:ef7eb2e8f9f7 5486 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
<> 144:ef7eb2e8f9f7 5487 #define ENET_EIMR_UN_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 5488 #define ENET_EIMR_UN_SHIFT (19U)
<> 144:ef7eb2e8f9f7 5489 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
<> 144:ef7eb2e8f9f7 5490 #define ENET_EIMR_RL_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 5491 #define ENET_EIMR_RL_SHIFT (20U)
<> 144:ef7eb2e8f9f7 5492 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
<> 144:ef7eb2e8f9f7 5493 #define ENET_EIMR_LC_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 5494 #define ENET_EIMR_LC_SHIFT (21U)
<> 144:ef7eb2e8f9f7 5495 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
<> 144:ef7eb2e8f9f7 5496 #define ENET_EIMR_EBERR_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 5497 #define ENET_EIMR_EBERR_SHIFT (22U)
<> 144:ef7eb2e8f9f7 5498 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
<> 144:ef7eb2e8f9f7 5499 #define ENET_EIMR_MII_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 5500 #define ENET_EIMR_MII_SHIFT (23U)
<> 144:ef7eb2e8f9f7 5501 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
<> 144:ef7eb2e8f9f7 5502 #define ENET_EIMR_RXB_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 5503 #define ENET_EIMR_RXB_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5504 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
<> 144:ef7eb2e8f9f7 5505 #define ENET_EIMR_RXF_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 5506 #define ENET_EIMR_RXF_SHIFT (25U)
<> 144:ef7eb2e8f9f7 5507 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
<> 144:ef7eb2e8f9f7 5508 #define ENET_EIMR_TXB_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 5509 #define ENET_EIMR_TXB_SHIFT (26U)
<> 144:ef7eb2e8f9f7 5510 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
<> 144:ef7eb2e8f9f7 5511 #define ENET_EIMR_TXF_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 5512 #define ENET_EIMR_TXF_SHIFT (27U)
<> 144:ef7eb2e8f9f7 5513 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
<> 144:ef7eb2e8f9f7 5514 #define ENET_EIMR_GRA_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 5515 #define ENET_EIMR_GRA_SHIFT (28U)
<> 144:ef7eb2e8f9f7 5516 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
<> 144:ef7eb2e8f9f7 5517 #define ENET_EIMR_BABT_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 5518 #define ENET_EIMR_BABT_SHIFT (29U)
<> 144:ef7eb2e8f9f7 5519 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
<> 144:ef7eb2e8f9f7 5520 #define ENET_EIMR_BABR_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 5521 #define ENET_EIMR_BABR_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5522 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
<> 144:ef7eb2e8f9f7 5523
<> 144:ef7eb2e8f9f7 5524 /*! @name RDAR - Receive Descriptor Active Register */
<> 144:ef7eb2e8f9f7 5525 #define ENET_RDAR_RDAR_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 5526 #define ENET_RDAR_RDAR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5527 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
<> 144:ef7eb2e8f9f7 5528
<> 144:ef7eb2e8f9f7 5529 /*! @name TDAR - Transmit Descriptor Active Register */
<> 144:ef7eb2e8f9f7 5530 #define ENET_TDAR_TDAR_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 5531 #define ENET_TDAR_TDAR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 5532 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
<> 144:ef7eb2e8f9f7 5533
<> 144:ef7eb2e8f9f7 5534 /*! @name ECR - Ethernet Control Register */
<> 144:ef7eb2e8f9f7 5535 #define ENET_ECR_RESET_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5536 #define ENET_ECR_RESET_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5537 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
<> 144:ef7eb2e8f9f7 5538 #define ENET_ECR_ETHEREN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5539 #define ENET_ECR_ETHEREN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5540 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
<> 144:ef7eb2e8f9f7 5541 #define ENET_ECR_MAGICEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5542 #define ENET_ECR_MAGICEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5543 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
<> 144:ef7eb2e8f9f7 5544 #define ENET_ECR_SLEEP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5545 #define ENET_ECR_SLEEP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5546 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
<> 144:ef7eb2e8f9f7 5547 #define ENET_ECR_EN1588_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5548 #define ENET_ECR_EN1588_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5549 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
<> 144:ef7eb2e8f9f7 5550 #define ENET_ECR_DBGEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5551 #define ENET_ECR_DBGEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5552 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
<> 144:ef7eb2e8f9f7 5553 #define ENET_ECR_STOPEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5554 #define ENET_ECR_STOPEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5555 #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
<> 144:ef7eb2e8f9f7 5556 #define ENET_ECR_DBSWP_MASK (0x100U)
<> 144:ef7eb2e8f9f7 5557 #define ENET_ECR_DBSWP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5558 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
<> 144:ef7eb2e8f9f7 5559
<> 144:ef7eb2e8f9f7 5560 /*! @name MMFR - MII Management Frame Register */
<> 144:ef7eb2e8f9f7 5561 #define ENET_MMFR_DATA_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5562 #define ENET_MMFR_DATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5563 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
<> 144:ef7eb2e8f9f7 5564 #define ENET_MMFR_TA_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 5565 #define ENET_MMFR_TA_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5566 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
<> 144:ef7eb2e8f9f7 5567 #define ENET_MMFR_RA_MASK (0x7C0000U)
<> 144:ef7eb2e8f9f7 5568 #define ENET_MMFR_RA_SHIFT (18U)
<> 144:ef7eb2e8f9f7 5569 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
<> 144:ef7eb2e8f9f7 5570 #define ENET_MMFR_PA_MASK (0xF800000U)
<> 144:ef7eb2e8f9f7 5571 #define ENET_MMFR_PA_SHIFT (23U)
<> 144:ef7eb2e8f9f7 5572 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
<> 144:ef7eb2e8f9f7 5573 #define ENET_MMFR_OP_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 5574 #define ENET_MMFR_OP_SHIFT (28U)
<> 144:ef7eb2e8f9f7 5575 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
<> 144:ef7eb2e8f9f7 5576 #define ENET_MMFR_ST_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 5577 #define ENET_MMFR_ST_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5578 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
<> 144:ef7eb2e8f9f7 5579
<> 144:ef7eb2e8f9f7 5580 /*! @name MSCR - MII Speed Control Register */
<> 144:ef7eb2e8f9f7 5581 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
<> 144:ef7eb2e8f9f7 5582 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5583 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
<> 144:ef7eb2e8f9f7 5584 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5585 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5586 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
<> 144:ef7eb2e8f9f7 5587 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
<> 144:ef7eb2e8f9f7 5588 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5589 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
<> 144:ef7eb2e8f9f7 5590
<> 144:ef7eb2e8f9f7 5591 /*! @name MIBC - MIB Control Register */
<> 144:ef7eb2e8f9f7 5592 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 5593 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
<> 144:ef7eb2e8f9f7 5594 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
<> 144:ef7eb2e8f9f7 5595 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 5596 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5597 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
<> 144:ef7eb2e8f9f7 5598 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 5599 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
<> 144:ef7eb2e8f9f7 5600 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
<> 144:ef7eb2e8f9f7 5601
<> 144:ef7eb2e8f9f7 5602 /*! @name RCR - Receive Control Register */
<> 144:ef7eb2e8f9f7 5603 #define ENET_RCR_LOOP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5604 #define ENET_RCR_LOOP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5605 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
<> 144:ef7eb2e8f9f7 5606 #define ENET_RCR_DRT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5607 #define ENET_RCR_DRT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5608 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
<> 144:ef7eb2e8f9f7 5609 #define ENET_RCR_MII_MODE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5610 #define ENET_RCR_MII_MODE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5611 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
<> 144:ef7eb2e8f9f7 5612 #define ENET_RCR_PROM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5613 #define ENET_RCR_PROM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5614 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
<> 144:ef7eb2e8f9f7 5615 #define ENET_RCR_BC_REJ_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5616 #define ENET_RCR_BC_REJ_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5617 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
<> 144:ef7eb2e8f9f7 5618 #define ENET_RCR_FCE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 5619 #define ENET_RCR_FCE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5620 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
<> 144:ef7eb2e8f9f7 5621 #define ENET_RCR_RMII_MODE_MASK (0x100U)
<> 144:ef7eb2e8f9f7 5622 #define ENET_RCR_RMII_MODE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5623 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
<> 144:ef7eb2e8f9f7 5624 #define ENET_RCR_RMII_10T_MASK (0x200U)
<> 144:ef7eb2e8f9f7 5625 #define ENET_RCR_RMII_10T_SHIFT (9U)
<> 144:ef7eb2e8f9f7 5626 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
<> 144:ef7eb2e8f9f7 5627 #define ENET_RCR_PADEN_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 5628 #define ENET_RCR_PADEN_SHIFT (12U)
<> 144:ef7eb2e8f9f7 5629 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
<> 144:ef7eb2e8f9f7 5630 #define ENET_RCR_PAUFWD_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 5631 #define ENET_RCR_PAUFWD_SHIFT (13U)
<> 144:ef7eb2e8f9f7 5632 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
<> 144:ef7eb2e8f9f7 5633 #define ENET_RCR_CRCFWD_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 5634 #define ENET_RCR_CRCFWD_SHIFT (14U)
<> 144:ef7eb2e8f9f7 5635 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
<> 144:ef7eb2e8f9f7 5636 #define ENET_RCR_CFEN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 5637 #define ENET_RCR_CFEN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 5638 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
<> 144:ef7eb2e8f9f7 5639 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
<> 144:ef7eb2e8f9f7 5640 #define ENET_RCR_MAX_FL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5641 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
<> 144:ef7eb2e8f9f7 5642 #define ENET_RCR_NLC_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 5643 #define ENET_RCR_NLC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 5644 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
<> 144:ef7eb2e8f9f7 5645 #define ENET_RCR_GRS_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 5646 #define ENET_RCR_GRS_SHIFT (31U)
<> 144:ef7eb2e8f9f7 5647 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
<> 144:ef7eb2e8f9f7 5648
<> 144:ef7eb2e8f9f7 5649 /*! @name TCR - Transmit Control Register */
<> 144:ef7eb2e8f9f7 5650 #define ENET_TCR_GTS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5651 #define ENET_TCR_GTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5652 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
<> 144:ef7eb2e8f9f7 5653 #define ENET_TCR_FDEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5654 #define ENET_TCR_FDEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5655 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
<> 144:ef7eb2e8f9f7 5656 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5657 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5658 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
<> 144:ef7eb2e8f9f7 5659 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5660 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5661 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
<> 144:ef7eb2e8f9f7 5662 #define ENET_TCR_ADDSEL_MASK (0xE0U)
<> 144:ef7eb2e8f9f7 5663 #define ENET_TCR_ADDSEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 5664 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
<> 144:ef7eb2e8f9f7 5665 #define ENET_TCR_ADDINS_MASK (0x100U)
<> 144:ef7eb2e8f9f7 5666 #define ENET_TCR_ADDINS_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5667 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
<> 144:ef7eb2e8f9f7 5668 #define ENET_TCR_CRCFWD_MASK (0x200U)
<> 144:ef7eb2e8f9f7 5669 #define ENET_TCR_CRCFWD_SHIFT (9U)
<> 144:ef7eb2e8f9f7 5670 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
<> 144:ef7eb2e8f9f7 5671
<> 144:ef7eb2e8f9f7 5672 /*! @name PALR - Physical Address Lower Register */
<> 144:ef7eb2e8f9f7 5673 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5674 #define ENET_PALR_PADDR1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5675 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
<> 144:ef7eb2e8f9f7 5676
<> 144:ef7eb2e8f9f7 5677 /*! @name PAUR - Physical Address Upper Register */
<> 144:ef7eb2e8f9f7 5678 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5679 #define ENET_PAUR_TYPE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5680 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
<> 144:ef7eb2e8f9f7 5681 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 5682 #define ENET_PAUR_PADDR2_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5683 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
<> 144:ef7eb2e8f9f7 5684
<> 144:ef7eb2e8f9f7 5685 /*! @name OPD - Opcode/Pause Duration Register */
<> 144:ef7eb2e8f9f7 5686 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5687 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5688 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
<> 144:ef7eb2e8f9f7 5689 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 5690 #define ENET_OPD_OPCODE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5691 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
<> 144:ef7eb2e8f9f7 5692
<> 144:ef7eb2e8f9f7 5693 /*! @name IAUR - Descriptor Individual Upper Address Register */
<> 144:ef7eb2e8f9f7 5694 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5695 #define ENET_IAUR_IADDR1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5696 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
<> 144:ef7eb2e8f9f7 5697
<> 144:ef7eb2e8f9f7 5698 /*! @name IALR - Descriptor Individual Lower Address Register */
<> 144:ef7eb2e8f9f7 5699 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5700 #define ENET_IALR_IADDR2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5701 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
<> 144:ef7eb2e8f9f7 5702
<> 144:ef7eb2e8f9f7 5703 /*! @name GAUR - Descriptor Group Upper Address Register */
<> 144:ef7eb2e8f9f7 5704 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5705 #define ENET_GAUR_GADDR1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5706 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
<> 144:ef7eb2e8f9f7 5707
<> 144:ef7eb2e8f9f7 5708 /*! @name GALR - Descriptor Group Lower Address Register */
<> 144:ef7eb2e8f9f7 5709 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5710 #define ENET_GALR_GADDR2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5711 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
<> 144:ef7eb2e8f9f7 5712
<> 144:ef7eb2e8f9f7 5713 /*! @name TFWR - Transmit FIFO Watermark Register */
<> 144:ef7eb2e8f9f7 5714 #define ENET_TFWR_TFWR_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 5715 #define ENET_TFWR_TFWR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5716 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
<> 144:ef7eb2e8f9f7 5717 #define ENET_TFWR_STRFWD_MASK (0x100U)
<> 144:ef7eb2e8f9f7 5718 #define ENET_TFWR_STRFWD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 5719 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
<> 144:ef7eb2e8f9f7 5720
<> 144:ef7eb2e8f9f7 5721 /*! @name RDSR - Receive Descriptor Ring Start Register */
<> 144:ef7eb2e8f9f7 5722 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
<> 144:ef7eb2e8f9f7 5723 #define ENET_RDSR_R_DES_START_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5724 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
<> 144:ef7eb2e8f9f7 5725
<> 144:ef7eb2e8f9f7 5726 /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
<> 144:ef7eb2e8f9f7 5727 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
<> 144:ef7eb2e8f9f7 5728 #define ENET_TDSR_X_DES_START_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5729 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
<> 144:ef7eb2e8f9f7 5730
<> 144:ef7eb2e8f9f7 5731 /*! @name MRBR - Maximum Receive Buffer Size Register */
<> 144:ef7eb2e8f9f7 5732 #define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
<> 144:ef7eb2e8f9f7 5733 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5734 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
<> 144:ef7eb2e8f9f7 5735
<> 144:ef7eb2e8f9f7 5736 /*! @name RSFL - Receive FIFO Section Full Threshold */
<> 144:ef7eb2e8f9f7 5737 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5738 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5739 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
<> 144:ef7eb2e8f9f7 5740
<> 144:ef7eb2e8f9f7 5741 /*! @name RSEM - Receive FIFO Section Empty Threshold */
<> 144:ef7eb2e8f9f7 5742 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5743 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5744 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
<> 144:ef7eb2e8f9f7 5745 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 5746 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
<> 144:ef7eb2e8f9f7 5747 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
<> 144:ef7eb2e8f9f7 5748
<> 144:ef7eb2e8f9f7 5749 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
<> 144:ef7eb2e8f9f7 5750 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5751 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5752 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
<> 144:ef7eb2e8f9f7 5753
<> 144:ef7eb2e8f9f7 5754 /*! @name RAFL - Receive FIFO Almost Full Threshold */
<> 144:ef7eb2e8f9f7 5755 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5756 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5757 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
<> 144:ef7eb2e8f9f7 5758
<> 144:ef7eb2e8f9f7 5759 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
<> 144:ef7eb2e8f9f7 5760 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5761 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5762 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
<> 144:ef7eb2e8f9f7 5763
<> 144:ef7eb2e8f9f7 5764 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
<> 144:ef7eb2e8f9f7 5765 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5766 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5767 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
<> 144:ef7eb2e8f9f7 5768
<> 144:ef7eb2e8f9f7 5769 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
<> 144:ef7eb2e8f9f7 5770 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 5771 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5772 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
<> 144:ef7eb2e8f9f7 5773
<> 144:ef7eb2e8f9f7 5774 /*! @name TIPG - Transmit Inter-Packet Gap */
<> 144:ef7eb2e8f9f7 5775 #define ENET_TIPG_IPG_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 5776 #define ENET_TIPG_IPG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5777 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
<> 144:ef7eb2e8f9f7 5778
<> 144:ef7eb2e8f9f7 5779 /*! @name FTRL - Frame Truncation Length */
<> 144:ef7eb2e8f9f7 5780 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
<> 144:ef7eb2e8f9f7 5781 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5782 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
<> 144:ef7eb2e8f9f7 5783
<> 144:ef7eb2e8f9f7 5784 /*! @name TACC - Transmit Accelerator Function Configuration */
<> 144:ef7eb2e8f9f7 5785 #define ENET_TACC_SHIFT16_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5786 #define ENET_TACC_SHIFT16_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5787 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
<> 144:ef7eb2e8f9f7 5788 #define ENET_TACC_IPCHK_MASK (0x8U)
<> 144:ef7eb2e8f9f7 5789 #define ENET_TACC_IPCHK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 5790 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
<> 144:ef7eb2e8f9f7 5791 #define ENET_TACC_PROCHK_MASK (0x10U)
<> 144:ef7eb2e8f9f7 5792 #define ENET_TACC_PROCHK_SHIFT (4U)
<> 144:ef7eb2e8f9f7 5793 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
<> 144:ef7eb2e8f9f7 5794
<> 144:ef7eb2e8f9f7 5795 /*! @name RACC - Receive Accelerator Function Configuration */
<> 144:ef7eb2e8f9f7 5796 #define ENET_RACC_PADREM_MASK (0x1U)
<> 144:ef7eb2e8f9f7 5797 #define ENET_RACC_PADREM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5798 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
<> 144:ef7eb2e8f9f7 5799 #define ENET_RACC_IPDIS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 5800 #define ENET_RACC_IPDIS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 5801 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
<> 144:ef7eb2e8f9f7 5802 #define ENET_RACC_PRODIS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 5803 #define ENET_RACC_PRODIS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 5804 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
<> 144:ef7eb2e8f9f7 5805 #define ENET_RACC_LINEDIS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 5806 #define ENET_RACC_LINEDIS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 5807 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
<> 144:ef7eb2e8f9f7 5808 #define ENET_RACC_SHIFT16_MASK (0x80U)
<> 144:ef7eb2e8f9f7 5809 #define ENET_RACC_SHIFT16_SHIFT (7U)
<> 144:ef7eb2e8f9f7 5810 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
<> 144:ef7eb2e8f9f7 5811
<> 144:ef7eb2e8f9f7 5812 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
<> 144:ef7eb2e8f9f7 5813 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5814 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5815 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5816
<> 144:ef7eb2e8f9f7 5817 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5818 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5819 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5820 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5821
<> 144:ef7eb2e8f9f7 5822 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5823 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5824 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5825 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5826
<> 144:ef7eb2e8f9f7 5827 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
<> 144:ef7eb2e8f9f7 5828 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5829 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5830 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5831
<> 144:ef7eb2e8f9f7 5832 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5833 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5834 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5835 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5836
<> 144:ef7eb2e8f9f7 5837 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5838 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5839 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5840 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5841
<> 144:ef7eb2e8f9f7 5842 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5843 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5844 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5845 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5846
<> 144:ef7eb2e8f9f7 5847 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5848 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5849 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5850 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5851
<> 144:ef7eb2e8f9f7 5852 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
<> 144:ef7eb2e8f9f7 5853 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5854 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5855 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5856
<> 144:ef7eb2e8f9f7 5857 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5858 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5859 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5860 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5861
<> 144:ef7eb2e8f9f7 5862 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5863 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5864 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5865 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5866
<> 144:ef7eb2e8f9f7 5867 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5868 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5869 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5870 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5871
<> 144:ef7eb2e8f9f7 5872 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5873 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5874 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5875 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5876
<> 144:ef7eb2e8f9f7 5877 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5878 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5879 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5880 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5881
<> 144:ef7eb2e8f9f7 5882 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5883 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5884 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5885 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5886
<> 144:ef7eb2e8f9f7 5887 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
<> 144:ef7eb2e8f9f7 5888 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5889 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5890 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
<> 144:ef7eb2e8f9f7 5891
<> 144:ef7eb2e8f9f7 5892 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
<> 144:ef7eb2e8f9f7 5893 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5894 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5895 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
<> 144:ef7eb2e8f9f7 5896
<> 144:ef7eb2e8f9f7 5897 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
<> 144:ef7eb2e8f9f7 5898 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5899 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5900 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5901
<> 144:ef7eb2e8f9f7 5902 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
<> 144:ef7eb2e8f9f7 5903 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5904 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5905 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5906
<> 144:ef7eb2e8f9f7 5907 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
<> 144:ef7eb2e8f9f7 5908 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5909 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5910 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5911
<> 144:ef7eb2e8f9f7 5912 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
<> 144:ef7eb2e8f9f7 5913 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5914 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5915 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5916
<> 144:ef7eb2e8f9f7 5917 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
<> 144:ef7eb2e8f9f7 5918 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5919 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5920 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5921
<> 144:ef7eb2e8f9f7 5922 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
<> 144:ef7eb2e8f9f7 5923 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5924 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5925 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5926
<> 144:ef7eb2e8f9f7 5927 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
<> 144:ef7eb2e8f9f7 5928 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5929 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5930 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5931
<> 144:ef7eb2e8f9f7 5932 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
<> 144:ef7eb2e8f9f7 5933 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5934 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5935 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5936
<> 144:ef7eb2e8f9f7 5937 /*! @name IEEE_T_SQE - */
<> 144:ef7eb2e8f9f7 5938 #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5939 #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5940 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5941
<> 144:ef7eb2e8f9f7 5942 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
<> 144:ef7eb2e8f9f7 5943 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5944 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5945 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5946
<> 144:ef7eb2e8f9f7 5947 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
<> 144:ef7eb2e8f9f7 5948 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 5949 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5950 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5951
<> 144:ef7eb2e8f9f7 5952 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
<> 144:ef7eb2e8f9f7 5953 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5954 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5955 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5956
<> 144:ef7eb2e8f9f7 5957 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5958 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5959 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5960 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5961
<> 144:ef7eb2e8f9f7 5962 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5963 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5964 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5965 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5966
<> 144:ef7eb2e8f9f7 5967 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
<> 144:ef7eb2e8f9f7 5968 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5969 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5970 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5971
<> 144:ef7eb2e8f9f7 5972 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5973 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5974 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5975 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5976
<> 144:ef7eb2e8f9f7 5977 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5978 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5979 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5980 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5981
<> 144:ef7eb2e8f9f7 5982 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5983 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5984 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5985 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5986
<> 144:ef7eb2e8f9f7 5987 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
<> 144:ef7eb2e8f9f7 5988 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5989 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5990 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5991
<> 144:ef7eb2e8f9f7 5992 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5993 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5994 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 5995 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
<> 144:ef7eb2e8f9f7 5996
<> 144:ef7eb2e8f9f7 5997 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 5998 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 5999 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6000 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6001
<> 144:ef7eb2e8f9f7 6002 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 6003 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6004 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6005 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6006
<> 144:ef7eb2e8f9f7 6007 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 6008 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6009 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6010 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6011
<> 144:ef7eb2e8f9f7 6012 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 6013 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6014 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6015 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6016
<> 144:ef7eb2e8f9f7 6017 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
<> 144:ef7eb2e8f9f7 6018 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6019 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6020 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6021
<> 144:ef7eb2e8f9f7 6022 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
<> 144:ef7eb2e8f9f7 6023 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6024 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6025 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6026
<> 144:ef7eb2e8f9f7 6027 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
<> 144:ef7eb2e8f9f7 6028 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6029 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6030 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6031
<> 144:ef7eb2e8f9f7 6032 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
<> 144:ef7eb2e8f9f7 6033 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6034 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6035 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6036
<> 144:ef7eb2e8f9f7 6037 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
<> 144:ef7eb2e8f9f7 6038 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6039 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6040 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6041
<> 144:ef7eb2e8f9f7 6042 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
<> 144:ef7eb2e8f9f7 6043 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6044 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6045 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6046
<> 144:ef7eb2e8f9f7 6047 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
<> 144:ef7eb2e8f9f7 6048 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6049 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6050 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6051
<> 144:ef7eb2e8f9f7 6052 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
<> 144:ef7eb2e8f9f7 6053 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6054 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6055 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6056
<> 144:ef7eb2e8f9f7 6057 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
<> 144:ef7eb2e8f9f7 6058 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 6059 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6060 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6061
<> 144:ef7eb2e8f9f7 6062 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
<> 144:ef7eb2e8f9f7 6063 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6064 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6065 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
<> 144:ef7eb2e8f9f7 6066
<> 144:ef7eb2e8f9f7 6067 /*! @name ATCR - Adjustable Timer Control Register */
<> 144:ef7eb2e8f9f7 6068 #define ENET_ATCR_EN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6069 #define ENET_ATCR_EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6070 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
<> 144:ef7eb2e8f9f7 6071 #define ENET_ATCR_OFFEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6072 #define ENET_ATCR_OFFEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6073 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
<> 144:ef7eb2e8f9f7 6074 #define ENET_ATCR_OFFRST_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6075 #define ENET_ATCR_OFFRST_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6076 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
<> 144:ef7eb2e8f9f7 6077 #define ENET_ATCR_PEREN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6078 #define ENET_ATCR_PEREN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6079 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
<> 144:ef7eb2e8f9f7 6080 #define ENET_ATCR_PINPER_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6081 #define ENET_ATCR_PINPER_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6082 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
<> 144:ef7eb2e8f9f7 6083 #define ENET_ATCR_RESTART_MASK (0x200U)
<> 144:ef7eb2e8f9f7 6084 #define ENET_ATCR_RESTART_SHIFT (9U)
<> 144:ef7eb2e8f9f7 6085 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
<> 144:ef7eb2e8f9f7 6086 #define ENET_ATCR_CAPTURE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 6087 #define ENET_ATCR_CAPTURE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 6088 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
<> 144:ef7eb2e8f9f7 6089 #define ENET_ATCR_SLAVE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 6090 #define ENET_ATCR_SLAVE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 6091 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
<> 144:ef7eb2e8f9f7 6092
<> 144:ef7eb2e8f9f7 6093 /*! @name ATVR - Timer Value Register */
<> 144:ef7eb2e8f9f7 6094 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6095 #define ENET_ATVR_ATIME_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6096 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
<> 144:ef7eb2e8f9f7 6097
<> 144:ef7eb2e8f9f7 6098 /*! @name ATOFF - Timer Offset Register */
<> 144:ef7eb2e8f9f7 6099 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6100 #define ENET_ATOFF_OFFSET_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6101 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
<> 144:ef7eb2e8f9f7 6102
<> 144:ef7eb2e8f9f7 6103 /*! @name ATPER - Timer Period Register */
<> 144:ef7eb2e8f9f7 6104 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6105 #define ENET_ATPER_PERIOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6106 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
<> 144:ef7eb2e8f9f7 6107
<> 144:ef7eb2e8f9f7 6108 /*! @name ATCOR - Timer Correction Register */
<> 144:ef7eb2e8f9f7 6109 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
<> 144:ef7eb2e8f9f7 6110 #define ENET_ATCOR_COR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6111 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
<> 144:ef7eb2e8f9f7 6112
<> 144:ef7eb2e8f9f7 6113 /*! @name ATINC - Time-Stamping Clock Period Register */
<> 144:ef7eb2e8f9f7 6114 #define ENET_ATINC_INC_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 6115 #define ENET_ATINC_INC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6116 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
<> 144:ef7eb2e8f9f7 6117 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
<> 144:ef7eb2e8f9f7 6118 #define ENET_ATINC_INC_CORR_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6119 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
<> 144:ef7eb2e8f9f7 6120
<> 144:ef7eb2e8f9f7 6121 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
<> 144:ef7eb2e8f9f7 6122 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6123 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6124 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
<> 144:ef7eb2e8f9f7 6125
<> 144:ef7eb2e8f9f7 6126 /*! @name TGSR - Timer Global Status Register */
<> 144:ef7eb2e8f9f7 6127 #define ENET_TGSR_TF0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6128 #define ENET_TGSR_TF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6129 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
<> 144:ef7eb2e8f9f7 6130 #define ENET_TGSR_TF1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6131 #define ENET_TGSR_TF1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6132 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
<> 144:ef7eb2e8f9f7 6133 #define ENET_TGSR_TF2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6134 #define ENET_TGSR_TF2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6135 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
<> 144:ef7eb2e8f9f7 6136 #define ENET_TGSR_TF3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6137 #define ENET_TGSR_TF3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6138 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
<> 144:ef7eb2e8f9f7 6139
<> 144:ef7eb2e8f9f7 6140 /*! @name TCSR - Timer Control Status Register */
<> 144:ef7eb2e8f9f7 6141 #define ENET_TCSR_TDRE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6142 #define ENET_TCSR_TDRE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6143 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
<> 144:ef7eb2e8f9f7 6144 #define ENET_TCSR_TMODE_MASK (0x3CU)
<> 144:ef7eb2e8f9f7 6145 #define ENET_TCSR_TMODE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6146 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
<> 144:ef7eb2e8f9f7 6147 #define ENET_TCSR_TIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6148 #define ENET_TCSR_TIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6149 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
<> 144:ef7eb2e8f9f7 6150 #define ENET_TCSR_TF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6151 #define ENET_TCSR_TF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6152 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
<> 144:ef7eb2e8f9f7 6153
<> 144:ef7eb2e8f9f7 6154 /* The count of ENET_TCSR */
<> 144:ef7eb2e8f9f7 6155 #define ENET_TCSR_COUNT (4U)
<> 144:ef7eb2e8f9f7 6156
<> 144:ef7eb2e8f9f7 6157 /*! @name TCCR - Timer Compare Capture Register */
<> 144:ef7eb2e8f9f7 6158 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6159 #define ENET_TCCR_TCC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6160 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
<> 144:ef7eb2e8f9f7 6161
<> 144:ef7eb2e8f9f7 6162 /* The count of ENET_TCCR */
<> 144:ef7eb2e8f9f7 6163 #define ENET_TCCR_COUNT (4U)
<> 144:ef7eb2e8f9f7 6164
<> 144:ef7eb2e8f9f7 6165
<> 144:ef7eb2e8f9f7 6166 /*!
<> 144:ef7eb2e8f9f7 6167 * @}
<> 144:ef7eb2e8f9f7 6168 */ /* end of group ENET_Register_Masks */
<> 144:ef7eb2e8f9f7 6169
<> 144:ef7eb2e8f9f7 6170
<> 144:ef7eb2e8f9f7 6171 /* ENET - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6172 /** Peripheral ENET base address */
<> 144:ef7eb2e8f9f7 6173 #define ENET_BASE (0x400C0000u)
<> 144:ef7eb2e8f9f7 6174 /** Peripheral ENET base pointer */
<> 144:ef7eb2e8f9f7 6175 #define ENET ((ENET_Type *)ENET_BASE)
<> 144:ef7eb2e8f9f7 6176 /** Array initializer of ENET peripheral base addresses */
<> 144:ef7eb2e8f9f7 6177 #define ENET_BASE_ADDRS { ENET_BASE }
<> 144:ef7eb2e8f9f7 6178 /** Array initializer of ENET peripheral base pointers */
<> 144:ef7eb2e8f9f7 6179 #define ENET_BASE_PTRS { ENET }
<> 144:ef7eb2e8f9f7 6180 /** Interrupt vectors for the ENET peripheral type */
<> 144:ef7eb2e8f9f7 6181 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
<> 144:ef7eb2e8f9f7 6182 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
<> 144:ef7eb2e8f9f7 6183 #define ENET_Error_IRQS { ENET_Error_IRQn }
<> 144:ef7eb2e8f9f7 6184 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
<> 144:ef7eb2e8f9f7 6185
<> 144:ef7eb2e8f9f7 6186 /*!
<> 144:ef7eb2e8f9f7 6187 * @}
<> 144:ef7eb2e8f9f7 6188 */ /* end of group ENET_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6189
<> 144:ef7eb2e8f9f7 6190
<> 144:ef7eb2e8f9f7 6191 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6192 -- EWM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6193 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6194
<> 144:ef7eb2e8f9f7 6195 /*!
<> 144:ef7eb2e8f9f7 6196 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6197 * @{
<> 144:ef7eb2e8f9f7 6198 */
<> 144:ef7eb2e8f9f7 6199
<> 144:ef7eb2e8f9f7 6200 /** EWM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6201 typedef struct {
<> 144:ef7eb2e8f9f7 6202 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6203 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 6204 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 6205 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 6206 } EWM_Type;
<> 144:ef7eb2e8f9f7 6207
<> 144:ef7eb2e8f9f7 6208 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6209 -- EWM Register Masks
<> 144:ef7eb2e8f9f7 6210 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6211
<> 144:ef7eb2e8f9f7 6212 /*!
<> 144:ef7eb2e8f9f7 6213 * @addtogroup EWM_Register_Masks EWM Register Masks
<> 144:ef7eb2e8f9f7 6214 * @{
<> 144:ef7eb2e8f9f7 6215 */
<> 144:ef7eb2e8f9f7 6216
<> 144:ef7eb2e8f9f7 6217 /*! @name CTRL - Control Register */
<> 144:ef7eb2e8f9f7 6218 #define EWM_CTRL_EWMEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6219 #define EWM_CTRL_EWMEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6220 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
<> 144:ef7eb2e8f9f7 6221 #define EWM_CTRL_ASSIN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6222 #define EWM_CTRL_ASSIN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6223 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
<> 144:ef7eb2e8f9f7 6224 #define EWM_CTRL_INEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6225 #define EWM_CTRL_INEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6226 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
<> 144:ef7eb2e8f9f7 6227 #define EWM_CTRL_INTEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6228 #define EWM_CTRL_INTEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6229 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
<> 144:ef7eb2e8f9f7 6230
<> 144:ef7eb2e8f9f7 6231 /*! @name SERV - Service Register */
<> 144:ef7eb2e8f9f7 6232 #define EWM_SERV_SERVICE_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6233 #define EWM_SERV_SERVICE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6234 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
<> 144:ef7eb2e8f9f7 6235
<> 144:ef7eb2e8f9f7 6236 /*! @name CMPL - Compare Low Register */
<> 144:ef7eb2e8f9f7 6237 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6238 #define EWM_CMPL_COMPAREL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6239 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
<> 144:ef7eb2e8f9f7 6240
<> 144:ef7eb2e8f9f7 6241 /*! @name CMPH - Compare High Register */
<> 144:ef7eb2e8f9f7 6242 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6243 #define EWM_CMPH_COMPAREH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6244 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
<> 144:ef7eb2e8f9f7 6245
<> 144:ef7eb2e8f9f7 6246
<> 144:ef7eb2e8f9f7 6247 /*!
<> 144:ef7eb2e8f9f7 6248 * @}
<> 144:ef7eb2e8f9f7 6249 */ /* end of group EWM_Register_Masks */
<> 144:ef7eb2e8f9f7 6250
<> 144:ef7eb2e8f9f7 6251
<> 144:ef7eb2e8f9f7 6252 /* EWM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6253 /** Peripheral EWM base address */
<> 144:ef7eb2e8f9f7 6254 #define EWM_BASE (0x40061000u)
<> 144:ef7eb2e8f9f7 6255 /** Peripheral EWM base pointer */
<> 144:ef7eb2e8f9f7 6256 #define EWM ((EWM_Type *)EWM_BASE)
<> 144:ef7eb2e8f9f7 6257 /** Array initializer of EWM peripheral base addresses */
<> 144:ef7eb2e8f9f7 6258 #define EWM_BASE_ADDRS { EWM_BASE }
<> 144:ef7eb2e8f9f7 6259 /** Array initializer of EWM peripheral base pointers */
<> 144:ef7eb2e8f9f7 6260 #define EWM_BASE_PTRS { EWM }
<> 144:ef7eb2e8f9f7 6261 /** Interrupt vectors for the EWM peripheral type */
<> 144:ef7eb2e8f9f7 6262 #define EWM_IRQS { WDOG_EWM_IRQn }
<> 144:ef7eb2e8f9f7 6263
<> 144:ef7eb2e8f9f7 6264 /*!
<> 144:ef7eb2e8f9f7 6265 * @}
<> 144:ef7eb2e8f9f7 6266 */ /* end of group EWM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6267
<> 144:ef7eb2e8f9f7 6268
<> 144:ef7eb2e8f9f7 6269 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6270 -- FB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6271 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6272
<> 144:ef7eb2e8f9f7 6273 /*!
<> 144:ef7eb2e8f9f7 6274 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6275 * @{
<> 144:ef7eb2e8f9f7 6276 */
<> 144:ef7eb2e8f9f7 6277
<> 144:ef7eb2e8f9f7 6278 /** FB - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6279 typedef struct {
<> 144:ef7eb2e8f9f7 6280 struct { /* offset: 0x0, array step: 0xC */
<> 144:ef7eb2e8f9f7 6281 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
<> 144:ef7eb2e8f9f7 6282 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
<> 144:ef7eb2e8f9f7 6283 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
<> 144:ef7eb2e8f9f7 6284 } CS[6];
<> 144:ef7eb2e8f9f7 6285 uint8_t RESERVED_0[24];
<> 144:ef7eb2e8f9f7 6286 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
<> 144:ef7eb2e8f9f7 6287 } FB_Type;
<> 144:ef7eb2e8f9f7 6288
<> 144:ef7eb2e8f9f7 6289 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6290 -- FB Register Masks
<> 144:ef7eb2e8f9f7 6291 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6292
<> 144:ef7eb2e8f9f7 6293 /*!
<> 144:ef7eb2e8f9f7 6294 * @addtogroup FB_Register_Masks FB Register Masks
<> 144:ef7eb2e8f9f7 6295 * @{
<> 144:ef7eb2e8f9f7 6296 */
<> 144:ef7eb2e8f9f7 6297
<> 144:ef7eb2e8f9f7 6298 /*! @name CSAR - Chip Select Address Register */
<> 144:ef7eb2e8f9f7 6299 #define FB_CSAR_BA_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 6300 #define FB_CSAR_BA_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6301 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
<> 144:ef7eb2e8f9f7 6302
<> 144:ef7eb2e8f9f7 6303 /* The count of FB_CSAR */
<> 144:ef7eb2e8f9f7 6304 #define FB_CSAR_COUNT (6U)
<> 144:ef7eb2e8f9f7 6305
<> 144:ef7eb2e8f9f7 6306 /*! @name CSMR - Chip Select Mask Register */
<> 144:ef7eb2e8f9f7 6307 #define FB_CSMR_V_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6308 #define FB_CSMR_V_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6309 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
<> 144:ef7eb2e8f9f7 6310 #define FB_CSMR_WP_MASK (0x100U)
<> 144:ef7eb2e8f9f7 6311 #define FB_CSMR_WP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6312 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
<> 144:ef7eb2e8f9f7 6313 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 6314 #define FB_CSMR_BAM_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6315 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
<> 144:ef7eb2e8f9f7 6316
<> 144:ef7eb2e8f9f7 6317 /* The count of FB_CSMR */
<> 144:ef7eb2e8f9f7 6318 #define FB_CSMR_COUNT (6U)
<> 144:ef7eb2e8f9f7 6319
<> 144:ef7eb2e8f9f7 6320 /*! @name CSCR - Chip Select Control Register */
<> 144:ef7eb2e8f9f7 6321 #define FB_CSCR_BSTW_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6322 #define FB_CSCR_BSTW_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6323 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
<> 144:ef7eb2e8f9f7 6324 #define FB_CSCR_BSTR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6325 #define FB_CSCR_BSTR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6326 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
<> 144:ef7eb2e8f9f7 6327 #define FB_CSCR_BEM_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6328 #define FB_CSCR_BEM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6329 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
<> 144:ef7eb2e8f9f7 6330 #define FB_CSCR_PS_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 6331 #define FB_CSCR_PS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6332 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
<> 144:ef7eb2e8f9f7 6333 #define FB_CSCR_AA_MASK (0x100U)
<> 144:ef7eb2e8f9f7 6334 #define FB_CSCR_AA_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6335 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
<> 144:ef7eb2e8f9f7 6336 #define FB_CSCR_BLS_MASK (0x200U)
<> 144:ef7eb2e8f9f7 6337 #define FB_CSCR_BLS_SHIFT (9U)
<> 144:ef7eb2e8f9f7 6338 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
<> 144:ef7eb2e8f9f7 6339 #define FB_CSCR_WS_MASK (0xFC00U)
<> 144:ef7eb2e8f9f7 6340 #define FB_CSCR_WS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 6341 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
<> 144:ef7eb2e8f9f7 6342 #define FB_CSCR_WRAH_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 6343 #define FB_CSCR_WRAH_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6344 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
<> 144:ef7eb2e8f9f7 6345 #define FB_CSCR_RDAH_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 6346 #define FB_CSCR_RDAH_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6347 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
<> 144:ef7eb2e8f9f7 6348 #define FB_CSCR_ASET_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 6349 #define FB_CSCR_ASET_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6350 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
<> 144:ef7eb2e8f9f7 6351 #define FB_CSCR_EXTS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 6352 #define FB_CSCR_EXTS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 6353 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
<> 144:ef7eb2e8f9f7 6354 #define FB_CSCR_SWSEN_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 6355 #define FB_CSCR_SWSEN_SHIFT (23U)
<> 144:ef7eb2e8f9f7 6356 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
<> 144:ef7eb2e8f9f7 6357 #define FB_CSCR_SWS_MASK (0xFC000000U)
<> 144:ef7eb2e8f9f7 6358 #define FB_CSCR_SWS_SHIFT (26U)
<> 144:ef7eb2e8f9f7 6359 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
<> 144:ef7eb2e8f9f7 6360
<> 144:ef7eb2e8f9f7 6361 /* The count of FB_CSCR */
<> 144:ef7eb2e8f9f7 6362 #define FB_CSCR_COUNT (6U)
<> 144:ef7eb2e8f9f7 6363
<> 144:ef7eb2e8f9f7 6364 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
<> 144:ef7eb2e8f9f7 6365 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 6366 #define FB_CSPMCR_GROUP5_SHIFT (12U)
<> 144:ef7eb2e8f9f7 6367 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
<> 144:ef7eb2e8f9f7 6368 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 6369 #define FB_CSPMCR_GROUP4_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6370 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
<> 144:ef7eb2e8f9f7 6371 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 6372 #define FB_CSPMCR_GROUP3_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6373 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
<> 144:ef7eb2e8f9f7 6374 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 6375 #define FB_CSPMCR_GROUP2_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6376 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
<> 144:ef7eb2e8f9f7 6377 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 6378 #define FB_CSPMCR_GROUP1_SHIFT (28U)
<> 144:ef7eb2e8f9f7 6379 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
<> 144:ef7eb2e8f9f7 6380
<> 144:ef7eb2e8f9f7 6381
<> 144:ef7eb2e8f9f7 6382 /*!
<> 144:ef7eb2e8f9f7 6383 * @}
<> 144:ef7eb2e8f9f7 6384 */ /* end of group FB_Register_Masks */
<> 144:ef7eb2e8f9f7 6385
<> 144:ef7eb2e8f9f7 6386
<> 144:ef7eb2e8f9f7 6387 /* FB - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6388 /** Peripheral FB base address */
<> 144:ef7eb2e8f9f7 6389 #define FB_BASE (0x4000C000u)
<> 144:ef7eb2e8f9f7 6390 /** Peripheral FB base pointer */
<> 144:ef7eb2e8f9f7 6391 #define FB ((FB_Type *)FB_BASE)
<> 144:ef7eb2e8f9f7 6392 /** Array initializer of FB peripheral base addresses */
<> 144:ef7eb2e8f9f7 6393 #define FB_BASE_ADDRS { FB_BASE }
<> 144:ef7eb2e8f9f7 6394 /** Array initializer of FB peripheral base pointers */
<> 144:ef7eb2e8f9f7 6395 #define FB_BASE_PTRS { FB }
<> 144:ef7eb2e8f9f7 6396
<> 144:ef7eb2e8f9f7 6397 /*!
<> 144:ef7eb2e8f9f7 6398 * @}
<> 144:ef7eb2e8f9f7 6399 */ /* end of group FB_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6400
<> 144:ef7eb2e8f9f7 6401
<> 144:ef7eb2e8f9f7 6402 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6403 -- FMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6404 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6405
<> 144:ef7eb2e8f9f7 6406 /*!
<> 144:ef7eb2e8f9f7 6407 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6408 * @{
<> 144:ef7eb2e8f9f7 6409 */
<> 144:ef7eb2e8f9f7 6410
<> 144:ef7eb2e8f9f7 6411 /** FMC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6412 typedef struct {
<> 144:ef7eb2e8f9f7 6413 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6414 __IO uint32_t PFB01CR; /**< Flash Bank 0-1 Control Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6415 __IO uint32_t PFB23CR; /**< Flash Bank 2-3 Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 6416 uint8_t RESERVED_0[244];
<> 144:ef7eb2e8f9f7 6417 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
<> 144:ef7eb2e8f9f7 6418 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
<> 144:ef7eb2e8f9f7 6419 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
<> 144:ef7eb2e8f9f7 6420 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
<> 144:ef7eb2e8f9f7 6421 uint8_t RESERVED_1[192];
<> 144:ef7eb2e8f9f7 6422 struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
<> 144:ef7eb2e8f9f7 6423 __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
<> 144:ef7eb2e8f9f7 6424 __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
<> 144:ef7eb2e8f9f7 6425 __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
<> 144:ef7eb2e8f9f7 6426 __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
<> 144:ef7eb2e8f9f7 6427 } SET[4][4];
<> 144:ef7eb2e8f9f7 6428 } FMC_Type;
<> 144:ef7eb2e8f9f7 6429
<> 144:ef7eb2e8f9f7 6430 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6431 -- FMC Register Masks
<> 144:ef7eb2e8f9f7 6432 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6433
<> 144:ef7eb2e8f9f7 6434 /*!
<> 144:ef7eb2e8f9f7 6435 * @addtogroup FMC_Register_Masks FMC Register Masks
<> 144:ef7eb2e8f9f7 6436 * @{
<> 144:ef7eb2e8f9f7 6437 */
<> 144:ef7eb2e8f9f7 6438
<> 144:ef7eb2e8f9f7 6439 /*! @name PFAPR - Flash Access Protection Register */
<> 144:ef7eb2e8f9f7 6440 #define FMC_PFAPR_M0AP_MASK (0x3U)
<> 144:ef7eb2e8f9f7 6441 #define FMC_PFAPR_M0AP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6442 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
<> 144:ef7eb2e8f9f7 6443 #define FMC_PFAPR_M1AP_MASK (0xCU)
<> 144:ef7eb2e8f9f7 6444 #define FMC_PFAPR_M1AP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6445 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
<> 144:ef7eb2e8f9f7 6446 #define FMC_PFAPR_M2AP_MASK (0x30U)
<> 144:ef7eb2e8f9f7 6447 #define FMC_PFAPR_M2AP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6448 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
<> 144:ef7eb2e8f9f7 6449 #define FMC_PFAPR_M3AP_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 6450 #define FMC_PFAPR_M3AP_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6451 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
<> 144:ef7eb2e8f9f7 6452 #define FMC_PFAPR_M4AP_MASK (0x300U)
<> 144:ef7eb2e8f9f7 6453 #define FMC_PFAPR_M4AP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 6454 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
<> 144:ef7eb2e8f9f7 6455 #define FMC_PFAPR_M5AP_MASK (0xC00U)
<> 144:ef7eb2e8f9f7 6456 #define FMC_PFAPR_M5AP_SHIFT (10U)
<> 144:ef7eb2e8f9f7 6457 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
<> 144:ef7eb2e8f9f7 6458 #define FMC_PFAPR_M6AP_MASK (0x3000U)
<> 144:ef7eb2e8f9f7 6459 #define FMC_PFAPR_M6AP_SHIFT (12U)
<> 144:ef7eb2e8f9f7 6460 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
<> 144:ef7eb2e8f9f7 6461 #define FMC_PFAPR_M7AP_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 6462 #define FMC_PFAPR_M7AP_SHIFT (14U)
<> 144:ef7eb2e8f9f7 6463 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
<> 144:ef7eb2e8f9f7 6464 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 6465 #define FMC_PFAPR_M0PFD_SHIFT (16U)
<> 144:ef7eb2e8f9f7 6466 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
<> 144:ef7eb2e8f9f7 6467 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 6468 #define FMC_PFAPR_M1PFD_SHIFT (17U)
<> 144:ef7eb2e8f9f7 6469 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
<> 144:ef7eb2e8f9f7 6470 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 6471 #define FMC_PFAPR_M2PFD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 6472 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
<> 144:ef7eb2e8f9f7 6473 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 6474 #define FMC_PFAPR_M3PFD_SHIFT (19U)
<> 144:ef7eb2e8f9f7 6475 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
<> 144:ef7eb2e8f9f7 6476 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 6477 #define FMC_PFAPR_M4PFD_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6478 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
<> 144:ef7eb2e8f9f7 6479 #define FMC_PFAPR_M5PFD_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 6480 #define FMC_PFAPR_M5PFD_SHIFT (21U)
<> 144:ef7eb2e8f9f7 6481 #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
<> 144:ef7eb2e8f9f7 6482 #define FMC_PFAPR_M6PFD_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 6483 #define FMC_PFAPR_M6PFD_SHIFT (22U)
<> 144:ef7eb2e8f9f7 6484 #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
<> 144:ef7eb2e8f9f7 6485 #define FMC_PFAPR_M7PFD_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 6486 #define FMC_PFAPR_M7PFD_SHIFT (23U)
<> 144:ef7eb2e8f9f7 6487 #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
<> 144:ef7eb2e8f9f7 6488
<> 144:ef7eb2e8f9f7 6489 /*! @name PFB01CR - Flash Bank 0-1 Control Register */
<> 144:ef7eb2e8f9f7 6490 #define FMC_PFB01CR_RFU_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6491 #define FMC_PFB01CR_RFU_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6492 #define FMC_PFB01CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
<> 144:ef7eb2e8f9f7 6493 #define FMC_PFB01CR_B0IPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6494 #define FMC_PFB01CR_B0IPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6495 #define FMC_PFB01CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
<> 144:ef7eb2e8f9f7 6496 #define FMC_PFB01CR_B0DPE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6497 #define FMC_PFB01CR_B0DPE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6498 #define FMC_PFB01CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
<> 144:ef7eb2e8f9f7 6499 #define FMC_PFB01CR_B0ICE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6500 #define FMC_PFB01CR_B0ICE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6501 #define FMC_PFB01CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
<> 144:ef7eb2e8f9f7 6502 #define FMC_PFB01CR_B0DCE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6503 #define FMC_PFB01CR_B0DCE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6504 #define FMC_PFB01CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
<> 144:ef7eb2e8f9f7 6505 #define FMC_PFB01CR_CRC_MASK (0xE0U)
<> 144:ef7eb2e8f9f7 6506 #define FMC_PFB01CR_CRC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6507 #define FMC_PFB01CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
<> 144:ef7eb2e8f9f7 6508 #define FMC_PFB01CR_B0MW_MASK (0x60000U)
<> 144:ef7eb2e8f9f7 6509 #define FMC_PFB01CR_B0MW_SHIFT (17U)
<> 144:ef7eb2e8f9f7 6510 #define FMC_PFB01CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
<> 144:ef7eb2e8f9f7 6511 #define FMC_PFB01CR_S_B_INV_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 6512 #define FMC_PFB01CR_S_B_INV_SHIFT (19U)
<> 144:ef7eb2e8f9f7 6513 #define FMC_PFB01CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
<> 144:ef7eb2e8f9f7 6514 #define FMC_PFB01CR_CINV_WAY_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 6515 #define FMC_PFB01CR_CINV_WAY_SHIFT (20U)
<> 144:ef7eb2e8f9f7 6516 #define FMC_PFB01CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
<> 144:ef7eb2e8f9f7 6517 #define FMC_PFB01CR_CLCK_WAY_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 6518 #define FMC_PFB01CR_CLCK_WAY_SHIFT (24U)
<> 144:ef7eb2e8f9f7 6519 #define FMC_PFB01CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
<> 144:ef7eb2e8f9f7 6520 #define FMC_PFB01CR_B0RWSC_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 6521 #define FMC_PFB01CR_B0RWSC_SHIFT (28U)
<> 144:ef7eb2e8f9f7 6522 #define FMC_PFB01CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
<> 144:ef7eb2e8f9f7 6523
<> 144:ef7eb2e8f9f7 6524 /*! @name PFB23CR - Flash Bank 2-3 Control Register */
<> 144:ef7eb2e8f9f7 6525 #define FMC_PFB23CR_RFU_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6526 #define FMC_PFB23CR_RFU_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6527 #define FMC_PFB23CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
<> 144:ef7eb2e8f9f7 6528 #define FMC_PFB23CR_B1IPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6529 #define FMC_PFB23CR_B1IPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6530 #define FMC_PFB23CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
<> 144:ef7eb2e8f9f7 6531 #define FMC_PFB23CR_B1DPE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6532 #define FMC_PFB23CR_B1DPE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6533 #define FMC_PFB23CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
<> 144:ef7eb2e8f9f7 6534 #define FMC_PFB23CR_B1ICE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6535 #define FMC_PFB23CR_B1ICE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6536 #define FMC_PFB23CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
<> 144:ef7eb2e8f9f7 6537 #define FMC_PFB23CR_B1DCE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6538 #define FMC_PFB23CR_B1DCE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6539 #define FMC_PFB23CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
<> 144:ef7eb2e8f9f7 6540 #define FMC_PFB23CR_B1MW_MASK (0x60000U)
<> 144:ef7eb2e8f9f7 6541 #define FMC_PFB23CR_B1MW_SHIFT (17U)
<> 144:ef7eb2e8f9f7 6542 #define FMC_PFB23CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
<> 144:ef7eb2e8f9f7 6543 #define FMC_PFB23CR_B1RWSC_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 6544 #define FMC_PFB23CR_B1RWSC_SHIFT (28U)
<> 144:ef7eb2e8f9f7 6545 #define FMC_PFB23CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
<> 144:ef7eb2e8f9f7 6546
<> 144:ef7eb2e8f9f7 6547 /*! @name TAGVDW0S - Cache Tag Storage */
<> 144:ef7eb2e8f9f7 6548 #define FMC_TAGVDW0S_valid_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6549 #define FMC_TAGVDW0S_valid_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6550 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
<> 144:ef7eb2e8f9f7 6551 #define FMC_TAGVDW0S_tag_MASK (0x3FFFC0U)
<> 144:ef7eb2e8f9f7 6552 #define FMC_TAGVDW0S_tag_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6553 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
<> 144:ef7eb2e8f9f7 6554
<> 144:ef7eb2e8f9f7 6555 /* The count of FMC_TAGVDW0S */
<> 144:ef7eb2e8f9f7 6556 #define FMC_TAGVDW0S_COUNT (4U)
<> 144:ef7eb2e8f9f7 6557
<> 144:ef7eb2e8f9f7 6558 /*! @name TAGVDW1S - Cache Tag Storage */
<> 144:ef7eb2e8f9f7 6559 #define FMC_TAGVDW1S_valid_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6560 #define FMC_TAGVDW1S_valid_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6561 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
<> 144:ef7eb2e8f9f7 6562 #define FMC_TAGVDW1S_tag_MASK (0x3FFFC0U)
<> 144:ef7eb2e8f9f7 6563 #define FMC_TAGVDW1S_tag_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6564 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
<> 144:ef7eb2e8f9f7 6565
<> 144:ef7eb2e8f9f7 6566 /* The count of FMC_TAGVDW1S */
<> 144:ef7eb2e8f9f7 6567 #define FMC_TAGVDW1S_COUNT (4U)
<> 144:ef7eb2e8f9f7 6568
<> 144:ef7eb2e8f9f7 6569 /*! @name TAGVDW2S - Cache Tag Storage */
<> 144:ef7eb2e8f9f7 6570 #define FMC_TAGVDW2S_valid_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6571 #define FMC_TAGVDW2S_valid_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6572 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
<> 144:ef7eb2e8f9f7 6573 #define FMC_TAGVDW2S_tag_MASK (0x3FFFC0U)
<> 144:ef7eb2e8f9f7 6574 #define FMC_TAGVDW2S_tag_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6575 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
<> 144:ef7eb2e8f9f7 6576
<> 144:ef7eb2e8f9f7 6577 /* The count of FMC_TAGVDW2S */
<> 144:ef7eb2e8f9f7 6578 #define FMC_TAGVDW2S_COUNT (4U)
<> 144:ef7eb2e8f9f7 6579
<> 144:ef7eb2e8f9f7 6580 /*! @name TAGVDW3S - Cache Tag Storage */
<> 144:ef7eb2e8f9f7 6581 #define FMC_TAGVDW3S_valid_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6582 #define FMC_TAGVDW3S_valid_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6583 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
<> 144:ef7eb2e8f9f7 6584 #define FMC_TAGVDW3S_tag_MASK (0x3FFFC0U)
<> 144:ef7eb2e8f9f7 6585 #define FMC_TAGVDW3S_tag_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6586 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
<> 144:ef7eb2e8f9f7 6587
<> 144:ef7eb2e8f9f7 6588 /* The count of FMC_TAGVDW3S */
<> 144:ef7eb2e8f9f7 6589 #define FMC_TAGVDW3S_COUNT (4U)
<> 144:ef7eb2e8f9f7 6590
<> 144:ef7eb2e8f9f7 6591 /*! @name DATA_UM - Cache Data Storage (uppermost word) */
<> 144:ef7eb2e8f9f7 6592 #define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6593 #define FMC_DATA_UM_data_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6594 #define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
<> 144:ef7eb2e8f9f7 6595
<> 144:ef7eb2e8f9f7 6596 /* The count of FMC_DATA_UM */
<> 144:ef7eb2e8f9f7 6597 #define FMC_DATA_UM_COUNT (4U)
<> 144:ef7eb2e8f9f7 6598
<> 144:ef7eb2e8f9f7 6599 /* The count of FMC_DATA_UM */
<> 144:ef7eb2e8f9f7 6600 #define FMC_DATA_UM_COUNT2 (4U)
<> 144:ef7eb2e8f9f7 6601
<> 144:ef7eb2e8f9f7 6602 /*! @name DATA_MU - Cache Data Storage (mid-upper word) */
<> 144:ef7eb2e8f9f7 6603 #define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6604 #define FMC_DATA_MU_data_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6605 #define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
<> 144:ef7eb2e8f9f7 6606
<> 144:ef7eb2e8f9f7 6607 /* The count of FMC_DATA_MU */
<> 144:ef7eb2e8f9f7 6608 #define FMC_DATA_MU_COUNT (4U)
<> 144:ef7eb2e8f9f7 6609
<> 144:ef7eb2e8f9f7 6610 /* The count of FMC_DATA_MU */
<> 144:ef7eb2e8f9f7 6611 #define FMC_DATA_MU_COUNT2 (4U)
<> 144:ef7eb2e8f9f7 6612
<> 144:ef7eb2e8f9f7 6613 /*! @name DATA_ML - Cache Data Storage (mid-lower word) */
<> 144:ef7eb2e8f9f7 6614 #define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6615 #define FMC_DATA_ML_data_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6616 #define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
<> 144:ef7eb2e8f9f7 6617
<> 144:ef7eb2e8f9f7 6618 /* The count of FMC_DATA_ML */
<> 144:ef7eb2e8f9f7 6619 #define FMC_DATA_ML_COUNT (4U)
<> 144:ef7eb2e8f9f7 6620
<> 144:ef7eb2e8f9f7 6621 /* The count of FMC_DATA_ML */
<> 144:ef7eb2e8f9f7 6622 #define FMC_DATA_ML_COUNT2 (4U)
<> 144:ef7eb2e8f9f7 6623
<> 144:ef7eb2e8f9f7 6624 /*! @name DATA_LM - Cache Data Storage (lowermost word) */
<> 144:ef7eb2e8f9f7 6625 #define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 6626 #define FMC_DATA_LM_data_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6627 #define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
<> 144:ef7eb2e8f9f7 6628
<> 144:ef7eb2e8f9f7 6629 /* The count of FMC_DATA_LM */
<> 144:ef7eb2e8f9f7 6630 #define FMC_DATA_LM_COUNT (4U)
<> 144:ef7eb2e8f9f7 6631
<> 144:ef7eb2e8f9f7 6632 /* The count of FMC_DATA_LM */
<> 144:ef7eb2e8f9f7 6633 #define FMC_DATA_LM_COUNT2 (4U)
<> 144:ef7eb2e8f9f7 6634
<> 144:ef7eb2e8f9f7 6635
<> 144:ef7eb2e8f9f7 6636 /*!
<> 144:ef7eb2e8f9f7 6637 * @}
<> 144:ef7eb2e8f9f7 6638 */ /* end of group FMC_Register_Masks */
<> 144:ef7eb2e8f9f7 6639
<> 144:ef7eb2e8f9f7 6640
<> 144:ef7eb2e8f9f7 6641 /* FMC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6642 /** Peripheral FMC base address */
<> 144:ef7eb2e8f9f7 6643 #define FMC_BASE (0x4001F000u)
<> 144:ef7eb2e8f9f7 6644 /** Peripheral FMC base pointer */
<> 144:ef7eb2e8f9f7 6645 #define FMC ((FMC_Type *)FMC_BASE)
<> 144:ef7eb2e8f9f7 6646 /** Array initializer of FMC peripheral base addresses */
<> 144:ef7eb2e8f9f7 6647 #define FMC_BASE_ADDRS { FMC_BASE }
<> 144:ef7eb2e8f9f7 6648 /** Array initializer of FMC peripheral base pointers */
<> 144:ef7eb2e8f9f7 6649 #define FMC_BASE_PTRS { FMC }
<> 144:ef7eb2e8f9f7 6650
<> 144:ef7eb2e8f9f7 6651 /*!
<> 144:ef7eb2e8f9f7 6652 * @}
<> 144:ef7eb2e8f9f7 6653 */ /* end of group FMC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6654
<> 144:ef7eb2e8f9f7 6655
<> 144:ef7eb2e8f9f7 6656 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6657 -- FTFE Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6658 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6659
<> 144:ef7eb2e8f9f7 6660 /*!
<> 144:ef7eb2e8f9f7 6661 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6662 * @{
<> 144:ef7eb2e8f9f7 6663 */
<> 144:ef7eb2e8f9f7 6664
<> 144:ef7eb2e8f9f7 6665 /** FTFE - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6666 typedef struct {
<> 144:ef7eb2e8f9f7 6667 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6668 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 6669 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 6670 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 6671 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6672 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
<> 144:ef7eb2e8f9f7 6673 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
<> 144:ef7eb2e8f9f7 6674 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
<> 144:ef7eb2e8f9f7 6675 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
<> 144:ef7eb2e8f9f7 6676 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
<> 144:ef7eb2e8f9f7 6677 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
<> 144:ef7eb2e8f9f7 6678 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
<> 144:ef7eb2e8f9f7 6679 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
<> 144:ef7eb2e8f9f7 6680 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
<> 144:ef7eb2e8f9f7 6681 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
<> 144:ef7eb2e8f9f7 6682 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
<> 144:ef7eb2e8f9f7 6683 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
<> 144:ef7eb2e8f9f7 6684 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
<> 144:ef7eb2e8f9f7 6685 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
<> 144:ef7eb2e8f9f7 6686 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
<> 144:ef7eb2e8f9f7 6687 uint8_t RESERVED_0[2];
<> 144:ef7eb2e8f9f7 6688 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
<> 144:ef7eb2e8f9f7 6689 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
<> 144:ef7eb2e8f9f7 6690 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
<> 144:ef7eb2e8f9f7 6691 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
<> 144:ef7eb2e8f9f7 6692 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
<> 144:ef7eb2e8f9f7 6693 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
<> 144:ef7eb2e8f9f7 6694 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
<> 144:ef7eb2e8f9f7 6695 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
<> 144:ef7eb2e8f9f7 6696 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
<> 144:ef7eb2e8f9f7 6697 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
<> 144:ef7eb2e8f9f7 6698 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
<> 144:ef7eb2e8f9f7 6699 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
<> 144:ef7eb2e8f9f7 6700 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
<> 144:ef7eb2e8f9f7 6701 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
<> 144:ef7eb2e8f9f7 6702 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
<> 144:ef7eb2e8f9f7 6703 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
<> 144:ef7eb2e8f9f7 6704 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
<> 144:ef7eb2e8f9f7 6705 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
<> 144:ef7eb2e8f9f7 6706 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 6707 uint8_t RESERVED_1[2];
<> 144:ef7eb2e8f9f7 6708 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
<> 144:ef7eb2e8f9f7 6709 } FTFE_Type;
<> 144:ef7eb2e8f9f7 6710
<> 144:ef7eb2e8f9f7 6711 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6712 -- FTFE Register Masks
<> 144:ef7eb2e8f9f7 6713 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6714
<> 144:ef7eb2e8f9f7 6715 /*!
<> 144:ef7eb2e8f9f7 6716 * @addtogroup FTFE_Register_Masks FTFE Register Masks
<> 144:ef7eb2e8f9f7 6717 * @{
<> 144:ef7eb2e8f9f7 6718 */
<> 144:ef7eb2e8f9f7 6719
<> 144:ef7eb2e8f9f7 6720 /*! @name FSTAT - Flash Status Register */
<> 144:ef7eb2e8f9f7 6721 #define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6722 #define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6723 #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
<> 144:ef7eb2e8f9f7 6724 #define FTFE_FSTAT_FPVIOL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6725 #define FTFE_FSTAT_FPVIOL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6726 #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
<> 144:ef7eb2e8f9f7 6727 #define FTFE_FSTAT_ACCERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6728 #define FTFE_FSTAT_ACCERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6729 #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
<> 144:ef7eb2e8f9f7 6730 #define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6731 #define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6732 #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
<> 144:ef7eb2e8f9f7 6733 #define FTFE_FSTAT_CCIF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6734 #define FTFE_FSTAT_CCIF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6735 #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
<> 144:ef7eb2e8f9f7 6736
<> 144:ef7eb2e8f9f7 6737 /*! @name FCNFG - Flash Configuration Register */
<> 144:ef7eb2e8f9f7 6738 #define FTFE_FCNFG_EEERDY_MASK (0x1U)
<> 144:ef7eb2e8f9f7 6739 #define FTFE_FCNFG_EEERDY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6740 #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
<> 144:ef7eb2e8f9f7 6741 #define FTFE_FCNFG_RAMRDY_MASK (0x2U)
<> 144:ef7eb2e8f9f7 6742 #define FTFE_FCNFG_RAMRDY_SHIFT (1U)
<> 144:ef7eb2e8f9f7 6743 #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
<> 144:ef7eb2e8f9f7 6744 #define FTFE_FCNFG_PFLSH_MASK (0x4U)
<> 144:ef7eb2e8f9f7 6745 #define FTFE_FCNFG_PFLSH_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6746 #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
<> 144:ef7eb2e8f9f7 6747 #define FTFE_FCNFG_SWAP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 6748 #define FTFE_FCNFG_SWAP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 6749 #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
<> 144:ef7eb2e8f9f7 6750 #define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 6751 #define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6752 #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
<> 144:ef7eb2e8f9f7 6753 #define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
<> 144:ef7eb2e8f9f7 6754 #define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
<> 144:ef7eb2e8f9f7 6755 #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
<> 144:ef7eb2e8f9f7 6756 #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 6757 #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6758 #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
<> 144:ef7eb2e8f9f7 6759 #define FTFE_FCNFG_CCIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 6760 #define FTFE_FCNFG_CCIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 6761 #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
<> 144:ef7eb2e8f9f7 6762
<> 144:ef7eb2e8f9f7 6763 /*! @name FSEC - Flash Security Register */
<> 144:ef7eb2e8f9f7 6764 #define FTFE_FSEC_SEC_MASK (0x3U)
<> 144:ef7eb2e8f9f7 6765 #define FTFE_FSEC_SEC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6766 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
<> 144:ef7eb2e8f9f7 6767 #define FTFE_FSEC_FSLACC_MASK (0xCU)
<> 144:ef7eb2e8f9f7 6768 #define FTFE_FSEC_FSLACC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 6769 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
<> 144:ef7eb2e8f9f7 6770 #define FTFE_FSEC_MEEN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 6771 #define FTFE_FSEC_MEEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 6772 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
<> 144:ef7eb2e8f9f7 6773 #define FTFE_FSEC_KEYEN_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 6774 #define FTFE_FSEC_KEYEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 6775 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
<> 144:ef7eb2e8f9f7 6776
<> 144:ef7eb2e8f9f7 6777 /*! @name FOPT - Flash Option Register */
<> 144:ef7eb2e8f9f7 6778 #define FTFE_FOPT_OPT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6779 #define FTFE_FOPT_OPT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6780 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
<> 144:ef7eb2e8f9f7 6781
<> 144:ef7eb2e8f9f7 6782 /*! @name FCCOB3 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6783 #define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6784 #define FTFE_FCCOB3_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6785 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6786
<> 144:ef7eb2e8f9f7 6787 /*! @name FCCOB2 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6788 #define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6789 #define FTFE_FCCOB2_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6790 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6791
<> 144:ef7eb2e8f9f7 6792 /*! @name FCCOB1 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6793 #define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6794 #define FTFE_FCCOB1_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6795 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6796
<> 144:ef7eb2e8f9f7 6797 /*! @name FCCOB0 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6798 #define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6799 #define FTFE_FCCOB0_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6800 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6801
<> 144:ef7eb2e8f9f7 6802 /*! @name FCCOB7 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6803 #define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6804 #define FTFE_FCCOB7_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6805 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6806
<> 144:ef7eb2e8f9f7 6807 /*! @name FCCOB6 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6808 #define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6809 #define FTFE_FCCOB6_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6810 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6811
<> 144:ef7eb2e8f9f7 6812 /*! @name FCCOB5 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6813 #define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6814 #define FTFE_FCCOB5_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6815 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6816
<> 144:ef7eb2e8f9f7 6817 /*! @name FCCOB4 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6818 #define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6819 #define FTFE_FCCOB4_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6820 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6821
<> 144:ef7eb2e8f9f7 6822 /*! @name FCCOBB - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6823 #define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6824 #define FTFE_FCCOBB_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6825 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6826
<> 144:ef7eb2e8f9f7 6827 /*! @name FCCOBA - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6828 #define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6829 #define FTFE_FCCOBA_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6830 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6831
<> 144:ef7eb2e8f9f7 6832 /*! @name FCCOB9 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6833 #define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6834 #define FTFE_FCCOB9_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6835 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6836
<> 144:ef7eb2e8f9f7 6837 /*! @name FCCOB8 - Flash Common Command Object Registers */
<> 144:ef7eb2e8f9f7 6838 #define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6839 #define FTFE_FCCOB8_CCOBn_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6840 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
<> 144:ef7eb2e8f9f7 6841
<> 144:ef7eb2e8f9f7 6842 /*! @name FPROT3 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 6843 #define FTFE_FPROT3_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6844 #define FTFE_FPROT3_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6845 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
<> 144:ef7eb2e8f9f7 6846
<> 144:ef7eb2e8f9f7 6847 /*! @name FPROT2 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 6848 #define FTFE_FPROT2_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6849 #define FTFE_FPROT2_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6850 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
<> 144:ef7eb2e8f9f7 6851
<> 144:ef7eb2e8f9f7 6852 /*! @name FPROT1 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 6853 #define FTFE_FPROT1_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6854 #define FTFE_FPROT1_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6855 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
<> 144:ef7eb2e8f9f7 6856
<> 144:ef7eb2e8f9f7 6857 /*! @name FPROT0 - Program Flash Protection Registers */
<> 144:ef7eb2e8f9f7 6858 #define FTFE_FPROT0_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6859 #define FTFE_FPROT0_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6860 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
<> 144:ef7eb2e8f9f7 6861
<> 144:ef7eb2e8f9f7 6862 /*! @name FEPROT - EEPROM Protection Register */
<> 144:ef7eb2e8f9f7 6863 #define FTFE_FEPROT_EPROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6864 #define FTFE_FEPROT_EPROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6865 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
<> 144:ef7eb2e8f9f7 6866
<> 144:ef7eb2e8f9f7 6867 /*! @name FDPROT - Data Flash Protection Register */
<> 144:ef7eb2e8f9f7 6868 #define FTFE_FDPROT_DPROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6869 #define FTFE_FDPROT_DPROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6870 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
<> 144:ef7eb2e8f9f7 6871
<> 144:ef7eb2e8f9f7 6872 /*! @name XACCH3 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6873 #define FTFE_XACCH3_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6874 #define FTFE_XACCH3_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6875 #define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
<> 144:ef7eb2e8f9f7 6876
<> 144:ef7eb2e8f9f7 6877 /*! @name XACCH2 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6878 #define FTFE_XACCH2_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6879 #define FTFE_XACCH2_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6880 #define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
<> 144:ef7eb2e8f9f7 6881
<> 144:ef7eb2e8f9f7 6882 /*! @name XACCH1 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6883 #define FTFE_XACCH1_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6884 #define FTFE_XACCH1_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6885 #define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
<> 144:ef7eb2e8f9f7 6886
<> 144:ef7eb2e8f9f7 6887 /*! @name XACCH0 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6888 #define FTFE_XACCH0_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6889 #define FTFE_XACCH0_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6890 #define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
<> 144:ef7eb2e8f9f7 6891
<> 144:ef7eb2e8f9f7 6892 /*! @name XACCL3 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6893 #define FTFE_XACCL3_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6894 #define FTFE_XACCL3_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6895 #define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
<> 144:ef7eb2e8f9f7 6896
<> 144:ef7eb2e8f9f7 6897 /*! @name XACCL2 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6898 #define FTFE_XACCL2_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6899 #define FTFE_XACCL2_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6900 #define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
<> 144:ef7eb2e8f9f7 6901
<> 144:ef7eb2e8f9f7 6902 /*! @name XACCL1 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6903 #define FTFE_XACCL1_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6904 #define FTFE_XACCL1_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6905 #define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
<> 144:ef7eb2e8f9f7 6906
<> 144:ef7eb2e8f9f7 6907 /*! @name XACCL0 - Execute-only Access Registers */
<> 144:ef7eb2e8f9f7 6908 #define FTFE_XACCL0_XA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6909 #define FTFE_XACCL0_XA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6910 #define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
<> 144:ef7eb2e8f9f7 6911
<> 144:ef7eb2e8f9f7 6912 /*! @name SACCH3 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6913 #define FTFE_SACCH3_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6914 #define FTFE_SACCH3_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6915 #define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
<> 144:ef7eb2e8f9f7 6916
<> 144:ef7eb2e8f9f7 6917 /*! @name SACCH2 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6918 #define FTFE_SACCH2_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6919 #define FTFE_SACCH2_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6920 #define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
<> 144:ef7eb2e8f9f7 6921
<> 144:ef7eb2e8f9f7 6922 /*! @name SACCH1 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6923 #define FTFE_SACCH1_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6924 #define FTFE_SACCH1_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6925 #define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
<> 144:ef7eb2e8f9f7 6926
<> 144:ef7eb2e8f9f7 6927 /*! @name SACCH0 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6928 #define FTFE_SACCH0_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6929 #define FTFE_SACCH0_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6930 #define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
<> 144:ef7eb2e8f9f7 6931
<> 144:ef7eb2e8f9f7 6932 /*! @name SACCL3 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6933 #define FTFE_SACCL3_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6934 #define FTFE_SACCL3_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6935 #define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
<> 144:ef7eb2e8f9f7 6936
<> 144:ef7eb2e8f9f7 6937 /*! @name SACCL2 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6938 #define FTFE_SACCL2_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6939 #define FTFE_SACCL2_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6940 #define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
<> 144:ef7eb2e8f9f7 6941
<> 144:ef7eb2e8f9f7 6942 /*! @name SACCL1 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6943 #define FTFE_SACCL1_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6944 #define FTFE_SACCL1_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6945 #define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
<> 144:ef7eb2e8f9f7 6946
<> 144:ef7eb2e8f9f7 6947 /*! @name SACCL0 - Supervisor-only Access Registers */
<> 144:ef7eb2e8f9f7 6948 #define FTFE_SACCL0_SA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6949 #define FTFE_SACCL0_SA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6950 #define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
<> 144:ef7eb2e8f9f7 6951
<> 144:ef7eb2e8f9f7 6952 /*! @name FACSS - Flash Access Segment Size Register */
<> 144:ef7eb2e8f9f7 6953 #define FTFE_FACSS_SGSIZE_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6954 #define FTFE_FACSS_SGSIZE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6955 #define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
<> 144:ef7eb2e8f9f7 6956
<> 144:ef7eb2e8f9f7 6957 /*! @name FACSN - Flash Access Segment Number Register */
<> 144:ef7eb2e8f9f7 6958 #define FTFE_FACSN_NUMSG_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 6959 #define FTFE_FACSN_NUMSG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 6960 #define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
<> 144:ef7eb2e8f9f7 6961
<> 144:ef7eb2e8f9f7 6962
<> 144:ef7eb2e8f9f7 6963 /*!
<> 144:ef7eb2e8f9f7 6964 * @}
<> 144:ef7eb2e8f9f7 6965 */ /* end of group FTFE_Register_Masks */
<> 144:ef7eb2e8f9f7 6966
<> 144:ef7eb2e8f9f7 6967
<> 144:ef7eb2e8f9f7 6968 /* FTFE - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 6969 /** Peripheral FTFE base address */
<> 144:ef7eb2e8f9f7 6970 #define FTFE_BASE (0x40020000u)
<> 144:ef7eb2e8f9f7 6971 /** Peripheral FTFE base pointer */
<> 144:ef7eb2e8f9f7 6972 #define FTFE ((FTFE_Type *)FTFE_BASE)
<> 144:ef7eb2e8f9f7 6973 /** Array initializer of FTFE peripheral base addresses */
<> 144:ef7eb2e8f9f7 6974 #define FTFE_BASE_ADDRS { FTFE_BASE }
<> 144:ef7eb2e8f9f7 6975 /** Array initializer of FTFE peripheral base pointers */
<> 144:ef7eb2e8f9f7 6976 #define FTFE_BASE_PTRS { FTFE }
<> 144:ef7eb2e8f9f7 6977 /** Interrupt vectors for the FTFE peripheral type */
<> 144:ef7eb2e8f9f7 6978 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
<> 144:ef7eb2e8f9f7 6979 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
<> 144:ef7eb2e8f9f7 6980
<> 144:ef7eb2e8f9f7 6981 /*!
<> 144:ef7eb2e8f9f7 6982 * @}
<> 144:ef7eb2e8f9f7 6983 */ /* end of group FTFE_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 6984
<> 144:ef7eb2e8f9f7 6985
<> 144:ef7eb2e8f9f7 6986 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6987 -- FTM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6988 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 6989
<> 144:ef7eb2e8f9f7 6990 /*!
<> 144:ef7eb2e8f9f7 6991 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 6992 * @{
<> 144:ef7eb2e8f9f7 6993 */
<> 144:ef7eb2e8f9f7 6994
<> 144:ef7eb2e8f9f7 6995 /** FTM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 6996 typedef struct {
<> 144:ef7eb2e8f9f7 6997 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
<> 144:ef7eb2e8f9f7 6998 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
<> 144:ef7eb2e8f9f7 6999 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
<> 144:ef7eb2e8f9f7 7000 struct { /* offset: 0xC, array step: 0x8 */
<> 144:ef7eb2e8f9f7 7001 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
<> 144:ef7eb2e8f9f7 7002 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
<> 144:ef7eb2e8f9f7 7003 } CONTROLS[8];
<> 144:ef7eb2e8f9f7 7004 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
<> 144:ef7eb2e8f9f7 7005 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
<> 144:ef7eb2e8f9f7 7006 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
<> 144:ef7eb2e8f9f7 7007 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
<> 144:ef7eb2e8f9f7 7008 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
<> 144:ef7eb2e8f9f7 7009 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
<> 144:ef7eb2e8f9f7 7010 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
<> 144:ef7eb2e8f9f7 7011 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
<> 144:ef7eb2e8f9f7 7012 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
<> 144:ef7eb2e8f9f7 7013 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
<> 144:ef7eb2e8f9f7 7014 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
<> 144:ef7eb2e8f9f7 7015 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
<> 144:ef7eb2e8f9f7 7016 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
<> 144:ef7eb2e8f9f7 7017 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
<> 144:ef7eb2e8f9f7 7018 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
<> 144:ef7eb2e8f9f7 7019 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
<> 144:ef7eb2e8f9f7 7020 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
<> 144:ef7eb2e8f9f7 7021 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
<> 144:ef7eb2e8f9f7 7022 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
<> 144:ef7eb2e8f9f7 7023 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
<> 144:ef7eb2e8f9f7 7024 } FTM_Type;
<> 144:ef7eb2e8f9f7 7025
<> 144:ef7eb2e8f9f7 7026 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7027 -- FTM Register Masks
<> 144:ef7eb2e8f9f7 7028 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7029
<> 144:ef7eb2e8f9f7 7030 /*!
<> 144:ef7eb2e8f9f7 7031 * @addtogroup FTM_Register_Masks FTM Register Masks
<> 144:ef7eb2e8f9f7 7032 * @{
<> 144:ef7eb2e8f9f7 7033 */
<> 144:ef7eb2e8f9f7 7034
<> 144:ef7eb2e8f9f7 7035 /*! @name SC - Status And Control */
<> 144:ef7eb2e8f9f7 7036 #define FTM_SC_PS_MASK (0x7U)
<> 144:ef7eb2e8f9f7 7037 #define FTM_SC_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7038 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
<> 144:ef7eb2e8f9f7 7039 #define FTM_SC_CLKS_MASK (0x18U)
<> 144:ef7eb2e8f9f7 7040 #define FTM_SC_CLKS_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7041 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
<> 144:ef7eb2e8f9f7 7042 #define FTM_SC_CPWMS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7043 #define FTM_SC_CPWMS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7044 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
<> 144:ef7eb2e8f9f7 7045 #define FTM_SC_TOIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7046 #define FTM_SC_TOIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7047 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
<> 144:ef7eb2e8f9f7 7048 #define FTM_SC_TOF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7049 #define FTM_SC_TOF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7050 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
<> 144:ef7eb2e8f9f7 7051
<> 144:ef7eb2e8f9f7 7052 /*! @name CNT - Counter */
<> 144:ef7eb2e8f9f7 7053 #define FTM_CNT_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 7054 #define FTM_CNT_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7055 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
<> 144:ef7eb2e8f9f7 7056
<> 144:ef7eb2e8f9f7 7057 /*! @name MOD - Modulo */
<> 144:ef7eb2e8f9f7 7058 #define FTM_MOD_MOD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 7059 #define FTM_MOD_MOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7060 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
<> 144:ef7eb2e8f9f7 7061
<> 144:ef7eb2e8f9f7 7062 /*! @name CnSC - Channel (n) Status And Control */
<> 144:ef7eb2e8f9f7 7063 #define FTM_CnSC_DMA_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7064 #define FTM_CnSC_DMA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7065 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
<> 144:ef7eb2e8f9f7 7066 #define FTM_CnSC_ELSA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7067 #define FTM_CnSC_ELSA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7068 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
<> 144:ef7eb2e8f9f7 7069 #define FTM_CnSC_ELSB_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7070 #define FTM_CnSC_ELSB_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7071 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
<> 144:ef7eb2e8f9f7 7072 #define FTM_CnSC_MSA_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7073 #define FTM_CnSC_MSA_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7074 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
<> 144:ef7eb2e8f9f7 7075 #define FTM_CnSC_MSB_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7076 #define FTM_CnSC_MSB_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7077 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
<> 144:ef7eb2e8f9f7 7078 #define FTM_CnSC_CHIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7079 #define FTM_CnSC_CHIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7080 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
<> 144:ef7eb2e8f9f7 7081 #define FTM_CnSC_CHF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7082 #define FTM_CnSC_CHF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7083 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
<> 144:ef7eb2e8f9f7 7084
<> 144:ef7eb2e8f9f7 7085 /* The count of FTM_CnSC */
<> 144:ef7eb2e8f9f7 7086 #define FTM_CnSC_COUNT (8U)
<> 144:ef7eb2e8f9f7 7087
<> 144:ef7eb2e8f9f7 7088 /*! @name CnV - Channel (n) Value */
<> 144:ef7eb2e8f9f7 7089 #define FTM_CnV_VAL_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 7090 #define FTM_CnV_VAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7091 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
<> 144:ef7eb2e8f9f7 7092
<> 144:ef7eb2e8f9f7 7093 /* The count of FTM_CnV */
<> 144:ef7eb2e8f9f7 7094 #define FTM_CnV_COUNT (8U)
<> 144:ef7eb2e8f9f7 7095
<> 144:ef7eb2e8f9f7 7096 /*! @name CNTIN - Counter Initial Value */
<> 144:ef7eb2e8f9f7 7097 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 7098 #define FTM_CNTIN_INIT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7099 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
<> 144:ef7eb2e8f9f7 7100
<> 144:ef7eb2e8f9f7 7101 /*! @name STATUS - Capture And Compare Status */
<> 144:ef7eb2e8f9f7 7102 #define FTM_STATUS_CH0F_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7103 #define FTM_STATUS_CH0F_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7104 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
<> 144:ef7eb2e8f9f7 7105 #define FTM_STATUS_CH1F_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7106 #define FTM_STATUS_CH1F_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7107 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
<> 144:ef7eb2e8f9f7 7108 #define FTM_STATUS_CH2F_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7109 #define FTM_STATUS_CH2F_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7110 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
<> 144:ef7eb2e8f9f7 7111 #define FTM_STATUS_CH3F_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7112 #define FTM_STATUS_CH3F_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7113 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
<> 144:ef7eb2e8f9f7 7114 #define FTM_STATUS_CH4F_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7115 #define FTM_STATUS_CH4F_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7116 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
<> 144:ef7eb2e8f9f7 7117 #define FTM_STATUS_CH5F_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7118 #define FTM_STATUS_CH5F_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7119 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
<> 144:ef7eb2e8f9f7 7120 #define FTM_STATUS_CH6F_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7121 #define FTM_STATUS_CH6F_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7122 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
<> 144:ef7eb2e8f9f7 7123 #define FTM_STATUS_CH7F_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7124 #define FTM_STATUS_CH7F_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7125 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
<> 144:ef7eb2e8f9f7 7126
<> 144:ef7eb2e8f9f7 7127 /*! @name MODE - Features Mode Selection */
<> 144:ef7eb2e8f9f7 7128 #define FTM_MODE_FTMEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7129 #define FTM_MODE_FTMEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7130 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
<> 144:ef7eb2e8f9f7 7131 #define FTM_MODE_INIT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7132 #define FTM_MODE_INIT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7133 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
<> 144:ef7eb2e8f9f7 7134 #define FTM_MODE_WPDIS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7135 #define FTM_MODE_WPDIS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7136 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
<> 144:ef7eb2e8f9f7 7137 #define FTM_MODE_PWMSYNC_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7138 #define FTM_MODE_PWMSYNC_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7139 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
<> 144:ef7eb2e8f9f7 7140 #define FTM_MODE_CAPTEST_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7141 #define FTM_MODE_CAPTEST_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7142 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
<> 144:ef7eb2e8f9f7 7143 #define FTM_MODE_FAULTM_MASK (0x60U)
<> 144:ef7eb2e8f9f7 7144 #define FTM_MODE_FAULTM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7145 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
<> 144:ef7eb2e8f9f7 7146 #define FTM_MODE_FAULTIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7147 #define FTM_MODE_FAULTIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7148 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
<> 144:ef7eb2e8f9f7 7149
<> 144:ef7eb2e8f9f7 7150 /*! @name SYNC - Synchronization */
<> 144:ef7eb2e8f9f7 7151 #define FTM_SYNC_CNTMIN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7152 #define FTM_SYNC_CNTMIN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7153 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
<> 144:ef7eb2e8f9f7 7154 #define FTM_SYNC_CNTMAX_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7155 #define FTM_SYNC_CNTMAX_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7156 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
<> 144:ef7eb2e8f9f7 7157 #define FTM_SYNC_REINIT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7158 #define FTM_SYNC_REINIT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7159 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
<> 144:ef7eb2e8f9f7 7160 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7161 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7162 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
<> 144:ef7eb2e8f9f7 7163 #define FTM_SYNC_TRIG0_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7164 #define FTM_SYNC_TRIG0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7165 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
<> 144:ef7eb2e8f9f7 7166 #define FTM_SYNC_TRIG1_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7167 #define FTM_SYNC_TRIG1_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7168 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
<> 144:ef7eb2e8f9f7 7169 #define FTM_SYNC_TRIG2_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7170 #define FTM_SYNC_TRIG2_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7171 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
<> 144:ef7eb2e8f9f7 7172 #define FTM_SYNC_SWSYNC_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7173 #define FTM_SYNC_SWSYNC_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7174 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
<> 144:ef7eb2e8f9f7 7175
<> 144:ef7eb2e8f9f7 7176 /*! @name OUTINIT - Initial State For Channels Output */
<> 144:ef7eb2e8f9f7 7177 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7178 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7179 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
<> 144:ef7eb2e8f9f7 7180 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7181 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7182 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
<> 144:ef7eb2e8f9f7 7183 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7184 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7185 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
<> 144:ef7eb2e8f9f7 7186 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7187 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7188 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
<> 144:ef7eb2e8f9f7 7189 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7190 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7191 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
<> 144:ef7eb2e8f9f7 7192 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7193 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7194 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
<> 144:ef7eb2e8f9f7 7195 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7196 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7197 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
<> 144:ef7eb2e8f9f7 7198 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7199 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7200 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
<> 144:ef7eb2e8f9f7 7201
<> 144:ef7eb2e8f9f7 7202 /*! @name OUTMASK - Output Mask */
<> 144:ef7eb2e8f9f7 7203 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7204 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7205 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
<> 144:ef7eb2e8f9f7 7206 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7207 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7208 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
<> 144:ef7eb2e8f9f7 7209 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7210 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7211 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
<> 144:ef7eb2e8f9f7 7212 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7213 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7214 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
<> 144:ef7eb2e8f9f7 7215 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7216 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7217 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
<> 144:ef7eb2e8f9f7 7218 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7219 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7220 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
<> 144:ef7eb2e8f9f7 7221 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7222 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7223 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
<> 144:ef7eb2e8f9f7 7224 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7225 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7226 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
<> 144:ef7eb2e8f9f7 7227
<> 144:ef7eb2e8f9f7 7228 /*! @name COMBINE - Function For Linked Channels */
<> 144:ef7eb2e8f9f7 7229 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7230 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7231 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
<> 144:ef7eb2e8f9f7 7232 #define FTM_COMBINE_COMP0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7233 #define FTM_COMBINE_COMP0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7234 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
<> 144:ef7eb2e8f9f7 7235 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7236 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7237 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
<> 144:ef7eb2e8f9f7 7238 #define FTM_COMBINE_DECAP0_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7239 #define FTM_COMBINE_DECAP0_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7240 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
<> 144:ef7eb2e8f9f7 7241 #define FTM_COMBINE_DTEN0_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7242 #define FTM_COMBINE_DTEN0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7243 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
<> 144:ef7eb2e8f9f7 7244 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7245 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7246 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
<> 144:ef7eb2e8f9f7 7247 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7248 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7249 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
<> 144:ef7eb2e8f9f7 7250 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
<> 144:ef7eb2e8f9f7 7251 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7252 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
<> 144:ef7eb2e8f9f7 7253 #define FTM_COMBINE_COMP1_MASK (0x200U)
<> 144:ef7eb2e8f9f7 7254 #define FTM_COMBINE_COMP1_SHIFT (9U)
<> 144:ef7eb2e8f9f7 7255 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
<> 144:ef7eb2e8f9f7 7256 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
<> 144:ef7eb2e8f9f7 7257 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
<> 144:ef7eb2e8f9f7 7258 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
<> 144:ef7eb2e8f9f7 7259 #define FTM_COMBINE_DECAP1_MASK (0x800U)
<> 144:ef7eb2e8f9f7 7260 #define FTM_COMBINE_DECAP1_SHIFT (11U)
<> 144:ef7eb2e8f9f7 7261 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
<> 144:ef7eb2e8f9f7 7262 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 7263 #define FTM_COMBINE_DTEN1_SHIFT (12U)
<> 144:ef7eb2e8f9f7 7264 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
<> 144:ef7eb2e8f9f7 7265 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 7266 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
<> 144:ef7eb2e8f9f7 7267 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
<> 144:ef7eb2e8f9f7 7268 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 7269 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
<> 144:ef7eb2e8f9f7 7270 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
<> 144:ef7eb2e8f9f7 7271 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 7272 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
<> 144:ef7eb2e8f9f7 7273 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
<> 144:ef7eb2e8f9f7 7274 #define FTM_COMBINE_COMP2_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 7275 #define FTM_COMBINE_COMP2_SHIFT (17U)
<> 144:ef7eb2e8f9f7 7276 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
<> 144:ef7eb2e8f9f7 7277 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 7278 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
<> 144:ef7eb2e8f9f7 7279 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
<> 144:ef7eb2e8f9f7 7280 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 7281 #define FTM_COMBINE_DECAP2_SHIFT (19U)
<> 144:ef7eb2e8f9f7 7282 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
<> 144:ef7eb2e8f9f7 7283 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 7284 #define FTM_COMBINE_DTEN2_SHIFT (20U)
<> 144:ef7eb2e8f9f7 7285 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
<> 144:ef7eb2e8f9f7 7286 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 7287 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
<> 144:ef7eb2e8f9f7 7288 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
<> 144:ef7eb2e8f9f7 7289 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 7290 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
<> 144:ef7eb2e8f9f7 7291 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
<> 144:ef7eb2e8f9f7 7292 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 7293 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
<> 144:ef7eb2e8f9f7 7294 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
<> 144:ef7eb2e8f9f7 7295 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 7296 #define FTM_COMBINE_COMP3_SHIFT (25U)
<> 144:ef7eb2e8f9f7 7297 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
<> 144:ef7eb2e8f9f7 7298 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 7299 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
<> 144:ef7eb2e8f9f7 7300 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
<> 144:ef7eb2e8f9f7 7301 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 7302 #define FTM_COMBINE_DECAP3_SHIFT (27U)
<> 144:ef7eb2e8f9f7 7303 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
<> 144:ef7eb2e8f9f7 7304 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 7305 #define FTM_COMBINE_DTEN3_SHIFT (28U)
<> 144:ef7eb2e8f9f7 7306 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
<> 144:ef7eb2e8f9f7 7307 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 7308 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
<> 144:ef7eb2e8f9f7 7309 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
<> 144:ef7eb2e8f9f7 7310 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 7311 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
<> 144:ef7eb2e8f9f7 7312 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
<> 144:ef7eb2e8f9f7 7313
<> 144:ef7eb2e8f9f7 7314 /*! @name DEADTIME - Deadtime Insertion Control */
<> 144:ef7eb2e8f9f7 7315 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 7316 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7317 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
<> 144:ef7eb2e8f9f7 7318 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 7319 #define FTM_DEADTIME_DTPS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7320 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
<> 144:ef7eb2e8f9f7 7321
<> 144:ef7eb2e8f9f7 7322 /*! @name EXTTRIG - FTM External Trigger */
<> 144:ef7eb2e8f9f7 7323 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7324 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7325 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
<> 144:ef7eb2e8f9f7 7326 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7327 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7328 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
<> 144:ef7eb2e8f9f7 7329 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7330 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7331 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
<> 144:ef7eb2e8f9f7 7332 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7333 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7334 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
<> 144:ef7eb2e8f9f7 7335 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7336 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7337 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
<> 144:ef7eb2e8f9f7 7338 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7339 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7340 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
<> 144:ef7eb2e8f9f7 7341 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7342 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7343 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
<> 144:ef7eb2e8f9f7 7344 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7345 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7346 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
<> 144:ef7eb2e8f9f7 7347
<> 144:ef7eb2e8f9f7 7348 /*! @name POL - Channels Polarity */
<> 144:ef7eb2e8f9f7 7349 #define FTM_POL_POL0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7350 #define FTM_POL_POL0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7351 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
<> 144:ef7eb2e8f9f7 7352 #define FTM_POL_POL1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7353 #define FTM_POL_POL1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7354 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
<> 144:ef7eb2e8f9f7 7355 #define FTM_POL_POL2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7356 #define FTM_POL_POL2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7357 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
<> 144:ef7eb2e8f9f7 7358 #define FTM_POL_POL3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7359 #define FTM_POL_POL3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7360 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
<> 144:ef7eb2e8f9f7 7361 #define FTM_POL_POL4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7362 #define FTM_POL_POL4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7363 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
<> 144:ef7eb2e8f9f7 7364 #define FTM_POL_POL5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7365 #define FTM_POL_POL5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7366 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
<> 144:ef7eb2e8f9f7 7367 #define FTM_POL_POL6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7368 #define FTM_POL_POL6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7369 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
<> 144:ef7eb2e8f9f7 7370 #define FTM_POL_POL7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7371 #define FTM_POL_POL7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7372 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
<> 144:ef7eb2e8f9f7 7373
<> 144:ef7eb2e8f9f7 7374 /*! @name FMS - Fault Mode Status */
<> 144:ef7eb2e8f9f7 7375 #define FTM_FMS_FAULTF0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7376 #define FTM_FMS_FAULTF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7377 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
<> 144:ef7eb2e8f9f7 7378 #define FTM_FMS_FAULTF1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7379 #define FTM_FMS_FAULTF1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7380 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
<> 144:ef7eb2e8f9f7 7381 #define FTM_FMS_FAULTF2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7382 #define FTM_FMS_FAULTF2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7383 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
<> 144:ef7eb2e8f9f7 7384 #define FTM_FMS_FAULTF3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7385 #define FTM_FMS_FAULTF3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7386 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
<> 144:ef7eb2e8f9f7 7387 #define FTM_FMS_FAULTIN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7388 #define FTM_FMS_FAULTIN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7389 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
<> 144:ef7eb2e8f9f7 7390 #define FTM_FMS_WPEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7391 #define FTM_FMS_WPEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7392 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
<> 144:ef7eb2e8f9f7 7393 #define FTM_FMS_FAULTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7394 #define FTM_FMS_FAULTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7395 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
<> 144:ef7eb2e8f9f7 7396
<> 144:ef7eb2e8f9f7 7397 /*! @name FILTER - Input Capture Filter Control */
<> 144:ef7eb2e8f9f7 7398 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 7399 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7400 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
<> 144:ef7eb2e8f9f7 7401 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 7402 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7403 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
<> 144:ef7eb2e8f9f7 7404 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 7405 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7406 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
<> 144:ef7eb2e8f9f7 7407 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 7408 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
<> 144:ef7eb2e8f9f7 7409 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
<> 144:ef7eb2e8f9f7 7410
<> 144:ef7eb2e8f9f7 7411 /*! @name FLTCTRL - Fault Control */
<> 144:ef7eb2e8f9f7 7412 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7413 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7414 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
<> 144:ef7eb2e8f9f7 7415 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7416 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7417 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
<> 144:ef7eb2e8f9f7 7418 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7419 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7420 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
<> 144:ef7eb2e8f9f7 7421 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7422 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7423 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
<> 144:ef7eb2e8f9f7 7424 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7425 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7426 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
<> 144:ef7eb2e8f9f7 7427 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7428 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7429 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
<> 144:ef7eb2e8f9f7 7430 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7431 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7432 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
<> 144:ef7eb2e8f9f7 7433 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7434 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7435 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
<> 144:ef7eb2e8f9f7 7436 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 7437 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7438 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
<> 144:ef7eb2e8f9f7 7439
<> 144:ef7eb2e8f9f7 7440 /*! @name QDCTRL - Quadrature Decoder Control And Status */
<> 144:ef7eb2e8f9f7 7441 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7442 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7443 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
<> 144:ef7eb2e8f9f7 7444 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7445 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7446 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
<> 144:ef7eb2e8f9f7 7447 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7448 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7449 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
<> 144:ef7eb2e8f9f7 7450 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7451 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7452 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
<> 144:ef7eb2e8f9f7 7453 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7454 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7455 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
<> 144:ef7eb2e8f9f7 7456 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7457 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7458 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
<> 144:ef7eb2e8f9f7 7459 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7460 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7461 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
<> 144:ef7eb2e8f9f7 7462 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7463 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7464 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
<> 144:ef7eb2e8f9f7 7465
<> 144:ef7eb2e8f9f7 7466 /*! @name CONF - Configuration */
<> 144:ef7eb2e8f9f7 7467 #define FTM_CONF_NUMTOF_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 7468 #define FTM_CONF_NUMTOF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7469 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
<> 144:ef7eb2e8f9f7 7470 #define FTM_CONF_BDMMODE_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 7471 #define FTM_CONF_BDMMODE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7472 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
<> 144:ef7eb2e8f9f7 7473 #define FTM_CONF_GTBEEN_MASK (0x200U)
<> 144:ef7eb2e8f9f7 7474 #define FTM_CONF_GTBEEN_SHIFT (9U)
<> 144:ef7eb2e8f9f7 7475 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
<> 144:ef7eb2e8f9f7 7476 #define FTM_CONF_GTBEOUT_MASK (0x400U)
<> 144:ef7eb2e8f9f7 7477 #define FTM_CONF_GTBEOUT_SHIFT (10U)
<> 144:ef7eb2e8f9f7 7478 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
<> 144:ef7eb2e8f9f7 7479
<> 144:ef7eb2e8f9f7 7480 /*! @name FLTPOL - FTM Fault Input Polarity */
<> 144:ef7eb2e8f9f7 7481 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7482 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7483 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
<> 144:ef7eb2e8f9f7 7484 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7485 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7486 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
<> 144:ef7eb2e8f9f7 7487 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7488 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7489 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
<> 144:ef7eb2e8f9f7 7490 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7491 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7492 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
<> 144:ef7eb2e8f9f7 7493
<> 144:ef7eb2e8f9f7 7494 /*! @name SYNCONF - Synchronization Configuration */
<> 144:ef7eb2e8f9f7 7495 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7496 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7497 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
<> 144:ef7eb2e8f9f7 7498 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7499 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7500 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
<> 144:ef7eb2e8f9f7 7501 #define FTM_SYNCONF_INVC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7502 #define FTM_SYNCONF_INVC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7503 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
<> 144:ef7eb2e8f9f7 7504 #define FTM_SYNCONF_SWOC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7505 #define FTM_SYNCONF_SWOC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7506 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
<> 144:ef7eb2e8f9f7 7507 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7508 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7509 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
<> 144:ef7eb2e8f9f7 7510 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
<> 144:ef7eb2e8f9f7 7511 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7512 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
<> 144:ef7eb2e8f9f7 7513 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
<> 144:ef7eb2e8f9f7 7514 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
<> 144:ef7eb2e8f9f7 7515 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
<> 144:ef7eb2e8f9f7 7516 #define FTM_SYNCONF_SWOM_MASK (0x400U)
<> 144:ef7eb2e8f9f7 7517 #define FTM_SYNCONF_SWOM_SHIFT (10U)
<> 144:ef7eb2e8f9f7 7518 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
<> 144:ef7eb2e8f9f7 7519 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
<> 144:ef7eb2e8f9f7 7520 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
<> 144:ef7eb2e8f9f7 7521 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
<> 144:ef7eb2e8f9f7 7522 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 7523 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
<> 144:ef7eb2e8f9f7 7524 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
<> 144:ef7eb2e8f9f7 7525 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 7526 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 7527 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
<> 144:ef7eb2e8f9f7 7528 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 7529 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
<> 144:ef7eb2e8f9f7 7530 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
<> 144:ef7eb2e8f9f7 7531 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 7532 #define FTM_SYNCONF_HWOM_SHIFT (18U)
<> 144:ef7eb2e8f9f7 7533 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
<> 144:ef7eb2e8f9f7 7534 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 7535 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
<> 144:ef7eb2e8f9f7 7536 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
<> 144:ef7eb2e8f9f7 7537 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 7538 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 7539 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
<> 144:ef7eb2e8f9f7 7540
<> 144:ef7eb2e8f9f7 7541 /*! @name INVCTRL - FTM Inverting Control */
<> 144:ef7eb2e8f9f7 7542 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7543 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7544 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
<> 144:ef7eb2e8f9f7 7545 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7546 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7547 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
<> 144:ef7eb2e8f9f7 7548 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7549 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7550 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
<> 144:ef7eb2e8f9f7 7551 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7552 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7553 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
<> 144:ef7eb2e8f9f7 7554
<> 144:ef7eb2e8f9f7 7555 /*! @name SWOCTRL - FTM Software Output Control */
<> 144:ef7eb2e8f9f7 7556 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7557 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7558 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
<> 144:ef7eb2e8f9f7 7559 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7560 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7561 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
<> 144:ef7eb2e8f9f7 7562 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7563 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7564 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
<> 144:ef7eb2e8f9f7 7565 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7566 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7567 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
<> 144:ef7eb2e8f9f7 7568 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7569 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7570 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
<> 144:ef7eb2e8f9f7 7571 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7572 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7573 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
<> 144:ef7eb2e8f9f7 7574 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7575 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7576 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
<> 144:ef7eb2e8f9f7 7577 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7578 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7579 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
<> 144:ef7eb2e8f9f7 7580 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
<> 144:ef7eb2e8f9f7 7581 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
<> 144:ef7eb2e8f9f7 7582 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
<> 144:ef7eb2e8f9f7 7583 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
<> 144:ef7eb2e8f9f7 7584 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
<> 144:ef7eb2e8f9f7 7585 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
<> 144:ef7eb2e8f9f7 7586 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
<> 144:ef7eb2e8f9f7 7587 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
<> 144:ef7eb2e8f9f7 7588 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
<> 144:ef7eb2e8f9f7 7589 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
<> 144:ef7eb2e8f9f7 7590 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
<> 144:ef7eb2e8f9f7 7591 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
<> 144:ef7eb2e8f9f7 7592 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 7593 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
<> 144:ef7eb2e8f9f7 7594 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
<> 144:ef7eb2e8f9f7 7595 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 7596 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
<> 144:ef7eb2e8f9f7 7597 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
<> 144:ef7eb2e8f9f7 7598 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 7599 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
<> 144:ef7eb2e8f9f7 7600 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
<> 144:ef7eb2e8f9f7 7601 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 7602 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
<> 144:ef7eb2e8f9f7 7603 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
<> 144:ef7eb2e8f9f7 7604
<> 144:ef7eb2e8f9f7 7605 /*! @name PWMLOAD - FTM PWM Load */
<> 144:ef7eb2e8f9f7 7606 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7607 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7608 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
<> 144:ef7eb2e8f9f7 7609 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7610 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7611 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
<> 144:ef7eb2e8f9f7 7612 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7613 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7614 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
<> 144:ef7eb2e8f9f7 7615 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7616 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7617 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
<> 144:ef7eb2e8f9f7 7618 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7619 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7620 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
<> 144:ef7eb2e8f9f7 7621 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7622 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7623 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
<> 144:ef7eb2e8f9f7 7624 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7625 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7626 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
<> 144:ef7eb2e8f9f7 7627 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7628 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7629 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
<> 144:ef7eb2e8f9f7 7630 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
<> 144:ef7eb2e8f9f7 7631 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
<> 144:ef7eb2e8f9f7 7632 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
<> 144:ef7eb2e8f9f7 7633
<> 144:ef7eb2e8f9f7 7634
<> 144:ef7eb2e8f9f7 7635 /*!
<> 144:ef7eb2e8f9f7 7636 * @}
<> 144:ef7eb2e8f9f7 7637 */ /* end of group FTM_Register_Masks */
<> 144:ef7eb2e8f9f7 7638
<> 144:ef7eb2e8f9f7 7639
<> 144:ef7eb2e8f9f7 7640 /* FTM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7641 /** Peripheral FTM0 base address */
<> 144:ef7eb2e8f9f7 7642 #define FTM0_BASE (0x40038000u)
<> 144:ef7eb2e8f9f7 7643 /** Peripheral FTM0 base pointer */
<> 144:ef7eb2e8f9f7 7644 #define FTM0 ((FTM_Type *)FTM0_BASE)
<> 144:ef7eb2e8f9f7 7645 /** Peripheral FTM1 base address */
<> 144:ef7eb2e8f9f7 7646 #define FTM1_BASE (0x40039000u)
<> 144:ef7eb2e8f9f7 7647 /** Peripheral FTM1 base pointer */
<> 144:ef7eb2e8f9f7 7648 #define FTM1 ((FTM_Type *)FTM1_BASE)
<> 144:ef7eb2e8f9f7 7649 /** Peripheral FTM2 base address */
<> 144:ef7eb2e8f9f7 7650 #define FTM2_BASE (0x4003A000u)
<> 144:ef7eb2e8f9f7 7651 /** Peripheral FTM2 base pointer */
<> 144:ef7eb2e8f9f7 7652 #define FTM2 ((FTM_Type *)FTM2_BASE)
<> 144:ef7eb2e8f9f7 7653 /** Peripheral FTM3 base address */
<> 144:ef7eb2e8f9f7 7654 #define FTM3_BASE (0x400B9000u)
<> 144:ef7eb2e8f9f7 7655 /** Peripheral FTM3 base pointer */
<> 144:ef7eb2e8f9f7 7656 #define FTM3 ((FTM_Type *)FTM3_BASE)
<> 144:ef7eb2e8f9f7 7657 /** Array initializer of FTM peripheral base addresses */
<> 144:ef7eb2e8f9f7 7658 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
<> 144:ef7eb2e8f9f7 7659 /** Array initializer of FTM peripheral base pointers */
<> 144:ef7eb2e8f9f7 7660 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
<> 144:ef7eb2e8f9f7 7661 /** Interrupt vectors for the FTM peripheral type */
<> 144:ef7eb2e8f9f7 7662 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
<> 144:ef7eb2e8f9f7 7663
<> 144:ef7eb2e8f9f7 7664 /*!
<> 144:ef7eb2e8f9f7 7665 * @}
<> 144:ef7eb2e8f9f7 7666 */ /* end of group FTM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7667
<> 144:ef7eb2e8f9f7 7668
<> 144:ef7eb2e8f9f7 7669 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7670 -- GPIO Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7671 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7672
<> 144:ef7eb2e8f9f7 7673 /*!
<> 144:ef7eb2e8f9f7 7674 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7675 * @{
<> 144:ef7eb2e8f9f7 7676 */
<> 144:ef7eb2e8f9f7 7677
<> 144:ef7eb2e8f9f7 7678 /** GPIO - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 7679 typedef struct {
<> 144:ef7eb2e8f9f7 7680 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 7681 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 7682 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 7683 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 7684 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 7685 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 7686 } GPIO_Type;
<> 144:ef7eb2e8f9f7 7687
<> 144:ef7eb2e8f9f7 7688 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7689 -- GPIO Register Masks
<> 144:ef7eb2e8f9f7 7690 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7691
<> 144:ef7eb2e8f9f7 7692 /*!
<> 144:ef7eb2e8f9f7 7693 * @addtogroup GPIO_Register_Masks GPIO Register Masks
<> 144:ef7eb2e8f9f7 7694 * @{
<> 144:ef7eb2e8f9f7 7695 */
<> 144:ef7eb2e8f9f7 7696
<> 144:ef7eb2e8f9f7 7697 /*! @name PDOR - Port Data Output Register */
<> 144:ef7eb2e8f9f7 7698 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 7699 #define GPIO_PDOR_PDO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7700 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
<> 144:ef7eb2e8f9f7 7701
<> 144:ef7eb2e8f9f7 7702 /*! @name PSOR - Port Set Output Register */
<> 144:ef7eb2e8f9f7 7703 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 7704 #define GPIO_PSOR_PTSO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7705 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
<> 144:ef7eb2e8f9f7 7706
<> 144:ef7eb2e8f9f7 7707 /*! @name PCOR - Port Clear Output Register */
<> 144:ef7eb2e8f9f7 7708 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 7709 #define GPIO_PCOR_PTCO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7710 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
<> 144:ef7eb2e8f9f7 7711
<> 144:ef7eb2e8f9f7 7712 /*! @name PTOR - Port Toggle Output Register */
<> 144:ef7eb2e8f9f7 7713 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 7714 #define GPIO_PTOR_PTTO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7715 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
<> 144:ef7eb2e8f9f7 7716
<> 144:ef7eb2e8f9f7 7717 /*! @name PDIR - Port Data Input Register */
<> 144:ef7eb2e8f9f7 7718 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 7719 #define GPIO_PDIR_PDI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7720 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
<> 144:ef7eb2e8f9f7 7721
<> 144:ef7eb2e8f9f7 7722 /*! @name PDDR - Port Data Direction Register */
<> 144:ef7eb2e8f9f7 7723 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 7724 #define GPIO_PDDR_PDD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7725 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
<> 144:ef7eb2e8f9f7 7726
<> 144:ef7eb2e8f9f7 7727
<> 144:ef7eb2e8f9f7 7728 /*!
<> 144:ef7eb2e8f9f7 7729 * @}
<> 144:ef7eb2e8f9f7 7730 */ /* end of group GPIO_Register_Masks */
<> 144:ef7eb2e8f9f7 7731
<> 144:ef7eb2e8f9f7 7732
<> 144:ef7eb2e8f9f7 7733 /* GPIO - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7734 /** Peripheral PTA base address */
<> 144:ef7eb2e8f9f7 7735 #define PTA_BASE (0x400FF000u)
<> 144:ef7eb2e8f9f7 7736 /** Peripheral PTA base pointer */
<> 144:ef7eb2e8f9f7 7737 #define PTA ((GPIO_Type *)PTA_BASE)
<> 144:ef7eb2e8f9f7 7738 /** Peripheral PTB base address */
<> 144:ef7eb2e8f9f7 7739 #define PTB_BASE (0x400FF040u)
<> 144:ef7eb2e8f9f7 7740 /** Peripheral PTB base pointer */
<> 144:ef7eb2e8f9f7 7741 #define PTB ((GPIO_Type *)PTB_BASE)
<> 144:ef7eb2e8f9f7 7742 /** Peripheral PTC base address */
<> 144:ef7eb2e8f9f7 7743 #define PTC_BASE (0x400FF080u)
<> 144:ef7eb2e8f9f7 7744 /** Peripheral PTC base pointer */
<> 144:ef7eb2e8f9f7 7745 #define PTC ((GPIO_Type *)PTC_BASE)
<> 144:ef7eb2e8f9f7 7746 /** Peripheral PTD base address */
<> 144:ef7eb2e8f9f7 7747 #define PTD_BASE (0x400FF0C0u)
<> 144:ef7eb2e8f9f7 7748 /** Peripheral PTD base pointer */
<> 144:ef7eb2e8f9f7 7749 #define PTD ((GPIO_Type *)PTD_BASE)
<> 144:ef7eb2e8f9f7 7750 /** Peripheral PTE base address */
<> 144:ef7eb2e8f9f7 7751 #define PTE_BASE (0x400FF100u)
<> 144:ef7eb2e8f9f7 7752 /** Peripheral PTE base pointer */
<> 144:ef7eb2e8f9f7 7753 #define PTE ((GPIO_Type *)PTE_BASE)
<> 144:ef7eb2e8f9f7 7754 /** Array initializer of GPIO peripheral base addresses */
<> 144:ef7eb2e8f9f7 7755 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
<> 144:ef7eb2e8f9f7 7756 /** Array initializer of GPIO peripheral base pointers */
<> 144:ef7eb2e8f9f7 7757 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
<> 144:ef7eb2e8f9f7 7758
<> 144:ef7eb2e8f9f7 7759 /*!
<> 144:ef7eb2e8f9f7 7760 * @}
<> 144:ef7eb2e8f9f7 7761 */ /* end of group GPIO_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7762
<> 144:ef7eb2e8f9f7 7763
<> 144:ef7eb2e8f9f7 7764 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7765 -- I2C Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7766 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7767
<> 144:ef7eb2e8f9f7 7768 /*!
<> 144:ef7eb2e8f9f7 7769 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7770 * @{
<> 144:ef7eb2e8f9f7 7771 */
<> 144:ef7eb2e8f9f7 7772
<> 144:ef7eb2e8f9f7 7773 /** I2C - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 7774 typedef struct {
<> 144:ef7eb2e8f9f7 7775 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
<> 144:ef7eb2e8f9f7 7776 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 7777 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
<> 144:ef7eb2e8f9f7 7778 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 7779 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 7780 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
<> 144:ef7eb2e8f9f7 7781 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 7782 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 7783 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 7784 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
<> 144:ef7eb2e8f9f7 7785 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
<> 144:ef7eb2e8f9f7 7786 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
<> 144:ef7eb2e8f9f7 7787 } I2C_Type;
<> 144:ef7eb2e8f9f7 7788
<> 144:ef7eb2e8f9f7 7789 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7790 -- I2C Register Masks
<> 144:ef7eb2e8f9f7 7791 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7792
<> 144:ef7eb2e8f9f7 7793 /*!
<> 144:ef7eb2e8f9f7 7794 * @addtogroup I2C_Register_Masks I2C Register Masks
<> 144:ef7eb2e8f9f7 7795 * @{
<> 144:ef7eb2e8f9f7 7796 */
<> 144:ef7eb2e8f9f7 7797
<> 144:ef7eb2e8f9f7 7798 /*! @name A1 - I2C Address Register 1 */
<> 144:ef7eb2e8f9f7 7799 #define I2C_A1_AD_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 7800 #define I2C_A1_AD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7801 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
<> 144:ef7eb2e8f9f7 7802
<> 144:ef7eb2e8f9f7 7803 /*! @name F - I2C Frequency Divider register */
<> 144:ef7eb2e8f9f7 7804 #define I2C_F_ICR_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 7805 #define I2C_F_ICR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7806 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
<> 144:ef7eb2e8f9f7 7807 #define I2C_F_MULT_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 7808 #define I2C_F_MULT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7809 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
<> 144:ef7eb2e8f9f7 7810
<> 144:ef7eb2e8f9f7 7811 /*! @name C1 - I2C Control Register 1 */
<> 144:ef7eb2e8f9f7 7812 #define I2C_C1_DMAEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7813 #define I2C_C1_DMAEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7814 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 7815 #define I2C_C1_WUEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7816 #define I2C_C1_WUEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7817 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
<> 144:ef7eb2e8f9f7 7818 #define I2C_C1_RSTA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7819 #define I2C_C1_RSTA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7820 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
<> 144:ef7eb2e8f9f7 7821 #define I2C_C1_TXAK_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7822 #define I2C_C1_TXAK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7823 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
<> 144:ef7eb2e8f9f7 7824 #define I2C_C1_TX_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7825 #define I2C_C1_TX_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7826 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
<> 144:ef7eb2e8f9f7 7827 #define I2C_C1_MST_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7828 #define I2C_C1_MST_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7829 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
<> 144:ef7eb2e8f9f7 7830 #define I2C_C1_IICIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7831 #define I2C_C1_IICIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7832 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
<> 144:ef7eb2e8f9f7 7833 #define I2C_C1_IICEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7834 #define I2C_C1_IICEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7835 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
<> 144:ef7eb2e8f9f7 7836
<> 144:ef7eb2e8f9f7 7837 /*! @name S - I2C Status register */
<> 144:ef7eb2e8f9f7 7838 #define I2C_S_RXAK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7839 #define I2C_S_RXAK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7840 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
<> 144:ef7eb2e8f9f7 7841 #define I2C_S_IICIF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7842 #define I2C_S_IICIF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7843 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
<> 144:ef7eb2e8f9f7 7844 #define I2C_S_SRW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7845 #define I2C_S_SRW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7846 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
<> 144:ef7eb2e8f9f7 7847 #define I2C_S_RAM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7848 #define I2C_S_RAM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7849 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
<> 144:ef7eb2e8f9f7 7850 #define I2C_S_ARBL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7851 #define I2C_S_ARBL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7852 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
<> 144:ef7eb2e8f9f7 7853 #define I2C_S_BUSY_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7854 #define I2C_S_BUSY_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7855 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
<> 144:ef7eb2e8f9f7 7856 #define I2C_S_IAAS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7857 #define I2C_S_IAAS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7858 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
<> 144:ef7eb2e8f9f7 7859 #define I2C_S_TCF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7860 #define I2C_S_TCF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7861 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
<> 144:ef7eb2e8f9f7 7862
<> 144:ef7eb2e8f9f7 7863 /*! @name D - I2C Data I/O register */
<> 144:ef7eb2e8f9f7 7864 #define I2C_D_DATA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7865 #define I2C_D_DATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7866 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
<> 144:ef7eb2e8f9f7 7867
<> 144:ef7eb2e8f9f7 7868 /*! @name C2 - I2C Control Register 2 */
<> 144:ef7eb2e8f9f7 7869 #define I2C_C2_AD_MASK (0x7U)
<> 144:ef7eb2e8f9f7 7870 #define I2C_C2_AD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7871 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
<> 144:ef7eb2e8f9f7 7872 #define I2C_C2_RMEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7873 #define I2C_C2_RMEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7874 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
<> 144:ef7eb2e8f9f7 7875 #define I2C_C2_SBRC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7876 #define I2C_C2_SBRC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7877 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
<> 144:ef7eb2e8f9f7 7878 #define I2C_C2_HDRS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7879 #define I2C_C2_HDRS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7880 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
<> 144:ef7eb2e8f9f7 7881 #define I2C_C2_ADEXT_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7882 #define I2C_C2_ADEXT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7883 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
<> 144:ef7eb2e8f9f7 7884 #define I2C_C2_GCAEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7885 #define I2C_C2_GCAEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7886 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
<> 144:ef7eb2e8f9f7 7887
<> 144:ef7eb2e8f9f7 7888 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
<> 144:ef7eb2e8f9f7 7889 #define I2C_FLT_FLT_MASK (0xFU)
<> 144:ef7eb2e8f9f7 7890 #define I2C_FLT_FLT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7891 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
<> 144:ef7eb2e8f9f7 7892 #define I2C_FLT_STARTF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7893 #define I2C_FLT_STARTF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7894 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
<> 144:ef7eb2e8f9f7 7895 #define I2C_FLT_SSIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7896 #define I2C_FLT_SSIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7897 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
<> 144:ef7eb2e8f9f7 7898 #define I2C_FLT_STOPF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7899 #define I2C_FLT_STOPF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7900 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
<> 144:ef7eb2e8f9f7 7901 #define I2C_FLT_SHEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7902 #define I2C_FLT_SHEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7903 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
<> 144:ef7eb2e8f9f7 7904
<> 144:ef7eb2e8f9f7 7905 /*! @name RA - I2C Range Address register */
<> 144:ef7eb2e8f9f7 7906 #define I2C_RA_RAD_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 7907 #define I2C_RA_RAD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7908 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
<> 144:ef7eb2e8f9f7 7909
<> 144:ef7eb2e8f9f7 7910 /*! @name SMB - I2C SMBus Control and Status register */
<> 144:ef7eb2e8f9f7 7911 #define I2C_SMB_SHTF2IE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 7912 #define I2C_SMB_SHTF2IE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7913 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
<> 144:ef7eb2e8f9f7 7914 #define I2C_SMB_SHTF2_MASK (0x2U)
<> 144:ef7eb2e8f9f7 7915 #define I2C_SMB_SHTF2_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7916 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
<> 144:ef7eb2e8f9f7 7917 #define I2C_SMB_SHTF1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 7918 #define I2C_SMB_SHTF1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 7919 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
<> 144:ef7eb2e8f9f7 7920 #define I2C_SMB_SLTF_MASK (0x8U)
<> 144:ef7eb2e8f9f7 7921 #define I2C_SMB_SLTF_SHIFT (3U)
<> 144:ef7eb2e8f9f7 7922 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
<> 144:ef7eb2e8f9f7 7923 #define I2C_SMB_TCKSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 7924 #define I2C_SMB_TCKSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 7925 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
<> 144:ef7eb2e8f9f7 7926 #define I2C_SMB_SIICAEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 7927 #define I2C_SMB_SIICAEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 7928 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
<> 144:ef7eb2e8f9f7 7929 #define I2C_SMB_ALERTEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 7930 #define I2C_SMB_ALERTEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 7931 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
<> 144:ef7eb2e8f9f7 7932 #define I2C_SMB_FACK_MASK (0x80U)
<> 144:ef7eb2e8f9f7 7933 #define I2C_SMB_FACK_SHIFT (7U)
<> 144:ef7eb2e8f9f7 7934 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
<> 144:ef7eb2e8f9f7 7935
<> 144:ef7eb2e8f9f7 7936 /*! @name A2 - I2C Address Register 2 */
<> 144:ef7eb2e8f9f7 7937 #define I2C_A2_SAD_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 7938 #define I2C_A2_SAD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 7939 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
<> 144:ef7eb2e8f9f7 7940
<> 144:ef7eb2e8f9f7 7941 /*! @name SLTH - I2C SCL Low Timeout Register High */
<> 144:ef7eb2e8f9f7 7942 #define I2C_SLTH_SSLT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7943 #define I2C_SLTH_SSLT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7944 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
<> 144:ef7eb2e8f9f7 7945
<> 144:ef7eb2e8f9f7 7946 /*! @name SLTL - I2C SCL Low Timeout Register Low */
<> 144:ef7eb2e8f9f7 7947 #define I2C_SLTL_SSLT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 7948 #define I2C_SLTL_SSLT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 7949 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
<> 144:ef7eb2e8f9f7 7950
<> 144:ef7eb2e8f9f7 7951
<> 144:ef7eb2e8f9f7 7952 /*!
<> 144:ef7eb2e8f9f7 7953 * @}
<> 144:ef7eb2e8f9f7 7954 */ /* end of group I2C_Register_Masks */
<> 144:ef7eb2e8f9f7 7955
<> 144:ef7eb2e8f9f7 7956
<> 144:ef7eb2e8f9f7 7957 /* I2C - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 7958 /** Peripheral I2C0 base address */
<> 144:ef7eb2e8f9f7 7959 #define I2C0_BASE (0x40066000u)
<> 144:ef7eb2e8f9f7 7960 /** Peripheral I2C0 base pointer */
<> 144:ef7eb2e8f9f7 7961 #define I2C0 ((I2C_Type *)I2C0_BASE)
<> 144:ef7eb2e8f9f7 7962 /** Peripheral I2C1 base address */
<> 144:ef7eb2e8f9f7 7963 #define I2C1_BASE (0x40067000u)
<> 144:ef7eb2e8f9f7 7964 /** Peripheral I2C1 base pointer */
<> 144:ef7eb2e8f9f7 7965 #define I2C1 ((I2C_Type *)I2C1_BASE)
<> 144:ef7eb2e8f9f7 7966 /** Peripheral I2C2 base address */
<> 144:ef7eb2e8f9f7 7967 #define I2C2_BASE (0x400E6000u)
<> 144:ef7eb2e8f9f7 7968 /** Peripheral I2C2 base pointer */
<> 144:ef7eb2e8f9f7 7969 #define I2C2 ((I2C_Type *)I2C2_BASE)
<> 144:ef7eb2e8f9f7 7970 /** Peripheral I2C3 base address */
<> 144:ef7eb2e8f9f7 7971 #define I2C3_BASE (0x400E7000u)
<> 144:ef7eb2e8f9f7 7972 /** Peripheral I2C3 base pointer */
<> 144:ef7eb2e8f9f7 7973 #define I2C3 ((I2C_Type *)I2C3_BASE)
<> 144:ef7eb2e8f9f7 7974 /** Array initializer of I2C peripheral base addresses */
<> 144:ef7eb2e8f9f7 7975 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
<> 144:ef7eb2e8f9f7 7976 /** Array initializer of I2C peripheral base pointers */
<> 144:ef7eb2e8f9f7 7977 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
<> 144:ef7eb2e8f9f7 7978 /** Interrupt vectors for the I2C peripheral type */
<> 144:ef7eb2e8f9f7 7979 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
<> 144:ef7eb2e8f9f7 7980
<> 144:ef7eb2e8f9f7 7981 /*!
<> 144:ef7eb2e8f9f7 7982 * @}
<> 144:ef7eb2e8f9f7 7983 */ /* end of group I2C_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 7984
<> 144:ef7eb2e8f9f7 7985
<> 144:ef7eb2e8f9f7 7986 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7987 -- I2S Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7988 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 7989
<> 144:ef7eb2e8f9f7 7990 /*!
<> 144:ef7eb2e8f9f7 7991 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
<> 144:ef7eb2e8f9f7 7992 * @{
<> 144:ef7eb2e8f9f7 7993 */
<> 144:ef7eb2e8f9f7 7994
<> 144:ef7eb2e8f9f7 7995 /** I2S - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 7996 typedef struct {
<> 144:ef7eb2e8f9f7 7997 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 7998 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 7999 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 8000 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 8001 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 8002 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 8003 uint8_t RESERVED_0[8];
<> 144:ef7eb2e8f9f7 8004 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
<> 144:ef7eb2e8f9f7 8005 uint8_t RESERVED_1[24];
<> 144:ef7eb2e8f9f7 8006 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
<> 144:ef7eb2e8f9f7 8007 uint8_t RESERVED_2[24];
<> 144:ef7eb2e8f9f7 8008 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
<> 144:ef7eb2e8f9f7 8009 uint8_t RESERVED_3[28];
<> 144:ef7eb2e8f9f7 8010 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 8011 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 8012 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
<> 144:ef7eb2e8f9f7 8013 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
<> 144:ef7eb2e8f9f7 8014 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
<> 144:ef7eb2e8f9f7 8015 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
<> 144:ef7eb2e8f9f7 8016 uint8_t RESERVED_4[8];
<> 144:ef7eb2e8f9f7 8017 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 8018 uint8_t RESERVED_5[24];
<> 144:ef7eb2e8f9f7 8019 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 8020 uint8_t RESERVED_6[24];
<> 144:ef7eb2e8f9f7 8021 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
<> 144:ef7eb2e8f9f7 8022 uint8_t RESERVED_7[28];
<> 144:ef7eb2e8f9f7 8023 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 8024 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
<> 144:ef7eb2e8f9f7 8025 } I2S_Type;
<> 144:ef7eb2e8f9f7 8026
<> 144:ef7eb2e8f9f7 8027 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8028 -- I2S Register Masks
<> 144:ef7eb2e8f9f7 8029 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8030
<> 144:ef7eb2e8f9f7 8031 /*!
<> 144:ef7eb2e8f9f7 8032 * @addtogroup I2S_Register_Masks I2S Register Masks
<> 144:ef7eb2e8f9f7 8033 * @{
<> 144:ef7eb2e8f9f7 8034 */
<> 144:ef7eb2e8f9f7 8035
<> 144:ef7eb2e8f9f7 8036 /*! @name TCSR - SAI Transmit Control Register */
<> 144:ef7eb2e8f9f7 8037 #define I2S_TCSR_FRDE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8038 #define I2S_TCSR_FRDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8039 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
<> 144:ef7eb2e8f9f7 8040 #define I2S_TCSR_FWDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8041 #define I2S_TCSR_FWDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8042 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
<> 144:ef7eb2e8f9f7 8043 #define I2S_TCSR_FRIE_MASK (0x100U)
<> 144:ef7eb2e8f9f7 8044 #define I2S_TCSR_FRIE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8045 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
<> 144:ef7eb2e8f9f7 8046 #define I2S_TCSR_FWIE_MASK (0x200U)
<> 144:ef7eb2e8f9f7 8047 #define I2S_TCSR_FWIE_SHIFT (9U)
<> 144:ef7eb2e8f9f7 8048 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
<> 144:ef7eb2e8f9f7 8049 #define I2S_TCSR_FEIE_MASK (0x400U)
<> 144:ef7eb2e8f9f7 8050 #define I2S_TCSR_FEIE_SHIFT (10U)
<> 144:ef7eb2e8f9f7 8051 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
<> 144:ef7eb2e8f9f7 8052 #define I2S_TCSR_SEIE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 8053 #define I2S_TCSR_SEIE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 8054 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
<> 144:ef7eb2e8f9f7 8055 #define I2S_TCSR_WSIE_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 8056 #define I2S_TCSR_WSIE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 8057 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
<> 144:ef7eb2e8f9f7 8058 #define I2S_TCSR_FRF_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 8059 #define I2S_TCSR_FRF_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8060 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
<> 144:ef7eb2e8f9f7 8061 #define I2S_TCSR_FWF_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 8062 #define I2S_TCSR_FWF_SHIFT (17U)
<> 144:ef7eb2e8f9f7 8063 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
<> 144:ef7eb2e8f9f7 8064 #define I2S_TCSR_FEF_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 8065 #define I2S_TCSR_FEF_SHIFT (18U)
<> 144:ef7eb2e8f9f7 8066 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
<> 144:ef7eb2e8f9f7 8067 #define I2S_TCSR_SEF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 8068 #define I2S_TCSR_SEF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 8069 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
<> 144:ef7eb2e8f9f7 8070 #define I2S_TCSR_WSF_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 8071 #define I2S_TCSR_WSF_SHIFT (20U)
<> 144:ef7eb2e8f9f7 8072 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
<> 144:ef7eb2e8f9f7 8073 #define I2S_TCSR_SR_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 8074 #define I2S_TCSR_SR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8075 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
<> 144:ef7eb2e8f9f7 8076 #define I2S_TCSR_FR_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 8077 #define I2S_TCSR_FR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 8078 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
<> 144:ef7eb2e8f9f7 8079 #define I2S_TCSR_BCE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 8080 #define I2S_TCSR_BCE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8081 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
<> 144:ef7eb2e8f9f7 8082 #define I2S_TCSR_DBGE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 8083 #define I2S_TCSR_DBGE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 8084 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
<> 144:ef7eb2e8f9f7 8085 #define I2S_TCSR_STOPE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 8086 #define I2S_TCSR_STOPE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 8087 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
<> 144:ef7eb2e8f9f7 8088 #define I2S_TCSR_TE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 8089 #define I2S_TCSR_TE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 8090 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
<> 144:ef7eb2e8f9f7 8091
<> 144:ef7eb2e8f9f7 8092 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
<> 144:ef7eb2e8f9f7 8093 #define I2S_TCR1_TFW_MASK (0x7U)
<> 144:ef7eb2e8f9f7 8094 #define I2S_TCR1_TFW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8095 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
<> 144:ef7eb2e8f9f7 8096
<> 144:ef7eb2e8f9f7 8097 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
<> 144:ef7eb2e8f9f7 8098 #define I2S_TCR2_DIV_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 8099 #define I2S_TCR2_DIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8100 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
<> 144:ef7eb2e8f9f7 8101 #define I2S_TCR2_BCD_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 8102 #define I2S_TCR2_BCD_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8103 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
<> 144:ef7eb2e8f9f7 8104 #define I2S_TCR2_BCP_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 8105 #define I2S_TCR2_BCP_SHIFT (25U)
<> 144:ef7eb2e8f9f7 8106 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
<> 144:ef7eb2e8f9f7 8107 #define I2S_TCR2_MSEL_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 8108 #define I2S_TCR2_MSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8109 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
<> 144:ef7eb2e8f9f7 8110 #define I2S_TCR2_BCI_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 8111 #define I2S_TCR2_BCI_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8112 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
<> 144:ef7eb2e8f9f7 8113 #define I2S_TCR2_BCS_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 8114 #define I2S_TCR2_BCS_SHIFT (29U)
<> 144:ef7eb2e8f9f7 8115 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
<> 144:ef7eb2e8f9f7 8116 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 8117 #define I2S_TCR2_SYNC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 8118 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
<> 144:ef7eb2e8f9f7 8119
<> 144:ef7eb2e8f9f7 8120 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
<> 144:ef7eb2e8f9f7 8121 #define I2S_TCR3_WDFL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 8122 #define I2S_TCR3_WDFL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8123 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
<> 144:ef7eb2e8f9f7 8124 #define I2S_TCR3_TCE_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 8125 #define I2S_TCR3_TCE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8126 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
<> 144:ef7eb2e8f9f7 8127 #define I2S_TCR3_CFR_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8128 #define I2S_TCR3_CFR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8129 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
<> 144:ef7eb2e8f9f7 8130
<> 144:ef7eb2e8f9f7 8131 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
<> 144:ef7eb2e8f9f7 8132 #define I2S_TCR4_FSD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8133 #define I2S_TCR4_FSD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8134 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
<> 144:ef7eb2e8f9f7 8135 #define I2S_TCR4_FSP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8136 #define I2S_TCR4_FSP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8137 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
<> 144:ef7eb2e8f9f7 8138 #define I2S_TCR4_ONDEM_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8139 #define I2S_TCR4_ONDEM_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8140 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
<> 144:ef7eb2e8f9f7 8141 #define I2S_TCR4_FSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8142 #define I2S_TCR4_FSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8143 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
<> 144:ef7eb2e8f9f7 8144 #define I2S_TCR4_MF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8145 #define I2S_TCR4_MF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8146 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
<> 144:ef7eb2e8f9f7 8147 #define I2S_TCR4_SYWD_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 8148 #define I2S_TCR4_SYWD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8149 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
<> 144:ef7eb2e8f9f7 8150 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 8151 #define I2S_TCR4_FRSZ_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8152 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
<> 144:ef7eb2e8f9f7 8153 #define I2S_TCR4_FPACK_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8154 #define I2S_TCR4_FPACK_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8155 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
<> 144:ef7eb2e8f9f7 8156 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 8157 #define I2S_TCR4_FCOMB_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8158 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
<> 144:ef7eb2e8f9f7 8159 #define I2S_TCR4_FCONT_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 8160 #define I2S_TCR4_FCONT_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8161 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
<> 144:ef7eb2e8f9f7 8162
<> 144:ef7eb2e8f9f7 8163 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
<> 144:ef7eb2e8f9f7 8164 #define I2S_TCR5_FBT_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 8165 #define I2S_TCR5_FBT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8166 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
<> 144:ef7eb2e8f9f7 8167 #define I2S_TCR5_W0W_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 8168 #define I2S_TCR5_W0W_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8169 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
<> 144:ef7eb2e8f9f7 8170 #define I2S_TCR5_WNW_MASK (0x1F000000U)
<> 144:ef7eb2e8f9f7 8171 #define I2S_TCR5_WNW_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8172 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
<> 144:ef7eb2e8f9f7 8173
<> 144:ef7eb2e8f9f7 8174 /*! @name TDR - SAI Transmit Data Register */
<> 144:ef7eb2e8f9f7 8175 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 8176 #define I2S_TDR_TDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8177 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
<> 144:ef7eb2e8f9f7 8178
<> 144:ef7eb2e8f9f7 8179 /* The count of I2S_TDR */
<> 144:ef7eb2e8f9f7 8180 #define I2S_TDR_COUNT (2U)
<> 144:ef7eb2e8f9f7 8181
<> 144:ef7eb2e8f9f7 8182 /*! @name TFR - SAI Transmit FIFO Register */
<> 144:ef7eb2e8f9f7 8183 #define I2S_TFR_RFP_MASK (0xFU)
<> 144:ef7eb2e8f9f7 8184 #define I2S_TFR_RFP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8185 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
<> 144:ef7eb2e8f9f7 8186 #define I2S_TFR_WFP_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 8187 #define I2S_TFR_WFP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8188 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
<> 144:ef7eb2e8f9f7 8189 #define I2S_TFR_WCP_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 8190 #define I2S_TFR_WCP_SHIFT (31U)
<> 144:ef7eb2e8f9f7 8191 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
<> 144:ef7eb2e8f9f7 8192
<> 144:ef7eb2e8f9f7 8193 /* The count of I2S_TFR */
<> 144:ef7eb2e8f9f7 8194 #define I2S_TFR_COUNT (2U)
<> 144:ef7eb2e8f9f7 8195
<> 144:ef7eb2e8f9f7 8196 /*! @name TMR - SAI Transmit Mask Register */
<> 144:ef7eb2e8f9f7 8197 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 8198 #define I2S_TMR_TWM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8199 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
<> 144:ef7eb2e8f9f7 8200
<> 144:ef7eb2e8f9f7 8201 /*! @name RCSR - SAI Receive Control Register */
<> 144:ef7eb2e8f9f7 8202 #define I2S_RCSR_FRDE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8203 #define I2S_RCSR_FRDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8204 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
<> 144:ef7eb2e8f9f7 8205 #define I2S_RCSR_FWDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8206 #define I2S_RCSR_FWDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8207 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
<> 144:ef7eb2e8f9f7 8208 #define I2S_RCSR_FRIE_MASK (0x100U)
<> 144:ef7eb2e8f9f7 8209 #define I2S_RCSR_FRIE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8210 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
<> 144:ef7eb2e8f9f7 8211 #define I2S_RCSR_FWIE_MASK (0x200U)
<> 144:ef7eb2e8f9f7 8212 #define I2S_RCSR_FWIE_SHIFT (9U)
<> 144:ef7eb2e8f9f7 8213 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
<> 144:ef7eb2e8f9f7 8214 #define I2S_RCSR_FEIE_MASK (0x400U)
<> 144:ef7eb2e8f9f7 8215 #define I2S_RCSR_FEIE_SHIFT (10U)
<> 144:ef7eb2e8f9f7 8216 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
<> 144:ef7eb2e8f9f7 8217 #define I2S_RCSR_SEIE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 8218 #define I2S_RCSR_SEIE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 8219 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
<> 144:ef7eb2e8f9f7 8220 #define I2S_RCSR_WSIE_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 8221 #define I2S_RCSR_WSIE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 8222 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
<> 144:ef7eb2e8f9f7 8223 #define I2S_RCSR_FRF_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 8224 #define I2S_RCSR_FRF_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8225 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
<> 144:ef7eb2e8f9f7 8226 #define I2S_RCSR_FWF_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 8227 #define I2S_RCSR_FWF_SHIFT (17U)
<> 144:ef7eb2e8f9f7 8228 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
<> 144:ef7eb2e8f9f7 8229 #define I2S_RCSR_FEF_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 8230 #define I2S_RCSR_FEF_SHIFT (18U)
<> 144:ef7eb2e8f9f7 8231 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
<> 144:ef7eb2e8f9f7 8232 #define I2S_RCSR_SEF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 8233 #define I2S_RCSR_SEF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 8234 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
<> 144:ef7eb2e8f9f7 8235 #define I2S_RCSR_WSF_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 8236 #define I2S_RCSR_WSF_SHIFT (20U)
<> 144:ef7eb2e8f9f7 8237 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
<> 144:ef7eb2e8f9f7 8238 #define I2S_RCSR_SR_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 8239 #define I2S_RCSR_SR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8240 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
<> 144:ef7eb2e8f9f7 8241 #define I2S_RCSR_FR_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 8242 #define I2S_RCSR_FR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 8243 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
<> 144:ef7eb2e8f9f7 8244 #define I2S_RCSR_BCE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 8245 #define I2S_RCSR_BCE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8246 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
<> 144:ef7eb2e8f9f7 8247 #define I2S_RCSR_DBGE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 8248 #define I2S_RCSR_DBGE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 8249 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
<> 144:ef7eb2e8f9f7 8250 #define I2S_RCSR_STOPE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 8251 #define I2S_RCSR_STOPE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 8252 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
<> 144:ef7eb2e8f9f7 8253 #define I2S_RCSR_RE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 8254 #define I2S_RCSR_RE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 8255 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
<> 144:ef7eb2e8f9f7 8256
<> 144:ef7eb2e8f9f7 8257 /*! @name RCR1 - SAI Receive Configuration 1 Register */
<> 144:ef7eb2e8f9f7 8258 #define I2S_RCR1_RFW_MASK (0x7U)
<> 144:ef7eb2e8f9f7 8259 #define I2S_RCR1_RFW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8260 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
<> 144:ef7eb2e8f9f7 8261
<> 144:ef7eb2e8f9f7 8262 /*! @name RCR2 - SAI Receive Configuration 2 Register */
<> 144:ef7eb2e8f9f7 8263 #define I2S_RCR2_DIV_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 8264 #define I2S_RCR2_DIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8265 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
<> 144:ef7eb2e8f9f7 8266 #define I2S_RCR2_BCD_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 8267 #define I2S_RCR2_BCD_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8268 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
<> 144:ef7eb2e8f9f7 8269 #define I2S_RCR2_BCP_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 8270 #define I2S_RCR2_BCP_SHIFT (25U)
<> 144:ef7eb2e8f9f7 8271 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
<> 144:ef7eb2e8f9f7 8272 #define I2S_RCR2_MSEL_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 8273 #define I2S_RCR2_MSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8274 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
<> 144:ef7eb2e8f9f7 8275 #define I2S_RCR2_BCI_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 8276 #define I2S_RCR2_BCI_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8277 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
<> 144:ef7eb2e8f9f7 8278 #define I2S_RCR2_BCS_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 8279 #define I2S_RCR2_BCS_SHIFT (29U)
<> 144:ef7eb2e8f9f7 8280 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
<> 144:ef7eb2e8f9f7 8281 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 8282 #define I2S_RCR2_SYNC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 8283 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
<> 144:ef7eb2e8f9f7 8284
<> 144:ef7eb2e8f9f7 8285 /*! @name RCR3 - SAI Receive Configuration 3 Register */
<> 144:ef7eb2e8f9f7 8286 #define I2S_RCR3_WDFL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 8287 #define I2S_RCR3_WDFL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8288 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
<> 144:ef7eb2e8f9f7 8289 #define I2S_RCR3_RCE_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 8290 #define I2S_RCR3_RCE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8291 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
<> 144:ef7eb2e8f9f7 8292 #define I2S_RCR3_CFR_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8293 #define I2S_RCR3_CFR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8294 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
<> 144:ef7eb2e8f9f7 8295
<> 144:ef7eb2e8f9f7 8296 /*! @name RCR4 - SAI Receive Configuration 4 Register */
<> 144:ef7eb2e8f9f7 8297 #define I2S_RCR4_FSD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8298 #define I2S_RCR4_FSD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8299 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
<> 144:ef7eb2e8f9f7 8300 #define I2S_RCR4_FSP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8301 #define I2S_RCR4_FSP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8302 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
<> 144:ef7eb2e8f9f7 8303 #define I2S_RCR4_ONDEM_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8304 #define I2S_RCR4_ONDEM_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8305 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
<> 144:ef7eb2e8f9f7 8306 #define I2S_RCR4_FSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8307 #define I2S_RCR4_FSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8308 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
<> 144:ef7eb2e8f9f7 8309 #define I2S_RCR4_MF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8310 #define I2S_RCR4_MF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8311 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
<> 144:ef7eb2e8f9f7 8312 #define I2S_RCR4_SYWD_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 8313 #define I2S_RCR4_SYWD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8314 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
<> 144:ef7eb2e8f9f7 8315 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 8316 #define I2S_RCR4_FRSZ_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8317 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
<> 144:ef7eb2e8f9f7 8318 #define I2S_RCR4_FPACK_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8319 #define I2S_RCR4_FPACK_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8320 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
<> 144:ef7eb2e8f9f7 8321 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 8322 #define I2S_RCR4_FCOMB_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8323 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
<> 144:ef7eb2e8f9f7 8324 #define I2S_RCR4_FCONT_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 8325 #define I2S_RCR4_FCONT_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8326 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
<> 144:ef7eb2e8f9f7 8327
<> 144:ef7eb2e8f9f7 8328 /*! @name RCR5 - SAI Receive Configuration 5 Register */
<> 144:ef7eb2e8f9f7 8329 #define I2S_RCR5_FBT_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 8330 #define I2S_RCR5_FBT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8331 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
<> 144:ef7eb2e8f9f7 8332 #define I2S_RCR5_W0W_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 8333 #define I2S_RCR5_W0W_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8334 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
<> 144:ef7eb2e8f9f7 8335 #define I2S_RCR5_WNW_MASK (0x1F000000U)
<> 144:ef7eb2e8f9f7 8336 #define I2S_RCR5_WNW_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8337 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
<> 144:ef7eb2e8f9f7 8338
<> 144:ef7eb2e8f9f7 8339 /*! @name RDR - SAI Receive Data Register */
<> 144:ef7eb2e8f9f7 8340 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 8341 #define I2S_RDR_RDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8342 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
<> 144:ef7eb2e8f9f7 8343
<> 144:ef7eb2e8f9f7 8344 /* The count of I2S_RDR */
<> 144:ef7eb2e8f9f7 8345 #define I2S_RDR_COUNT (2U)
<> 144:ef7eb2e8f9f7 8346
<> 144:ef7eb2e8f9f7 8347 /*! @name RFR - SAI Receive FIFO Register */
<> 144:ef7eb2e8f9f7 8348 #define I2S_RFR_RFP_MASK (0xFU)
<> 144:ef7eb2e8f9f7 8349 #define I2S_RFR_RFP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8350 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
<> 144:ef7eb2e8f9f7 8351 #define I2S_RFR_RCP_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 8352 #define I2S_RFR_RCP_SHIFT (15U)
<> 144:ef7eb2e8f9f7 8353 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
<> 144:ef7eb2e8f9f7 8354 #define I2S_RFR_WFP_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 8355 #define I2S_RFR_WFP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8356 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
<> 144:ef7eb2e8f9f7 8357
<> 144:ef7eb2e8f9f7 8358 /* The count of I2S_RFR */
<> 144:ef7eb2e8f9f7 8359 #define I2S_RFR_COUNT (2U)
<> 144:ef7eb2e8f9f7 8360
<> 144:ef7eb2e8f9f7 8361 /*! @name RMR - SAI Receive Mask Register */
<> 144:ef7eb2e8f9f7 8362 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 8363 #define I2S_RMR_RWM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8364 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
<> 144:ef7eb2e8f9f7 8365
<> 144:ef7eb2e8f9f7 8366 /*! @name MCR - SAI MCLK Control Register */
<> 144:ef7eb2e8f9f7 8367 #define I2S_MCR_MICS_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8368 #define I2S_MCR_MICS_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8369 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
<> 144:ef7eb2e8f9f7 8370 #define I2S_MCR_MOE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 8371 #define I2S_MCR_MOE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 8372 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
<> 144:ef7eb2e8f9f7 8373 #define I2S_MCR_DUF_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 8374 #define I2S_MCR_DUF_SHIFT (31U)
<> 144:ef7eb2e8f9f7 8375 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
<> 144:ef7eb2e8f9f7 8376
<> 144:ef7eb2e8f9f7 8377 /*! @name MDR - SAI MCLK Divide Register */
<> 144:ef7eb2e8f9f7 8378 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
<> 144:ef7eb2e8f9f7 8379 #define I2S_MDR_DIVIDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8380 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
<> 144:ef7eb2e8f9f7 8381 #define I2S_MDR_FRACT_MASK (0xFF000U)
<> 144:ef7eb2e8f9f7 8382 #define I2S_MDR_FRACT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 8383 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
<> 144:ef7eb2e8f9f7 8384
<> 144:ef7eb2e8f9f7 8385
<> 144:ef7eb2e8f9f7 8386 /*!
<> 144:ef7eb2e8f9f7 8387 * @}
<> 144:ef7eb2e8f9f7 8388 */ /* end of group I2S_Register_Masks */
<> 144:ef7eb2e8f9f7 8389
<> 144:ef7eb2e8f9f7 8390
<> 144:ef7eb2e8f9f7 8391 /* I2S - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 8392 /** Peripheral I2S0 base address */
<> 144:ef7eb2e8f9f7 8393 #define I2S0_BASE (0x4002F000u)
<> 144:ef7eb2e8f9f7 8394 /** Peripheral I2S0 base pointer */
<> 144:ef7eb2e8f9f7 8395 #define I2S0 ((I2S_Type *)I2S0_BASE)
<> 144:ef7eb2e8f9f7 8396 /** Array initializer of I2S peripheral base addresses */
<> 144:ef7eb2e8f9f7 8397 #define I2S_BASE_ADDRS { I2S0_BASE }
<> 144:ef7eb2e8f9f7 8398 /** Array initializer of I2S peripheral base pointers */
<> 144:ef7eb2e8f9f7 8399 #define I2S_BASE_PTRS { I2S0 }
<> 144:ef7eb2e8f9f7 8400 /** Interrupt vectors for the I2S peripheral type */
<> 144:ef7eb2e8f9f7 8401 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
<> 144:ef7eb2e8f9f7 8402 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
<> 144:ef7eb2e8f9f7 8403
<> 144:ef7eb2e8f9f7 8404 /*!
<> 144:ef7eb2e8f9f7 8405 * @}
<> 144:ef7eb2e8f9f7 8406 */ /* end of group I2S_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 8407
<> 144:ef7eb2e8f9f7 8408
<> 144:ef7eb2e8f9f7 8409 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8410 -- LLWU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 8411 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8412
<> 144:ef7eb2e8f9f7 8413 /*!
<> 144:ef7eb2e8f9f7 8414 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 8415 * @{
<> 144:ef7eb2e8f9f7 8416 */
<> 144:ef7eb2e8f9f7 8417
<> 144:ef7eb2e8f9f7 8418 /** LLWU - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 8419 typedef struct {
<> 144:ef7eb2e8f9f7 8420 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 8421 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 8422 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 8423 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 8424 __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 8425 __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 8426 __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 8427 __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 8428 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 8429 __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
<> 144:ef7eb2e8f9f7 8430 __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
<> 144:ef7eb2e8f9f7 8431 __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
<> 144:ef7eb2e8f9f7 8432 __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
<> 144:ef7eb2e8f9f7 8433 __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
<> 144:ef7eb2e8f9f7 8434 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
<> 144:ef7eb2e8f9f7 8435 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
<> 144:ef7eb2e8f9f7 8436 __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 8437 __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */
<> 144:ef7eb2e8f9f7 8438 } LLWU_Type;
<> 144:ef7eb2e8f9f7 8439
<> 144:ef7eb2e8f9f7 8440 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8441 -- LLWU Register Masks
<> 144:ef7eb2e8f9f7 8442 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8443
<> 144:ef7eb2e8f9f7 8444 /*!
<> 144:ef7eb2e8f9f7 8445 * @addtogroup LLWU_Register_Masks LLWU Register Masks
<> 144:ef7eb2e8f9f7 8446 * @{
<> 144:ef7eb2e8f9f7 8447 */
<> 144:ef7eb2e8f9f7 8448
<> 144:ef7eb2e8f9f7 8449 /*! @name PE1 - LLWU Pin Enable 1 register */
<> 144:ef7eb2e8f9f7 8450 #define LLWU_PE1_WUPE0_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8451 #define LLWU_PE1_WUPE0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8452 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
<> 144:ef7eb2e8f9f7 8453 #define LLWU_PE1_WUPE1_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8454 #define LLWU_PE1_WUPE1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8455 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
<> 144:ef7eb2e8f9f7 8456 #define LLWU_PE1_WUPE2_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8457 #define LLWU_PE1_WUPE2_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8458 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
<> 144:ef7eb2e8f9f7 8459 #define LLWU_PE1_WUPE3_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8460 #define LLWU_PE1_WUPE3_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8461 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
<> 144:ef7eb2e8f9f7 8462
<> 144:ef7eb2e8f9f7 8463 /*! @name PE2 - LLWU Pin Enable 2 register */
<> 144:ef7eb2e8f9f7 8464 #define LLWU_PE2_WUPE4_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8465 #define LLWU_PE2_WUPE4_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8466 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
<> 144:ef7eb2e8f9f7 8467 #define LLWU_PE2_WUPE5_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8468 #define LLWU_PE2_WUPE5_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8469 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
<> 144:ef7eb2e8f9f7 8470 #define LLWU_PE2_WUPE6_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8471 #define LLWU_PE2_WUPE6_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8472 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
<> 144:ef7eb2e8f9f7 8473 #define LLWU_PE2_WUPE7_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8474 #define LLWU_PE2_WUPE7_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8475 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
<> 144:ef7eb2e8f9f7 8476
<> 144:ef7eb2e8f9f7 8477 /*! @name PE3 - LLWU Pin Enable 3 register */
<> 144:ef7eb2e8f9f7 8478 #define LLWU_PE3_WUPE8_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8479 #define LLWU_PE3_WUPE8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8480 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
<> 144:ef7eb2e8f9f7 8481 #define LLWU_PE3_WUPE9_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8482 #define LLWU_PE3_WUPE9_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8483 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
<> 144:ef7eb2e8f9f7 8484 #define LLWU_PE3_WUPE10_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8485 #define LLWU_PE3_WUPE10_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8486 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
<> 144:ef7eb2e8f9f7 8487 #define LLWU_PE3_WUPE11_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8488 #define LLWU_PE3_WUPE11_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8489 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
<> 144:ef7eb2e8f9f7 8490
<> 144:ef7eb2e8f9f7 8491 /*! @name PE4 - LLWU Pin Enable 4 register */
<> 144:ef7eb2e8f9f7 8492 #define LLWU_PE4_WUPE12_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8493 #define LLWU_PE4_WUPE12_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8494 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
<> 144:ef7eb2e8f9f7 8495 #define LLWU_PE4_WUPE13_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8496 #define LLWU_PE4_WUPE13_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8497 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
<> 144:ef7eb2e8f9f7 8498 #define LLWU_PE4_WUPE14_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8499 #define LLWU_PE4_WUPE14_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8500 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
<> 144:ef7eb2e8f9f7 8501 #define LLWU_PE4_WUPE15_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8502 #define LLWU_PE4_WUPE15_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8503 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
<> 144:ef7eb2e8f9f7 8504
<> 144:ef7eb2e8f9f7 8505 /*! @name PE5 - LLWU Pin Enable 5 register */
<> 144:ef7eb2e8f9f7 8506 #define LLWU_PE5_WUPE16_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8507 #define LLWU_PE5_WUPE16_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8508 #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
<> 144:ef7eb2e8f9f7 8509 #define LLWU_PE5_WUPE17_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8510 #define LLWU_PE5_WUPE17_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8511 #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
<> 144:ef7eb2e8f9f7 8512 #define LLWU_PE5_WUPE18_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8513 #define LLWU_PE5_WUPE18_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8514 #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
<> 144:ef7eb2e8f9f7 8515 #define LLWU_PE5_WUPE19_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8516 #define LLWU_PE5_WUPE19_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8517 #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
<> 144:ef7eb2e8f9f7 8518
<> 144:ef7eb2e8f9f7 8519 /*! @name PE6 - LLWU Pin Enable 6 register */
<> 144:ef7eb2e8f9f7 8520 #define LLWU_PE6_WUPE20_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8521 #define LLWU_PE6_WUPE20_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8522 #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
<> 144:ef7eb2e8f9f7 8523 #define LLWU_PE6_WUPE21_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8524 #define LLWU_PE6_WUPE21_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8525 #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
<> 144:ef7eb2e8f9f7 8526 #define LLWU_PE6_WUPE22_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8527 #define LLWU_PE6_WUPE22_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8528 #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
<> 144:ef7eb2e8f9f7 8529 #define LLWU_PE6_WUPE23_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8530 #define LLWU_PE6_WUPE23_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8531 #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
<> 144:ef7eb2e8f9f7 8532
<> 144:ef7eb2e8f9f7 8533 /*! @name PE7 - LLWU Pin Enable 7 register */
<> 144:ef7eb2e8f9f7 8534 #define LLWU_PE7_WUPE24_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8535 #define LLWU_PE7_WUPE24_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8536 #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
<> 144:ef7eb2e8f9f7 8537 #define LLWU_PE7_WUPE25_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8538 #define LLWU_PE7_WUPE25_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8539 #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
<> 144:ef7eb2e8f9f7 8540 #define LLWU_PE7_WUPE26_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8541 #define LLWU_PE7_WUPE26_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8542 #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
<> 144:ef7eb2e8f9f7 8543 #define LLWU_PE7_WUPE27_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8544 #define LLWU_PE7_WUPE27_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8545 #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
<> 144:ef7eb2e8f9f7 8546
<> 144:ef7eb2e8f9f7 8547 /*! @name PE8 - LLWU Pin Enable 8 register */
<> 144:ef7eb2e8f9f7 8548 #define LLWU_PE8_WUPE28_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8549 #define LLWU_PE8_WUPE28_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8550 #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
<> 144:ef7eb2e8f9f7 8551 #define LLWU_PE8_WUPE29_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8552 #define LLWU_PE8_WUPE29_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8553 #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
<> 144:ef7eb2e8f9f7 8554 #define LLWU_PE8_WUPE30_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8555 #define LLWU_PE8_WUPE30_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8556 #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
<> 144:ef7eb2e8f9f7 8557 #define LLWU_PE8_WUPE31_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8558 #define LLWU_PE8_WUPE31_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8559 #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
<> 144:ef7eb2e8f9f7 8560
<> 144:ef7eb2e8f9f7 8561 /*! @name ME - LLWU Module Enable register */
<> 144:ef7eb2e8f9f7 8562 #define LLWU_ME_WUME0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8563 #define LLWU_ME_WUME0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8564 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
<> 144:ef7eb2e8f9f7 8565 #define LLWU_ME_WUME1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8566 #define LLWU_ME_WUME1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8567 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
<> 144:ef7eb2e8f9f7 8568 #define LLWU_ME_WUME2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8569 #define LLWU_ME_WUME2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8570 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
<> 144:ef7eb2e8f9f7 8571 #define LLWU_ME_WUME3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8572 #define LLWU_ME_WUME3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8573 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
<> 144:ef7eb2e8f9f7 8574 #define LLWU_ME_WUME4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8575 #define LLWU_ME_WUME4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8576 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
<> 144:ef7eb2e8f9f7 8577 #define LLWU_ME_WUME5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 8578 #define LLWU_ME_WUME5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8579 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
<> 144:ef7eb2e8f9f7 8580 #define LLWU_ME_WUME6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 8581 #define LLWU_ME_WUME6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8582 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
<> 144:ef7eb2e8f9f7 8583 #define LLWU_ME_WUME7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8584 #define LLWU_ME_WUME7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8585 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
<> 144:ef7eb2e8f9f7 8586
<> 144:ef7eb2e8f9f7 8587 /*! @name PF1 - LLWU Pin Flag 1 register */
<> 144:ef7eb2e8f9f7 8588 #define LLWU_PF1_WUF0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8589 #define LLWU_PF1_WUF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8590 #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
<> 144:ef7eb2e8f9f7 8591 #define LLWU_PF1_WUF1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8592 #define LLWU_PF1_WUF1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8593 #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
<> 144:ef7eb2e8f9f7 8594 #define LLWU_PF1_WUF2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8595 #define LLWU_PF1_WUF2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8596 #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
<> 144:ef7eb2e8f9f7 8597 #define LLWU_PF1_WUF3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8598 #define LLWU_PF1_WUF3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8599 #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
<> 144:ef7eb2e8f9f7 8600 #define LLWU_PF1_WUF4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8601 #define LLWU_PF1_WUF4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8602 #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
<> 144:ef7eb2e8f9f7 8603 #define LLWU_PF1_WUF5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 8604 #define LLWU_PF1_WUF5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8605 #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
<> 144:ef7eb2e8f9f7 8606 #define LLWU_PF1_WUF6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 8607 #define LLWU_PF1_WUF6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8608 #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
<> 144:ef7eb2e8f9f7 8609 #define LLWU_PF1_WUF7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8610 #define LLWU_PF1_WUF7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8611 #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
<> 144:ef7eb2e8f9f7 8612
<> 144:ef7eb2e8f9f7 8613 /*! @name PF2 - LLWU Pin Flag 2 register */
<> 144:ef7eb2e8f9f7 8614 #define LLWU_PF2_WUF8_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8615 #define LLWU_PF2_WUF8_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8616 #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
<> 144:ef7eb2e8f9f7 8617 #define LLWU_PF2_WUF9_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8618 #define LLWU_PF2_WUF9_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8619 #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
<> 144:ef7eb2e8f9f7 8620 #define LLWU_PF2_WUF10_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8621 #define LLWU_PF2_WUF10_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8622 #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
<> 144:ef7eb2e8f9f7 8623 #define LLWU_PF2_WUF11_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8624 #define LLWU_PF2_WUF11_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8625 #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
<> 144:ef7eb2e8f9f7 8626 #define LLWU_PF2_WUF12_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8627 #define LLWU_PF2_WUF12_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8628 #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
<> 144:ef7eb2e8f9f7 8629 #define LLWU_PF2_WUF13_MASK (0x20U)
<> 144:ef7eb2e8f9f7 8630 #define LLWU_PF2_WUF13_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8631 #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
<> 144:ef7eb2e8f9f7 8632 #define LLWU_PF2_WUF14_MASK (0x40U)
<> 144:ef7eb2e8f9f7 8633 #define LLWU_PF2_WUF14_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8634 #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
<> 144:ef7eb2e8f9f7 8635 #define LLWU_PF2_WUF15_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8636 #define LLWU_PF2_WUF15_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8637 #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
<> 144:ef7eb2e8f9f7 8638
<> 144:ef7eb2e8f9f7 8639 /*! @name PF3 - LLWU Pin Flag 3 register */
<> 144:ef7eb2e8f9f7 8640 #define LLWU_PF3_WUF16_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8641 #define LLWU_PF3_WUF16_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8642 #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
<> 144:ef7eb2e8f9f7 8643 #define LLWU_PF3_WUF17_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8644 #define LLWU_PF3_WUF17_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8645 #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
<> 144:ef7eb2e8f9f7 8646 #define LLWU_PF3_WUF18_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8647 #define LLWU_PF3_WUF18_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8648 #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
<> 144:ef7eb2e8f9f7 8649 #define LLWU_PF3_WUF19_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8650 #define LLWU_PF3_WUF19_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8651 #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
<> 144:ef7eb2e8f9f7 8652 #define LLWU_PF3_WUF20_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8653 #define LLWU_PF3_WUF20_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8654 #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
<> 144:ef7eb2e8f9f7 8655 #define LLWU_PF3_WUF21_MASK (0x20U)
<> 144:ef7eb2e8f9f7 8656 #define LLWU_PF3_WUF21_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8657 #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
<> 144:ef7eb2e8f9f7 8658 #define LLWU_PF3_WUF22_MASK (0x40U)
<> 144:ef7eb2e8f9f7 8659 #define LLWU_PF3_WUF22_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8660 #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
<> 144:ef7eb2e8f9f7 8661 #define LLWU_PF3_WUF23_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8662 #define LLWU_PF3_WUF23_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8663 #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
<> 144:ef7eb2e8f9f7 8664
<> 144:ef7eb2e8f9f7 8665 /*! @name PF4 - LLWU Pin Flag 4 register */
<> 144:ef7eb2e8f9f7 8666 #define LLWU_PF4_WUF24_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8667 #define LLWU_PF4_WUF24_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8668 #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
<> 144:ef7eb2e8f9f7 8669 #define LLWU_PF4_WUF25_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8670 #define LLWU_PF4_WUF25_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8671 #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
<> 144:ef7eb2e8f9f7 8672 #define LLWU_PF4_WUF26_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8673 #define LLWU_PF4_WUF26_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8674 #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
<> 144:ef7eb2e8f9f7 8675 #define LLWU_PF4_WUF27_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8676 #define LLWU_PF4_WUF27_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8677 #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
<> 144:ef7eb2e8f9f7 8678 #define LLWU_PF4_WUF28_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8679 #define LLWU_PF4_WUF28_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8680 #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
<> 144:ef7eb2e8f9f7 8681 #define LLWU_PF4_WUF29_MASK (0x20U)
<> 144:ef7eb2e8f9f7 8682 #define LLWU_PF4_WUF29_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8683 #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
<> 144:ef7eb2e8f9f7 8684 #define LLWU_PF4_WUF30_MASK (0x40U)
<> 144:ef7eb2e8f9f7 8685 #define LLWU_PF4_WUF30_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8686 #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
<> 144:ef7eb2e8f9f7 8687 #define LLWU_PF4_WUF31_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8688 #define LLWU_PF4_WUF31_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8689 #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
<> 144:ef7eb2e8f9f7 8690
<> 144:ef7eb2e8f9f7 8691 /*! @name MF5 - LLWU Module Flag 5 register */
<> 144:ef7eb2e8f9f7 8692 #define LLWU_MF5_MWUF0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8693 #define LLWU_MF5_MWUF0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8694 #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
<> 144:ef7eb2e8f9f7 8695 #define LLWU_MF5_MWUF1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8696 #define LLWU_MF5_MWUF1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8697 #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
<> 144:ef7eb2e8f9f7 8698 #define LLWU_MF5_MWUF2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8699 #define LLWU_MF5_MWUF2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8700 #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
<> 144:ef7eb2e8f9f7 8701 #define LLWU_MF5_MWUF3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8702 #define LLWU_MF5_MWUF3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8703 #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
<> 144:ef7eb2e8f9f7 8704 #define LLWU_MF5_MWUF4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 8705 #define LLWU_MF5_MWUF4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8706 #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
<> 144:ef7eb2e8f9f7 8707 #define LLWU_MF5_MWUF5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 8708 #define LLWU_MF5_MWUF5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8709 #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
<> 144:ef7eb2e8f9f7 8710 #define LLWU_MF5_MWUF6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 8711 #define LLWU_MF5_MWUF6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8712 #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
<> 144:ef7eb2e8f9f7 8713 #define LLWU_MF5_MWUF7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8714 #define LLWU_MF5_MWUF7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8715 #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
<> 144:ef7eb2e8f9f7 8716
<> 144:ef7eb2e8f9f7 8717 /*! @name FILT1 - LLWU Pin Filter 1 register */
<> 144:ef7eb2e8f9f7 8718 #define LLWU_FILT1_FILTSEL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 8719 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8720 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
<> 144:ef7eb2e8f9f7 8721 #define LLWU_FILT1_FILTE_MASK (0x60U)
<> 144:ef7eb2e8f9f7 8722 #define LLWU_FILT1_FILTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8723 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
<> 144:ef7eb2e8f9f7 8724 #define LLWU_FILT1_FILTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8725 #define LLWU_FILT1_FILTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8726 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
<> 144:ef7eb2e8f9f7 8727
<> 144:ef7eb2e8f9f7 8728 /*! @name FILT2 - LLWU Pin Filter 2 register */
<> 144:ef7eb2e8f9f7 8729 #define LLWU_FILT2_FILTSEL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 8730 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8731 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
<> 144:ef7eb2e8f9f7 8732 #define LLWU_FILT2_FILTE_MASK (0x60U)
<> 144:ef7eb2e8f9f7 8733 #define LLWU_FILT2_FILTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8734 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
<> 144:ef7eb2e8f9f7 8735 #define LLWU_FILT2_FILTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8736 #define LLWU_FILT2_FILTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8737 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
<> 144:ef7eb2e8f9f7 8738
<> 144:ef7eb2e8f9f7 8739 /*! @name FILT3 - LLWU Pin Filter 3 register */
<> 144:ef7eb2e8f9f7 8740 #define LLWU_FILT3_FILTSEL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 8741 #define LLWU_FILT3_FILTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8742 #define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
<> 144:ef7eb2e8f9f7 8743 #define LLWU_FILT3_FILTE_MASK (0x60U)
<> 144:ef7eb2e8f9f7 8744 #define LLWU_FILT3_FILTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8745 #define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
<> 144:ef7eb2e8f9f7 8746 #define LLWU_FILT3_FILTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8747 #define LLWU_FILT3_FILTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8748 #define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
<> 144:ef7eb2e8f9f7 8749
<> 144:ef7eb2e8f9f7 8750 /*! @name FILT4 - LLWU Pin Filter 4 register */
<> 144:ef7eb2e8f9f7 8751 #define LLWU_FILT4_FILTSEL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 8752 #define LLWU_FILT4_FILTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8753 #define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
<> 144:ef7eb2e8f9f7 8754 #define LLWU_FILT4_FILTE_MASK (0x60U)
<> 144:ef7eb2e8f9f7 8755 #define LLWU_FILT4_FILTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 8756 #define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
<> 144:ef7eb2e8f9f7 8757 #define LLWU_FILT4_FILTF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 8758 #define LLWU_FILT4_FILTF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 8759 #define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
<> 144:ef7eb2e8f9f7 8760
<> 144:ef7eb2e8f9f7 8761
<> 144:ef7eb2e8f9f7 8762 /*!
<> 144:ef7eb2e8f9f7 8763 * @}
<> 144:ef7eb2e8f9f7 8764 */ /* end of group LLWU_Register_Masks */
<> 144:ef7eb2e8f9f7 8765
<> 144:ef7eb2e8f9f7 8766
<> 144:ef7eb2e8f9f7 8767 /* LLWU - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 8768 /** Peripheral LLWU base address */
<> 144:ef7eb2e8f9f7 8769 #define LLWU_BASE (0x4007C000u)
<> 144:ef7eb2e8f9f7 8770 /** Peripheral LLWU base pointer */
<> 144:ef7eb2e8f9f7 8771 #define LLWU ((LLWU_Type *)LLWU_BASE)
<> 144:ef7eb2e8f9f7 8772 /** Array initializer of LLWU peripheral base addresses */
<> 144:ef7eb2e8f9f7 8773 #define LLWU_BASE_ADDRS { LLWU_BASE }
<> 144:ef7eb2e8f9f7 8774 /** Array initializer of LLWU peripheral base pointers */
<> 144:ef7eb2e8f9f7 8775 #define LLWU_BASE_PTRS { LLWU }
<> 144:ef7eb2e8f9f7 8776 /** Interrupt vectors for the LLWU peripheral type */
<> 144:ef7eb2e8f9f7 8777 #define LLWU_IRQS { LLWU_IRQn }
<> 144:ef7eb2e8f9f7 8778
<> 144:ef7eb2e8f9f7 8779 /*!
<> 144:ef7eb2e8f9f7 8780 * @}
<> 144:ef7eb2e8f9f7 8781 */ /* end of group LLWU_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 8782
<> 144:ef7eb2e8f9f7 8783
<> 144:ef7eb2e8f9f7 8784 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8785 -- LMEM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 8786 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8787
<> 144:ef7eb2e8f9f7 8788 /*!
<> 144:ef7eb2e8f9f7 8789 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 8790 * @{
<> 144:ef7eb2e8f9f7 8791 */
<> 144:ef7eb2e8f9f7 8792
<> 144:ef7eb2e8f9f7 8793 /** LMEM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 8794 typedef struct {
<> 144:ef7eb2e8f9f7 8795 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 8796 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 8797 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 8798 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
<> 144:ef7eb2e8f9f7 8799 uint8_t RESERVED_0[16];
<> 144:ef7eb2e8f9f7 8800 __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 8801 } LMEM_Type;
<> 144:ef7eb2e8f9f7 8802
<> 144:ef7eb2e8f9f7 8803 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8804 -- LMEM Register Masks
<> 144:ef7eb2e8f9f7 8805 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8806
<> 144:ef7eb2e8f9f7 8807 /*!
<> 144:ef7eb2e8f9f7 8808 * @addtogroup LMEM_Register_Masks LMEM Register Masks
<> 144:ef7eb2e8f9f7 8809 * @{
<> 144:ef7eb2e8f9f7 8810 */
<> 144:ef7eb2e8f9f7 8811
<> 144:ef7eb2e8f9f7 8812 /*! @name PCCCR - Cache control register */
<> 144:ef7eb2e8f9f7 8813 #define LMEM_PCCCR_ENCACHE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8814 #define LMEM_PCCCR_ENCACHE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8815 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
<> 144:ef7eb2e8f9f7 8816 #define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8817 #define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8818 #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
<> 144:ef7eb2e8f9f7 8819 #define LMEM_PCCCR_PCCR2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8820 #define LMEM_PCCCR_PCCR2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8821 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
<> 144:ef7eb2e8f9f7 8822 #define LMEM_PCCCR_PCCR3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8823 #define LMEM_PCCCR_PCCR3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8824 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
<> 144:ef7eb2e8f9f7 8825 #define LMEM_PCCCR_INVW0_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 8826 #define LMEM_PCCCR_INVW0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8827 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
<> 144:ef7eb2e8f9f7 8828 #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 8829 #define LMEM_PCCCR_PUSHW0_SHIFT (25U)
<> 144:ef7eb2e8f9f7 8830 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
<> 144:ef7eb2e8f9f7 8831 #define LMEM_PCCCR_INVW1_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 8832 #define LMEM_PCCCR_INVW1_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8833 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
<> 144:ef7eb2e8f9f7 8834 #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 8835 #define LMEM_PCCCR_PUSHW1_SHIFT (27U)
<> 144:ef7eb2e8f9f7 8836 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
<> 144:ef7eb2e8f9f7 8837 #define LMEM_PCCCR_GO_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 8838 #define LMEM_PCCCR_GO_SHIFT (31U)
<> 144:ef7eb2e8f9f7 8839 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
<> 144:ef7eb2e8f9f7 8840
<> 144:ef7eb2e8f9f7 8841 /*! @name PCCLCR - Cache line control register */
<> 144:ef7eb2e8f9f7 8842 #define LMEM_PCCLCR_LGO_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8843 #define LMEM_PCCLCR_LGO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8844 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
<> 144:ef7eb2e8f9f7 8845 #define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
<> 144:ef7eb2e8f9f7 8846 #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8847 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
<> 144:ef7eb2e8f9f7 8848 #define LMEM_PCCLCR_WSEL_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 8849 #define LMEM_PCCLCR_WSEL_SHIFT (14U)
<> 144:ef7eb2e8f9f7 8850 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
<> 144:ef7eb2e8f9f7 8851 #define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 8852 #define LMEM_PCCLCR_TDSEL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8853 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
<> 144:ef7eb2e8f9f7 8854 #define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 8855 #define LMEM_PCCLCR_LCIVB_SHIFT (20U)
<> 144:ef7eb2e8f9f7 8856 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
<> 144:ef7eb2e8f9f7 8857 #define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 8858 #define LMEM_PCCLCR_LCIMB_SHIFT (21U)
<> 144:ef7eb2e8f9f7 8859 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
<> 144:ef7eb2e8f9f7 8860 #define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 8861 #define LMEM_PCCLCR_LCWAY_SHIFT (22U)
<> 144:ef7eb2e8f9f7 8862 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
<> 144:ef7eb2e8f9f7 8863 #define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8864 #define LMEM_PCCLCR_LCMD_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8865 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
<> 144:ef7eb2e8f9f7 8866 #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 8867 #define LMEM_PCCLCR_LADSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8868 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
<> 144:ef7eb2e8f9f7 8869 #define LMEM_PCCLCR_LACC_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 8870 #define LMEM_PCCLCR_LACC_SHIFT (27U)
<> 144:ef7eb2e8f9f7 8871 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
<> 144:ef7eb2e8f9f7 8872
<> 144:ef7eb2e8f9f7 8873 /*! @name PCCSAR - Cache search address register */
<> 144:ef7eb2e8f9f7 8874 #define LMEM_PCCSAR_LGO_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8875 #define LMEM_PCCSAR_LGO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8876 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
<> 144:ef7eb2e8f9f7 8877 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
<> 144:ef7eb2e8f9f7 8878 #define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8879 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
<> 144:ef7eb2e8f9f7 8880
<> 144:ef7eb2e8f9f7 8881 /*! @name PCCCVR - Cache read/write value register */
<> 144:ef7eb2e8f9f7 8882 #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 8883 #define LMEM_PCCCVR_DATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8884 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
<> 144:ef7eb2e8f9f7 8885
<> 144:ef7eb2e8f9f7 8886 /*! @name PCCRMR - Cache regions mode register */
<> 144:ef7eb2e8f9f7 8887 #define LMEM_PCCRMR_R15_MASK (0x3U)
<> 144:ef7eb2e8f9f7 8888 #define LMEM_PCCRMR_R15_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8889 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
<> 144:ef7eb2e8f9f7 8890 #define LMEM_PCCRMR_R14_MASK (0xCU)
<> 144:ef7eb2e8f9f7 8891 #define LMEM_PCCRMR_R14_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8892 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
<> 144:ef7eb2e8f9f7 8893 #define LMEM_PCCRMR_R13_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8894 #define LMEM_PCCRMR_R13_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8895 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
<> 144:ef7eb2e8f9f7 8896 #define LMEM_PCCRMR_R12_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 8897 #define LMEM_PCCRMR_R12_SHIFT (6U)
<> 144:ef7eb2e8f9f7 8898 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
<> 144:ef7eb2e8f9f7 8899 #define LMEM_PCCRMR_R11_MASK (0x300U)
<> 144:ef7eb2e8f9f7 8900 #define LMEM_PCCRMR_R11_SHIFT (8U)
<> 144:ef7eb2e8f9f7 8901 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
<> 144:ef7eb2e8f9f7 8902 #define LMEM_PCCRMR_R10_MASK (0xC00U)
<> 144:ef7eb2e8f9f7 8903 #define LMEM_PCCRMR_R10_SHIFT (10U)
<> 144:ef7eb2e8f9f7 8904 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
<> 144:ef7eb2e8f9f7 8905 #define LMEM_PCCRMR_R9_MASK (0x3000U)
<> 144:ef7eb2e8f9f7 8906 #define LMEM_PCCRMR_R9_SHIFT (12U)
<> 144:ef7eb2e8f9f7 8907 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
<> 144:ef7eb2e8f9f7 8908 #define LMEM_PCCRMR_R8_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 8909 #define LMEM_PCCRMR_R8_SHIFT (14U)
<> 144:ef7eb2e8f9f7 8910 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
<> 144:ef7eb2e8f9f7 8911 #define LMEM_PCCRMR_R7_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 8912 #define LMEM_PCCRMR_R7_SHIFT (16U)
<> 144:ef7eb2e8f9f7 8913 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
<> 144:ef7eb2e8f9f7 8914 #define LMEM_PCCRMR_R6_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 8915 #define LMEM_PCCRMR_R6_SHIFT (18U)
<> 144:ef7eb2e8f9f7 8916 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
<> 144:ef7eb2e8f9f7 8917 #define LMEM_PCCRMR_R5_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 8918 #define LMEM_PCCRMR_R5_SHIFT (20U)
<> 144:ef7eb2e8f9f7 8919 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
<> 144:ef7eb2e8f9f7 8920 #define LMEM_PCCRMR_R4_MASK (0xC00000U)
<> 144:ef7eb2e8f9f7 8921 #define LMEM_PCCRMR_R4_SHIFT (22U)
<> 144:ef7eb2e8f9f7 8922 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
<> 144:ef7eb2e8f9f7 8923 #define LMEM_PCCRMR_R3_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 8924 #define LMEM_PCCRMR_R3_SHIFT (24U)
<> 144:ef7eb2e8f9f7 8925 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
<> 144:ef7eb2e8f9f7 8926 #define LMEM_PCCRMR_R2_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 8927 #define LMEM_PCCRMR_R2_SHIFT (26U)
<> 144:ef7eb2e8f9f7 8928 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
<> 144:ef7eb2e8f9f7 8929 #define LMEM_PCCRMR_R1_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 8930 #define LMEM_PCCRMR_R1_SHIFT (28U)
<> 144:ef7eb2e8f9f7 8931 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
<> 144:ef7eb2e8f9f7 8932 #define LMEM_PCCRMR_R0_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 8933 #define LMEM_PCCRMR_R0_SHIFT (30U)
<> 144:ef7eb2e8f9f7 8934 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
<> 144:ef7eb2e8f9f7 8935
<> 144:ef7eb2e8f9f7 8936
<> 144:ef7eb2e8f9f7 8937 /*!
<> 144:ef7eb2e8f9f7 8938 * @}
<> 144:ef7eb2e8f9f7 8939 */ /* end of group LMEM_Register_Masks */
<> 144:ef7eb2e8f9f7 8940
<> 144:ef7eb2e8f9f7 8941
<> 144:ef7eb2e8f9f7 8942 /* LMEM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 8943 /** Peripheral LMEM base address */
<> 144:ef7eb2e8f9f7 8944 #define LMEM_BASE (0xE0082000u)
<> 144:ef7eb2e8f9f7 8945 /** Peripheral LMEM base pointer */
<> 144:ef7eb2e8f9f7 8946 #define LMEM ((LMEM_Type *)LMEM_BASE)
<> 144:ef7eb2e8f9f7 8947 /** Array initializer of LMEM peripheral base addresses */
<> 144:ef7eb2e8f9f7 8948 #define LMEM_BASE_ADDRS { LMEM_BASE }
<> 144:ef7eb2e8f9f7 8949 /** Array initializer of LMEM peripheral base pointers */
<> 144:ef7eb2e8f9f7 8950 #define LMEM_BASE_PTRS { LMEM }
<> 144:ef7eb2e8f9f7 8951
<> 144:ef7eb2e8f9f7 8952 /*!
<> 144:ef7eb2e8f9f7 8953 * @}
<> 144:ef7eb2e8f9f7 8954 */ /* end of group LMEM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 8955
<> 144:ef7eb2e8f9f7 8956
<> 144:ef7eb2e8f9f7 8957 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8958 -- LPTMR Peripheral Access Layer
<> 144:ef7eb2e8f9f7 8959 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8960
<> 144:ef7eb2e8f9f7 8961 /*!
<> 144:ef7eb2e8f9f7 8962 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
<> 144:ef7eb2e8f9f7 8963 * @{
<> 144:ef7eb2e8f9f7 8964 */
<> 144:ef7eb2e8f9f7 8965
<> 144:ef7eb2e8f9f7 8966 /** LPTMR - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 8967 typedef struct {
<> 144:ef7eb2e8f9f7 8968 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 8969 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 8970 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 8971 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 8972 } LPTMR_Type;
<> 144:ef7eb2e8f9f7 8973
<> 144:ef7eb2e8f9f7 8974 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8975 -- LPTMR Register Masks
<> 144:ef7eb2e8f9f7 8976 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 8977
<> 144:ef7eb2e8f9f7 8978 /*!
<> 144:ef7eb2e8f9f7 8979 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
<> 144:ef7eb2e8f9f7 8980 * @{
<> 144:ef7eb2e8f9f7 8981 */
<> 144:ef7eb2e8f9f7 8982
<> 144:ef7eb2e8f9f7 8983 /*! @name CSR - Low Power Timer Control Status Register */
<> 144:ef7eb2e8f9f7 8984 #define LPTMR_CSR_TEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 8985 #define LPTMR_CSR_TEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 8986 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
<> 144:ef7eb2e8f9f7 8987 #define LPTMR_CSR_TMS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 8988 #define LPTMR_CSR_TMS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 8989 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
<> 144:ef7eb2e8f9f7 8990 #define LPTMR_CSR_TFC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 8991 #define LPTMR_CSR_TFC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 8992 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
<> 144:ef7eb2e8f9f7 8993 #define LPTMR_CSR_TPP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 8994 #define LPTMR_CSR_TPP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 8995 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
<> 144:ef7eb2e8f9f7 8996 #define LPTMR_CSR_TPS_MASK (0x30U)
<> 144:ef7eb2e8f9f7 8997 #define LPTMR_CSR_TPS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 8998 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
<> 144:ef7eb2e8f9f7 8999 #define LPTMR_CSR_TIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9000 #define LPTMR_CSR_TIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9001 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
<> 144:ef7eb2e8f9f7 9002 #define LPTMR_CSR_TCF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9003 #define LPTMR_CSR_TCF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9004 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
<> 144:ef7eb2e8f9f7 9005
<> 144:ef7eb2e8f9f7 9006 /*! @name PSR - Low Power Timer Prescale Register */
<> 144:ef7eb2e8f9f7 9007 #define LPTMR_PSR_PCS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 9008 #define LPTMR_PSR_PCS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9009 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
<> 144:ef7eb2e8f9f7 9010 #define LPTMR_PSR_PBYP_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9011 #define LPTMR_PSR_PBYP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9012 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
<> 144:ef7eb2e8f9f7 9013 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
<> 144:ef7eb2e8f9f7 9014 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9015 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
<> 144:ef7eb2e8f9f7 9016
<> 144:ef7eb2e8f9f7 9017 /*! @name CMR - Low Power Timer Compare Register */
<> 144:ef7eb2e8f9f7 9018 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 9019 #define LPTMR_CMR_COMPARE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9020 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
<> 144:ef7eb2e8f9f7 9021
<> 144:ef7eb2e8f9f7 9022 /*! @name CNR - Low Power Timer Counter Register */
<> 144:ef7eb2e8f9f7 9023 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 9024 #define LPTMR_CNR_COUNTER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9025 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
<> 144:ef7eb2e8f9f7 9026
<> 144:ef7eb2e8f9f7 9027
<> 144:ef7eb2e8f9f7 9028 /*!
<> 144:ef7eb2e8f9f7 9029 * @}
<> 144:ef7eb2e8f9f7 9030 */ /* end of group LPTMR_Register_Masks */
<> 144:ef7eb2e8f9f7 9031
<> 144:ef7eb2e8f9f7 9032
<> 144:ef7eb2e8f9f7 9033 /* LPTMR - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 9034 /** Peripheral LPTMR0 base address */
<> 144:ef7eb2e8f9f7 9035 #define LPTMR0_BASE (0x40040000u)
<> 144:ef7eb2e8f9f7 9036 /** Peripheral LPTMR0 base pointer */
<> 144:ef7eb2e8f9f7 9037 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
<> 144:ef7eb2e8f9f7 9038 /** Array initializer of LPTMR peripheral base addresses */
<> 144:ef7eb2e8f9f7 9039 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
<> 144:ef7eb2e8f9f7 9040 /** Array initializer of LPTMR peripheral base pointers */
<> 144:ef7eb2e8f9f7 9041 #define LPTMR_BASE_PTRS { LPTMR0 }
<> 144:ef7eb2e8f9f7 9042 /** Interrupt vectors for the LPTMR peripheral type */
<> 144:ef7eb2e8f9f7 9043 #define LPTMR_IRQS { LPTMR0_IRQn }
<> 144:ef7eb2e8f9f7 9044
<> 144:ef7eb2e8f9f7 9045 /*!
<> 144:ef7eb2e8f9f7 9046 * @}
<> 144:ef7eb2e8f9f7 9047 */ /* end of group LPTMR_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 9048
<> 144:ef7eb2e8f9f7 9049
<> 144:ef7eb2e8f9f7 9050 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9051 -- LPUART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9052 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9053
<> 144:ef7eb2e8f9f7 9054 /*!
<> 144:ef7eb2e8f9f7 9055 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9056 * @{
<> 144:ef7eb2e8f9f7 9057 */
<> 144:ef7eb2e8f9f7 9058
<> 144:ef7eb2e8f9f7 9059 /** LPUART - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 9060 typedef struct {
<> 144:ef7eb2e8f9f7 9061 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 9062 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 9063 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 9064 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 9065 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 9066 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 9067 } LPUART_Type;
<> 144:ef7eb2e8f9f7 9068
<> 144:ef7eb2e8f9f7 9069 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9070 -- LPUART Register Masks
<> 144:ef7eb2e8f9f7 9071 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9072
<> 144:ef7eb2e8f9f7 9073 /*!
<> 144:ef7eb2e8f9f7 9074 * @addtogroup LPUART_Register_Masks LPUART Register Masks
<> 144:ef7eb2e8f9f7 9075 * @{
<> 144:ef7eb2e8f9f7 9076 */
<> 144:ef7eb2e8f9f7 9077
<> 144:ef7eb2e8f9f7 9078 /*! @name BAUD - LPUART Baud Rate Register */
<> 144:ef7eb2e8f9f7 9079 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
<> 144:ef7eb2e8f9f7 9080 #define LPUART_BAUD_SBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9081 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
<> 144:ef7eb2e8f9f7 9082 #define LPUART_BAUD_SBNS_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 9083 #define LPUART_BAUD_SBNS_SHIFT (13U)
<> 144:ef7eb2e8f9f7 9084 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
<> 144:ef7eb2e8f9f7 9085 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 9086 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 9087 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
<> 144:ef7eb2e8f9f7 9088 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 9089 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 9090 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
<> 144:ef7eb2e8f9f7 9091 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 9092 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9093 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
<> 144:ef7eb2e8f9f7 9094 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 9095 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 9096 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
<> 144:ef7eb2e8f9f7 9097 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 9098 #define LPUART_BAUD_MATCFG_SHIFT (18U)
<> 144:ef7eb2e8f9f7 9099 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
<> 144:ef7eb2e8f9f7 9100 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 9101 #define LPUART_BAUD_RDMAE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 9102 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
<> 144:ef7eb2e8f9f7 9103 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 9104 #define LPUART_BAUD_TDMAE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 9105 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
<> 144:ef7eb2e8f9f7 9106 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
<> 144:ef7eb2e8f9f7 9107 #define LPUART_BAUD_OSR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9108 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
<> 144:ef7eb2e8f9f7 9109 #define LPUART_BAUD_M10_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 9110 #define LPUART_BAUD_M10_SHIFT (29U)
<> 144:ef7eb2e8f9f7 9111 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
<> 144:ef7eb2e8f9f7 9112 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 9113 #define LPUART_BAUD_MAEN2_SHIFT (30U)
<> 144:ef7eb2e8f9f7 9114 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
<> 144:ef7eb2e8f9f7 9115 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 9116 #define LPUART_BAUD_MAEN1_SHIFT (31U)
<> 144:ef7eb2e8f9f7 9117 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
<> 144:ef7eb2e8f9f7 9118
<> 144:ef7eb2e8f9f7 9119 /*! @name STAT - LPUART Status Register */
<> 144:ef7eb2e8f9f7 9120 #define LPUART_STAT_MA2F_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 9121 #define LPUART_STAT_MA2F_SHIFT (14U)
<> 144:ef7eb2e8f9f7 9122 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
<> 144:ef7eb2e8f9f7 9123 #define LPUART_STAT_MA1F_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 9124 #define LPUART_STAT_MA1F_SHIFT (15U)
<> 144:ef7eb2e8f9f7 9125 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
<> 144:ef7eb2e8f9f7 9126 #define LPUART_STAT_PF_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 9127 #define LPUART_STAT_PF_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9128 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
<> 144:ef7eb2e8f9f7 9129 #define LPUART_STAT_FE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 9130 #define LPUART_STAT_FE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 9131 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
<> 144:ef7eb2e8f9f7 9132 #define LPUART_STAT_NF_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 9133 #define LPUART_STAT_NF_SHIFT (18U)
<> 144:ef7eb2e8f9f7 9134 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
<> 144:ef7eb2e8f9f7 9135 #define LPUART_STAT_OR_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 9136 #define LPUART_STAT_OR_SHIFT (19U)
<> 144:ef7eb2e8f9f7 9137 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
<> 144:ef7eb2e8f9f7 9138 #define LPUART_STAT_IDLE_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 9139 #define LPUART_STAT_IDLE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 9140 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
<> 144:ef7eb2e8f9f7 9141 #define LPUART_STAT_RDRF_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 9142 #define LPUART_STAT_RDRF_SHIFT (21U)
<> 144:ef7eb2e8f9f7 9143 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
<> 144:ef7eb2e8f9f7 9144 #define LPUART_STAT_TC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 9145 #define LPUART_STAT_TC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 9146 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
<> 144:ef7eb2e8f9f7 9147 #define LPUART_STAT_TDRE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 9148 #define LPUART_STAT_TDRE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 9149 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
<> 144:ef7eb2e8f9f7 9150 #define LPUART_STAT_RAF_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 9151 #define LPUART_STAT_RAF_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9152 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
<> 144:ef7eb2e8f9f7 9153 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 9154 #define LPUART_STAT_LBKDE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 9155 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
<> 144:ef7eb2e8f9f7 9156 #define LPUART_STAT_BRK13_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 9157 #define LPUART_STAT_BRK13_SHIFT (26U)
<> 144:ef7eb2e8f9f7 9158 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
<> 144:ef7eb2e8f9f7 9159 #define LPUART_STAT_RWUID_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 9160 #define LPUART_STAT_RWUID_SHIFT (27U)
<> 144:ef7eb2e8f9f7 9161 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
<> 144:ef7eb2e8f9f7 9162 #define LPUART_STAT_RXINV_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 9163 #define LPUART_STAT_RXINV_SHIFT (28U)
<> 144:ef7eb2e8f9f7 9164 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
<> 144:ef7eb2e8f9f7 9165 #define LPUART_STAT_MSBF_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 9166 #define LPUART_STAT_MSBF_SHIFT (29U)
<> 144:ef7eb2e8f9f7 9167 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
<> 144:ef7eb2e8f9f7 9168 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 9169 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
<> 144:ef7eb2e8f9f7 9170 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
<> 144:ef7eb2e8f9f7 9171 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 9172 #define LPUART_STAT_LBKDIF_SHIFT (31U)
<> 144:ef7eb2e8f9f7 9173 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
<> 144:ef7eb2e8f9f7 9174
<> 144:ef7eb2e8f9f7 9175 /*! @name CTRL - LPUART Control Register */
<> 144:ef7eb2e8f9f7 9176 #define LPUART_CTRL_PT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9177 #define LPUART_CTRL_PT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9178 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
<> 144:ef7eb2e8f9f7 9179 #define LPUART_CTRL_PE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9180 #define LPUART_CTRL_PE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9181 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
<> 144:ef7eb2e8f9f7 9182 #define LPUART_CTRL_ILT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9183 #define LPUART_CTRL_ILT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9184 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
<> 144:ef7eb2e8f9f7 9185 #define LPUART_CTRL_WAKE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 9186 #define LPUART_CTRL_WAKE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9187 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
<> 144:ef7eb2e8f9f7 9188 #define LPUART_CTRL_M_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9189 #define LPUART_CTRL_M_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9190 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
<> 144:ef7eb2e8f9f7 9191 #define LPUART_CTRL_RSRC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9192 #define LPUART_CTRL_RSRC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9193 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
<> 144:ef7eb2e8f9f7 9194 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9195 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9196 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
<> 144:ef7eb2e8f9f7 9197 #define LPUART_CTRL_LOOPS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9198 #define LPUART_CTRL_LOOPS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9199 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
<> 144:ef7eb2e8f9f7 9200 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
<> 144:ef7eb2e8f9f7 9201 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
<> 144:ef7eb2e8f9f7 9202 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
<> 144:ef7eb2e8f9f7 9203 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 9204 #define LPUART_CTRL_MA2IE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 9205 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
<> 144:ef7eb2e8f9f7 9206 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 9207 #define LPUART_CTRL_MA1IE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 9208 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
<> 144:ef7eb2e8f9f7 9209 #define LPUART_CTRL_SBK_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 9210 #define LPUART_CTRL_SBK_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9211 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
<> 144:ef7eb2e8f9f7 9212 #define LPUART_CTRL_RWU_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 9213 #define LPUART_CTRL_RWU_SHIFT (17U)
<> 144:ef7eb2e8f9f7 9214 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
<> 144:ef7eb2e8f9f7 9215 #define LPUART_CTRL_RE_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 9216 #define LPUART_CTRL_RE_SHIFT (18U)
<> 144:ef7eb2e8f9f7 9217 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
<> 144:ef7eb2e8f9f7 9218 #define LPUART_CTRL_TE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 9219 #define LPUART_CTRL_TE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 9220 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
<> 144:ef7eb2e8f9f7 9221 #define LPUART_CTRL_ILIE_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 9222 #define LPUART_CTRL_ILIE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 9223 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
<> 144:ef7eb2e8f9f7 9224 #define LPUART_CTRL_RIE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 9225 #define LPUART_CTRL_RIE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 9226 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
<> 144:ef7eb2e8f9f7 9227 #define LPUART_CTRL_TCIE_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 9228 #define LPUART_CTRL_TCIE_SHIFT (22U)
<> 144:ef7eb2e8f9f7 9229 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
<> 144:ef7eb2e8f9f7 9230 #define LPUART_CTRL_TIE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 9231 #define LPUART_CTRL_TIE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 9232 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
<> 144:ef7eb2e8f9f7 9233 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 9234 #define LPUART_CTRL_PEIE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9235 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
<> 144:ef7eb2e8f9f7 9236 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 9237 #define LPUART_CTRL_FEIE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 9238 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
<> 144:ef7eb2e8f9f7 9239 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 9240 #define LPUART_CTRL_NEIE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 9241 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
<> 144:ef7eb2e8f9f7 9242 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 9243 #define LPUART_CTRL_ORIE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 9244 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
<> 144:ef7eb2e8f9f7 9245 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 9246 #define LPUART_CTRL_TXINV_SHIFT (28U)
<> 144:ef7eb2e8f9f7 9247 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
<> 144:ef7eb2e8f9f7 9248 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 9249 #define LPUART_CTRL_TXDIR_SHIFT (29U)
<> 144:ef7eb2e8f9f7 9250 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
<> 144:ef7eb2e8f9f7 9251 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 9252 #define LPUART_CTRL_R9T8_SHIFT (30U)
<> 144:ef7eb2e8f9f7 9253 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
<> 144:ef7eb2e8f9f7 9254 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 9255 #define LPUART_CTRL_R8T9_SHIFT (31U)
<> 144:ef7eb2e8f9f7 9256 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
<> 144:ef7eb2e8f9f7 9257
<> 144:ef7eb2e8f9f7 9258 /*! @name DATA - LPUART Data Register */
<> 144:ef7eb2e8f9f7 9259 #define LPUART_DATA_R0T0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9260 #define LPUART_DATA_R0T0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9261 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
<> 144:ef7eb2e8f9f7 9262 #define LPUART_DATA_R1T1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9263 #define LPUART_DATA_R1T1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9264 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
<> 144:ef7eb2e8f9f7 9265 #define LPUART_DATA_R2T2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9266 #define LPUART_DATA_R2T2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9267 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
<> 144:ef7eb2e8f9f7 9268 #define LPUART_DATA_R3T3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 9269 #define LPUART_DATA_R3T3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9270 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
<> 144:ef7eb2e8f9f7 9271 #define LPUART_DATA_R4T4_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9272 #define LPUART_DATA_R4T4_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9273 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
<> 144:ef7eb2e8f9f7 9274 #define LPUART_DATA_R5T5_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9275 #define LPUART_DATA_R5T5_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9276 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
<> 144:ef7eb2e8f9f7 9277 #define LPUART_DATA_R6T6_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9278 #define LPUART_DATA_R6T6_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9279 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
<> 144:ef7eb2e8f9f7 9280 #define LPUART_DATA_R7T7_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9281 #define LPUART_DATA_R7T7_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9282 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
<> 144:ef7eb2e8f9f7 9283 #define LPUART_DATA_R8T8_MASK (0x100U)
<> 144:ef7eb2e8f9f7 9284 #define LPUART_DATA_R8T8_SHIFT (8U)
<> 144:ef7eb2e8f9f7 9285 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
<> 144:ef7eb2e8f9f7 9286 #define LPUART_DATA_R9T9_MASK (0x200U)
<> 144:ef7eb2e8f9f7 9287 #define LPUART_DATA_R9T9_SHIFT (9U)
<> 144:ef7eb2e8f9f7 9288 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
<> 144:ef7eb2e8f9f7 9289 #define LPUART_DATA_IDLINE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 9290 #define LPUART_DATA_IDLINE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 9291 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
<> 144:ef7eb2e8f9f7 9292 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 9293 #define LPUART_DATA_RXEMPT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 9294 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
<> 144:ef7eb2e8f9f7 9295 #define LPUART_DATA_FRETSC_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 9296 #define LPUART_DATA_FRETSC_SHIFT (13U)
<> 144:ef7eb2e8f9f7 9297 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
<> 144:ef7eb2e8f9f7 9298 #define LPUART_DATA_PARITYE_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 9299 #define LPUART_DATA_PARITYE_SHIFT (14U)
<> 144:ef7eb2e8f9f7 9300 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
<> 144:ef7eb2e8f9f7 9301 #define LPUART_DATA_NOISY_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 9302 #define LPUART_DATA_NOISY_SHIFT (15U)
<> 144:ef7eb2e8f9f7 9303 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
<> 144:ef7eb2e8f9f7 9304
<> 144:ef7eb2e8f9f7 9305 /*! @name MATCH - LPUART Match Address Register */
<> 144:ef7eb2e8f9f7 9306 #define LPUART_MATCH_MA1_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 9307 #define LPUART_MATCH_MA1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9308 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
<> 144:ef7eb2e8f9f7 9309 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 9310 #define LPUART_MATCH_MA2_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9311 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
<> 144:ef7eb2e8f9f7 9312
<> 144:ef7eb2e8f9f7 9313 /*! @name MODIR - LPUART Modem IrDA Register */
<> 144:ef7eb2e8f9f7 9314 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9315 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9316 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
<> 144:ef7eb2e8f9f7 9317 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9318 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9319 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
<> 144:ef7eb2e8f9f7 9320 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9321 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9322 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
<> 144:ef7eb2e8f9f7 9323 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 9324 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9325 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
<> 144:ef7eb2e8f9f7 9326 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9327 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9328 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
<> 144:ef7eb2e8f9f7 9329 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9330 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9331 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
<> 144:ef7eb2e8f9f7 9332 #define LPUART_MODIR_TNP_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 9333 #define LPUART_MODIR_TNP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9334 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
<> 144:ef7eb2e8f9f7 9335 #define LPUART_MODIR_IREN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 9336 #define LPUART_MODIR_IREN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 9337 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
<> 144:ef7eb2e8f9f7 9338
<> 144:ef7eb2e8f9f7 9339
<> 144:ef7eb2e8f9f7 9340 /*!
<> 144:ef7eb2e8f9f7 9341 * @}
<> 144:ef7eb2e8f9f7 9342 */ /* end of group LPUART_Register_Masks */
<> 144:ef7eb2e8f9f7 9343
<> 144:ef7eb2e8f9f7 9344
<> 144:ef7eb2e8f9f7 9345 /* LPUART - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 9346 /** Peripheral LPUART0 base address */
<> 144:ef7eb2e8f9f7 9347 #define LPUART0_BASE (0x400C4000u)
<> 144:ef7eb2e8f9f7 9348 /** Peripheral LPUART0 base pointer */
<> 144:ef7eb2e8f9f7 9349 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
<> 144:ef7eb2e8f9f7 9350 /** Array initializer of LPUART peripheral base addresses */
<> 144:ef7eb2e8f9f7 9351 #define LPUART_BASE_ADDRS { LPUART0_BASE }
<> 144:ef7eb2e8f9f7 9352 /** Array initializer of LPUART peripheral base pointers */
<> 144:ef7eb2e8f9f7 9353 #define LPUART_BASE_PTRS { LPUART0 }
<> 144:ef7eb2e8f9f7 9354 /** Interrupt vectors for the LPUART peripheral type */
<> 144:ef7eb2e8f9f7 9355 #define LPUART_RX_TX_IRQS { LPUART0_IRQn }
<> 144:ef7eb2e8f9f7 9356 #define LPUART_ERR_IRQS { LPUART0_IRQn }
<> 144:ef7eb2e8f9f7 9357
<> 144:ef7eb2e8f9f7 9358 /*!
<> 144:ef7eb2e8f9f7 9359 * @}
<> 144:ef7eb2e8f9f7 9360 */ /* end of group LPUART_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 9361
<> 144:ef7eb2e8f9f7 9362
<> 144:ef7eb2e8f9f7 9363 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9364 -- MCG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9365 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9366
<> 144:ef7eb2e8f9f7 9367 /*!
<> 144:ef7eb2e8f9f7 9368 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9369 * @{
<> 144:ef7eb2e8f9f7 9370 */
<> 144:ef7eb2e8f9f7 9371
<> 144:ef7eb2e8f9f7 9372 /** MCG - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 9373 typedef struct {
<> 144:ef7eb2e8f9f7 9374 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 9375 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 9376 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 9377 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 9378 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 9379 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 9380 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
<> 144:ef7eb2e8f9f7 9381 uint8_t RESERVED_0[1];
<> 144:ef7eb2e8f9f7 9382 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 9383 uint8_t RESERVED_1[1];
<> 144:ef7eb2e8f9f7 9384 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
<> 144:ef7eb2e8f9f7 9385 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
<> 144:ef7eb2e8f9f7 9386 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 9387 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
<> 144:ef7eb2e8f9f7 9388 __IO uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
<> 144:ef7eb2e8f9f7 9389 uint8_t RESERVED_2[1];
<> 144:ef7eb2e8f9f7 9390 __IO uint8_t C11; /**< MCG Control 11 Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 9391 uint8_t RESERVED_3[1];
<> 144:ef7eb2e8f9f7 9392 __I uint8_t S2; /**< MCG Status 2 Register, offset: 0x12 */
<> 144:ef7eb2e8f9f7 9393 } MCG_Type;
<> 144:ef7eb2e8f9f7 9394
<> 144:ef7eb2e8f9f7 9395 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9396 -- MCG Register Masks
<> 144:ef7eb2e8f9f7 9397 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9398
<> 144:ef7eb2e8f9f7 9399 /*!
<> 144:ef7eb2e8f9f7 9400 * @addtogroup MCG_Register_Masks MCG Register Masks
<> 144:ef7eb2e8f9f7 9401 * @{
<> 144:ef7eb2e8f9f7 9402 */
<> 144:ef7eb2e8f9f7 9403
<> 144:ef7eb2e8f9f7 9404 /*! @name C1 - MCG Control 1 Register */
<> 144:ef7eb2e8f9f7 9405 #define MCG_C1_IREFSTEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9406 #define MCG_C1_IREFSTEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9407 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
<> 144:ef7eb2e8f9f7 9408 #define MCG_C1_IRCLKEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9409 #define MCG_C1_IRCLKEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9410 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
<> 144:ef7eb2e8f9f7 9411 #define MCG_C1_IREFS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9412 #define MCG_C1_IREFS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9413 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
<> 144:ef7eb2e8f9f7 9414 #define MCG_C1_FRDIV_MASK (0x38U)
<> 144:ef7eb2e8f9f7 9415 #define MCG_C1_FRDIV_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9416 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
<> 144:ef7eb2e8f9f7 9417 #define MCG_C1_CLKS_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 9418 #define MCG_C1_CLKS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9419 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
<> 144:ef7eb2e8f9f7 9420
<> 144:ef7eb2e8f9f7 9421 /*! @name C2 - MCG Control 2 Register */
<> 144:ef7eb2e8f9f7 9422 #define MCG_C2_IRCS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9423 #define MCG_C2_IRCS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9424 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
<> 144:ef7eb2e8f9f7 9425 #define MCG_C2_LP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9426 #define MCG_C2_LP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9427 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
<> 144:ef7eb2e8f9f7 9428 #define MCG_C2_EREFS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9429 #define MCG_C2_EREFS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9430 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
<> 144:ef7eb2e8f9f7 9431 #define MCG_C2_HGO_MASK (0x8U)
<> 144:ef7eb2e8f9f7 9432 #define MCG_C2_HGO_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9433 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
<> 144:ef7eb2e8f9f7 9434 #define MCG_C2_RANGE_MASK (0x30U)
<> 144:ef7eb2e8f9f7 9435 #define MCG_C2_RANGE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9436 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
<> 144:ef7eb2e8f9f7 9437 #define MCG_C2_FCFTRIM_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9438 #define MCG_C2_FCFTRIM_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9439 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
<> 144:ef7eb2e8f9f7 9440 #define MCG_C2_LOCRE0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9441 #define MCG_C2_LOCRE0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9442 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
<> 144:ef7eb2e8f9f7 9443
<> 144:ef7eb2e8f9f7 9444 /*! @name C3 - MCG Control 3 Register */
<> 144:ef7eb2e8f9f7 9445 #define MCG_C3_SCTRIM_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 9446 #define MCG_C3_SCTRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9447 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
<> 144:ef7eb2e8f9f7 9448
<> 144:ef7eb2e8f9f7 9449 /*! @name C4 - MCG Control 4 Register */
<> 144:ef7eb2e8f9f7 9450 #define MCG_C4_SCFTRIM_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9451 #define MCG_C4_SCFTRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9452 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
<> 144:ef7eb2e8f9f7 9453 #define MCG_C4_FCTRIM_MASK (0x1EU)
<> 144:ef7eb2e8f9f7 9454 #define MCG_C4_FCTRIM_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9455 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
<> 144:ef7eb2e8f9f7 9456 #define MCG_C4_DRST_DRS_MASK (0x60U)
<> 144:ef7eb2e8f9f7 9457 #define MCG_C4_DRST_DRS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9458 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
<> 144:ef7eb2e8f9f7 9459 #define MCG_C4_DMX32_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9460 #define MCG_C4_DMX32_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9461 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
<> 144:ef7eb2e8f9f7 9462
<> 144:ef7eb2e8f9f7 9463 /*! @name C5 - MCG Control 5 Register */
<> 144:ef7eb2e8f9f7 9464 #define MCG_C5_PRDIV_MASK (0x7U)
<> 144:ef7eb2e8f9f7 9465 #define MCG_C5_PRDIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9466 #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
<> 144:ef7eb2e8f9f7 9467 #define MCG_C5_PLLSTEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9468 #define MCG_C5_PLLSTEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9469 #define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
<> 144:ef7eb2e8f9f7 9470 #define MCG_C5_PLLCLKEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9471 #define MCG_C5_PLLCLKEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9472 #define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
<> 144:ef7eb2e8f9f7 9473
<> 144:ef7eb2e8f9f7 9474 /*! @name C6 - MCG Control 6 Register */
<> 144:ef7eb2e8f9f7 9475 #define MCG_C6_VDIV_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 9476 #define MCG_C6_VDIV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9477 #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
<> 144:ef7eb2e8f9f7 9478 #define MCG_C6_CME0_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9479 #define MCG_C6_CME0_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9480 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
<> 144:ef7eb2e8f9f7 9481 #define MCG_C6_PLLS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9482 #define MCG_C6_PLLS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9483 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
<> 144:ef7eb2e8f9f7 9484 #define MCG_C6_LOLIE0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9485 #define MCG_C6_LOLIE0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9486 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
<> 144:ef7eb2e8f9f7 9487
<> 144:ef7eb2e8f9f7 9488 /*! @name S - MCG Status Register */
<> 144:ef7eb2e8f9f7 9489 #define MCG_S_IRCST_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9490 #define MCG_S_IRCST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9491 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
<> 144:ef7eb2e8f9f7 9492 #define MCG_S_OSCINIT0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9493 #define MCG_S_OSCINIT0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9494 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
<> 144:ef7eb2e8f9f7 9495 #define MCG_S_CLKST_MASK (0xCU)
<> 144:ef7eb2e8f9f7 9496 #define MCG_S_CLKST_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9497 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
<> 144:ef7eb2e8f9f7 9498 #define MCG_S_IREFST_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9499 #define MCG_S_IREFST_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9500 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
<> 144:ef7eb2e8f9f7 9501 #define MCG_S_PLLST_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9502 #define MCG_S_PLLST_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9503 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
<> 144:ef7eb2e8f9f7 9504 #define MCG_S_LOCK0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9505 #define MCG_S_LOCK0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9506 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
<> 144:ef7eb2e8f9f7 9507 #define MCG_S_LOLS0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9508 #define MCG_S_LOLS0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9509 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
<> 144:ef7eb2e8f9f7 9510
<> 144:ef7eb2e8f9f7 9511 /*! @name SC - MCG Status and Control Register */
<> 144:ef7eb2e8f9f7 9512 #define MCG_SC_LOCS0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9513 #define MCG_SC_LOCS0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9514 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
<> 144:ef7eb2e8f9f7 9515 #define MCG_SC_FCRDIV_MASK (0xEU)
<> 144:ef7eb2e8f9f7 9516 #define MCG_SC_FCRDIV_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9517 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
<> 144:ef7eb2e8f9f7 9518 #define MCG_SC_FLTPRSRV_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9519 #define MCG_SC_FLTPRSRV_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9520 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
<> 144:ef7eb2e8f9f7 9521 #define MCG_SC_ATMF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9522 #define MCG_SC_ATMF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9523 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
<> 144:ef7eb2e8f9f7 9524 #define MCG_SC_ATMS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9525 #define MCG_SC_ATMS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9526 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
<> 144:ef7eb2e8f9f7 9527 #define MCG_SC_ATME_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9528 #define MCG_SC_ATME_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9529 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
<> 144:ef7eb2e8f9f7 9530
<> 144:ef7eb2e8f9f7 9531 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
<> 144:ef7eb2e8f9f7 9532 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 9533 #define MCG_ATCVH_ATCVH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9534 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
<> 144:ef7eb2e8f9f7 9535
<> 144:ef7eb2e8f9f7 9536 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
<> 144:ef7eb2e8f9f7 9537 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 9538 #define MCG_ATCVL_ATCVL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9539 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
<> 144:ef7eb2e8f9f7 9540
<> 144:ef7eb2e8f9f7 9541 /*! @name C7 - MCG Control 7 Register */
<> 144:ef7eb2e8f9f7 9542 #define MCG_C7_OSCSEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 9543 #define MCG_C7_OSCSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9544 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
<> 144:ef7eb2e8f9f7 9545
<> 144:ef7eb2e8f9f7 9546 /*! @name C8 - MCG Control 8 Register */
<> 144:ef7eb2e8f9f7 9547 #define MCG_C8_LOCS1_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9548 #define MCG_C8_LOCS1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9549 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
<> 144:ef7eb2e8f9f7 9550 #define MCG_C8_CME1_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9551 #define MCG_C8_CME1_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9552 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
<> 144:ef7eb2e8f9f7 9553 #define MCG_C8_LOLRE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 9554 #define MCG_C8_LOLRE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9555 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
<> 144:ef7eb2e8f9f7 9556 #define MCG_C8_LOCRE1_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9557 #define MCG_C8_LOCRE1_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9558 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
<> 144:ef7eb2e8f9f7 9559
<> 144:ef7eb2e8f9f7 9560 /*! @name C9 - MCG Control 9 Register */
<> 144:ef7eb2e8f9f7 9561 #define MCG_C9_EXT_PLL_LOCS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9562 #define MCG_C9_EXT_PLL_LOCS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9563 #define MCG_C9_EXT_PLL_LOCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
<> 144:ef7eb2e8f9f7 9564 #define MCG_C9_PLL_LOCRE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9565 #define MCG_C9_PLL_LOCRE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9566 #define MCG_C9_PLL_LOCRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
<> 144:ef7eb2e8f9f7 9567 #define MCG_C9_PLL_CME_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9568 #define MCG_C9_PLL_CME_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9569 #define MCG_C9_PLL_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
<> 144:ef7eb2e8f9f7 9570
<> 144:ef7eb2e8f9f7 9571 /*! @name C11 - MCG Control 11 Register */
<> 144:ef7eb2e8f9f7 9572 #define MCG_C11_PLLCS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9573 #define MCG_C11_PLLCS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9574 #define MCG_C11_PLLCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
<> 144:ef7eb2e8f9f7 9575
<> 144:ef7eb2e8f9f7 9576 /*! @name S2 - MCG Status 2 Register */
<> 144:ef7eb2e8f9f7 9577 #define MCG_S2_PLLCST_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9578 #define MCG_S2_PLLCST_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9579 #define MCG_S2_PLLCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
<> 144:ef7eb2e8f9f7 9580
<> 144:ef7eb2e8f9f7 9581
<> 144:ef7eb2e8f9f7 9582 /*!
<> 144:ef7eb2e8f9f7 9583 * @}
<> 144:ef7eb2e8f9f7 9584 */ /* end of group MCG_Register_Masks */
<> 144:ef7eb2e8f9f7 9585
<> 144:ef7eb2e8f9f7 9586
<> 144:ef7eb2e8f9f7 9587 /* MCG - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 9588 /** Peripheral MCG base address */
<> 144:ef7eb2e8f9f7 9589 #define MCG_BASE (0x40064000u)
<> 144:ef7eb2e8f9f7 9590 /** Peripheral MCG base pointer */
<> 144:ef7eb2e8f9f7 9591 #define MCG ((MCG_Type *)MCG_BASE)
<> 144:ef7eb2e8f9f7 9592 /** Array initializer of MCG peripheral base addresses */
<> 144:ef7eb2e8f9f7 9593 #define MCG_BASE_ADDRS { MCG_BASE }
<> 144:ef7eb2e8f9f7 9594 /** Array initializer of MCG peripheral base pointers */
<> 144:ef7eb2e8f9f7 9595 #define MCG_BASE_PTRS { MCG }
<> 144:ef7eb2e8f9f7 9596 /* MCG C5[PLLCLKEN0] backward compatibility */
<> 144:ef7eb2e8f9f7 9597 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
<> 144:ef7eb2e8f9f7 9598 #define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
<> 144:ef7eb2e8f9f7 9599 #define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
<> 144:ef7eb2e8f9f7 9600 #define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
<> 144:ef7eb2e8f9f7 9601
<> 144:ef7eb2e8f9f7 9602 /* MCG C5[PLLSTEN0] backward compatibility */
<> 144:ef7eb2e8f9f7 9603 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
<> 144:ef7eb2e8f9f7 9604 #define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
<> 144:ef7eb2e8f9f7 9605 #define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
<> 144:ef7eb2e8f9f7 9606 #define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
<> 144:ef7eb2e8f9f7 9607
<> 144:ef7eb2e8f9f7 9608 /* MCG C5[PRDIV0] backward compatibility */
<> 144:ef7eb2e8f9f7 9609 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
<> 144:ef7eb2e8f9f7 9610 #define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
<> 144:ef7eb2e8f9f7 9611 #define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
<> 144:ef7eb2e8f9f7 9612 #define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
<> 144:ef7eb2e8f9f7 9613
<> 144:ef7eb2e8f9f7 9614 /* MCG C6[VDIV0] backward compatibility */
<> 144:ef7eb2e8f9f7 9615 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
<> 144:ef7eb2e8f9f7 9616 #define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
<> 144:ef7eb2e8f9f7 9617 #define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
<> 144:ef7eb2e8f9f7 9618 #define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
<> 144:ef7eb2e8f9f7 9619
<> 144:ef7eb2e8f9f7 9620
<> 144:ef7eb2e8f9f7 9621 /*!
<> 144:ef7eb2e8f9f7 9622 * @}
<> 144:ef7eb2e8f9f7 9623 */ /* end of group MCG_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 9624
<> 144:ef7eb2e8f9f7 9625
<> 144:ef7eb2e8f9f7 9626 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9627 -- MCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9628 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9629
<> 144:ef7eb2e8f9f7 9630 /*!
<> 144:ef7eb2e8f9f7 9631 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9632 * @{
<> 144:ef7eb2e8f9f7 9633 */
<> 144:ef7eb2e8f9f7 9634
<> 144:ef7eb2e8f9f7 9635 /** MCM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 9636 typedef struct {
<> 144:ef7eb2e8f9f7 9637 uint8_t RESERVED_0[8];
<> 144:ef7eb2e8f9f7 9638 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
<> 144:ef7eb2e8f9f7 9639 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
<> 144:ef7eb2e8f9f7 9640 __IO uint32_t CR; /**< Control Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 9641 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 9642 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 9643 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 9644 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 9645 __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 9646 __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 9647 __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 9648 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 9649 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 9650 uint8_t RESERVED_2[12];
<> 144:ef7eb2e8f9f7 9651 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 9652 } MCM_Type;
<> 144:ef7eb2e8f9f7 9653
<> 144:ef7eb2e8f9f7 9654 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9655 -- MCM Register Masks
<> 144:ef7eb2e8f9f7 9656 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9657
<> 144:ef7eb2e8f9f7 9658 /*!
<> 144:ef7eb2e8f9f7 9659 * @addtogroup MCM_Register_Masks MCM Register Masks
<> 144:ef7eb2e8f9f7 9660 * @{
<> 144:ef7eb2e8f9f7 9661 */
<> 144:ef7eb2e8f9f7 9662
<> 144:ef7eb2e8f9f7 9663 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
<> 144:ef7eb2e8f9f7 9664 #define MCM_PLASC_ASC_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 9665 #define MCM_PLASC_ASC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9666 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
<> 144:ef7eb2e8f9f7 9667
<> 144:ef7eb2e8f9f7 9668 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
<> 144:ef7eb2e8f9f7 9669 #define MCM_PLAMC_AMC_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 9670 #define MCM_PLAMC_AMC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9671 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
<> 144:ef7eb2e8f9f7 9672
<> 144:ef7eb2e8f9f7 9673 /*! @name CR - Control Register */
<> 144:ef7eb2e8f9f7 9674 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 9675 #define MCM_CR_SRAMUAP_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9676 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
<> 144:ef7eb2e8f9f7 9677 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 9678 #define MCM_CR_SRAMUWP_SHIFT (26U)
<> 144:ef7eb2e8f9f7 9679 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
<> 144:ef7eb2e8f9f7 9680 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 9681 #define MCM_CR_SRAMLAP_SHIFT (28U)
<> 144:ef7eb2e8f9f7 9682 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
<> 144:ef7eb2e8f9f7 9683 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 9684 #define MCM_CR_SRAMLWP_SHIFT (30U)
<> 144:ef7eb2e8f9f7 9685 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
<> 144:ef7eb2e8f9f7 9686
<> 144:ef7eb2e8f9f7 9687 /*! @name ISCR - Interrupt Status Register */
<> 144:ef7eb2e8f9f7 9688 #define MCM_ISCR_IRQ_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9689 #define MCM_ISCR_IRQ_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9690 #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
<> 144:ef7eb2e8f9f7 9691 #define MCM_ISCR_NMI_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9692 #define MCM_ISCR_NMI_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9693 #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
<> 144:ef7eb2e8f9f7 9694 #define MCM_ISCR_DHREQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 9695 #define MCM_ISCR_DHREQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9696 #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
<> 144:ef7eb2e8f9f7 9697 #define MCM_ISCR_FIOC_MASK (0x100U)
<> 144:ef7eb2e8f9f7 9698 #define MCM_ISCR_FIOC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 9699 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
<> 144:ef7eb2e8f9f7 9700 #define MCM_ISCR_FDZC_MASK (0x200U)
<> 144:ef7eb2e8f9f7 9701 #define MCM_ISCR_FDZC_SHIFT (9U)
<> 144:ef7eb2e8f9f7 9702 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
<> 144:ef7eb2e8f9f7 9703 #define MCM_ISCR_FOFC_MASK (0x400U)
<> 144:ef7eb2e8f9f7 9704 #define MCM_ISCR_FOFC_SHIFT (10U)
<> 144:ef7eb2e8f9f7 9705 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
<> 144:ef7eb2e8f9f7 9706 #define MCM_ISCR_FUFC_MASK (0x800U)
<> 144:ef7eb2e8f9f7 9707 #define MCM_ISCR_FUFC_SHIFT (11U)
<> 144:ef7eb2e8f9f7 9708 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
<> 144:ef7eb2e8f9f7 9709 #define MCM_ISCR_FIXC_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 9710 #define MCM_ISCR_FIXC_SHIFT (12U)
<> 144:ef7eb2e8f9f7 9711 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
<> 144:ef7eb2e8f9f7 9712 #define MCM_ISCR_FIDC_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 9713 #define MCM_ISCR_FIDC_SHIFT (15U)
<> 144:ef7eb2e8f9f7 9714 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
<> 144:ef7eb2e8f9f7 9715 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 9716 #define MCM_ISCR_FIOCE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9717 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
<> 144:ef7eb2e8f9f7 9718 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 9719 #define MCM_ISCR_FDZCE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 9720 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
<> 144:ef7eb2e8f9f7 9721 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 9722 #define MCM_ISCR_FOFCE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 9723 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
<> 144:ef7eb2e8f9f7 9724 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 9725 #define MCM_ISCR_FUFCE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 9726 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
<> 144:ef7eb2e8f9f7 9727 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 9728 #define MCM_ISCR_FIXCE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 9729 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
<> 144:ef7eb2e8f9f7 9730 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 9731 #define MCM_ISCR_FIDCE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 9732 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
<> 144:ef7eb2e8f9f7 9733
<> 144:ef7eb2e8f9f7 9734 /*! @name ETBCC - ETB Counter Control register */
<> 144:ef7eb2e8f9f7 9735 #define MCM_ETBCC_CNTEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9736 #define MCM_ETBCC_CNTEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9737 #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
<> 144:ef7eb2e8f9f7 9738 #define MCM_ETBCC_RSPT_MASK (0x6U)
<> 144:ef7eb2e8f9f7 9739 #define MCM_ETBCC_RSPT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9740 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
<> 144:ef7eb2e8f9f7 9741 #define MCM_ETBCC_RLRQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 9742 #define MCM_ETBCC_RLRQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9743 #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
<> 144:ef7eb2e8f9f7 9744 #define MCM_ETBCC_ETDIS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 9745 #define MCM_ETBCC_ETDIS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9746 #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
<> 144:ef7eb2e8f9f7 9747 #define MCM_ETBCC_ITDIS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9748 #define MCM_ETBCC_ITDIS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9749 #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
<> 144:ef7eb2e8f9f7 9750
<> 144:ef7eb2e8f9f7 9751 /*! @name ETBRL - ETB Reload register */
<> 144:ef7eb2e8f9f7 9752 #define MCM_ETBRL_RELOAD_MASK (0x7FFU)
<> 144:ef7eb2e8f9f7 9753 #define MCM_ETBRL_RELOAD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9754 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
<> 144:ef7eb2e8f9f7 9755
<> 144:ef7eb2e8f9f7 9756 /*! @name ETBCNT - ETB Counter Value register */
<> 144:ef7eb2e8f9f7 9757 #define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
<> 144:ef7eb2e8f9f7 9758 #define MCM_ETBCNT_COUNTER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9759 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
<> 144:ef7eb2e8f9f7 9760
<> 144:ef7eb2e8f9f7 9761 /*! @name FADR - Fault address register */
<> 144:ef7eb2e8f9f7 9762 #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 9763 #define MCM_FADR_ADDRESS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9764 #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
<> 144:ef7eb2e8f9f7 9765
<> 144:ef7eb2e8f9f7 9766 /*! @name FATR - Fault attributes register */
<> 144:ef7eb2e8f9f7 9767 #define MCM_FATR_BEDA_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9768 #define MCM_FATR_BEDA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9769 #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
<> 144:ef7eb2e8f9f7 9770 #define MCM_FATR_BEMD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9771 #define MCM_FATR_BEMD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9772 #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
<> 144:ef7eb2e8f9f7 9773 #define MCM_FATR_BESZ_MASK (0x30U)
<> 144:ef7eb2e8f9f7 9774 #define MCM_FATR_BESZ_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9775 #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
<> 144:ef7eb2e8f9f7 9776 #define MCM_FATR_BEWT_MASK (0x80U)
<> 144:ef7eb2e8f9f7 9777 #define MCM_FATR_BEWT_SHIFT (7U)
<> 144:ef7eb2e8f9f7 9778 #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
<> 144:ef7eb2e8f9f7 9779 #define MCM_FATR_BEMN_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 9780 #define MCM_FATR_BEMN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 9781 #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
<> 144:ef7eb2e8f9f7 9782 #define MCM_FATR_BEOVR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 9783 #define MCM_FATR_BEOVR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 9784 #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
<> 144:ef7eb2e8f9f7 9785
<> 144:ef7eb2e8f9f7 9786 /*! @name FDR - Fault data register */
<> 144:ef7eb2e8f9f7 9787 #define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 9788 #define MCM_FDR_DATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9789 #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
<> 144:ef7eb2e8f9f7 9790
<> 144:ef7eb2e8f9f7 9791 /*! @name PID - Process ID register */
<> 144:ef7eb2e8f9f7 9792 #define MCM_PID_PID_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 9793 #define MCM_PID_PID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9794 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
<> 144:ef7eb2e8f9f7 9795
<> 144:ef7eb2e8f9f7 9796 /*! @name CPO - Compute Operation Control Register */
<> 144:ef7eb2e8f9f7 9797 #define MCM_CPO_CPOREQ_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9798 #define MCM_CPO_CPOREQ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9799 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
<> 144:ef7eb2e8f9f7 9800 #define MCM_CPO_CPOACK_MASK (0x2U)
<> 144:ef7eb2e8f9f7 9801 #define MCM_CPO_CPOACK_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9802 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
<> 144:ef7eb2e8f9f7 9803 #define MCM_CPO_CPOWOI_MASK (0x4U)
<> 144:ef7eb2e8f9f7 9804 #define MCM_CPO_CPOWOI_SHIFT (2U)
<> 144:ef7eb2e8f9f7 9805 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
<> 144:ef7eb2e8f9f7 9806
<> 144:ef7eb2e8f9f7 9807
<> 144:ef7eb2e8f9f7 9808 /*!
<> 144:ef7eb2e8f9f7 9809 * @}
<> 144:ef7eb2e8f9f7 9810 */ /* end of group MCM_Register_Masks */
<> 144:ef7eb2e8f9f7 9811
<> 144:ef7eb2e8f9f7 9812
<> 144:ef7eb2e8f9f7 9813 /* MCM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 9814 /** Peripheral MCM base address */
<> 144:ef7eb2e8f9f7 9815 #define MCM_BASE (0xE0080000u)
<> 144:ef7eb2e8f9f7 9816 /** Peripheral MCM base pointer */
<> 144:ef7eb2e8f9f7 9817 #define MCM ((MCM_Type *)MCM_BASE)
<> 144:ef7eb2e8f9f7 9818 /** Array initializer of MCM peripheral base addresses */
<> 144:ef7eb2e8f9f7 9819 #define MCM_BASE_ADDRS { MCM_BASE }
<> 144:ef7eb2e8f9f7 9820 /** Array initializer of MCM peripheral base pointers */
<> 144:ef7eb2e8f9f7 9821 #define MCM_BASE_PTRS { MCM }
<> 144:ef7eb2e8f9f7 9822 /** Interrupt vectors for the MCM peripheral type */
<> 144:ef7eb2e8f9f7 9823 #define MCM_IRQS { MCM_IRQn }
<> 144:ef7eb2e8f9f7 9824
<> 144:ef7eb2e8f9f7 9825 /*!
<> 144:ef7eb2e8f9f7 9826 * @}
<> 144:ef7eb2e8f9f7 9827 */ /* end of group MCM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 9828
<> 144:ef7eb2e8f9f7 9829
<> 144:ef7eb2e8f9f7 9830 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9831 -- MPU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9832 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9833
<> 144:ef7eb2e8f9f7 9834 /*!
<> 144:ef7eb2e8f9f7 9835 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
<> 144:ef7eb2e8f9f7 9836 * @{
<> 144:ef7eb2e8f9f7 9837 */
<> 144:ef7eb2e8f9f7 9838
<> 144:ef7eb2e8f9f7 9839 /** MPU - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 9840 typedef struct {
<> 144:ef7eb2e8f9f7 9841 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 9842 uint8_t RESERVED_0[12];
<> 144:ef7eb2e8f9f7 9843 struct { /* offset: 0x10, array step: 0x8 */
<> 144:ef7eb2e8f9f7 9844 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
<> 144:ef7eb2e8f9f7 9845 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
<> 144:ef7eb2e8f9f7 9846 } SP[5];
<> 144:ef7eb2e8f9f7 9847 uint8_t RESERVED_1[968];
<> 144:ef7eb2e8f9f7 9848 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
<> 144:ef7eb2e8f9f7 9849 uint8_t RESERVED_2[832];
<> 144:ef7eb2e8f9f7 9850 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
<> 144:ef7eb2e8f9f7 9851 } MPU_Type;
<> 144:ef7eb2e8f9f7 9852
<> 144:ef7eb2e8f9f7 9853 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9854 -- MPU Register Masks
<> 144:ef7eb2e8f9f7 9855 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 9856
<> 144:ef7eb2e8f9f7 9857 /*!
<> 144:ef7eb2e8f9f7 9858 * @addtogroup MPU_Register_Masks MPU Register Masks
<> 144:ef7eb2e8f9f7 9859 * @{
<> 144:ef7eb2e8f9f7 9860 */
<> 144:ef7eb2e8f9f7 9861
<> 144:ef7eb2e8f9f7 9862 /*! @name CESR - Control/Error Status Register */
<> 144:ef7eb2e8f9f7 9863 #define MPU_CESR_VLD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9864 #define MPU_CESR_VLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9865 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
<> 144:ef7eb2e8f9f7 9866 #define MPU_CESR_NRGD_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 9867 #define MPU_CESR_NRGD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 9868 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
<> 144:ef7eb2e8f9f7 9869 #define MPU_CESR_NSP_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 9870 #define MPU_CESR_NSP_SHIFT (12U)
<> 144:ef7eb2e8f9f7 9871 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
<> 144:ef7eb2e8f9f7 9872 #define MPU_CESR_HRL_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 9873 #define MPU_CESR_HRL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9874 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
<> 144:ef7eb2e8f9f7 9875 #define MPU_CESR_SPERR_MASK (0xF8000000U)
<> 144:ef7eb2e8f9f7 9876 #define MPU_CESR_SPERR_SHIFT (27U)
<> 144:ef7eb2e8f9f7 9877 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
<> 144:ef7eb2e8f9f7 9878
<> 144:ef7eb2e8f9f7 9879 /*! @name EAR - Error Address Register, slave port n */
<> 144:ef7eb2e8f9f7 9880 #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 9881 #define MPU_EAR_EADDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9882 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
<> 144:ef7eb2e8f9f7 9883
<> 144:ef7eb2e8f9f7 9884 /* The count of MPU_EAR */
<> 144:ef7eb2e8f9f7 9885 #define MPU_EAR_COUNT (5U)
<> 144:ef7eb2e8f9f7 9886
<> 144:ef7eb2e8f9f7 9887 /*! @name EDR - Error Detail Register, slave port n */
<> 144:ef7eb2e8f9f7 9888 #define MPU_EDR_ERW_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9889 #define MPU_EDR_ERW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9890 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
<> 144:ef7eb2e8f9f7 9891 #define MPU_EDR_EATTR_MASK (0xEU)
<> 144:ef7eb2e8f9f7 9892 #define MPU_EDR_EATTR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 9893 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
<> 144:ef7eb2e8f9f7 9894 #define MPU_EDR_EMN_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 9895 #define MPU_EDR_EMN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 9896 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
<> 144:ef7eb2e8f9f7 9897 #define MPU_EDR_EPID_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 9898 #define MPU_EDR_EPID_SHIFT (8U)
<> 144:ef7eb2e8f9f7 9899 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
<> 144:ef7eb2e8f9f7 9900 #define MPU_EDR_EACD_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 9901 #define MPU_EDR_EACD_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9902 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
<> 144:ef7eb2e8f9f7 9903
<> 144:ef7eb2e8f9f7 9904 /* The count of MPU_EDR */
<> 144:ef7eb2e8f9f7 9905 #define MPU_EDR_COUNT (5U)
<> 144:ef7eb2e8f9f7 9906
<> 144:ef7eb2e8f9f7 9907 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
<> 144:ef7eb2e8f9f7 9908 #define MPU_WORD_VLD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 9909 #define MPU_WORD_VLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9910 #define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
<> 144:ef7eb2e8f9f7 9911 #define MPU_WORD_M0UM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 9912 #define MPU_WORD_M0UM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9913 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
<> 144:ef7eb2e8f9f7 9914 #define MPU_WORD_M0SM_MASK (0x18U)
<> 144:ef7eb2e8f9f7 9915 #define MPU_WORD_M0SM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9916 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
<> 144:ef7eb2e8f9f7 9917 #define MPU_WORD_M0PE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9918 #define MPU_WORD_M0PE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9919 #define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
<> 144:ef7eb2e8f9f7 9920 #define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
<> 144:ef7eb2e8f9f7 9921 #define MPU_WORD_ENDADDR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9922 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
<> 144:ef7eb2e8f9f7 9923 #define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
<> 144:ef7eb2e8f9f7 9924 #define MPU_WORD_SRTADDR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9925 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
<> 144:ef7eb2e8f9f7 9926 #define MPU_WORD_M1UM_MASK (0x1C0U)
<> 144:ef7eb2e8f9f7 9927 #define MPU_WORD_M1UM_SHIFT (6U)
<> 144:ef7eb2e8f9f7 9928 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
<> 144:ef7eb2e8f9f7 9929 #define MPU_WORD_M1SM_MASK (0x600U)
<> 144:ef7eb2e8f9f7 9930 #define MPU_WORD_M1SM_SHIFT (9U)
<> 144:ef7eb2e8f9f7 9931 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
<> 144:ef7eb2e8f9f7 9932 #define MPU_WORD_M1PE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 9933 #define MPU_WORD_M1PE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 9934 #define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
<> 144:ef7eb2e8f9f7 9935 #define MPU_WORD_M2UM_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 9936 #define MPU_WORD_M2UM_SHIFT (12U)
<> 144:ef7eb2e8f9f7 9937 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
<> 144:ef7eb2e8f9f7 9938 #define MPU_WORD_M2SM_MASK (0x18000U)
<> 144:ef7eb2e8f9f7 9939 #define MPU_WORD_M2SM_SHIFT (15U)
<> 144:ef7eb2e8f9f7 9940 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
<> 144:ef7eb2e8f9f7 9941 #define MPU_WORD_PIDMASK_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 9942 #define MPU_WORD_PIDMASK_SHIFT (16U)
<> 144:ef7eb2e8f9f7 9943 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
<> 144:ef7eb2e8f9f7 9944 #define MPU_WORD_M2PE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 9945 #define MPU_WORD_M2PE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 9946 #define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
<> 144:ef7eb2e8f9f7 9947 #define MPU_WORD_M3UM_MASK (0x1C0000U)
<> 144:ef7eb2e8f9f7 9948 #define MPU_WORD_M3UM_SHIFT (18U)
<> 144:ef7eb2e8f9f7 9949 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
<> 144:ef7eb2e8f9f7 9950 #define MPU_WORD_M3SM_MASK (0x600000U)
<> 144:ef7eb2e8f9f7 9951 #define MPU_WORD_M3SM_SHIFT (21U)
<> 144:ef7eb2e8f9f7 9952 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
<> 144:ef7eb2e8f9f7 9953 #define MPU_WORD_M3PE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 9954 #define MPU_WORD_M3PE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 9955 #define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
<> 144:ef7eb2e8f9f7 9956 #define MPU_WORD_PID_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 9957 #define MPU_WORD_PID_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9958 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
<> 144:ef7eb2e8f9f7 9959 #define MPU_WORD_M4WE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 9960 #define MPU_WORD_M4WE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 9961 #define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
<> 144:ef7eb2e8f9f7 9962 #define MPU_WORD_M4RE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 9963 #define MPU_WORD_M4RE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 9964 #define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
<> 144:ef7eb2e8f9f7 9965 #define MPU_WORD_M5WE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 9966 #define MPU_WORD_M5WE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 9967 #define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
<> 144:ef7eb2e8f9f7 9968 #define MPU_WORD_M5RE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 9969 #define MPU_WORD_M5RE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 9970 #define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
<> 144:ef7eb2e8f9f7 9971 #define MPU_WORD_M6WE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 9972 #define MPU_WORD_M6WE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 9973 #define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
<> 144:ef7eb2e8f9f7 9974 #define MPU_WORD_M6RE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 9975 #define MPU_WORD_M6RE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 9976 #define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
<> 144:ef7eb2e8f9f7 9977 #define MPU_WORD_M7WE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 9978 #define MPU_WORD_M7WE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 9979 #define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
<> 144:ef7eb2e8f9f7 9980 #define MPU_WORD_M7RE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 9981 #define MPU_WORD_M7RE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 9982 #define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
<> 144:ef7eb2e8f9f7 9983
<> 144:ef7eb2e8f9f7 9984 /* The count of MPU_WORD */
<> 144:ef7eb2e8f9f7 9985 #define MPU_WORD_COUNT (12U)
<> 144:ef7eb2e8f9f7 9986
<> 144:ef7eb2e8f9f7 9987 /* The count of MPU_WORD */
<> 144:ef7eb2e8f9f7 9988 #define MPU_WORD_COUNT2 (4U)
<> 144:ef7eb2e8f9f7 9989
<> 144:ef7eb2e8f9f7 9990 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
<> 144:ef7eb2e8f9f7 9991 #define MPU_RGDAAC_M0UM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 9992 #define MPU_RGDAAC_M0UM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 9993 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
<> 144:ef7eb2e8f9f7 9994 #define MPU_RGDAAC_M0SM_MASK (0x18U)
<> 144:ef7eb2e8f9f7 9995 #define MPU_RGDAAC_M0SM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 9996 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
<> 144:ef7eb2e8f9f7 9997 #define MPU_RGDAAC_M0PE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 9998 #define MPU_RGDAAC_M0PE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 9999 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
<> 144:ef7eb2e8f9f7 10000 #define MPU_RGDAAC_M1UM_MASK (0x1C0U)
<> 144:ef7eb2e8f9f7 10001 #define MPU_RGDAAC_M1UM_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10002 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
<> 144:ef7eb2e8f9f7 10003 #define MPU_RGDAAC_M1SM_MASK (0x600U)
<> 144:ef7eb2e8f9f7 10004 #define MPU_RGDAAC_M1SM_SHIFT (9U)
<> 144:ef7eb2e8f9f7 10005 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
<> 144:ef7eb2e8f9f7 10006 #define MPU_RGDAAC_M1PE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 10007 #define MPU_RGDAAC_M1PE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 10008 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
<> 144:ef7eb2e8f9f7 10009 #define MPU_RGDAAC_M2UM_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 10010 #define MPU_RGDAAC_M2UM_SHIFT (12U)
<> 144:ef7eb2e8f9f7 10011 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
<> 144:ef7eb2e8f9f7 10012 #define MPU_RGDAAC_M2SM_MASK (0x18000U)
<> 144:ef7eb2e8f9f7 10013 #define MPU_RGDAAC_M2SM_SHIFT (15U)
<> 144:ef7eb2e8f9f7 10014 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
<> 144:ef7eb2e8f9f7 10015 #define MPU_RGDAAC_M2PE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 10016 #define MPU_RGDAAC_M2PE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 10017 #define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
<> 144:ef7eb2e8f9f7 10018 #define MPU_RGDAAC_M3UM_MASK (0x1C0000U)
<> 144:ef7eb2e8f9f7 10019 #define MPU_RGDAAC_M3UM_SHIFT (18U)
<> 144:ef7eb2e8f9f7 10020 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
<> 144:ef7eb2e8f9f7 10021 #define MPU_RGDAAC_M3SM_MASK (0x600000U)
<> 144:ef7eb2e8f9f7 10022 #define MPU_RGDAAC_M3SM_SHIFT (21U)
<> 144:ef7eb2e8f9f7 10023 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
<> 144:ef7eb2e8f9f7 10024 #define MPU_RGDAAC_M3PE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 10025 #define MPU_RGDAAC_M3PE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 10026 #define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
<> 144:ef7eb2e8f9f7 10027 #define MPU_RGDAAC_M4WE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 10028 #define MPU_RGDAAC_M4WE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 10029 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
<> 144:ef7eb2e8f9f7 10030 #define MPU_RGDAAC_M4RE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 10031 #define MPU_RGDAAC_M4RE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 10032 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
<> 144:ef7eb2e8f9f7 10033 #define MPU_RGDAAC_M5WE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 10034 #define MPU_RGDAAC_M5WE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 10035 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
<> 144:ef7eb2e8f9f7 10036 #define MPU_RGDAAC_M5RE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 10037 #define MPU_RGDAAC_M5RE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 10038 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
<> 144:ef7eb2e8f9f7 10039 #define MPU_RGDAAC_M6WE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 10040 #define MPU_RGDAAC_M6WE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 10041 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
<> 144:ef7eb2e8f9f7 10042 #define MPU_RGDAAC_M6RE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 10043 #define MPU_RGDAAC_M6RE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 10044 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
<> 144:ef7eb2e8f9f7 10045 #define MPU_RGDAAC_M7WE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 10046 #define MPU_RGDAAC_M7WE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 10047 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
<> 144:ef7eb2e8f9f7 10048 #define MPU_RGDAAC_M7RE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 10049 #define MPU_RGDAAC_M7RE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 10050 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
<> 144:ef7eb2e8f9f7 10051
<> 144:ef7eb2e8f9f7 10052 /* The count of MPU_RGDAAC */
<> 144:ef7eb2e8f9f7 10053 #define MPU_RGDAAC_COUNT (12U)
<> 144:ef7eb2e8f9f7 10054
<> 144:ef7eb2e8f9f7 10055
<> 144:ef7eb2e8f9f7 10056 /*!
<> 144:ef7eb2e8f9f7 10057 * @}
<> 144:ef7eb2e8f9f7 10058 */ /* end of group MPU_Register_Masks */
<> 144:ef7eb2e8f9f7 10059
<> 144:ef7eb2e8f9f7 10060
<> 144:ef7eb2e8f9f7 10061 /* MPU - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10062 /** Peripheral MPU base address */
<> 144:ef7eb2e8f9f7 10063 #define MPU_BASE (0x4000D000u)
<> 144:ef7eb2e8f9f7 10064 /** Peripheral MPU base pointer */
<> 144:ef7eb2e8f9f7 10065 #define MPU ((MPU_Type *)MPU_BASE)
<> 144:ef7eb2e8f9f7 10066 /** Array initializer of MPU peripheral base addresses */
<> 144:ef7eb2e8f9f7 10067 #define MPU_BASE_ADDRS { MPU_BASE }
<> 144:ef7eb2e8f9f7 10068 /** Array initializer of MPU peripheral base pointers */
<> 144:ef7eb2e8f9f7 10069 #define MPU_BASE_PTRS { MPU }
<> 144:ef7eb2e8f9f7 10070
<> 144:ef7eb2e8f9f7 10071 /*!
<> 144:ef7eb2e8f9f7 10072 * @}
<> 144:ef7eb2e8f9f7 10073 */ /* end of group MPU_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10074
<> 144:ef7eb2e8f9f7 10075
<> 144:ef7eb2e8f9f7 10076 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10077 -- NV Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10078 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10079
<> 144:ef7eb2e8f9f7 10080 /*!
<> 144:ef7eb2e8f9f7 10081 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10082 * @{
<> 144:ef7eb2e8f9f7 10083 */
<> 144:ef7eb2e8f9f7 10084
<> 144:ef7eb2e8f9f7 10085 /** NV - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10086 typedef struct {
<> 144:ef7eb2e8f9f7 10087 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
<> 144:ef7eb2e8f9f7 10088 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
<> 144:ef7eb2e8f9f7 10089 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
<> 144:ef7eb2e8f9f7 10090 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
<> 144:ef7eb2e8f9f7 10091 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
<> 144:ef7eb2e8f9f7 10092 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
<> 144:ef7eb2e8f9f7 10093 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
<> 144:ef7eb2e8f9f7 10094 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
<> 144:ef7eb2e8f9f7 10095 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 10096 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
<> 144:ef7eb2e8f9f7 10097 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
<> 144:ef7eb2e8f9f7 10098 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
<> 144:ef7eb2e8f9f7 10099 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 10100 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
<> 144:ef7eb2e8f9f7 10101 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
<> 144:ef7eb2e8f9f7 10102 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
<> 144:ef7eb2e8f9f7 10103 } NV_Type;
<> 144:ef7eb2e8f9f7 10104
<> 144:ef7eb2e8f9f7 10105 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10106 -- NV Register Masks
<> 144:ef7eb2e8f9f7 10107 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10108
<> 144:ef7eb2e8f9f7 10109 /*!
<> 144:ef7eb2e8f9f7 10110 * @addtogroup NV_Register_Masks NV Register Masks
<> 144:ef7eb2e8f9f7 10111 * @{
<> 144:ef7eb2e8f9f7 10112 */
<> 144:ef7eb2e8f9f7 10113
<> 144:ef7eb2e8f9f7 10114 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
<> 144:ef7eb2e8f9f7 10115 #define NV_BACKKEY3_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10116 #define NV_BACKKEY3_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10117 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
<> 144:ef7eb2e8f9f7 10118
<> 144:ef7eb2e8f9f7 10119 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
<> 144:ef7eb2e8f9f7 10120 #define NV_BACKKEY2_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10121 #define NV_BACKKEY2_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10122 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
<> 144:ef7eb2e8f9f7 10123
<> 144:ef7eb2e8f9f7 10124 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
<> 144:ef7eb2e8f9f7 10125 #define NV_BACKKEY1_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10126 #define NV_BACKKEY1_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10127 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
<> 144:ef7eb2e8f9f7 10128
<> 144:ef7eb2e8f9f7 10129 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
<> 144:ef7eb2e8f9f7 10130 #define NV_BACKKEY0_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10131 #define NV_BACKKEY0_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10132 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
<> 144:ef7eb2e8f9f7 10133
<> 144:ef7eb2e8f9f7 10134 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
<> 144:ef7eb2e8f9f7 10135 #define NV_BACKKEY7_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10136 #define NV_BACKKEY7_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10137 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
<> 144:ef7eb2e8f9f7 10138
<> 144:ef7eb2e8f9f7 10139 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
<> 144:ef7eb2e8f9f7 10140 #define NV_BACKKEY6_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10141 #define NV_BACKKEY6_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10142 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
<> 144:ef7eb2e8f9f7 10143
<> 144:ef7eb2e8f9f7 10144 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
<> 144:ef7eb2e8f9f7 10145 #define NV_BACKKEY5_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10146 #define NV_BACKKEY5_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10147 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
<> 144:ef7eb2e8f9f7 10148
<> 144:ef7eb2e8f9f7 10149 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
<> 144:ef7eb2e8f9f7 10150 #define NV_BACKKEY4_KEY_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10151 #define NV_BACKKEY4_KEY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10152 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
<> 144:ef7eb2e8f9f7 10153
<> 144:ef7eb2e8f9f7 10154 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
<> 144:ef7eb2e8f9f7 10155 #define NV_FPROT3_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10156 #define NV_FPROT3_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10157 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
<> 144:ef7eb2e8f9f7 10158
<> 144:ef7eb2e8f9f7 10159 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
<> 144:ef7eb2e8f9f7 10160 #define NV_FPROT2_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10161 #define NV_FPROT2_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10162 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
<> 144:ef7eb2e8f9f7 10163
<> 144:ef7eb2e8f9f7 10164 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
<> 144:ef7eb2e8f9f7 10165 #define NV_FPROT1_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10166 #define NV_FPROT1_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10167 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
<> 144:ef7eb2e8f9f7 10168
<> 144:ef7eb2e8f9f7 10169 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
<> 144:ef7eb2e8f9f7 10170 #define NV_FPROT0_PROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10171 #define NV_FPROT0_PROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10172 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
<> 144:ef7eb2e8f9f7 10173
<> 144:ef7eb2e8f9f7 10174 /*! @name FSEC - Non-volatile Flash Security Register */
<> 144:ef7eb2e8f9f7 10175 #define NV_FSEC_SEC_MASK (0x3U)
<> 144:ef7eb2e8f9f7 10176 #define NV_FSEC_SEC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10177 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
<> 144:ef7eb2e8f9f7 10178 #define NV_FSEC_FSLACC_MASK (0xCU)
<> 144:ef7eb2e8f9f7 10179 #define NV_FSEC_FSLACC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10180 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
<> 144:ef7eb2e8f9f7 10181 #define NV_FSEC_MEEN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 10182 #define NV_FSEC_MEEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 10183 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
<> 144:ef7eb2e8f9f7 10184 #define NV_FSEC_KEYEN_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 10185 #define NV_FSEC_KEYEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10186 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
<> 144:ef7eb2e8f9f7 10187
<> 144:ef7eb2e8f9f7 10188 /*! @name FOPT - Non-volatile Flash Option Register */
<> 144:ef7eb2e8f9f7 10189 #define NV_FOPT_LPBOOT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10190 #define NV_FOPT_LPBOOT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10191 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
<> 144:ef7eb2e8f9f7 10192 #define NV_FOPT_EZPORT_DIS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10193 #define NV_FOPT_EZPORT_DIS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10194 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
<> 144:ef7eb2e8f9f7 10195 #define NV_FOPT_NMI_DIS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10196 #define NV_FOPT_NMI_DIS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10197 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
<> 144:ef7eb2e8f9f7 10198
<> 144:ef7eb2e8f9f7 10199 /*! @name FEPROT - Non-volatile EERAM Protection Register */
<> 144:ef7eb2e8f9f7 10200 #define NV_FEPROT_EPROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10201 #define NV_FEPROT_EPROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10202 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
<> 144:ef7eb2e8f9f7 10203
<> 144:ef7eb2e8f9f7 10204 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
<> 144:ef7eb2e8f9f7 10205 #define NV_FDPROT_DPROT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10206 #define NV_FDPROT_DPROT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10207 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
<> 144:ef7eb2e8f9f7 10208
<> 144:ef7eb2e8f9f7 10209
<> 144:ef7eb2e8f9f7 10210 /*!
<> 144:ef7eb2e8f9f7 10211 * @}
<> 144:ef7eb2e8f9f7 10212 */ /* end of group NV_Register_Masks */
<> 144:ef7eb2e8f9f7 10213
<> 144:ef7eb2e8f9f7 10214
<> 144:ef7eb2e8f9f7 10215 /* NV - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10216 /** Peripheral FTFE_FlashConfig base address */
<> 144:ef7eb2e8f9f7 10217 #define FTFE_FlashConfig_BASE (0x400u)
<> 144:ef7eb2e8f9f7 10218 /** Peripheral FTFE_FlashConfig base pointer */
<> 144:ef7eb2e8f9f7 10219 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
<> 144:ef7eb2e8f9f7 10220 /** Array initializer of NV peripheral base addresses */
<> 144:ef7eb2e8f9f7 10221 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
<> 144:ef7eb2e8f9f7 10222 /** Array initializer of NV peripheral base pointers */
<> 144:ef7eb2e8f9f7 10223 #define NV_BASE_PTRS { FTFE_FlashConfig }
<> 144:ef7eb2e8f9f7 10224
<> 144:ef7eb2e8f9f7 10225 /*!
<> 144:ef7eb2e8f9f7 10226 * @}
<> 144:ef7eb2e8f9f7 10227 */ /* end of group NV_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10228
<> 144:ef7eb2e8f9f7 10229
<> 144:ef7eb2e8f9f7 10230 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10231 -- OSC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10232 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10233
<> 144:ef7eb2e8f9f7 10234 /*!
<> 144:ef7eb2e8f9f7 10235 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10236 * @{
<> 144:ef7eb2e8f9f7 10237 */
<> 144:ef7eb2e8f9f7 10238
<> 144:ef7eb2e8f9f7 10239 /** OSC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10240 typedef struct {
<> 144:ef7eb2e8f9f7 10241 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 10242 uint8_t RESERVED_0[1];
<> 144:ef7eb2e8f9f7 10243 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
<> 144:ef7eb2e8f9f7 10244 } OSC_Type;
<> 144:ef7eb2e8f9f7 10245
<> 144:ef7eb2e8f9f7 10246 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10247 -- OSC Register Masks
<> 144:ef7eb2e8f9f7 10248 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10249
<> 144:ef7eb2e8f9f7 10250 /*!
<> 144:ef7eb2e8f9f7 10251 * @addtogroup OSC_Register_Masks OSC Register Masks
<> 144:ef7eb2e8f9f7 10252 * @{
<> 144:ef7eb2e8f9f7 10253 */
<> 144:ef7eb2e8f9f7 10254
<> 144:ef7eb2e8f9f7 10255 /*! @name CR - OSC Control Register */
<> 144:ef7eb2e8f9f7 10256 #define OSC_CR_SC16P_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10257 #define OSC_CR_SC16P_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10258 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
<> 144:ef7eb2e8f9f7 10259 #define OSC_CR_SC8P_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10260 #define OSC_CR_SC8P_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10261 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
<> 144:ef7eb2e8f9f7 10262 #define OSC_CR_SC4P_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10263 #define OSC_CR_SC4P_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10264 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
<> 144:ef7eb2e8f9f7 10265 #define OSC_CR_SC2P_MASK (0x8U)
<> 144:ef7eb2e8f9f7 10266 #define OSC_CR_SC2P_SHIFT (3U)
<> 144:ef7eb2e8f9f7 10267 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
<> 144:ef7eb2e8f9f7 10268 #define OSC_CR_EREFSTEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10269 #define OSC_CR_EREFSTEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10270 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
<> 144:ef7eb2e8f9f7 10271 #define OSC_CR_ERCLKEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 10272 #define OSC_CR_ERCLKEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 10273 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
<> 144:ef7eb2e8f9f7 10274
<> 144:ef7eb2e8f9f7 10275 /*! @name DIV - OSC_DIV */
<> 144:ef7eb2e8f9f7 10276 #define OSC_DIV_ERPS_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 10277 #define OSC_DIV_ERPS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10278 #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
<> 144:ef7eb2e8f9f7 10279
<> 144:ef7eb2e8f9f7 10280
<> 144:ef7eb2e8f9f7 10281 /*!
<> 144:ef7eb2e8f9f7 10282 * @}
<> 144:ef7eb2e8f9f7 10283 */ /* end of group OSC_Register_Masks */
<> 144:ef7eb2e8f9f7 10284
<> 144:ef7eb2e8f9f7 10285
<> 144:ef7eb2e8f9f7 10286 /* OSC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10287 /** Peripheral OSC base address */
<> 144:ef7eb2e8f9f7 10288 #define OSC_BASE (0x40065000u)
<> 144:ef7eb2e8f9f7 10289 /** Peripheral OSC base pointer */
<> 144:ef7eb2e8f9f7 10290 #define OSC ((OSC_Type *)OSC_BASE)
<> 144:ef7eb2e8f9f7 10291 /** Array initializer of OSC peripheral base addresses */
<> 144:ef7eb2e8f9f7 10292 #define OSC_BASE_ADDRS { OSC_BASE }
<> 144:ef7eb2e8f9f7 10293 /** Array initializer of OSC peripheral base pointers */
<> 144:ef7eb2e8f9f7 10294 #define OSC_BASE_PTRS { OSC }
<> 144:ef7eb2e8f9f7 10295
<> 144:ef7eb2e8f9f7 10296 /*!
<> 144:ef7eb2e8f9f7 10297 * @}
<> 144:ef7eb2e8f9f7 10298 */ /* end of group OSC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10299
<> 144:ef7eb2e8f9f7 10300
<> 144:ef7eb2e8f9f7 10301 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10302 -- PDB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10303 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10304
<> 144:ef7eb2e8f9f7 10305 /*!
<> 144:ef7eb2e8f9f7 10306 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10307 * @{
<> 144:ef7eb2e8f9f7 10308 */
<> 144:ef7eb2e8f9f7 10309
<> 144:ef7eb2e8f9f7 10310 /** PDB - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10311 typedef struct {
<> 144:ef7eb2e8f9f7 10312 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 10313 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 10314 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 10315 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
<> 144:ef7eb2e8f9f7 10316 struct { /* offset: 0x10, array step: 0x28 */
<> 144:ef7eb2e8f9f7 10317 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
<> 144:ef7eb2e8f9f7 10318 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
<> 144:ef7eb2e8f9f7 10319 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
<> 144:ef7eb2e8f9f7 10320 uint8_t RESERVED_0[24];
<> 144:ef7eb2e8f9f7 10321 } CH[2];
<> 144:ef7eb2e8f9f7 10322 uint8_t RESERVED_0[240];
<> 144:ef7eb2e8f9f7 10323 struct { /* offset: 0x150, array step: 0x8 */
<> 144:ef7eb2e8f9f7 10324 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
<> 144:ef7eb2e8f9f7 10325 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
<> 144:ef7eb2e8f9f7 10326 } DAC[2];
<> 144:ef7eb2e8f9f7 10327 uint8_t RESERVED_1[48];
<> 144:ef7eb2e8f9f7 10328 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
<> 144:ef7eb2e8f9f7 10329 __IO uint32_t PODLY[4]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
<> 144:ef7eb2e8f9f7 10330 } PDB_Type;
<> 144:ef7eb2e8f9f7 10331
<> 144:ef7eb2e8f9f7 10332 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10333 -- PDB Register Masks
<> 144:ef7eb2e8f9f7 10334 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10335
<> 144:ef7eb2e8f9f7 10336 /*!
<> 144:ef7eb2e8f9f7 10337 * @addtogroup PDB_Register_Masks PDB Register Masks
<> 144:ef7eb2e8f9f7 10338 * @{
<> 144:ef7eb2e8f9f7 10339 */
<> 144:ef7eb2e8f9f7 10340
<> 144:ef7eb2e8f9f7 10341 /*! @name SC - Status and Control register */
<> 144:ef7eb2e8f9f7 10342 #define PDB_SC_LDOK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10343 #define PDB_SC_LDOK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10344 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
<> 144:ef7eb2e8f9f7 10345 #define PDB_SC_CONT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10346 #define PDB_SC_CONT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10347 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
<> 144:ef7eb2e8f9f7 10348 #define PDB_SC_MULT_MASK (0xCU)
<> 144:ef7eb2e8f9f7 10349 #define PDB_SC_MULT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10350 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
<> 144:ef7eb2e8f9f7 10351 #define PDB_SC_PDBIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10352 #define PDB_SC_PDBIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10353 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
<> 144:ef7eb2e8f9f7 10354 #define PDB_SC_PDBIF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 10355 #define PDB_SC_PDBIF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10356 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
<> 144:ef7eb2e8f9f7 10357 #define PDB_SC_PDBEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 10358 #define PDB_SC_PDBEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 10359 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
<> 144:ef7eb2e8f9f7 10360 #define PDB_SC_TRGSEL_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 10361 #define PDB_SC_TRGSEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 10362 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 10363 #define PDB_SC_PRESCALER_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 10364 #define PDB_SC_PRESCALER_SHIFT (12U)
<> 144:ef7eb2e8f9f7 10365 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
<> 144:ef7eb2e8f9f7 10366 #define PDB_SC_DMAEN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 10367 #define PDB_SC_DMAEN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 10368 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 10369 #define PDB_SC_SWTRIG_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 10370 #define PDB_SC_SWTRIG_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10371 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
<> 144:ef7eb2e8f9f7 10372 #define PDB_SC_PDBEIE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 10373 #define PDB_SC_PDBEIE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 10374 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
<> 144:ef7eb2e8f9f7 10375 #define PDB_SC_LDMOD_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 10376 #define PDB_SC_LDMOD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 10377 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
<> 144:ef7eb2e8f9f7 10378
<> 144:ef7eb2e8f9f7 10379 /*! @name MOD - Modulus register */
<> 144:ef7eb2e8f9f7 10380 #define PDB_MOD_MOD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10381 #define PDB_MOD_MOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10382 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
<> 144:ef7eb2e8f9f7 10383
<> 144:ef7eb2e8f9f7 10384 /*! @name CNT - Counter register */
<> 144:ef7eb2e8f9f7 10385 #define PDB_CNT_CNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10386 #define PDB_CNT_CNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10387 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
<> 144:ef7eb2e8f9f7 10388
<> 144:ef7eb2e8f9f7 10389 /*! @name IDLY - Interrupt Delay register */
<> 144:ef7eb2e8f9f7 10390 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10391 #define PDB_IDLY_IDLY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10392 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
<> 144:ef7eb2e8f9f7 10393
<> 144:ef7eb2e8f9f7 10394 /*! @name C1 - Channel n Control register 1 */
<> 144:ef7eb2e8f9f7 10395 #define PDB_C1_EN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10396 #define PDB_C1_EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10397 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
<> 144:ef7eb2e8f9f7 10398 #define PDB_C1_TOS_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 10399 #define PDB_C1_TOS_SHIFT (8U)
<> 144:ef7eb2e8f9f7 10400 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
<> 144:ef7eb2e8f9f7 10401 #define PDB_C1_BB_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 10402 #define PDB_C1_BB_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10403 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
<> 144:ef7eb2e8f9f7 10404
<> 144:ef7eb2e8f9f7 10405 /* The count of PDB_C1 */
<> 144:ef7eb2e8f9f7 10406 #define PDB_C1_COUNT (2U)
<> 144:ef7eb2e8f9f7 10407
<> 144:ef7eb2e8f9f7 10408 /*! @name S - Channel n Status register */
<> 144:ef7eb2e8f9f7 10409 #define PDB_S_ERR_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10410 #define PDB_S_ERR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10411 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
<> 144:ef7eb2e8f9f7 10412 #define PDB_S_CF_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 10413 #define PDB_S_CF_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10414 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
<> 144:ef7eb2e8f9f7 10415
<> 144:ef7eb2e8f9f7 10416 /* The count of PDB_S */
<> 144:ef7eb2e8f9f7 10417 #define PDB_S_COUNT (2U)
<> 144:ef7eb2e8f9f7 10418
<> 144:ef7eb2e8f9f7 10419 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
<> 144:ef7eb2e8f9f7 10420 #define PDB_DLY_DLY_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10421 #define PDB_DLY_DLY_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10422 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
<> 144:ef7eb2e8f9f7 10423
<> 144:ef7eb2e8f9f7 10424 /* The count of PDB_DLY */
<> 144:ef7eb2e8f9f7 10425 #define PDB_DLY_COUNT (2U)
<> 144:ef7eb2e8f9f7 10426
<> 144:ef7eb2e8f9f7 10427 /* The count of PDB_DLY */
<> 144:ef7eb2e8f9f7 10428 #define PDB_DLY_COUNT2 (2U)
<> 144:ef7eb2e8f9f7 10429
<> 144:ef7eb2e8f9f7 10430 /*! @name INTC - DAC Interval Trigger n Control register */
<> 144:ef7eb2e8f9f7 10431 #define PDB_INTC_TOE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10432 #define PDB_INTC_TOE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10433 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
<> 144:ef7eb2e8f9f7 10434 #define PDB_INTC_EXT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10435 #define PDB_INTC_EXT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10436 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
<> 144:ef7eb2e8f9f7 10437
<> 144:ef7eb2e8f9f7 10438 /* The count of PDB_INTC */
<> 144:ef7eb2e8f9f7 10439 #define PDB_INTC_COUNT (2U)
<> 144:ef7eb2e8f9f7 10440
<> 144:ef7eb2e8f9f7 10441 /*! @name INT - DAC Interval n register */
<> 144:ef7eb2e8f9f7 10442 #define PDB_INT_INT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10443 #define PDB_INT_INT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10444 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
<> 144:ef7eb2e8f9f7 10445
<> 144:ef7eb2e8f9f7 10446 /* The count of PDB_INT */
<> 144:ef7eb2e8f9f7 10447 #define PDB_INT_COUNT (2U)
<> 144:ef7eb2e8f9f7 10448
<> 144:ef7eb2e8f9f7 10449 /*! @name POEN - Pulse-Out n Enable register */
<> 144:ef7eb2e8f9f7 10450 #define PDB_POEN_POEN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 10451 #define PDB_POEN_POEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10452 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
<> 144:ef7eb2e8f9f7 10453
<> 144:ef7eb2e8f9f7 10454 /*! @name PODLY - Pulse-Out n Delay register */
<> 144:ef7eb2e8f9f7 10455 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10456 #define PDB_PODLY_DLY2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10457 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
<> 144:ef7eb2e8f9f7 10458 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 10459 #define PDB_PODLY_DLY1_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10460 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
<> 144:ef7eb2e8f9f7 10461
<> 144:ef7eb2e8f9f7 10462 /* The count of PDB_PODLY */
<> 144:ef7eb2e8f9f7 10463 #define PDB_PODLY_COUNT (4U)
<> 144:ef7eb2e8f9f7 10464
<> 144:ef7eb2e8f9f7 10465
<> 144:ef7eb2e8f9f7 10466 /*!
<> 144:ef7eb2e8f9f7 10467 * @}
<> 144:ef7eb2e8f9f7 10468 */ /* end of group PDB_Register_Masks */
<> 144:ef7eb2e8f9f7 10469
<> 144:ef7eb2e8f9f7 10470
<> 144:ef7eb2e8f9f7 10471 /* PDB - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10472 /** Peripheral PDB0 base address */
<> 144:ef7eb2e8f9f7 10473 #define PDB0_BASE (0x40036000u)
<> 144:ef7eb2e8f9f7 10474 /** Peripheral PDB0 base pointer */
<> 144:ef7eb2e8f9f7 10475 #define PDB0 ((PDB_Type *)PDB0_BASE)
<> 144:ef7eb2e8f9f7 10476 /** Array initializer of PDB peripheral base addresses */
<> 144:ef7eb2e8f9f7 10477 #define PDB_BASE_ADDRS { PDB0_BASE }
<> 144:ef7eb2e8f9f7 10478 /** Array initializer of PDB peripheral base pointers */
<> 144:ef7eb2e8f9f7 10479 #define PDB_BASE_PTRS { PDB0 }
<> 144:ef7eb2e8f9f7 10480 /** Interrupt vectors for the PDB peripheral type */
<> 144:ef7eb2e8f9f7 10481 #define PDB_IRQS { PDB0_IRQn }
<> 144:ef7eb2e8f9f7 10482
<> 144:ef7eb2e8f9f7 10483 /*!
<> 144:ef7eb2e8f9f7 10484 * @}
<> 144:ef7eb2e8f9f7 10485 */ /* end of group PDB_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10486
<> 144:ef7eb2e8f9f7 10487
<> 144:ef7eb2e8f9f7 10488 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10489 -- PIT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10490 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10491
<> 144:ef7eb2e8f9f7 10492 /*!
<> 144:ef7eb2e8f9f7 10493 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10494 * @{
<> 144:ef7eb2e8f9f7 10495 */
<> 144:ef7eb2e8f9f7 10496
<> 144:ef7eb2e8f9f7 10497 /** PIT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10498 typedef struct {
<> 144:ef7eb2e8f9f7 10499 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 10500 uint8_t RESERVED_0[220];
<> 144:ef7eb2e8f9f7 10501 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
<> 144:ef7eb2e8f9f7 10502 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
<> 144:ef7eb2e8f9f7 10503 uint8_t RESERVED_1[24];
<> 144:ef7eb2e8f9f7 10504 struct { /* offset: 0x100, array step: 0x10 */
<> 144:ef7eb2e8f9f7 10505 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
<> 144:ef7eb2e8f9f7 10506 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
<> 144:ef7eb2e8f9f7 10507 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
<> 144:ef7eb2e8f9f7 10508 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
<> 144:ef7eb2e8f9f7 10509 } CHANNEL[4];
<> 144:ef7eb2e8f9f7 10510 } PIT_Type;
<> 144:ef7eb2e8f9f7 10511
<> 144:ef7eb2e8f9f7 10512 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10513 -- PIT Register Masks
<> 144:ef7eb2e8f9f7 10514 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10515
<> 144:ef7eb2e8f9f7 10516 /*!
<> 144:ef7eb2e8f9f7 10517 * @addtogroup PIT_Register_Masks PIT Register Masks
<> 144:ef7eb2e8f9f7 10518 * @{
<> 144:ef7eb2e8f9f7 10519 */
<> 144:ef7eb2e8f9f7 10520
<> 144:ef7eb2e8f9f7 10521 /*! @name MCR - PIT Module Control Register */
<> 144:ef7eb2e8f9f7 10522 #define PIT_MCR_FRZ_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10523 #define PIT_MCR_FRZ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10524 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
<> 144:ef7eb2e8f9f7 10525 #define PIT_MCR_MDIS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10526 #define PIT_MCR_MDIS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10527 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
<> 144:ef7eb2e8f9f7 10528
<> 144:ef7eb2e8f9f7 10529 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
<> 144:ef7eb2e8f9f7 10530 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 10531 #define PIT_LTMR64H_LTH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10532 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
<> 144:ef7eb2e8f9f7 10533
<> 144:ef7eb2e8f9f7 10534 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
<> 144:ef7eb2e8f9f7 10535 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 10536 #define PIT_LTMR64L_LTL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10537 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
<> 144:ef7eb2e8f9f7 10538
<> 144:ef7eb2e8f9f7 10539 /*! @name LDVAL - Timer Load Value Register */
<> 144:ef7eb2e8f9f7 10540 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 10541 #define PIT_LDVAL_TSV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10542 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
<> 144:ef7eb2e8f9f7 10543
<> 144:ef7eb2e8f9f7 10544 /* The count of PIT_LDVAL */
<> 144:ef7eb2e8f9f7 10545 #define PIT_LDVAL_COUNT (4U)
<> 144:ef7eb2e8f9f7 10546
<> 144:ef7eb2e8f9f7 10547 /*! @name CVAL - Current Timer Value Register */
<> 144:ef7eb2e8f9f7 10548 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 10549 #define PIT_CVAL_TVL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10550 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
<> 144:ef7eb2e8f9f7 10551
<> 144:ef7eb2e8f9f7 10552 /* The count of PIT_CVAL */
<> 144:ef7eb2e8f9f7 10553 #define PIT_CVAL_COUNT (4U)
<> 144:ef7eb2e8f9f7 10554
<> 144:ef7eb2e8f9f7 10555 /*! @name TCTRL - Timer Control Register */
<> 144:ef7eb2e8f9f7 10556 #define PIT_TCTRL_TEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10557 #define PIT_TCTRL_TEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10558 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
<> 144:ef7eb2e8f9f7 10559 #define PIT_TCTRL_TIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10560 #define PIT_TCTRL_TIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10561 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
<> 144:ef7eb2e8f9f7 10562 #define PIT_TCTRL_CHN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10563 #define PIT_TCTRL_CHN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10564 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
<> 144:ef7eb2e8f9f7 10565
<> 144:ef7eb2e8f9f7 10566 /* The count of PIT_TCTRL */
<> 144:ef7eb2e8f9f7 10567 #define PIT_TCTRL_COUNT (4U)
<> 144:ef7eb2e8f9f7 10568
<> 144:ef7eb2e8f9f7 10569 /*! @name TFLG - Timer Flag Register */
<> 144:ef7eb2e8f9f7 10570 #define PIT_TFLG_TIF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10571 #define PIT_TFLG_TIF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10572 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
<> 144:ef7eb2e8f9f7 10573
<> 144:ef7eb2e8f9f7 10574 /* The count of PIT_TFLG */
<> 144:ef7eb2e8f9f7 10575 #define PIT_TFLG_COUNT (4U)
<> 144:ef7eb2e8f9f7 10576
<> 144:ef7eb2e8f9f7 10577
<> 144:ef7eb2e8f9f7 10578 /*!
<> 144:ef7eb2e8f9f7 10579 * @}
<> 144:ef7eb2e8f9f7 10580 */ /* end of group PIT_Register_Masks */
<> 144:ef7eb2e8f9f7 10581
<> 144:ef7eb2e8f9f7 10582
<> 144:ef7eb2e8f9f7 10583 /* PIT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10584 /** Peripheral PIT base address */
<> 144:ef7eb2e8f9f7 10585 #define PIT_BASE (0x40037000u)
<> 144:ef7eb2e8f9f7 10586 /** Peripheral PIT base pointer */
<> 144:ef7eb2e8f9f7 10587 #define PIT ((PIT_Type *)PIT_BASE)
<> 144:ef7eb2e8f9f7 10588 /** Array initializer of PIT peripheral base addresses */
<> 144:ef7eb2e8f9f7 10589 #define PIT_BASE_ADDRS { PIT_BASE }
<> 144:ef7eb2e8f9f7 10590 /** Array initializer of PIT peripheral base pointers */
<> 144:ef7eb2e8f9f7 10591 #define PIT_BASE_PTRS { PIT }
<> 144:ef7eb2e8f9f7 10592 /** Interrupt vectors for the PIT peripheral type */
<> 144:ef7eb2e8f9f7 10593 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
<> 144:ef7eb2e8f9f7 10594
<> 144:ef7eb2e8f9f7 10595 /*!
<> 144:ef7eb2e8f9f7 10596 * @}
<> 144:ef7eb2e8f9f7 10597 */ /* end of group PIT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10598
<> 144:ef7eb2e8f9f7 10599
<> 144:ef7eb2e8f9f7 10600 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10601 -- PMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10602 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10603
<> 144:ef7eb2e8f9f7 10604 /*!
<> 144:ef7eb2e8f9f7 10605 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10606 * @{
<> 144:ef7eb2e8f9f7 10607 */
<> 144:ef7eb2e8f9f7 10608
<> 144:ef7eb2e8f9f7 10609 /** PMC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10610 typedef struct {
<> 144:ef7eb2e8f9f7 10611 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 10612 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 10613 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 10614 } PMC_Type;
<> 144:ef7eb2e8f9f7 10615
<> 144:ef7eb2e8f9f7 10616 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10617 -- PMC Register Masks
<> 144:ef7eb2e8f9f7 10618 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10619
<> 144:ef7eb2e8f9f7 10620 /*!
<> 144:ef7eb2e8f9f7 10621 * @addtogroup PMC_Register_Masks PMC Register Masks
<> 144:ef7eb2e8f9f7 10622 * @{
<> 144:ef7eb2e8f9f7 10623 */
<> 144:ef7eb2e8f9f7 10624
<> 144:ef7eb2e8f9f7 10625 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
<> 144:ef7eb2e8f9f7 10626 #define PMC_LVDSC1_LVDV_MASK (0x3U)
<> 144:ef7eb2e8f9f7 10627 #define PMC_LVDSC1_LVDV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10628 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
<> 144:ef7eb2e8f9f7 10629 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 10630 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 10631 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
<> 144:ef7eb2e8f9f7 10632 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10633 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10634 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
<> 144:ef7eb2e8f9f7 10635 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
<> 144:ef7eb2e8f9f7 10636 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10637 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
<> 144:ef7eb2e8f9f7 10638 #define PMC_LVDSC1_LVDF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 10639 #define PMC_LVDSC1_LVDF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 10640 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
<> 144:ef7eb2e8f9f7 10641
<> 144:ef7eb2e8f9f7 10642 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
<> 144:ef7eb2e8f9f7 10643 #define PMC_LVDSC2_LVWV_MASK (0x3U)
<> 144:ef7eb2e8f9f7 10644 #define PMC_LVDSC2_LVWV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10645 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
<> 144:ef7eb2e8f9f7 10646 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10647 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10648 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
<> 144:ef7eb2e8f9f7 10649 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
<> 144:ef7eb2e8f9f7 10650 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10651 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
<> 144:ef7eb2e8f9f7 10652 #define PMC_LVDSC2_LVWF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 10653 #define PMC_LVDSC2_LVWF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 10654 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
<> 144:ef7eb2e8f9f7 10655
<> 144:ef7eb2e8f9f7 10656 /*! @name REGSC - Regulator Status And Control register */
<> 144:ef7eb2e8f9f7 10657 #define PMC_REGSC_BGBE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10658 #define PMC_REGSC_BGBE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10659 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
<> 144:ef7eb2e8f9f7 10660 #define PMC_REGSC_REGONS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10661 #define PMC_REGSC_REGONS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10662 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
<> 144:ef7eb2e8f9f7 10663 #define PMC_REGSC_ACKISO_MASK (0x8U)
<> 144:ef7eb2e8f9f7 10664 #define PMC_REGSC_ACKISO_SHIFT (3U)
<> 144:ef7eb2e8f9f7 10665 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
<> 144:ef7eb2e8f9f7 10666 #define PMC_REGSC_BGEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 10667 #define PMC_REGSC_BGEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 10668 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
<> 144:ef7eb2e8f9f7 10669
<> 144:ef7eb2e8f9f7 10670
<> 144:ef7eb2e8f9f7 10671 /*!
<> 144:ef7eb2e8f9f7 10672 * @}
<> 144:ef7eb2e8f9f7 10673 */ /* end of group PMC_Register_Masks */
<> 144:ef7eb2e8f9f7 10674
<> 144:ef7eb2e8f9f7 10675
<> 144:ef7eb2e8f9f7 10676 /* PMC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10677 /** Peripheral PMC base address */
<> 144:ef7eb2e8f9f7 10678 #define PMC_BASE (0x4007D000u)
<> 144:ef7eb2e8f9f7 10679 /** Peripheral PMC base pointer */
<> 144:ef7eb2e8f9f7 10680 #define PMC ((PMC_Type *)PMC_BASE)
<> 144:ef7eb2e8f9f7 10681 /** Array initializer of PMC peripheral base addresses */
<> 144:ef7eb2e8f9f7 10682 #define PMC_BASE_ADDRS { PMC_BASE }
<> 144:ef7eb2e8f9f7 10683 /** Array initializer of PMC peripheral base pointers */
<> 144:ef7eb2e8f9f7 10684 #define PMC_BASE_PTRS { PMC }
<> 144:ef7eb2e8f9f7 10685 /** Interrupt vectors for the PMC peripheral type */
<> 144:ef7eb2e8f9f7 10686 #define PMC_IRQS { LVD_LVW_IRQn }
<> 144:ef7eb2e8f9f7 10687
<> 144:ef7eb2e8f9f7 10688 /*!
<> 144:ef7eb2e8f9f7 10689 * @}
<> 144:ef7eb2e8f9f7 10690 */ /* end of group PMC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10691
<> 144:ef7eb2e8f9f7 10692
<> 144:ef7eb2e8f9f7 10693 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10694 -- PORT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10695 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10696
<> 144:ef7eb2e8f9f7 10697 /*!
<> 144:ef7eb2e8f9f7 10698 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10699 * @{
<> 144:ef7eb2e8f9f7 10700 */
<> 144:ef7eb2e8f9f7 10701
<> 144:ef7eb2e8f9f7 10702 /** PORT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10703 typedef struct {
<> 144:ef7eb2e8f9f7 10704 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 10705 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 10706 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 10707 uint8_t RESERVED_0[24];
<> 144:ef7eb2e8f9f7 10708 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
<> 144:ef7eb2e8f9f7 10709 uint8_t RESERVED_1[28];
<> 144:ef7eb2e8f9f7 10710 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
<> 144:ef7eb2e8f9f7 10711 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
<> 144:ef7eb2e8f9f7 10712 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
<> 144:ef7eb2e8f9f7 10713 } PORT_Type;
<> 144:ef7eb2e8f9f7 10714
<> 144:ef7eb2e8f9f7 10715 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10716 -- PORT Register Masks
<> 144:ef7eb2e8f9f7 10717 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10718
<> 144:ef7eb2e8f9f7 10719 /*!
<> 144:ef7eb2e8f9f7 10720 * @addtogroup PORT_Register_Masks PORT Register Masks
<> 144:ef7eb2e8f9f7 10721 * @{
<> 144:ef7eb2e8f9f7 10722 */
<> 144:ef7eb2e8f9f7 10723
<> 144:ef7eb2e8f9f7 10724 /*! @name PCR - Pin Control Register n */
<> 144:ef7eb2e8f9f7 10725 #define PORT_PCR_PS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10726 #define PORT_PCR_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10727 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
<> 144:ef7eb2e8f9f7 10728 #define PORT_PCR_PE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10729 #define PORT_PCR_PE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10730 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
<> 144:ef7eb2e8f9f7 10731 #define PORT_PCR_SRE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10732 #define PORT_PCR_SRE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10733 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
<> 144:ef7eb2e8f9f7 10734 #define PORT_PCR_PFE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 10735 #define PORT_PCR_PFE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 10736 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
<> 144:ef7eb2e8f9f7 10737 #define PORT_PCR_ODE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10738 #define PORT_PCR_ODE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10739 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
<> 144:ef7eb2e8f9f7 10740 #define PORT_PCR_DSE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 10741 #define PORT_PCR_DSE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10742 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
<> 144:ef7eb2e8f9f7 10743 #define PORT_PCR_MUX_MASK (0x700U)
<> 144:ef7eb2e8f9f7 10744 #define PORT_PCR_MUX_SHIFT (8U)
<> 144:ef7eb2e8f9f7 10745 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
<> 144:ef7eb2e8f9f7 10746 #define PORT_PCR_LK_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 10747 #define PORT_PCR_LK_SHIFT (15U)
<> 144:ef7eb2e8f9f7 10748 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
<> 144:ef7eb2e8f9f7 10749 #define PORT_PCR_IRQC_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 10750 #define PORT_PCR_IRQC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10751 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
<> 144:ef7eb2e8f9f7 10752 #define PORT_PCR_ISF_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 10753 #define PORT_PCR_ISF_SHIFT (24U)
<> 144:ef7eb2e8f9f7 10754 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
<> 144:ef7eb2e8f9f7 10755
<> 144:ef7eb2e8f9f7 10756 /* The count of PORT_PCR */
<> 144:ef7eb2e8f9f7 10757 #define PORT_PCR_COUNT (32U)
<> 144:ef7eb2e8f9f7 10758
<> 144:ef7eb2e8f9f7 10759 /*! @name GPCLR - Global Pin Control Low Register */
<> 144:ef7eb2e8f9f7 10760 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10761 #define PORT_GPCLR_GPWD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10762 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
<> 144:ef7eb2e8f9f7 10763 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 10764 #define PORT_GPCLR_GPWE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10765 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
<> 144:ef7eb2e8f9f7 10766
<> 144:ef7eb2e8f9f7 10767 /*! @name GPCHR - Global Pin Control High Register */
<> 144:ef7eb2e8f9f7 10768 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 10769 #define PORT_GPCHR_GPWD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10770 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
<> 144:ef7eb2e8f9f7 10771 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 10772 #define PORT_GPCHR_GPWE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 10773 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
<> 144:ef7eb2e8f9f7 10774
<> 144:ef7eb2e8f9f7 10775 /*! @name ISFR - Interrupt Status Flag Register */
<> 144:ef7eb2e8f9f7 10776 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 10777 #define PORT_ISFR_ISF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10778 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
<> 144:ef7eb2e8f9f7 10779
<> 144:ef7eb2e8f9f7 10780 /*! @name DFER - Digital Filter Enable Register */
<> 144:ef7eb2e8f9f7 10781 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 10782 #define PORT_DFER_DFE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10783 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
<> 144:ef7eb2e8f9f7 10784
<> 144:ef7eb2e8f9f7 10785 /*! @name DFCR - Digital Filter Clock Register */
<> 144:ef7eb2e8f9f7 10786 #define PORT_DFCR_CS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10787 #define PORT_DFCR_CS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10788 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
<> 144:ef7eb2e8f9f7 10789
<> 144:ef7eb2e8f9f7 10790 /*! @name DFWR - Digital Filter Width Register */
<> 144:ef7eb2e8f9f7 10791 #define PORT_DFWR_FILT_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 10792 #define PORT_DFWR_FILT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10793 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
<> 144:ef7eb2e8f9f7 10794
<> 144:ef7eb2e8f9f7 10795
<> 144:ef7eb2e8f9f7 10796 /*!
<> 144:ef7eb2e8f9f7 10797 * @}
<> 144:ef7eb2e8f9f7 10798 */ /* end of group PORT_Register_Masks */
<> 144:ef7eb2e8f9f7 10799
<> 144:ef7eb2e8f9f7 10800
<> 144:ef7eb2e8f9f7 10801 /* PORT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10802 /** Peripheral PORTA base address */
<> 144:ef7eb2e8f9f7 10803 #define PORTA_BASE (0x40049000u)
<> 144:ef7eb2e8f9f7 10804 /** Peripheral PORTA base pointer */
<> 144:ef7eb2e8f9f7 10805 #define PORTA ((PORT_Type *)PORTA_BASE)
<> 144:ef7eb2e8f9f7 10806 /** Peripheral PORTB base address */
<> 144:ef7eb2e8f9f7 10807 #define PORTB_BASE (0x4004A000u)
<> 144:ef7eb2e8f9f7 10808 /** Peripheral PORTB base pointer */
<> 144:ef7eb2e8f9f7 10809 #define PORTB ((PORT_Type *)PORTB_BASE)
<> 144:ef7eb2e8f9f7 10810 /** Peripheral PORTC base address */
<> 144:ef7eb2e8f9f7 10811 #define PORTC_BASE (0x4004B000u)
<> 144:ef7eb2e8f9f7 10812 /** Peripheral PORTC base pointer */
<> 144:ef7eb2e8f9f7 10813 #define PORTC ((PORT_Type *)PORTC_BASE)
<> 144:ef7eb2e8f9f7 10814 /** Peripheral PORTD base address */
<> 144:ef7eb2e8f9f7 10815 #define PORTD_BASE (0x4004C000u)
<> 144:ef7eb2e8f9f7 10816 /** Peripheral PORTD base pointer */
<> 144:ef7eb2e8f9f7 10817 #define PORTD ((PORT_Type *)PORTD_BASE)
<> 144:ef7eb2e8f9f7 10818 /** Peripheral PORTE base address */
<> 144:ef7eb2e8f9f7 10819 #define PORTE_BASE (0x4004D000u)
<> 144:ef7eb2e8f9f7 10820 /** Peripheral PORTE base pointer */
<> 144:ef7eb2e8f9f7 10821 #define PORTE ((PORT_Type *)PORTE_BASE)
<> 144:ef7eb2e8f9f7 10822 /** Array initializer of PORT peripheral base addresses */
<> 144:ef7eb2e8f9f7 10823 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
<> 144:ef7eb2e8f9f7 10824 /** Array initializer of PORT peripheral base pointers */
<> 144:ef7eb2e8f9f7 10825 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
<> 144:ef7eb2e8f9f7 10826 /** Interrupt vectors for the PORT peripheral type */
<> 144:ef7eb2e8f9f7 10827 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
<> 144:ef7eb2e8f9f7 10828
<> 144:ef7eb2e8f9f7 10829 /*!
<> 144:ef7eb2e8f9f7 10830 * @}
<> 144:ef7eb2e8f9f7 10831 */ /* end of group PORT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10832
<> 144:ef7eb2e8f9f7 10833
<> 144:ef7eb2e8f9f7 10834 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10835 -- RCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10836 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10837
<> 144:ef7eb2e8f9f7 10838 /*!
<> 144:ef7eb2e8f9f7 10839 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10840 * @{
<> 144:ef7eb2e8f9f7 10841 */
<> 144:ef7eb2e8f9f7 10842
<> 144:ef7eb2e8f9f7 10843 /** RCM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 10844 typedef struct {
<> 144:ef7eb2e8f9f7 10845 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
<> 144:ef7eb2e8f9f7 10846 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
<> 144:ef7eb2e8f9f7 10847 uint8_t RESERVED_0[2];
<> 144:ef7eb2e8f9f7 10848 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 10849 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
<> 144:ef7eb2e8f9f7 10850 uint8_t RESERVED_1[1];
<> 144:ef7eb2e8f9f7 10851 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 10852 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
<> 144:ef7eb2e8f9f7 10853 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
<> 144:ef7eb2e8f9f7 10854 } RCM_Type;
<> 144:ef7eb2e8f9f7 10855
<> 144:ef7eb2e8f9f7 10856 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10857 -- RCM Register Masks
<> 144:ef7eb2e8f9f7 10858 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10859
<> 144:ef7eb2e8f9f7 10860 /*!
<> 144:ef7eb2e8f9f7 10861 * @addtogroup RCM_Register_Masks RCM Register Masks
<> 144:ef7eb2e8f9f7 10862 * @{
<> 144:ef7eb2e8f9f7 10863 */
<> 144:ef7eb2e8f9f7 10864
<> 144:ef7eb2e8f9f7 10865 /*! @name SRS0 - System Reset Status Register 0 */
<> 144:ef7eb2e8f9f7 10866 #define RCM_SRS0_WAKEUP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10867 #define RCM_SRS0_WAKEUP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10868 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
<> 144:ef7eb2e8f9f7 10869 #define RCM_SRS0_LVD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10870 #define RCM_SRS0_LVD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10871 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
<> 144:ef7eb2e8f9f7 10872 #define RCM_SRS0_LOC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10873 #define RCM_SRS0_LOC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10874 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
<> 144:ef7eb2e8f9f7 10875 #define RCM_SRS0_LOL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 10876 #define RCM_SRS0_LOL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 10877 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
<> 144:ef7eb2e8f9f7 10878 #define RCM_SRS0_WDOG_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10879 #define RCM_SRS0_WDOG_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10880 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
<> 144:ef7eb2e8f9f7 10881 #define RCM_SRS0_PIN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 10882 #define RCM_SRS0_PIN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10883 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
<> 144:ef7eb2e8f9f7 10884 #define RCM_SRS0_POR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 10885 #define RCM_SRS0_POR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 10886 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
<> 144:ef7eb2e8f9f7 10887
<> 144:ef7eb2e8f9f7 10888 /*! @name SRS1 - System Reset Status Register 1 */
<> 144:ef7eb2e8f9f7 10889 #define RCM_SRS1_JTAG_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10890 #define RCM_SRS1_JTAG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10891 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
<> 144:ef7eb2e8f9f7 10892 #define RCM_SRS1_LOCKUP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10893 #define RCM_SRS1_LOCKUP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10894 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
<> 144:ef7eb2e8f9f7 10895 #define RCM_SRS1_SW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10896 #define RCM_SRS1_SW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10897 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
<> 144:ef7eb2e8f9f7 10898 #define RCM_SRS1_MDM_AP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 10899 #define RCM_SRS1_MDM_AP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 10900 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
<> 144:ef7eb2e8f9f7 10901 #define RCM_SRS1_EZPT_MASK (0x10U)
<> 144:ef7eb2e8f9f7 10902 #define RCM_SRS1_EZPT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 10903 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
<> 144:ef7eb2e8f9f7 10904 #define RCM_SRS1_SACKERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10905 #define RCM_SRS1_SACKERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10906 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
<> 144:ef7eb2e8f9f7 10907
<> 144:ef7eb2e8f9f7 10908 /*! @name RPFC - Reset Pin Filter Control register */
<> 144:ef7eb2e8f9f7 10909 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
<> 144:ef7eb2e8f9f7 10910 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10911 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
<> 144:ef7eb2e8f9f7 10912 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10913 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10914 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
<> 144:ef7eb2e8f9f7 10915
<> 144:ef7eb2e8f9f7 10916 /*! @name RPFW - Reset Pin Filter Width register */
<> 144:ef7eb2e8f9f7 10917 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 10918 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10919 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
<> 144:ef7eb2e8f9f7 10920
<> 144:ef7eb2e8f9f7 10921 /*! @name MR - Mode Register */
<> 144:ef7eb2e8f9f7 10922 #define RCM_MR_EZP_MS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10923 #define RCM_MR_EZP_MS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10924 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
<> 144:ef7eb2e8f9f7 10925
<> 144:ef7eb2e8f9f7 10926 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
<> 144:ef7eb2e8f9f7 10927 #define RCM_SSRS0_SWAKEUP_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10928 #define RCM_SSRS0_SWAKEUP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10929 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
<> 144:ef7eb2e8f9f7 10930 #define RCM_SSRS0_SLVD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10931 #define RCM_SSRS0_SLVD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10932 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
<> 144:ef7eb2e8f9f7 10933 #define RCM_SSRS0_SLOC_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10934 #define RCM_SSRS0_SLOC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10935 #define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
<> 144:ef7eb2e8f9f7 10936 #define RCM_SSRS0_SLOL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 10937 #define RCM_SSRS0_SLOL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 10938 #define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
<> 144:ef7eb2e8f9f7 10939 #define RCM_SSRS0_SWDOG_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10940 #define RCM_SSRS0_SWDOG_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10941 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
<> 144:ef7eb2e8f9f7 10942 #define RCM_SSRS0_SPIN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 10943 #define RCM_SSRS0_SPIN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 10944 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
<> 144:ef7eb2e8f9f7 10945 #define RCM_SSRS0_SPOR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 10946 #define RCM_SSRS0_SPOR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 10947 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
<> 144:ef7eb2e8f9f7 10948
<> 144:ef7eb2e8f9f7 10949 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
<> 144:ef7eb2e8f9f7 10950 #define RCM_SSRS1_SJTAG_MASK (0x1U)
<> 144:ef7eb2e8f9f7 10951 #define RCM_SSRS1_SJTAG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 10952 #define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
<> 144:ef7eb2e8f9f7 10953 #define RCM_SSRS1_SLOCKUP_MASK (0x2U)
<> 144:ef7eb2e8f9f7 10954 #define RCM_SSRS1_SLOCKUP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 10955 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
<> 144:ef7eb2e8f9f7 10956 #define RCM_SSRS1_SSW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 10957 #define RCM_SSRS1_SSW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 10958 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
<> 144:ef7eb2e8f9f7 10959 #define RCM_SSRS1_SMDM_AP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 10960 #define RCM_SSRS1_SMDM_AP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 10961 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
<> 144:ef7eb2e8f9f7 10962 #define RCM_SSRS1_SEZPT_MASK (0x10U)
<> 144:ef7eb2e8f9f7 10963 #define RCM_SSRS1_SEZPT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 10964 #define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
<> 144:ef7eb2e8f9f7 10965 #define RCM_SSRS1_SSACKERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 10966 #define RCM_SSRS1_SSACKERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 10967 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
<> 144:ef7eb2e8f9f7 10968
<> 144:ef7eb2e8f9f7 10969
<> 144:ef7eb2e8f9f7 10970 /*!
<> 144:ef7eb2e8f9f7 10971 * @}
<> 144:ef7eb2e8f9f7 10972 */ /* end of group RCM_Register_Masks */
<> 144:ef7eb2e8f9f7 10973
<> 144:ef7eb2e8f9f7 10974
<> 144:ef7eb2e8f9f7 10975 /* RCM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 10976 /** Peripheral RCM base address */
<> 144:ef7eb2e8f9f7 10977 #define RCM_BASE (0x4007F000u)
<> 144:ef7eb2e8f9f7 10978 /** Peripheral RCM base pointer */
<> 144:ef7eb2e8f9f7 10979 #define RCM ((RCM_Type *)RCM_BASE)
<> 144:ef7eb2e8f9f7 10980 /** Array initializer of RCM peripheral base addresses */
<> 144:ef7eb2e8f9f7 10981 #define RCM_BASE_ADDRS { RCM_BASE }
<> 144:ef7eb2e8f9f7 10982 /** Array initializer of RCM peripheral base pointers */
<> 144:ef7eb2e8f9f7 10983 #define RCM_BASE_PTRS { RCM }
<> 144:ef7eb2e8f9f7 10984
<> 144:ef7eb2e8f9f7 10985 /*!
<> 144:ef7eb2e8f9f7 10986 * @}
<> 144:ef7eb2e8f9f7 10987 */ /* end of group RCM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 10988
<> 144:ef7eb2e8f9f7 10989
<> 144:ef7eb2e8f9f7 10990 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 10991 -- RFSYS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10992 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 10993
<> 144:ef7eb2e8f9f7 10994 /*!
<> 144:ef7eb2e8f9f7 10995 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 10996 * @{
<> 144:ef7eb2e8f9f7 10997 */
<> 144:ef7eb2e8f9f7 10998
<> 144:ef7eb2e8f9f7 10999 /** RFSYS - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 11000 typedef struct {
<> 144:ef7eb2e8f9f7 11001 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 11002 } RFSYS_Type;
<> 144:ef7eb2e8f9f7 11003
<> 144:ef7eb2e8f9f7 11004 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11005 -- RFSYS Register Masks
<> 144:ef7eb2e8f9f7 11006 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11007
<> 144:ef7eb2e8f9f7 11008 /*!
<> 144:ef7eb2e8f9f7 11009 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
<> 144:ef7eb2e8f9f7 11010 * @{
<> 144:ef7eb2e8f9f7 11011 */
<> 144:ef7eb2e8f9f7 11012
<> 144:ef7eb2e8f9f7 11013 /*! @name REG - Register file register */
<> 144:ef7eb2e8f9f7 11014 #define RFSYS_REG_LL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 11015 #define RFSYS_REG_LL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11016 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
<> 144:ef7eb2e8f9f7 11017 #define RFSYS_REG_LH_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 11018 #define RFSYS_REG_LH_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11019 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
<> 144:ef7eb2e8f9f7 11020 #define RFSYS_REG_HL_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 11021 #define RFSYS_REG_HL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11022 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
<> 144:ef7eb2e8f9f7 11023 #define RFSYS_REG_HH_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 11024 #define RFSYS_REG_HH_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11025 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
<> 144:ef7eb2e8f9f7 11026
<> 144:ef7eb2e8f9f7 11027 /* The count of RFSYS_REG */
<> 144:ef7eb2e8f9f7 11028 #define RFSYS_REG_COUNT (8U)
<> 144:ef7eb2e8f9f7 11029
<> 144:ef7eb2e8f9f7 11030
<> 144:ef7eb2e8f9f7 11031 /*!
<> 144:ef7eb2e8f9f7 11032 * @}
<> 144:ef7eb2e8f9f7 11033 */ /* end of group RFSYS_Register_Masks */
<> 144:ef7eb2e8f9f7 11034
<> 144:ef7eb2e8f9f7 11035
<> 144:ef7eb2e8f9f7 11036 /* RFSYS - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 11037 /** Peripheral RFSYS base address */
<> 144:ef7eb2e8f9f7 11038 #define RFSYS_BASE (0x40041000u)
<> 144:ef7eb2e8f9f7 11039 /** Peripheral RFSYS base pointer */
<> 144:ef7eb2e8f9f7 11040 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
<> 144:ef7eb2e8f9f7 11041 /** Array initializer of RFSYS peripheral base addresses */
<> 144:ef7eb2e8f9f7 11042 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
<> 144:ef7eb2e8f9f7 11043 /** Array initializer of RFSYS peripheral base pointers */
<> 144:ef7eb2e8f9f7 11044 #define RFSYS_BASE_PTRS { RFSYS }
<> 144:ef7eb2e8f9f7 11045
<> 144:ef7eb2e8f9f7 11046 /*!
<> 144:ef7eb2e8f9f7 11047 * @}
<> 144:ef7eb2e8f9f7 11048 */ /* end of group RFSYS_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 11049
<> 144:ef7eb2e8f9f7 11050
<> 144:ef7eb2e8f9f7 11051 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11052 -- RFVBAT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11053 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11054
<> 144:ef7eb2e8f9f7 11055 /*!
<> 144:ef7eb2e8f9f7 11056 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11057 * @{
<> 144:ef7eb2e8f9f7 11058 */
<> 144:ef7eb2e8f9f7 11059
<> 144:ef7eb2e8f9f7 11060 /** RFVBAT - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 11061 typedef struct {
<> 144:ef7eb2e8f9f7 11062 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 11063 } RFVBAT_Type;
<> 144:ef7eb2e8f9f7 11064
<> 144:ef7eb2e8f9f7 11065 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11066 -- RFVBAT Register Masks
<> 144:ef7eb2e8f9f7 11067 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11068
<> 144:ef7eb2e8f9f7 11069 /*!
<> 144:ef7eb2e8f9f7 11070 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
<> 144:ef7eb2e8f9f7 11071 * @{
<> 144:ef7eb2e8f9f7 11072 */
<> 144:ef7eb2e8f9f7 11073
<> 144:ef7eb2e8f9f7 11074 /*! @name REG - VBAT register file register */
<> 144:ef7eb2e8f9f7 11075 #define RFVBAT_REG_LL_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 11076 #define RFVBAT_REG_LL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11077 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
<> 144:ef7eb2e8f9f7 11078 #define RFVBAT_REG_LH_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 11079 #define RFVBAT_REG_LH_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11080 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
<> 144:ef7eb2e8f9f7 11081 #define RFVBAT_REG_HL_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 11082 #define RFVBAT_REG_HL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11083 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
<> 144:ef7eb2e8f9f7 11084 #define RFVBAT_REG_HH_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 11085 #define RFVBAT_REG_HH_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11086 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
<> 144:ef7eb2e8f9f7 11087
<> 144:ef7eb2e8f9f7 11088 /* The count of RFVBAT_REG */
<> 144:ef7eb2e8f9f7 11089 #define RFVBAT_REG_COUNT (8U)
<> 144:ef7eb2e8f9f7 11090
<> 144:ef7eb2e8f9f7 11091
<> 144:ef7eb2e8f9f7 11092 /*!
<> 144:ef7eb2e8f9f7 11093 * @}
<> 144:ef7eb2e8f9f7 11094 */ /* end of group RFVBAT_Register_Masks */
<> 144:ef7eb2e8f9f7 11095
<> 144:ef7eb2e8f9f7 11096
<> 144:ef7eb2e8f9f7 11097 /* RFVBAT - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 11098 /** Peripheral RFVBAT base address */
<> 144:ef7eb2e8f9f7 11099 #define RFVBAT_BASE (0x4003E000u)
<> 144:ef7eb2e8f9f7 11100 /** Peripheral RFVBAT base pointer */
<> 144:ef7eb2e8f9f7 11101 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
<> 144:ef7eb2e8f9f7 11102 /** Array initializer of RFVBAT peripheral base addresses */
<> 144:ef7eb2e8f9f7 11103 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
<> 144:ef7eb2e8f9f7 11104 /** Array initializer of RFVBAT peripheral base pointers */
<> 144:ef7eb2e8f9f7 11105 #define RFVBAT_BASE_PTRS { RFVBAT }
<> 144:ef7eb2e8f9f7 11106
<> 144:ef7eb2e8f9f7 11107 /*!
<> 144:ef7eb2e8f9f7 11108 * @}
<> 144:ef7eb2e8f9f7 11109 */ /* end of group RFVBAT_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 11110
<> 144:ef7eb2e8f9f7 11111
<> 144:ef7eb2e8f9f7 11112 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11113 -- RNG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11114 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11115
<> 144:ef7eb2e8f9f7 11116 /*!
<> 144:ef7eb2e8f9f7 11117 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11118 * @{
<> 144:ef7eb2e8f9f7 11119 */
<> 144:ef7eb2e8f9f7 11120
<> 144:ef7eb2e8f9f7 11121 /** RNG - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 11122 typedef struct {
<> 144:ef7eb2e8f9f7 11123 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 11124 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 11125 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 11126 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 11127 } RNG_Type;
<> 144:ef7eb2e8f9f7 11128
<> 144:ef7eb2e8f9f7 11129 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11130 -- RNG Register Masks
<> 144:ef7eb2e8f9f7 11131 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11132
<> 144:ef7eb2e8f9f7 11133 /*!
<> 144:ef7eb2e8f9f7 11134 * @addtogroup RNG_Register_Masks RNG Register Masks
<> 144:ef7eb2e8f9f7 11135 * @{
<> 144:ef7eb2e8f9f7 11136 */
<> 144:ef7eb2e8f9f7 11137
<> 144:ef7eb2e8f9f7 11138 /*! @name CR - RNGA Control Register */
<> 144:ef7eb2e8f9f7 11139 #define RNG_CR_GO_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11140 #define RNG_CR_GO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11141 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
<> 144:ef7eb2e8f9f7 11142 #define RNG_CR_HA_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11143 #define RNG_CR_HA_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11144 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
<> 144:ef7eb2e8f9f7 11145 #define RNG_CR_INTM_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11146 #define RNG_CR_INTM_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11147 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
<> 144:ef7eb2e8f9f7 11148 #define RNG_CR_CLRI_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11149 #define RNG_CR_CLRI_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11150 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
<> 144:ef7eb2e8f9f7 11151 #define RNG_CR_SLP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11152 #define RNG_CR_SLP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11153 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
<> 144:ef7eb2e8f9f7 11154
<> 144:ef7eb2e8f9f7 11155 /*! @name SR - RNGA Status Register */
<> 144:ef7eb2e8f9f7 11156 #define RNG_SR_SECV_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11157 #define RNG_SR_SECV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11158 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
<> 144:ef7eb2e8f9f7 11159 #define RNG_SR_LRS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11160 #define RNG_SR_LRS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11161 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
<> 144:ef7eb2e8f9f7 11162 #define RNG_SR_ORU_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11163 #define RNG_SR_ORU_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11164 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
<> 144:ef7eb2e8f9f7 11165 #define RNG_SR_ERRI_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11166 #define RNG_SR_ERRI_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11167 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
<> 144:ef7eb2e8f9f7 11168 #define RNG_SR_SLP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11169 #define RNG_SR_SLP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11170 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
<> 144:ef7eb2e8f9f7 11171 #define RNG_SR_OREG_LVL_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 11172 #define RNG_SR_OREG_LVL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11173 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
<> 144:ef7eb2e8f9f7 11174 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 11175 #define RNG_SR_OREG_SIZE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11176 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
<> 144:ef7eb2e8f9f7 11177
<> 144:ef7eb2e8f9f7 11178 /*! @name ER - RNGA Entropy Register */
<> 144:ef7eb2e8f9f7 11179 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11180 #define RNG_ER_EXT_ENT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11181 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
<> 144:ef7eb2e8f9f7 11182
<> 144:ef7eb2e8f9f7 11183 /*! @name OR - RNGA Output Register */
<> 144:ef7eb2e8f9f7 11184 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11185 #define RNG_OR_RANDOUT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11186 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
<> 144:ef7eb2e8f9f7 11187
<> 144:ef7eb2e8f9f7 11188
<> 144:ef7eb2e8f9f7 11189 /*!
<> 144:ef7eb2e8f9f7 11190 * @}
<> 144:ef7eb2e8f9f7 11191 */ /* end of group RNG_Register_Masks */
<> 144:ef7eb2e8f9f7 11192
<> 144:ef7eb2e8f9f7 11193
<> 144:ef7eb2e8f9f7 11194 /* RNG - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 11195 /** Peripheral RNG base address */
<> 144:ef7eb2e8f9f7 11196 #define RNG_BASE (0x400A0000u)
<> 144:ef7eb2e8f9f7 11197 /** Peripheral RNG base pointer */
<> 144:ef7eb2e8f9f7 11198 #define RNG ((RNG_Type *)RNG_BASE)
<> 144:ef7eb2e8f9f7 11199 /** Array initializer of RNG peripheral base addresses */
<> 144:ef7eb2e8f9f7 11200 #define RNG_BASE_ADDRS { RNG_BASE }
<> 144:ef7eb2e8f9f7 11201 /** Array initializer of RNG peripheral base pointers */
<> 144:ef7eb2e8f9f7 11202 #define RNG_BASE_PTRS { RNG }
<> 144:ef7eb2e8f9f7 11203 /** Interrupt vectors for the RNG peripheral type */
<> 144:ef7eb2e8f9f7 11204 #define RNG_IRQS { RNG_IRQn }
<> 144:ef7eb2e8f9f7 11205
<> 144:ef7eb2e8f9f7 11206 /*!
<> 144:ef7eb2e8f9f7 11207 * @}
<> 144:ef7eb2e8f9f7 11208 */ /* end of group RNG_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 11209
<> 144:ef7eb2e8f9f7 11210
<> 144:ef7eb2e8f9f7 11211 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11212 -- RTC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11213 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11214
<> 144:ef7eb2e8f9f7 11215 /*!
<> 144:ef7eb2e8f9f7 11216 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11217 * @{
<> 144:ef7eb2e8f9f7 11218 */
<> 144:ef7eb2e8f9f7 11219
<> 144:ef7eb2e8f9f7 11220 /** RTC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 11221 typedef struct {
<> 144:ef7eb2e8f9f7 11222 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 11223 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 11224 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 11225 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 11226 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 11227 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 11228 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 11229 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 11230 __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 11231 __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 11232 __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 11233 __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 11234 uint8_t RESERVED_0[2000];
<> 144:ef7eb2e8f9f7 11235 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
<> 144:ef7eb2e8f9f7 11236 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
<> 144:ef7eb2e8f9f7 11237 } RTC_Type;
<> 144:ef7eb2e8f9f7 11238
<> 144:ef7eb2e8f9f7 11239 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11240 -- RTC Register Masks
<> 144:ef7eb2e8f9f7 11241 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11242
<> 144:ef7eb2e8f9f7 11243 /*!
<> 144:ef7eb2e8f9f7 11244 * @addtogroup RTC_Register_Masks RTC Register Masks
<> 144:ef7eb2e8f9f7 11245 * @{
<> 144:ef7eb2e8f9f7 11246 */
<> 144:ef7eb2e8f9f7 11247
<> 144:ef7eb2e8f9f7 11248 /*! @name TSR - RTC Time Seconds Register */
<> 144:ef7eb2e8f9f7 11249 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11250 #define RTC_TSR_TSR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11251 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
<> 144:ef7eb2e8f9f7 11252
<> 144:ef7eb2e8f9f7 11253 /*! @name TPR - RTC Time Prescaler Register */
<> 144:ef7eb2e8f9f7 11254 #define RTC_TPR_TPR_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 11255 #define RTC_TPR_TPR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11256 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
<> 144:ef7eb2e8f9f7 11257
<> 144:ef7eb2e8f9f7 11258 /*! @name TAR - RTC Time Alarm Register */
<> 144:ef7eb2e8f9f7 11259 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11260 #define RTC_TAR_TAR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11261 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
<> 144:ef7eb2e8f9f7 11262
<> 144:ef7eb2e8f9f7 11263 /*! @name TCR - RTC Time Compensation Register */
<> 144:ef7eb2e8f9f7 11264 #define RTC_TCR_TCR_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 11265 #define RTC_TCR_TCR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11266 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
<> 144:ef7eb2e8f9f7 11267 #define RTC_TCR_CIR_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 11268 #define RTC_TCR_CIR_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11269 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
<> 144:ef7eb2e8f9f7 11270 #define RTC_TCR_TCV_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 11271 #define RTC_TCR_TCV_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11272 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
<> 144:ef7eb2e8f9f7 11273 #define RTC_TCR_CIC_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 11274 #define RTC_TCR_CIC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11275 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
<> 144:ef7eb2e8f9f7 11276
<> 144:ef7eb2e8f9f7 11277 /*! @name CR - RTC Control Register */
<> 144:ef7eb2e8f9f7 11278 #define RTC_CR_SWR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11279 #define RTC_CR_SWR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11280 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
<> 144:ef7eb2e8f9f7 11281 #define RTC_CR_WPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11282 #define RTC_CR_WPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11283 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
<> 144:ef7eb2e8f9f7 11284 #define RTC_CR_SUP_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11285 #define RTC_CR_SUP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11286 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
<> 144:ef7eb2e8f9f7 11287 #define RTC_CR_UM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11288 #define RTC_CR_UM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11289 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
<> 144:ef7eb2e8f9f7 11290 #define RTC_CR_WPS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11291 #define RTC_CR_WPS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11292 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
<> 144:ef7eb2e8f9f7 11293 #define RTC_CR_OSCE_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11294 #define RTC_CR_OSCE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11295 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
<> 144:ef7eb2e8f9f7 11296 #define RTC_CR_CLKO_MASK (0x200U)
<> 144:ef7eb2e8f9f7 11297 #define RTC_CR_CLKO_SHIFT (9U)
<> 144:ef7eb2e8f9f7 11298 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
<> 144:ef7eb2e8f9f7 11299 #define RTC_CR_SC16P_MASK (0x400U)
<> 144:ef7eb2e8f9f7 11300 #define RTC_CR_SC16P_SHIFT (10U)
<> 144:ef7eb2e8f9f7 11301 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
<> 144:ef7eb2e8f9f7 11302 #define RTC_CR_SC8P_MASK (0x800U)
<> 144:ef7eb2e8f9f7 11303 #define RTC_CR_SC8P_SHIFT (11U)
<> 144:ef7eb2e8f9f7 11304 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
<> 144:ef7eb2e8f9f7 11305 #define RTC_CR_SC4P_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 11306 #define RTC_CR_SC4P_SHIFT (12U)
<> 144:ef7eb2e8f9f7 11307 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
<> 144:ef7eb2e8f9f7 11308 #define RTC_CR_SC2P_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 11309 #define RTC_CR_SC2P_SHIFT (13U)
<> 144:ef7eb2e8f9f7 11310 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
<> 144:ef7eb2e8f9f7 11311
<> 144:ef7eb2e8f9f7 11312 /*! @name SR - RTC Status Register */
<> 144:ef7eb2e8f9f7 11313 #define RTC_SR_TIF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11314 #define RTC_SR_TIF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11315 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
<> 144:ef7eb2e8f9f7 11316 #define RTC_SR_TOF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11317 #define RTC_SR_TOF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11318 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
<> 144:ef7eb2e8f9f7 11319 #define RTC_SR_TAF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11320 #define RTC_SR_TAF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11321 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
<> 144:ef7eb2e8f9f7 11322 #define RTC_SR_MOF_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11323 #define RTC_SR_MOF_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11324 #define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
<> 144:ef7eb2e8f9f7 11325 #define RTC_SR_TCE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11326 #define RTC_SR_TCE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11327 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
<> 144:ef7eb2e8f9f7 11328
<> 144:ef7eb2e8f9f7 11329 /*! @name LR - RTC Lock Register */
<> 144:ef7eb2e8f9f7 11330 #define RTC_LR_TCL_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11331 #define RTC_LR_TCL_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11332 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
<> 144:ef7eb2e8f9f7 11333 #define RTC_LR_CRL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11334 #define RTC_LR_CRL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11335 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
<> 144:ef7eb2e8f9f7 11336 #define RTC_LR_SRL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11337 #define RTC_LR_SRL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11338 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
<> 144:ef7eb2e8f9f7 11339 #define RTC_LR_LRL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11340 #define RTC_LR_LRL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11341 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
<> 144:ef7eb2e8f9f7 11342 #define RTC_LR_TTSL_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11343 #define RTC_LR_TTSL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11344 #define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
<> 144:ef7eb2e8f9f7 11345 #define RTC_LR_MEL_MASK (0x200U)
<> 144:ef7eb2e8f9f7 11346 #define RTC_LR_MEL_SHIFT (9U)
<> 144:ef7eb2e8f9f7 11347 #define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
<> 144:ef7eb2e8f9f7 11348 #define RTC_LR_MCLL_MASK (0x400U)
<> 144:ef7eb2e8f9f7 11349 #define RTC_LR_MCLL_SHIFT (10U)
<> 144:ef7eb2e8f9f7 11350 #define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
<> 144:ef7eb2e8f9f7 11351 #define RTC_LR_MCHL_MASK (0x800U)
<> 144:ef7eb2e8f9f7 11352 #define RTC_LR_MCHL_SHIFT (11U)
<> 144:ef7eb2e8f9f7 11353 #define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
<> 144:ef7eb2e8f9f7 11354
<> 144:ef7eb2e8f9f7 11355 /*! @name IER - RTC Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 11356 #define RTC_IER_TIIE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11357 #define RTC_IER_TIIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11358 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
<> 144:ef7eb2e8f9f7 11359 #define RTC_IER_TOIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11360 #define RTC_IER_TOIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11361 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
<> 144:ef7eb2e8f9f7 11362 #define RTC_IER_TAIE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11363 #define RTC_IER_TAIE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11364 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
<> 144:ef7eb2e8f9f7 11365 #define RTC_IER_MOIE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11366 #define RTC_IER_MOIE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11367 #define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
<> 144:ef7eb2e8f9f7 11368 #define RTC_IER_TSIE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11369 #define RTC_IER_TSIE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11370 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
<> 144:ef7eb2e8f9f7 11371 #define RTC_IER_WPON_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11372 #define RTC_IER_WPON_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11373 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
<> 144:ef7eb2e8f9f7 11374
<> 144:ef7eb2e8f9f7 11375 /*! @name TTSR - RTC Tamper Time Seconds Register */
<> 144:ef7eb2e8f9f7 11376 #define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11377 #define RTC_TTSR_TTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11378 #define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
<> 144:ef7eb2e8f9f7 11379
<> 144:ef7eb2e8f9f7 11380 /*! @name MER - RTC Monotonic Enable Register */
<> 144:ef7eb2e8f9f7 11381 #define RTC_MER_MCE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11382 #define RTC_MER_MCE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11383 #define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
<> 144:ef7eb2e8f9f7 11384
<> 144:ef7eb2e8f9f7 11385 /*! @name MCLR - RTC Monotonic Counter Low Register */
<> 144:ef7eb2e8f9f7 11386 #define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11387 #define RTC_MCLR_MCL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11388 #define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
<> 144:ef7eb2e8f9f7 11389
<> 144:ef7eb2e8f9f7 11390 /*! @name MCHR - RTC Monotonic Counter High Register */
<> 144:ef7eb2e8f9f7 11391 #define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11392 #define RTC_MCHR_MCH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11393 #define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
<> 144:ef7eb2e8f9f7 11394
<> 144:ef7eb2e8f9f7 11395 /*! @name WAR - RTC Write Access Register */
<> 144:ef7eb2e8f9f7 11396 #define RTC_WAR_TSRW_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11397 #define RTC_WAR_TSRW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11398 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
<> 144:ef7eb2e8f9f7 11399 #define RTC_WAR_TPRW_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11400 #define RTC_WAR_TPRW_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11401 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
<> 144:ef7eb2e8f9f7 11402 #define RTC_WAR_TARW_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11403 #define RTC_WAR_TARW_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11404 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
<> 144:ef7eb2e8f9f7 11405 #define RTC_WAR_TCRW_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11406 #define RTC_WAR_TCRW_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11407 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
<> 144:ef7eb2e8f9f7 11408 #define RTC_WAR_CRW_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11409 #define RTC_WAR_CRW_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11410 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
<> 144:ef7eb2e8f9f7 11411 #define RTC_WAR_SRW_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11412 #define RTC_WAR_SRW_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11413 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
<> 144:ef7eb2e8f9f7 11414 #define RTC_WAR_LRW_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11415 #define RTC_WAR_LRW_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11416 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
<> 144:ef7eb2e8f9f7 11417 #define RTC_WAR_IERW_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11418 #define RTC_WAR_IERW_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11419 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
<> 144:ef7eb2e8f9f7 11420 #define RTC_WAR_TTSW_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11421 #define RTC_WAR_TTSW_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11422 #define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
<> 144:ef7eb2e8f9f7 11423 #define RTC_WAR_MERW_MASK (0x200U)
<> 144:ef7eb2e8f9f7 11424 #define RTC_WAR_MERW_SHIFT (9U)
<> 144:ef7eb2e8f9f7 11425 #define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
<> 144:ef7eb2e8f9f7 11426 #define RTC_WAR_MCLW_MASK (0x400U)
<> 144:ef7eb2e8f9f7 11427 #define RTC_WAR_MCLW_SHIFT (10U)
<> 144:ef7eb2e8f9f7 11428 #define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
<> 144:ef7eb2e8f9f7 11429 #define RTC_WAR_MCHW_MASK (0x800U)
<> 144:ef7eb2e8f9f7 11430 #define RTC_WAR_MCHW_SHIFT (11U)
<> 144:ef7eb2e8f9f7 11431 #define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
<> 144:ef7eb2e8f9f7 11432
<> 144:ef7eb2e8f9f7 11433 /*! @name RAR - RTC Read Access Register */
<> 144:ef7eb2e8f9f7 11434 #define RTC_RAR_TSRR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11435 #define RTC_RAR_TSRR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11436 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
<> 144:ef7eb2e8f9f7 11437 #define RTC_RAR_TPRR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11438 #define RTC_RAR_TPRR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11439 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
<> 144:ef7eb2e8f9f7 11440 #define RTC_RAR_TARR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11441 #define RTC_RAR_TARR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11442 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
<> 144:ef7eb2e8f9f7 11443 #define RTC_RAR_TCRR_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11444 #define RTC_RAR_TCRR_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11445 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
<> 144:ef7eb2e8f9f7 11446 #define RTC_RAR_CRR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11447 #define RTC_RAR_CRR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11448 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
<> 144:ef7eb2e8f9f7 11449 #define RTC_RAR_SRR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11450 #define RTC_RAR_SRR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11451 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
<> 144:ef7eb2e8f9f7 11452 #define RTC_RAR_LRR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11453 #define RTC_RAR_LRR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11454 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
<> 144:ef7eb2e8f9f7 11455 #define RTC_RAR_IERR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11456 #define RTC_RAR_IERR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11457 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
<> 144:ef7eb2e8f9f7 11458 #define RTC_RAR_TTSR_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11459 #define RTC_RAR_TTSR_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11460 #define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
<> 144:ef7eb2e8f9f7 11461 #define RTC_RAR_MERR_MASK (0x200U)
<> 144:ef7eb2e8f9f7 11462 #define RTC_RAR_MERR_SHIFT (9U)
<> 144:ef7eb2e8f9f7 11463 #define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
<> 144:ef7eb2e8f9f7 11464 #define RTC_RAR_MCLR_MASK (0x400U)
<> 144:ef7eb2e8f9f7 11465 #define RTC_RAR_MCLR_SHIFT (10U)
<> 144:ef7eb2e8f9f7 11466 #define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
<> 144:ef7eb2e8f9f7 11467 #define RTC_RAR_MCHR_MASK (0x800U)
<> 144:ef7eb2e8f9f7 11468 #define RTC_RAR_MCHR_SHIFT (11U)
<> 144:ef7eb2e8f9f7 11469 #define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
<> 144:ef7eb2e8f9f7 11470
<> 144:ef7eb2e8f9f7 11471
<> 144:ef7eb2e8f9f7 11472 /*!
<> 144:ef7eb2e8f9f7 11473 * @}
<> 144:ef7eb2e8f9f7 11474 */ /* end of group RTC_Register_Masks */
<> 144:ef7eb2e8f9f7 11475
<> 144:ef7eb2e8f9f7 11476
<> 144:ef7eb2e8f9f7 11477 /* RTC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 11478 /** Peripheral RTC base address */
<> 144:ef7eb2e8f9f7 11479 #define RTC_BASE (0x4003D000u)
<> 144:ef7eb2e8f9f7 11480 /** Peripheral RTC base pointer */
<> 144:ef7eb2e8f9f7 11481 #define RTC ((RTC_Type *)RTC_BASE)
<> 144:ef7eb2e8f9f7 11482 /** Array initializer of RTC peripheral base addresses */
<> 144:ef7eb2e8f9f7 11483 #define RTC_BASE_ADDRS { RTC_BASE }
<> 144:ef7eb2e8f9f7 11484 /** Array initializer of RTC peripheral base pointers */
<> 144:ef7eb2e8f9f7 11485 #define RTC_BASE_PTRS { RTC }
<> 144:ef7eb2e8f9f7 11486 /** Interrupt vectors for the RTC peripheral type */
<> 144:ef7eb2e8f9f7 11487 #define RTC_IRQS { RTC_IRQn }
<> 144:ef7eb2e8f9f7 11488 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
<> 144:ef7eb2e8f9f7 11489
<> 144:ef7eb2e8f9f7 11490 /*!
<> 144:ef7eb2e8f9f7 11491 * @}
<> 144:ef7eb2e8f9f7 11492 */ /* end of group RTC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 11493
<> 144:ef7eb2e8f9f7 11494
<> 144:ef7eb2e8f9f7 11495 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11496 -- SDHC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11497 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11498
<> 144:ef7eb2e8f9f7 11499 /*!
<> 144:ef7eb2e8f9f7 11500 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 11501 * @{
<> 144:ef7eb2e8f9f7 11502 */
<> 144:ef7eb2e8f9f7 11503
<> 144:ef7eb2e8f9f7 11504 /** SDHC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 11505 typedef struct {
<> 144:ef7eb2e8f9f7 11506 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 11507 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 11508 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 11509 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
<> 144:ef7eb2e8f9f7 11510 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
<> 144:ef7eb2e8f9f7 11511 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 11512 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 11513 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 11514 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 11515 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 11516 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
<> 144:ef7eb2e8f9f7 11517 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
<> 144:ef7eb2e8f9f7 11518 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
<> 144:ef7eb2e8f9f7 11519 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
<> 144:ef7eb2e8f9f7 11520 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
<> 144:ef7eb2e8f9f7 11521 uint8_t RESERVED_0[8];
<> 144:ef7eb2e8f9f7 11522 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
<> 144:ef7eb2e8f9f7 11523 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
<> 144:ef7eb2e8f9f7 11524 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
<> 144:ef7eb2e8f9f7 11525 uint8_t RESERVED_1[100];
<> 144:ef7eb2e8f9f7 11526 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
<> 144:ef7eb2e8f9f7 11527 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
<> 144:ef7eb2e8f9f7 11528 uint8_t RESERVED_2[52];
<> 144:ef7eb2e8f9f7 11529 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
<> 144:ef7eb2e8f9f7 11530 } SDHC_Type;
<> 144:ef7eb2e8f9f7 11531
<> 144:ef7eb2e8f9f7 11532 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11533 -- SDHC Register Masks
<> 144:ef7eb2e8f9f7 11534 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 11535
<> 144:ef7eb2e8f9f7 11536 /*!
<> 144:ef7eb2e8f9f7 11537 * @addtogroup SDHC_Register_Masks SDHC Register Masks
<> 144:ef7eb2e8f9f7 11538 * @{
<> 144:ef7eb2e8f9f7 11539 */
<> 144:ef7eb2e8f9f7 11540
<> 144:ef7eb2e8f9f7 11541 /*! @name DSADDR - DMA System Address register */
<> 144:ef7eb2e8f9f7 11542 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
<> 144:ef7eb2e8f9f7 11543 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11544 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
<> 144:ef7eb2e8f9f7 11545
<> 144:ef7eb2e8f9f7 11546 /*! @name BLKATTR - Block Attributes register */
<> 144:ef7eb2e8f9f7 11547 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
<> 144:ef7eb2e8f9f7 11548 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11549 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
<> 144:ef7eb2e8f9f7 11550 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 11551 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11552 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
<> 144:ef7eb2e8f9f7 11553
<> 144:ef7eb2e8f9f7 11554 /*! @name CMDARG - Command Argument register */
<> 144:ef7eb2e8f9f7 11555 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11556 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11557 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
<> 144:ef7eb2e8f9f7 11558
<> 144:ef7eb2e8f9f7 11559 /*! @name XFERTYP - Transfer Type register */
<> 144:ef7eb2e8f9f7 11560 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11561 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11562 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 11563 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11564 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11565 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
<> 144:ef7eb2e8f9f7 11566 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11567 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11568 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
<> 144:ef7eb2e8f9f7 11569 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11570 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11571 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
<> 144:ef7eb2e8f9f7 11572 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11573 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11574 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
<> 144:ef7eb2e8f9f7 11575 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 11576 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11577 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
<> 144:ef7eb2e8f9f7 11578 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 11579 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
<> 144:ef7eb2e8f9f7 11580 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
<> 144:ef7eb2e8f9f7 11581 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 11582 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
<> 144:ef7eb2e8f9f7 11583 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
<> 144:ef7eb2e8f9f7 11584 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 11585 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
<> 144:ef7eb2e8f9f7 11586 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
<> 144:ef7eb2e8f9f7 11587 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
<> 144:ef7eb2e8f9f7 11588 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
<> 144:ef7eb2e8f9f7 11589 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
<> 144:ef7eb2e8f9f7 11590 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
<> 144:ef7eb2e8f9f7 11591 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11592 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
<> 144:ef7eb2e8f9f7 11593
<> 144:ef7eb2e8f9f7 11594 /*! @name CMDRSP - Command Response 0..Command Response 3 */
<> 144:ef7eb2e8f9f7 11595 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11596 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11597 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
<> 144:ef7eb2e8f9f7 11598 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11599 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11600 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
<> 144:ef7eb2e8f9f7 11601 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11602 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11603 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
<> 144:ef7eb2e8f9f7 11604 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11605 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11606 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
<> 144:ef7eb2e8f9f7 11607
<> 144:ef7eb2e8f9f7 11608 /* The count of SDHC_CMDRSP */
<> 144:ef7eb2e8f9f7 11609 #define SDHC_CMDRSP_COUNT (4U)
<> 144:ef7eb2e8f9f7 11610
<> 144:ef7eb2e8f9f7 11611 /*! @name DATPORT - Buffer Data Port register */
<> 144:ef7eb2e8f9f7 11612 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 11613 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11614 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
<> 144:ef7eb2e8f9f7 11615
<> 144:ef7eb2e8f9f7 11616 /*! @name PRSSTAT - Present State register */
<> 144:ef7eb2e8f9f7 11617 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11618 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11619 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
<> 144:ef7eb2e8f9f7 11620 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11621 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11622 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
<> 144:ef7eb2e8f9f7 11623 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11624 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11625 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
<> 144:ef7eb2e8f9f7 11626 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11627 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11628 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
<> 144:ef7eb2e8f9f7 11629 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11630 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11631 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
<> 144:ef7eb2e8f9f7 11632 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11633 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11634 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
<> 144:ef7eb2e8f9f7 11635 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11636 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11637 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
<> 144:ef7eb2e8f9f7 11638 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11639 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11640 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
<> 144:ef7eb2e8f9f7 11641 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11642 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11643 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
<> 144:ef7eb2e8f9f7 11644 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
<> 144:ef7eb2e8f9f7 11645 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
<> 144:ef7eb2e8f9f7 11646 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
<> 144:ef7eb2e8f9f7 11647 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
<> 144:ef7eb2e8f9f7 11648 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
<> 144:ef7eb2e8f9f7 11649 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
<> 144:ef7eb2e8f9f7 11650 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
<> 144:ef7eb2e8f9f7 11651 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
<> 144:ef7eb2e8f9f7 11652 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
<> 144:ef7eb2e8f9f7 11653 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 11654 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11655 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
<> 144:ef7eb2e8f9f7 11656 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 11657 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
<> 144:ef7eb2e8f9f7 11658 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
<> 144:ef7eb2e8f9f7 11659 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 11660 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11661 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
<> 144:ef7eb2e8f9f7 11662
<> 144:ef7eb2e8f9f7 11663 /*! @name PROCTL - Protocol Control register */
<> 144:ef7eb2e8f9f7 11664 #define SDHC_PROCTL_LCTL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11665 #define SDHC_PROCTL_LCTL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11666 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
<> 144:ef7eb2e8f9f7 11667 #define SDHC_PROCTL_DTW_MASK (0x6U)
<> 144:ef7eb2e8f9f7 11668 #define SDHC_PROCTL_DTW_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11669 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
<> 144:ef7eb2e8f9f7 11670 #define SDHC_PROCTL_D3CD_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11671 #define SDHC_PROCTL_D3CD_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11672 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
<> 144:ef7eb2e8f9f7 11673 #define SDHC_PROCTL_EMODE_MASK (0x30U)
<> 144:ef7eb2e8f9f7 11674 #define SDHC_PROCTL_EMODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11675 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
<> 144:ef7eb2e8f9f7 11676 #define SDHC_PROCTL_CDTL_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11677 #define SDHC_PROCTL_CDTL_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11678 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
<> 144:ef7eb2e8f9f7 11679 #define SDHC_PROCTL_CDSS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11680 #define SDHC_PROCTL_CDSS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11681 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
<> 144:ef7eb2e8f9f7 11682 #define SDHC_PROCTL_DMAS_MASK (0x300U)
<> 144:ef7eb2e8f9f7 11683 #define SDHC_PROCTL_DMAS_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11684 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
<> 144:ef7eb2e8f9f7 11685 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 11686 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11687 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
<> 144:ef7eb2e8f9f7 11688 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 11689 #define SDHC_PROCTL_CREQ_SHIFT (17U)
<> 144:ef7eb2e8f9f7 11690 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
<> 144:ef7eb2e8f9f7 11691 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 11692 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
<> 144:ef7eb2e8f9f7 11693 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
<> 144:ef7eb2e8f9f7 11694 #define SDHC_PROCTL_IABG_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 11695 #define SDHC_PROCTL_IABG_SHIFT (19U)
<> 144:ef7eb2e8f9f7 11696 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
<> 144:ef7eb2e8f9f7 11697 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11698 #define SDHC_PROCTL_WECINT_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11699 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
<> 144:ef7eb2e8f9f7 11700 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 11701 #define SDHC_PROCTL_WECINS_SHIFT (25U)
<> 144:ef7eb2e8f9f7 11702 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
<> 144:ef7eb2e8f9f7 11703 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 11704 #define SDHC_PROCTL_WECRM_SHIFT (26U)
<> 144:ef7eb2e8f9f7 11705 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
<> 144:ef7eb2e8f9f7 11706
<> 144:ef7eb2e8f9f7 11707 /*! @name SYSCTL - System Control register */
<> 144:ef7eb2e8f9f7 11708 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11709 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11710 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
<> 144:ef7eb2e8f9f7 11711 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11712 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11713 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
<> 144:ef7eb2e8f9f7 11714 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11715 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11716 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
<> 144:ef7eb2e8f9f7 11717 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11718 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11719 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
<> 144:ef7eb2e8f9f7 11720 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 11721 #define SDHC_SYSCTL_DVS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11722 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
<> 144:ef7eb2e8f9f7 11723 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 11724 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11725 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
<> 144:ef7eb2e8f9f7 11726 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 11727 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11728 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
<> 144:ef7eb2e8f9f7 11729 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11730 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11731 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
<> 144:ef7eb2e8f9f7 11732 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 11733 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
<> 144:ef7eb2e8f9f7 11734 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
<> 144:ef7eb2e8f9f7 11735 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 11736 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
<> 144:ef7eb2e8f9f7 11737 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
<> 144:ef7eb2e8f9f7 11738 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 11739 #define SDHC_SYSCTL_INITA_SHIFT (27U)
<> 144:ef7eb2e8f9f7 11740 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
<> 144:ef7eb2e8f9f7 11741
<> 144:ef7eb2e8f9f7 11742 /*! @name IRQSTAT - Interrupt Status register */
<> 144:ef7eb2e8f9f7 11743 #define SDHC_IRQSTAT_CC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11744 #define SDHC_IRQSTAT_CC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11745 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
<> 144:ef7eb2e8f9f7 11746 #define SDHC_IRQSTAT_TC_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11747 #define SDHC_IRQSTAT_TC_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11748 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
<> 144:ef7eb2e8f9f7 11749 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11750 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11751 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
<> 144:ef7eb2e8f9f7 11752 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11753 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11754 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
<> 144:ef7eb2e8f9f7 11755 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11756 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11757 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
<> 144:ef7eb2e8f9f7 11758 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11759 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11760 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
<> 144:ef7eb2e8f9f7 11761 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11762 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11763 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
<> 144:ef7eb2e8f9f7 11764 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11765 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11766 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
<> 144:ef7eb2e8f9f7 11767 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11768 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11769 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
<> 144:ef7eb2e8f9f7 11770 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 11771 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11772 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
<> 144:ef7eb2e8f9f7 11773 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 11774 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 11775 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
<> 144:ef7eb2e8f9f7 11776 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 11777 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
<> 144:ef7eb2e8f9f7 11778 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
<> 144:ef7eb2e8f9f7 11779 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 11780 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 11781 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
<> 144:ef7eb2e8f9f7 11782 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 11783 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 11784 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
<> 144:ef7eb2e8f9f7 11785 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 11786 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 11787 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
<> 144:ef7eb2e8f9f7 11788 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 11789 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
<> 144:ef7eb2e8f9f7 11790 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
<> 144:ef7eb2e8f9f7 11791 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11792 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11793 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
<> 144:ef7eb2e8f9f7 11794 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 11795 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 11796 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
<> 144:ef7eb2e8f9f7 11797
<> 144:ef7eb2e8f9f7 11798 /*! @name IRQSTATEN - Interrupt Status Enable register */
<> 144:ef7eb2e8f9f7 11799 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11800 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11801 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
<> 144:ef7eb2e8f9f7 11802 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11803 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11804 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
<> 144:ef7eb2e8f9f7 11805 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11806 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11807 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
<> 144:ef7eb2e8f9f7 11808 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11809 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11810 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
<> 144:ef7eb2e8f9f7 11811 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11812 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11813 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
<> 144:ef7eb2e8f9f7 11814 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11815 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11816 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
<> 144:ef7eb2e8f9f7 11817 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11818 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11819 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
<> 144:ef7eb2e8f9f7 11820 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11821 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11822 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
<> 144:ef7eb2e8f9f7 11823 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11824 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11825 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
<> 144:ef7eb2e8f9f7 11826 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 11827 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11828 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
<> 144:ef7eb2e8f9f7 11829 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 11830 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
<> 144:ef7eb2e8f9f7 11831 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
<> 144:ef7eb2e8f9f7 11832 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 11833 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 11834 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
<> 144:ef7eb2e8f9f7 11835 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 11836 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
<> 144:ef7eb2e8f9f7 11837 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
<> 144:ef7eb2e8f9f7 11838 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 11839 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
<> 144:ef7eb2e8f9f7 11840 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
<> 144:ef7eb2e8f9f7 11841 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 11842 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
<> 144:ef7eb2e8f9f7 11843 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
<> 144:ef7eb2e8f9f7 11844 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 11845 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
<> 144:ef7eb2e8f9f7 11846 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
<> 144:ef7eb2e8f9f7 11847 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11848 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11849 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
<> 144:ef7eb2e8f9f7 11850 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 11851 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
<> 144:ef7eb2e8f9f7 11852 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
<> 144:ef7eb2e8f9f7 11853
<> 144:ef7eb2e8f9f7 11854 /*! @name IRQSIGEN - Interrupt Signal Enable register */
<> 144:ef7eb2e8f9f7 11855 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11856 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11857 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
<> 144:ef7eb2e8f9f7 11858 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11859 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11860 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
<> 144:ef7eb2e8f9f7 11861 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11862 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11863 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
<> 144:ef7eb2e8f9f7 11864 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11865 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11866 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
<> 144:ef7eb2e8f9f7 11867 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11868 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11869 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
<> 144:ef7eb2e8f9f7 11870 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 11871 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 11872 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
<> 144:ef7eb2e8f9f7 11873 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 11874 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 11875 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
<> 144:ef7eb2e8f9f7 11876 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11877 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11878 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
<> 144:ef7eb2e8f9f7 11879 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
<> 144:ef7eb2e8f9f7 11880 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 11881 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
<> 144:ef7eb2e8f9f7 11882 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 11883 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11884 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
<> 144:ef7eb2e8f9f7 11885 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 11886 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
<> 144:ef7eb2e8f9f7 11887 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
<> 144:ef7eb2e8f9f7 11888 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 11889 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 11890 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
<> 144:ef7eb2e8f9f7 11891 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 11892 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
<> 144:ef7eb2e8f9f7 11893 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
<> 144:ef7eb2e8f9f7 11894 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 11895 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
<> 144:ef7eb2e8f9f7 11896 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
<> 144:ef7eb2e8f9f7 11897 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 11898 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
<> 144:ef7eb2e8f9f7 11899 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
<> 144:ef7eb2e8f9f7 11900 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 11901 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
<> 144:ef7eb2e8f9f7 11902 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
<> 144:ef7eb2e8f9f7 11903 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11904 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11905 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
<> 144:ef7eb2e8f9f7 11906 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 11907 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
<> 144:ef7eb2e8f9f7 11908 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
<> 144:ef7eb2e8f9f7 11909
<> 144:ef7eb2e8f9f7 11910 /*! @name AC12ERR - Auto CMD12 Error Status Register */
<> 144:ef7eb2e8f9f7 11911 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11912 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11913 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
<> 144:ef7eb2e8f9f7 11914 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11915 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11916 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
<> 144:ef7eb2e8f9f7 11917 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11918 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11919 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
<> 144:ef7eb2e8f9f7 11920 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11921 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11922 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
<> 144:ef7eb2e8f9f7 11923 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11924 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11925 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
<> 144:ef7eb2e8f9f7 11926 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11927 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11928 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
<> 144:ef7eb2e8f9f7 11929
<> 144:ef7eb2e8f9f7 11930 /*! @name HTCAPBLT - Host Controller Capabilities */
<> 144:ef7eb2e8f9f7 11931 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
<> 144:ef7eb2e8f9f7 11932 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11933 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
<> 144:ef7eb2e8f9f7 11934 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 11935 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
<> 144:ef7eb2e8f9f7 11936 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
<> 144:ef7eb2e8f9f7 11937 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 11938 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
<> 144:ef7eb2e8f9f7 11939 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
<> 144:ef7eb2e8f9f7 11940 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 11941 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 11942 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
<> 144:ef7eb2e8f9f7 11943 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 11944 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
<> 144:ef7eb2e8f9f7 11945 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
<> 144:ef7eb2e8f9f7 11946 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11947 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
<> 144:ef7eb2e8f9f7 11948 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
<> 144:ef7eb2e8f9f7 11949
<> 144:ef7eb2e8f9f7 11950 /*! @name WML - Watermark Level Register */
<> 144:ef7eb2e8f9f7 11951 #define SDHC_WML_RDWML_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 11952 #define SDHC_WML_RDWML_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11953 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
<> 144:ef7eb2e8f9f7 11954 #define SDHC_WML_WRWML_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 11955 #define SDHC_WML_WRWML_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11956 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
<> 144:ef7eb2e8f9f7 11957
<> 144:ef7eb2e8f9f7 11958 /*! @name FEVT - Force Event register */
<> 144:ef7eb2e8f9f7 11959 #define SDHC_FEVT_AC12NE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 11960 #define SDHC_FEVT_AC12NE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 11961 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
<> 144:ef7eb2e8f9f7 11962 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 11963 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 11964 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
<> 144:ef7eb2e8f9f7 11965 #define SDHC_FEVT_AC12CE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 11966 #define SDHC_FEVT_AC12CE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 11967 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
<> 144:ef7eb2e8f9f7 11968 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 11969 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 11970 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
<> 144:ef7eb2e8f9f7 11971 #define SDHC_FEVT_AC12IE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 11972 #define SDHC_FEVT_AC12IE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 11973 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
<> 144:ef7eb2e8f9f7 11974 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
<> 144:ef7eb2e8f9f7 11975 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
<> 144:ef7eb2e8f9f7 11976 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
<> 144:ef7eb2e8f9f7 11977 #define SDHC_FEVT_CTOE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 11978 #define SDHC_FEVT_CTOE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 11979 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
<> 144:ef7eb2e8f9f7 11980 #define SDHC_FEVT_CCE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 11981 #define SDHC_FEVT_CCE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 11982 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
<> 144:ef7eb2e8f9f7 11983 #define SDHC_FEVT_CEBE_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 11984 #define SDHC_FEVT_CEBE_SHIFT (18U)
<> 144:ef7eb2e8f9f7 11985 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
<> 144:ef7eb2e8f9f7 11986 #define SDHC_FEVT_CIE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 11987 #define SDHC_FEVT_CIE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 11988 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
<> 144:ef7eb2e8f9f7 11989 #define SDHC_FEVT_DTOE_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 11990 #define SDHC_FEVT_DTOE_SHIFT (20U)
<> 144:ef7eb2e8f9f7 11991 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
<> 144:ef7eb2e8f9f7 11992 #define SDHC_FEVT_DCE_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 11993 #define SDHC_FEVT_DCE_SHIFT (21U)
<> 144:ef7eb2e8f9f7 11994 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
<> 144:ef7eb2e8f9f7 11995 #define SDHC_FEVT_DEBE_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 11996 #define SDHC_FEVT_DEBE_SHIFT (22U)
<> 144:ef7eb2e8f9f7 11997 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
<> 144:ef7eb2e8f9f7 11998 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 11999 #define SDHC_FEVT_AC12E_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12000 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
<> 144:ef7eb2e8f9f7 12001 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 12002 #define SDHC_FEVT_DMAE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12003 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
<> 144:ef7eb2e8f9f7 12004 #define SDHC_FEVT_CINT_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12005 #define SDHC_FEVT_CINT_SHIFT (31U)
<> 144:ef7eb2e8f9f7 12006 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
<> 144:ef7eb2e8f9f7 12007
<> 144:ef7eb2e8f9f7 12008 /*! @name ADMAES - ADMA Error Status register */
<> 144:ef7eb2e8f9f7 12009 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
<> 144:ef7eb2e8f9f7 12010 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12011 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
<> 144:ef7eb2e8f9f7 12012 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
<> 144:ef7eb2e8f9f7 12013 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12014 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
<> 144:ef7eb2e8f9f7 12015 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12016 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12017 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
<> 144:ef7eb2e8f9f7 12018
<> 144:ef7eb2e8f9f7 12019 /*! @name ADSADDR - ADMA System Addressregister */
<> 144:ef7eb2e8f9f7 12020 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
<> 144:ef7eb2e8f9f7 12021 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12022 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
<> 144:ef7eb2e8f9f7 12023
<> 144:ef7eb2e8f9f7 12024 /*! @name VENDOR - Vendor Specific register */
<> 144:ef7eb2e8f9f7 12025 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12026 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12027 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
<> 144:ef7eb2e8f9f7 12028 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 12029 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12030 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
<> 144:ef7eb2e8f9f7 12031
<> 144:ef7eb2e8f9f7 12032 /*! @name MMCBOOT - MMC Boot register */
<> 144:ef7eb2e8f9f7 12033 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
<> 144:ef7eb2e8f9f7 12034 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12035 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
<> 144:ef7eb2e8f9f7 12036 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12037 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12038 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
<> 144:ef7eb2e8f9f7 12039 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 12040 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 12041 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
<> 144:ef7eb2e8f9f7 12042 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 12043 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 12044 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
<> 144:ef7eb2e8f9f7 12045 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 12046 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 12047 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
<> 144:ef7eb2e8f9f7 12048 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 12049 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12050 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
<> 144:ef7eb2e8f9f7 12051
<> 144:ef7eb2e8f9f7 12052 /*! @name HOSTVER - Host Controller Version */
<> 144:ef7eb2e8f9f7 12053 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 12054 #define SDHC_HOSTVER_SVN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12055 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
<> 144:ef7eb2e8f9f7 12056 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 12057 #define SDHC_HOSTVER_VVN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12058 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
<> 144:ef7eb2e8f9f7 12059
<> 144:ef7eb2e8f9f7 12060
<> 144:ef7eb2e8f9f7 12061 /*!
<> 144:ef7eb2e8f9f7 12062 * @}
<> 144:ef7eb2e8f9f7 12063 */ /* end of group SDHC_Register_Masks */
<> 144:ef7eb2e8f9f7 12064
<> 144:ef7eb2e8f9f7 12065
<> 144:ef7eb2e8f9f7 12066 /* SDHC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 12067 /** Peripheral SDHC base address */
<> 144:ef7eb2e8f9f7 12068 #define SDHC_BASE (0x400B1000u)
<> 144:ef7eb2e8f9f7 12069 /** Peripheral SDHC base pointer */
<> 144:ef7eb2e8f9f7 12070 #define SDHC ((SDHC_Type *)SDHC_BASE)
<> 144:ef7eb2e8f9f7 12071 /** Array initializer of SDHC peripheral base addresses */
<> 144:ef7eb2e8f9f7 12072 #define SDHC_BASE_ADDRS { SDHC_BASE }
<> 144:ef7eb2e8f9f7 12073 /** Array initializer of SDHC peripheral base pointers */
<> 144:ef7eb2e8f9f7 12074 #define SDHC_BASE_PTRS { SDHC }
<> 144:ef7eb2e8f9f7 12075 /** Interrupt vectors for the SDHC peripheral type */
<> 144:ef7eb2e8f9f7 12076 #define SDHC_IRQS { SDHC_IRQn }
<> 144:ef7eb2e8f9f7 12077
<> 144:ef7eb2e8f9f7 12078 /*!
<> 144:ef7eb2e8f9f7 12079 * @}
<> 144:ef7eb2e8f9f7 12080 */ /* end of group SDHC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 12081
<> 144:ef7eb2e8f9f7 12082
<> 144:ef7eb2e8f9f7 12083 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12084 -- SDRAM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12085 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12086
<> 144:ef7eb2e8f9f7 12087 /*!
<> 144:ef7eb2e8f9f7 12088 * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12089 * @{
<> 144:ef7eb2e8f9f7 12090 */
<> 144:ef7eb2e8f9f7 12091
<> 144:ef7eb2e8f9f7 12092 /** SDRAM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 12093 typedef struct {
<> 144:ef7eb2e8f9f7 12094 uint8_t RESERVED_0[66];
<> 144:ef7eb2e8f9f7 12095 __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */
<> 144:ef7eb2e8f9f7 12096 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 12097 struct { /* offset: 0x48, array step: 0x8 */
<> 144:ef7eb2e8f9f7 12098 __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
<> 144:ef7eb2e8f9f7 12099 __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */
<> 144:ef7eb2e8f9f7 12100 } BLOCK[2];
<> 144:ef7eb2e8f9f7 12101 } SDRAM_Type;
<> 144:ef7eb2e8f9f7 12102
<> 144:ef7eb2e8f9f7 12103 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12104 -- SDRAM Register Masks
<> 144:ef7eb2e8f9f7 12105 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12106
<> 144:ef7eb2e8f9f7 12107 /*!
<> 144:ef7eb2e8f9f7 12108 * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
<> 144:ef7eb2e8f9f7 12109 * @{
<> 144:ef7eb2e8f9f7 12110 */
<> 144:ef7eb2e8f9f7 12111
<> 144:ef7eb2e8f9f7 12112 /*! @name CTRL - Control Register */
<> 144:ef7eb2e8f9f7 12113 #define SDRAM_CTRL_RC_MASK (0x1FFU)
<> 144:ef7eb2e8f9f7 12114 #define SDRAM_CTRL_RC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12115 #define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
<> 144:ef7eb2e8f9f7 12116 #define SDRAM_CTRL_RTIM_MASK (0x600U)
<> 144:ef7eb2e8f9f7 12117 #define SDRAM_CTRL_RTIM_SHIFT (9U)
<> 144:ef7eb2e8f9f7 12118 #define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
<> 144:ef7eb2e8f9f7 12119 #define SDRAM_CTRL_IS_MASK (0x800U)
<> 144:ef7eb2e8f9f7 12120 #define SDRAM_CTRL_IS_SHIFT (11U)
<> 144:ef7eb2e8f9f7 12121 #define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
<> 144:ef7eb2e8f9f7 12122
<> 144:ef7eb2e8f9f7 12123 /*! @name AC - Address and Control Register */
<> 144:ef7eb2e8f9f7 12124 #define SDRAM_AC_IP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12125 #define SDRAM_AC_IP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12126 #define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
<> 144:ef7eb2e8f9f7 12127 #define SDRAM_AC_PS_MASK (0x30U)
<> 144:ef7eb2e8f9f7 12128 #define SDRAM_AC_PS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12129 #define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
<> 144:ef7eb2e8f9f7 12130 #define SDRAM_AC_IMRS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 12131 #define SDRAM_AC_IMRS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 12132 #define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
<> 144:ef7eb2e8f9f7 12133 #define SDRAM_AC_CBM_MASK (0x700U)
<> 144:ef7eb2e8f9f7 12134 #define SDRAM_AC_CBM_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12135 #define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
<> 144:ef7eb2e8f9f7 12136 #define SDRAM_AC_CASL_MASK (0x3000U)
<> 144:ef7eb2e8f9f7 12137 #define SDRAM_AC_CASL_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12138 #define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
<> 144:ef7eb2e8f9f7 12139 #define SDRAM_AC_RE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 12140 #define SDRAM_AC_RE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 12141 #define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
<> 144:ef7eb2e8f9f7 12142 #define SDRAM_AC_BA_MASK (0xFFFC0000U)
<> 144:ef7eb2e8f9f7 12143 #define SDRAM_AC_BA_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12144 #define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
<> 144:ef7eb2e8f9f7 12145
<> 144:ef7eb2e8f9f7 12146 /* The count of SDRAM_AC */
<> 144:ef7eb2e8f9f7 12147 #define SDRAM_AC_COUNT (2U)
<> 144:ef7eb2e8f9f7 12148
<> 144:ef7eb2e8f9f7 12149 /*! @name CM - Control Mask */
<> 144:ef7eb2e8f9f7 12150 #define SDRAM_CM_V_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12151 #define SDRAM_CM_V_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12152 #define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
<> 144:ef7eb2e8f9f7 12153 #define SDRAM_CM_WP_MASK (0x100U)
<> 144:ef7eb2e8f9f7 12154 #define SDRAM_CM_WP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12155 #define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
<> 144:ef7eb2e8f9f7 12156 #define SDRAM_CM_BAM_MASK (0xFFFC0000U)
<> 144:ef7eb2e8f9f7 12157 #define SDRAM_CM_BAM_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12158 #define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
<> 144:ef7eb2e8f9f7 12159
<> 144:ef7eb2e8f9f7 12160 /* The count of SDRAM_CM */
<> 144:ef7eb2e8f9f7 12161 #define SDRAM_CM_COUNT (2U)
<> 144:ef7eb2e8f9f7 12162
<> 144:ef7eb2e8f9f7 12163
<> 144:ef7eb2e8f9f7 12164 /*!
<> 144:ef7eb2e8f9f7 12165 * @}
<> 144:ef7eb2e8f9f7 12166 */ /* end of group SDRAM_Register_Masks */
<> 144:ef7eb2e8f9f7 12167
<> 144:ef7eb2e8f9f7 12168
<> 144:ef7eb2e8f9f7 12169 /* SDRAM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 12170 /** Peripheral SDRAM base address */
<> 144:ef7eb2e8f9f7 12171 #define SDRAM_BASE (0x4000F000u)
<> 144:ef7eb2e8f9f7 12172 /** Peripheral SDRAM base pointer */
<> 144:ef7eb2e8f9f7 12173 #define SDRAM ((SDRAM_Type *)SDRAM_BASE)
<> 144:ef7eb2e8f9f7 12174 /** Array initializer of SDRAM peripheral base addresses */
<> 144:ef7eb2e8f9f7 12175 #define SDRAM_BASE_ADDRS { SDRAM_BASE }
<> 144:ef7eb2e8f9f7 12176 /** Array initializer of SDRAM peripheral base pointers */
<> 144:ef7eb2e8f9f7 12177 #define SDRAM_BASE_PTRS { SDRAM }
<> 144:ef7eb2e8f9f7 12178
<> 144:ef7eb2e8f9f7 12179 /*!
<> 144:ef7eb2e8f9f7 12180 * @}
<> 144:ef7eb2e8f9f7 12181 */ /* end of group SDRAM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 12182
<> 144:ef7eb2e8f9f7 12183
<> 144:ef7eb2e8f9f7 12184 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12185 -- SIM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12186 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12187
<> 144:ef7eb2e8f9f7 12188 /*!
<> 144:ef7eb2e8f9f7 12189 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12190 * @{
<> 144:ef7eb2e8f9f7 12191 */
<> 144:ef7eb2e8f9f7 12192
<> 144:ef7eb2e8f9f7 12193 /** SIM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 12194 typedef struct {
<> 144:ef7eb2e8f9f7 12195 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
<> 144:ef7eb2e8f9f7 12196 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 12197 __IO uint32_t USBPHYCTL; /**< USB PHY Control Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 12198 uint8_t RESERVED_0[4088];
<> 144:ef7eb2e8f9f7 12199 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
<> 144:ef7eb2e8f9f7 12200 uint8_t RESERVED_1[4];
<> 144:ef7eb2e8f9f7 12201 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
<> 144:ef7eb2e8f9f7 12202 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
<> 144:ef7eb2e8f9f7 12203 uint8_t RESERVED_2[4];
<> 144:ef7eb2e8f9f7 12204 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
<> 144:ef7eb2e8f9f7 12205 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
<> 144:ef7eb2e8f9f7 12206 __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
<> 144:ef7eb2e8f9f7 12207 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
<> 144:ef7eb2e8f9f7 12208 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
<> 144:ef7eb2e8f9f7 12209 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
<> 144:ef7eb2e8f9f7 12210 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
<> 144:ef7eb2e8f9f7 12211 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
<> 144:ef7eb2e8f9f7 12212 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
<> 144:ef7eb2e8f9f7 12213 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
<> 144:ef7eb2e8f9f7 12214 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
<> 144:ef7eb2e8f9f7 12215 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
<> 144:ef7eb2e8f9f7 12216 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
<> 144:ef7eb2e8f9f7 12217 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
<> 144:ef7eb2e8f9f7 12218 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
<> 144:ef7eb2e8f9f7 12219 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
<> 144:ef7eb2e8f9f7 12220 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
<> 144:ef7eb2e8f9f7 12221 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
<> 144:ef7eb2e8f9f7 12222 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
<> 144:ef7eb2e8f9f7 12223 __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
<> 144:ef7eb2e8f9f7 12224 __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */
<> 144:ef7eb2e8f9f7 12225 } SIM_Type;
<> 144:ef7eb2e8f9f7 12226
<> 144:ef7eb2e8f9f7 12227 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12228 -- SIM Register Masks
<> 144:ef7eb2e8f9f7 12229 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12230
<> 144:ef7eb2e8f9f7 12231 /*!
<> 144:ef7eb2e8f9f7 12232 * @addtogroup SIM_Register_Masks SIM Register Masks
<> 144:ef7eb2e8f9f7 12233 * @{
<> 144:ef7eb2e8f9f7 12234 */
<> 144:ef7eb2e8f9f7 12235
<> 144:ef7eb2e8f9f7 12236 /*! @name SOPT1 - System Options Register 1 */
<> 144:ef7eb2e8f9f7 12237 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 12238 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12239 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
<> 144:ef7eb2e8f9f7 12240 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 12241 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12242 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
<> 144:ef7eb2e8f9f7 12243 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 12244 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
<> 144:ef7eb2e8f9f7 12245 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
<> 144:ef7eb2e8f9f7 12246 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 12247 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
<> 144:ef7eb2e8f9f7 12248 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
<> 144:ef7eb2e8f9f7 12249 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12250 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 12251 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
<> 144:ef7eb2e8f9f7 12252
<> 144:ef7eb2e8f9f7 12253 /*! @name SOPT1CFG - SOPT1 Configuration Register */
<> 144:ef7eb2e8f9f7 12254 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 12255 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12256 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
<> 144:ef7eb2e8f9f7 12257 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12258 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12259 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
<> 144:ef7eb2e8f9f7 12260 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 12261 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12262 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
<> 144:ef7eb2e8f9f7 12263
<> 144:ef7eb2e8f9f7 12264 /*! @name USBPHYCTL - USB PHY Control Register */
<> 144:ef7eb2e8f9f7 12265 #define SIM_USBPHYCTL_USBVREGSEL_MASK (0x100U)
<> 144:ef7eb2e8f9f7 12266 #define SIM_USBPHYCTL_USBVREGSEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12267 #define SIM_USBPHYCTL_USBVREGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
<> 144:ef7eb2e8f9f7 12268 #define SIM_USBPHYCTL_USBVREGPD_MASK (0x200U)
<> 144:ef7eb2e8f9f7 12269 #define SIM_USBPHYCTL_USBVREGPD_SHIFT (9U)
<> 144:ef7eb2e8f9f7 12270 #define SIM_USBPHYCTL_USBVREGPD(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
<> 144:ef7eb2e8f9f7 12271 #define SIM_USBPHYCTL_USB3VOUTTRG_MASK (0x700000U)
<> 144:ef7eb2e8f9f7 12272 #define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12273 #define SIM_USBPHYCTL_USB3VOUTTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
<> 144:ef7eb2e8f9f7 12274 #define SIM_USBPHYCTL_USBDISILIM_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 12275 #define SIM_USBPHYCTL_USBDISILIM_SHIFT (23U)
<> 144:ef7eb2e8f9f7 12276 #define SIM_USBPHYCTL_USBDISILIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
<> 144:ef7eb2e8f9f7 12277
<> 144:ef7eb2e8f9f7 12278 /*! @name SOPT2 - System Options Register 2 */
<> 144:ef7eb2e8f9f7 12279 #define SIM_SOPT2_USBSLSRC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12280 #define SIM_SOPT2_USBSLSRC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12281 #define SIM_SOPT2_USBSLSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
<> 144:ef7eb2e8f9f7 12282 #define SIM_SOPT2_USBREGEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12283 #define SIM_SOPT2_USBREGEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12284 #define SIM_SOPT2_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
<> 144:ef7eb2e8f9f7 12285 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12286 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12287 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
<> 144:ef7eb2e8f9f7 12288 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
<> 144:ef7eb2e8f9f7 12289 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
<> 144:ef7eb2e8f9f7 12290 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
<> 144:ef7eb2e8f9f7 12291 #define SIM_SOPT2_FBSL_MASK (0x300U)
<> 144:ef7eb2e8f9f7 12292 #define SIM_SOPT2_FBSL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12293 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
<> 144:ef7eb2e8f9f7 12294 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12295 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12296 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12297 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 12298 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12299 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
<> 144:ef7eb2e8f9f7 12300 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 12301 #define SIM_SOPT2_USBSRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12302 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
<> 144:ef7eb2e8f9f7 12303 #define SIM_SOPT2_RMIISRC_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 12304 #define SIM_SOPT2_RMIISRC_SHIFT (19U)
<> 144:ef7eb2e8f9f7 12305 #define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
<> 144:ef7eb2e8f9f7 12306 #define SIM_SOPT2_TIMESRC_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 12307 #define SIM_SOPT2_TIMESRC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12308 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
<> 144:ef7eb2e8f9f7 12309 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
<> 144:ef7eb2e8f9f7 12310 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12311 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
<> 144:ef7eb2e8f9f7 12312 #define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 12313 #define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12314 #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
<> 144:ef7eb2e8f9f7 12315 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 12316 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12317 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
<> 144:ef7eb2e8f9f7 12318
<> 144:ef7eb2e8f9f7 12319 /*! @name SOPT4 - System Options Register 4 */
<> 144:ef7eb2e8f9f7 12320 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12321 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12322 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
<> 144:ef7eb2e8f9f7 12323 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12324 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12325 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
<> 144:ef7eb2e8f9f7 12326 #define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
<> 144:ef7eb2e8f9f7 12327 #define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12328 #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
<> 144:ef7eb2e8f9f7 12329 #define SIM_SOPT4_FTM0FLT3_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12330 #define SIM_SOPT4_FTM0FLT3_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12331 #define SIM_SOPT4_FTM0FLT3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
<> 144:ef7eb2e8f9f7 12332 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12333 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12334 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
<> 144:ef7eb2e8f9f7 12335 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
<> 144:ef7eb2e8f9f7 12336 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12337 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
<> 144:ef7eb2e8f9f7 12338 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12339 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12340 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
<> 144:ef7eb2e8f9f7 12341 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 12342 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12343 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
<> 144:ef7eb2e8f9f7 12344 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 12345 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12346 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
<> 144:ef7eb2e8f9f7 12347 #define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 12348 #define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 12349 #define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
<> 144:ef7eb2e8f9f7 12350 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 12351 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12352 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12353 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12354 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12355 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12356 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 12357 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12358 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12359 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 12360 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
<> 144:ef7eb2e8f9f7 12361 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12362 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 12363 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12364 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
<> 144:ef7eb2e8f9f7 12365 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 12366 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
<> 144:ef7eb2e8f9f7 12367 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
<> 144:ef7eb2e8f9f7 12368 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 12369 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 12370 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
<> 144:ef7eb2e8f9f7 12371 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12372 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
<> 144:ef7eb2e8f9f7 12373 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
<> 144:ef7eb2e8f9f7 12374
<> 144:ef7eb2e8f9f7 12375 /*! @name SOPT5 - System Options Register 5 */
<> 144:ef7eb2e8f9f7 12376 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
<> 144:ef7eb2e8f9f7 12377 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12378 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
<> 144:ef7eb2e8f9f7 12379 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
<> 144:ef7eb2e8f9f7 12380 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12381 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
<> 144:ef7eb2e8f9f7 12382 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
<> 144:ef7eb2e8f9f7 12383 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12384 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
<> 144:ef7eb2e8f9f7 12385 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 12386 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 12387 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
<> 144:ef7eb2e8f9f7 12388 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 12389 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12390 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
<> 144:ef7eb2e8f9f7 12391 #define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 12392 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12393 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
<> 144:ef7eb2e8f9f7 12394
<> 144:ef7eb2e8f9f7 12395 /*! @name SOPT7 - System Options Register 7 */
<> 144:ef7eb2e8f9f7 12396 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 12397 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12398 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 12399 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12400 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12401 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
<> 144:ef7eb2e8f9f7 12402 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 12403 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 12404 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
<> 144:ef7eb2e8f9f7 12405 #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 12406 #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12407 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 12408 #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12409 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12410 #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
<> 144:ef7eb2e8f9f7 12411 #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 12412 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 12413 #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
<> 144:ef7eb2e8f9f7 12414
<> 144:ef7eb2e8f9f7 12415 /*! @name SOPT8 - System Options Register 8 */
<> 144:ef7eb2e8f9f7 12416 #define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12417 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12418 #define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
<> 144:ef7eb2e8f9f7 12419 #define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12420 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12421 #define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
<> 144:ef7eb2e8f9f7 12422 #define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 12423 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12424 #define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
<> 144:ef7eb2e8f9f7 12425 #define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12426 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12427 #define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
<> 144:ef7eb2e8f9f7 12428 #define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 12429 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12430 #define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
<> 144:ef7eb2e8f9f7 12431 #define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 12432 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
<> 144:ef7eb2e8f9f7 12433 #define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
<> 144:ef7eb2e8f9f7 12434 #define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 12435 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12436 #define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
<> 144:ef7eb2e8f9f7 12437 #define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 12438 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
<> 144:ef7eb2e8f9f7 12439 #define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
<> 144:ef7eb2e8f9f7 12440 #define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 12441 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12442 #define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
<> 144:ef7eb2e8f9f7 12443 #define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 12444 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
<> 144:ef7eb2e8f9f7 12445 #define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
<> 144:ef7eb2e8f9f7 12446 #define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 12447 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 12448 #define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
<> 144:ef7eb2e8f9f7 12449 #define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 12450 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
<> 144:ef7eb2e8f9f7 12451 #define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
<> 144:ef7eb2e8f9f7 12452 #define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 12453 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12454 #define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
<> 144:ef7eb2e8f9f7 12455 #define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12456 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12457 #define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
<> 144:ef7eb2e8f9f7 12458 #define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 12459 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12460 #define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
<> 144:ef7eb2e8f9f7 12461 #define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 12462 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
<> 144:ef7eb2e8f9f7 12463 #define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
<> 144:ef7eb2e8f9f7 12464 #define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 12465 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12466 #define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
<> 144:ef7eb2e8f9f7 12467 #define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 12468 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
<> 144:ef7eb2e8f9f7 12469 #define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
<> 144:ef7eb2e8f9f7 12470 #define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 12471 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
<> 144:ef7eb2e8f9f7 12472 #define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
<> 144:ef7eb2e8f9f7 12473 #define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12474 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
<> 144:ef7eb2e8f9f7 12475 #define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
<> 144:ef7eb2e8f9f7 12476
<> 144:ef7eb2e8f9f7 12477 /*! @name SOPT9 - System Options Register 9 */
<> 144:ef7eb2e8f9f7 12478 #define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 12479 #define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12480 #define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
<> 144:ef7eb2e8f9f7 12481 #define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 12482 #define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12483 #define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
<> 144:ef7eb2e8f9f7 12484 #define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12485 #define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12486 #define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12487 #define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 12488 #define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12489 #define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
<> 144:ef7eb2e8f9f7 12490
<> 144:ef7eb2e8f9f7 12491 /*! @name SDID - System Device Identification Register */
<> 144:ef7eb2e8f9f7 12492 #define SIM_SDID_PINID_MASK (0xFU)
<> 144:ef7eb2e8f9f7 12493 #define SIM_SDID_PINID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12494 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
<> 144:ef7eb2e8f9f7 12495 #define SIM_SDID_FAMID_MASK (0x70U)
<> 144:ef7eb2e8f9f7 12496 #define SIM_SDID_FAMID_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12497 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
<> 144:ef7eb2e8f9f7 12498 #define SIM_SDID_DIEID_MASK (0xF80U)
<> 144:ef7eb2e8f9f7 12499 #define SIM_SDID_DIEID_SHIFT (7U)
<> 144:ef7eb2e8f9f7 12500 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
<> 144:ef7eb2e8f9f7 12501 #define SIM_SDID_REVID_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 12502 #define SIM_SDID_REVID_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12503 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
<> 144:ef7eb2e8f9f7 12504 #define SIM_SDID_SERIESID_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 12505 #define SIM_SDID_SERIESID_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12506 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
<> 144:ef7eb2e8f9f7 12507 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 12508 #define SIM_SDID_SUBFAMID_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12509 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
<> 144:ef7eb2e8f9f7 12510 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 12511 #define SIM_SDID_FAMILYID_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12512 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
<> 144:ef7eb2e8f9f7 12513
<> 144:ef7eb2e8f9f7 12514 /*! @name SCGC1 - System Clock Gating Control Register 1 */
<> 144:ef7eb2e8f9f7 12515 #define SIM_SCGC1_I2C2_MASK (0x40U)
<> 144:ef7eb2e8f9f7 12516 #define SIM_SCGC1_I2C2_SHIFT (6U)
<> 144:ef7eb2e8f9f7 12517 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
<> 144:ef7eb2e8f9f7 12518 #define SIM_SCGC1_I2C3_MASK (0x80U)
<> 144:ef7eb2e8f9f7 12519 #define SIM_SCGC1_I2C3_SHIFT (7U)
<> 144:ef7eb2e8f9f7 12520 #define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
<> 144:ef7eb2e8f9f7 12521 #define SIM_SCGC1_UART4_MASK (0x400U)
<> 144:ef7eb2e8f9f7 12522 #define SIM_SCGC1_UART4_SHIFT (10U)
<> 144:ef7eb2e8f9f7 12523 #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
<> 144:ef7eb2e8f9f7 12524
<> 144:ef7eb2e8f9f7 12525 /*! @name SCGC2 - System Clock Gating Control Register 2 */
<> 144:ef7eb2e8f9f7 12526 #define SIM_SCGC2_ENET_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12527 #define SIM_SCGC2_ENET_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12528 #define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
<> 144:ef7eb2e8f9f7 12529 #define SIM_SCGC2_LPUART0_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12530 #define SIM_SCGC2_LPUART0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12531 #define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
<> 144:ef7eb2e8f9f7 12532 #define SIM_SCGC2_TPM1_MASK (0x200U)
<> 144:ef7eb2e8f9f7 12533 #define SIM_SCGC2_TPM1_SHIFT (9U)
<> 144:ef7eb2e8f9f7 12534 #define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
<> 144:ef7eb2e8f9f7 12535 #define SIM_SCGC2_TPM2_MASK (0x400U)
<> 144:ef7eb2e8f9f7 12536 #define SIM_SCGC2_TPM2_SHIFT (10U)
<> 144:ef7eb2e8f9f7 12537 #define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
<> 144:ef7eb2e8f9f7 12538 #define SIM_SCGC2_DAC0_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12539 #define SIM_SCGC2_DAC0_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12540 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
<> 144:ef7eb2e8f9f7 12541 #define SIM_SCGC2_DAC1_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 12542 #define SIM_SCGC2_DAC1_SHIFT (13U)
<> 144:ef7eb2e8f9f7 12543 #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
<> 144:ef7eb2e8f9f7 12544
<> 144:ef7eb2e8f9f7 12545 /*! @name SCGC3 - System Clock Gating Control Register 3 */
<> 144:ef7eb2e8f9f7 12546 #define SIM_SCGC3_RNGA_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12547 #define SIM_SCGC3_RNGA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12548 #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
<> 144:ef7eb2e8f9f7 12549 #define SIM_SCGC3_USBHS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12550 #define SIM_SCGC3_USBHS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12551 #define SIM_SCGC3_USBHS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
<> 144:ef7eb2e8f9f7 12552 #define SIM_SCGC3_USBHSPHY_MASK (0x4U)
<> 144:ef7eb2e8f9f7 12553 #define SIM_SCGC3_USBHSPHY_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12554 #define SIM_SCGC3_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
<> 144:ef7eb2e8f9f7 12555 #define SIM_SCGC3_USBHSDCD_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12556 #define SIM_SCGC3_USBHSDCD_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12557 #define SIM_SCGC3_USBHSDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
<> 144:ef7eb2e8f9f7 12558 #define SIM_SCGC3_FLEXCAN1_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12559 #define SIM_SCGC3_FLEXCAN1_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12560 #define SIM_SCGC3_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
<> 144:ef7eb2e8f9f7 12561 #define SIM_SCGC3_SPI2_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12562 #define SIM_SCGC3_SPI2_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12563 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
<> 144:ef7eb2e8f9f7 12564 #define SIM_SCGC3_SDHC_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 12565 #define SIM_SCGC3_SDHC_SHIFT (17U)
<> 144:ef7eb2e8f9f7 12566 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
<> 144:ef7eb2e8f9f7 12567 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 12568 #define SIM_SCGC3_FTM2_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12569 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
<> 144:ef7eb2e8f9f7 12570 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12571 #define SIM_SCGC3_FTM3_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12572 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
<> 144:ef7eb2e8f9f7 12573 #define SIM_SCGC3_ADC1_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 12574 #define SIM_SCGC3_ADC1_SHIFT (27U)
<> 144:ef7eb2e8f9f7 12575 #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
<> 144:ef7eb2e8f9f7 12576
<> 144:ef7eb2e8f9f7 12577 /*! @name SCGC4 - System Clock Gating Control Register 4 */
<> 144:ef7eb2e8f9f7 12578 #define SIM_SCGC4_EWM_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12579 #define SIM_SCGC4_EWM_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12580 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
<> 144:ef7eb2e8f9f7 12581 #define SIM_SCGC4_CMT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 12582 #define SIM_SCGC4_CMT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12583 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
<> 144:ef7eb2e8f9f7 12584 #define SIM_SCGC4_I2C0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 12585 #define SIM_SCGC4_I2C0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 12586 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
<> 144:ef7eb2e8f9f7 12587 #define SIM_SCGC4_I2C1_MASK (0x80U)
<> 144:ef7eb2e8f9f7 12588 #define SIM_SCGC4_I2C1_SHIFT (7U)
<> 144:ef7eb2e8f9f7 12589 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
<> 144:ef7eb2e8f9f7 12590 #define SIM_SCGC4_UART0_MASK (0x400U)
<> 144:ef7eb2e8f9f7 12591 #define SIM_SCGC4_UART0_SHIFT (10U)
<> 144:ef7eb2e8f9f7 12592 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
<> 144:ef7eb2e8f9f7 12593 #define SIM_SCGC4_UART1_MASK (0x800U)
<> 144:ef7eb2e8f9f7 12594 #define SIM_SCGC4_UART1_SHIFT (11U)
<> 144:ef7eb2e8f9f7 12595 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
<> 144:ef7eb2e8f9f7 12596 #define SIM_SCGC4_UART2_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12597 #define SIM_SCGC4_UART2_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12598 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
<> 144:ef7eb2e8f9f7 12599 #define SIM_SCGC4_UART3_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 12600 #define SIM_SCGC4_UART3_SHIFT (13U)
<> 144:ef7eb2e8f9f7 12601 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
<> 144:ef7eb2e8f9f7 12602 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 12603 #define SIM_SCGC4_USBOTG_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12604 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
<> 144:ef7eb2e8f9f7 12605 #define SIM_SCGC4_CMP_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 12606 #define SIM_SCGC4_CMP_SHIFT (19U)
<> 144:ef7eb2e8f9f7 12607 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
<> 144:ef7eb2e8f9f7 12608 #define SIM_SCGC4_VREF_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 12609 #define SIM_SCGC4_VREF_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12610 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
<> 144:ef7eb2e8f9f7 12611
<> 144:ef7eb2e8f9f7 12612 /*! @name SCGC5 - System Clock Gating Control Register 5 */
<> 144:ef7eb2e8f9f7 12613 #define SIM_SCGC5_LPTMR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12614 #define SIM_SCGC5_LPTMR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12615 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
<> 144:ef7eb2e8f9f7 12616 #define SIM_SCGC5_TSI_MASK (0x20U)
<> 144:ef7eb2e8f9f7 12617 #define SIM_SCGC5_TSI_SHIFT (5U)
<> 144:ef7eb2e8f9f7 12618 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
<> 144:ef7eb2e8f9f7 12619 #define SIM_SCGC5_PORTA_MASK (0x200U)
<> 144:ef7eb2e8f9f7 12620 #define SIM_SCGC5_PORTA_SHIFT (9U)
<> 144:ef7eb2e8f9f7 12621 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
<> 144:ef7eb2e8f9f7 12622 #define SIM_SCGC5_PORTB_MASK (0x400U)
<> 144:ef7eb2e8f9f7 12623 #define SIM_SCGC5_PORTB_SHIFT (10U)
<> 144:ef7eb2e8f9f7 12624 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
<> 144:ef7eb2e8f9f7 12625 #define SIM_SCGC5_PORTC_MASK (0x800U)
<> 144:ef7eb2e8f9f7 12626 #define SIM_SCGC5_PORTC_SHIFT (11U)
<> 144:ef7eb2e8f9f7 12627 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
<> 144:ef7eb2e8f9f7 12628 #define SIM_SCGC5_PORTD_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12629 #define SIM_SCGC5_PORTD_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12630 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
<> 144:ef7eb2e8f9f7 12631 #define SIM_SCGC5_PORTE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 12632 #define SIM_SCGC5_PORTE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 12633 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
<> 144:ef7eb2e8f9f7 12634
<> 144:ef7eb2e8f9f7 12635 /*! @name SCGC6 - System Clock Gating Control Register 6 */
<> 144:ef7eb2e8f9f7 12636 #define SIM_SCGC6_FTF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12637 #define SIM_SCGC6_FTF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12638 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
<> 144:ef7eb2e8f9f7 12639 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12640 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12641 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
<> 144:ef7eb2e8f9f7 12642 #define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12643 #define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12644 #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
<> 144:ef7eb2e8f9f7 12645 #define SIM_SCGC6_RNGA_MASK (0x200U)
<> 144:ef7eb2e8f9f7 12646 #define SIM_SCGC6_RNGA_SHIFT (9U)
<> 144:ef7eb2e8f9f7 12647 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
<> 144:ef7eb2e8f9f7 12648 #define SIM_SCGC6_SPI0_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12649 #define SIM_SCGC6_SPI0_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12650 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
<> 144:ef7eb2e8f9f7 12651 #define SIM_SCGC6_SPI1_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 12652 #define SIM_SCGC6_SPI1_SHIFT (13U)
<> 144:ef7eb2e8f9f7 12653 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
<> 144:ef7eb2e8f9f7 12654 #define SIM_SCGC6_I2S_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 12655 #define SIM_SCGC6_I2S_SHIFT (15U)
<> 144:ef7eb2e8f9f7 12656 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
<> 144:ef7eb2e8f9f7 12657 #define SIM_SCGC6_CRC_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 12658 #define SIM_SCGC6_CRC_SHIFT (18U)
<> 144:ef7eb2e8f9f7 12659 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
<> 144:ef7eb2e8f9f7 12660 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 12661 #define SIM_SCGC6_USBDCD_SHIFT (21U)
<> 144:ef7eb2e8f9f7 12662 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
<> 144:ef7eb2e8f9f7 12663 #define SIM_SCGC6_PDB_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 12664 #define SIM_SCGC6_PDB_SHIFT (22U)
<> 144:ef7eb2e8f9f7 12665 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
<> 144:ef7eb2e8f9f7 12666 #define SIM_SCGC6_PIT_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 12667 #define SIM_SCGC6_PIT_SHIFT (23U)
<> 144:ef7eb2e8f9f7 12668 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
<> 144:ef7eb2e8f9f7 12669 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 12670 #define SIM_SCGC6_FTM0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12671 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
<> 144:ef7eb2e8f9f7 12672 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12673 #define SIM_SCGC6_FTM1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12674 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
<> 144:ef7eb2e8f9f7 12675 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 12676 #define SIM_SCGC6_FTM2_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12677 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
<> 144:ef7eb2e8f9f7 12678 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 12679 #define SIM_SCGC6_ADC0_SHIFT (27U)
<> 144:ef7eb2e8f9f7 12680 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
<> 144:ef7eb2e8f9f7 12681 #define SIM_SCGC6_RTC_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 12682 #define SIM_SCGC6_RTC_SHIFT (29U)
<> 144:ef7eb2e8f9f7 12683 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
<> 144:ef7eb2e8f9f7 12684 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12685 #define SIM_SCGC6_DAC0_SHIFT (31U)
<> 144:ef7eb2e8f9f7 12686 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
<> 144:ef7eb2e8f9f7 12687
<> 144:ef7eb2e8f9f7 12688 /*! @name SCGC7 - System Clock Gating Control Register 7 */
<> 144:ef7eb2e8f9f7 12689 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12690 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12691 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
<> 144:ef7eb2e8f9f7 12692 #define SIM_SCGC7_DMA_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12693 #define SIM_SCGC7_DMA_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12694 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
<> 144:ef7eb2e8f9f7 12695 #define SIM_SCGC7_MPU_MASK (0x4U)
<> 144:ef7eb2e8f9f7 12696 #define SIM_SCGC7_MPU_SHIFT (2U)
<> 144:ef7eb2e8f9f7 12697 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
<> 144:ef7eb2e8f9f7 12698 #define SIM_SCGC7_SDRAMC_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12699 #define SIM_SCGC7_SDRAMC_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12700 #define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
<> 144:ef7eb2e8f9f7 12701
<> 144:ef7eb2e8f9f7 12702 /*! @name CLKDIV1 - System Clock Divider Register 1 */
<> 144:ef7eb2e8f9f7 12703 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 12704 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12705 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
<> 144:ef7eb2e8f9f7 12706 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 12707 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
<> 144:ef7eb2e8f9f7 12708 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
<> 144:ef7eb2e8f9f7 12709 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 12710 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12711 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
<> 144:ef7eb2e8f9f7 12712 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 12713 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12714 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
<> 144:ef7eb2e8f9f7 12715
<> 144:ef7eb2e8f9f7 12716 /*! @name CLKDIV2 - System Clock Divider Register 2 */
<> 144:ef7eb2e8f9f7 12717 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12718 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12719 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
<> 144:ef7eb2e8f9f7 12720 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
<> 144:ef7eb2e8f9f7 12721 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12722 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
<> 144:ef7eb2e8f9f7 12723
<> 144:ef7eb2e8f9f7 12724 /*! @name FCFG1 - Flash Configuration Register 1 */
<> 144:ef7eb2e8f9f7 12725 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12726 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12727 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
<> 144:ef7eb2e8f9f7 12728 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12729 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12730 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
<> 144:ef7eb2e8f9f7 12731 #define SIM_FCFG1_DEPART_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 12732 #define SIM_FCFG1_DEPART_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12733 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
<> 144:ef7eb2e8f9f7 12734 #define SIM_FCFG1_EESIZE_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 12735 #define SIM_FCFG1_EESIZE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12736 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
<> 144:ef7eb2e8f9f7 12737 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 12738 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12739 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
<> 144:ef7eb2e8f9f7 12740 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 12741 #define SIM_FCFG1_NVMSIZE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12742 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
<> 144:ef7eb2e8f9f7 12743
<> 144:ef7eb2e8f9f7 12744 /*! @name FCFG2 - Flash Configuration Register 2 */
<> 144:ef7eb2e8f9f7 12745 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
<> 144:ef7eb2e8f9f7 12746 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12747 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
<> 144:ef7eb2e8f9f7 12748 #define SIM_FCFG2_PFLSH_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 12749 #define SIM_FCFG2_PFLSH_SHIFT (23U)
<> 144:ef7eb2e8f9f7 12750 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
<> 144:ef7eb2e8f9f7 12751 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
<> 144:ef7eb2e8f9f7 12752 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12753 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
<> 144:ef7eb2e8f9f7 12754 #define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12755 #define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
<> 144:ef7eb2e8f9f7 12756 #define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
<> 144:ef7eb2e8f9f7 12757
<> 144:ef7eb2e8f9f7 12758 /*! @name UIDH - Unique Identification Register High */
<> 144:ef7eb2e8f9f7 12759 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 12760 #define SIM_UIDH_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12761 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
<> 144:ef7eb2e8f9f7 12762
<> 144:ef7eb2e8f9f7 12763 /*! @name UIDMH - Unique Identification Register Mid-High */
<> 144:ef7eb2e8f9f7 12764 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 12765 #define SIM_UIDMH_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12766 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
<> 144:ef7eb2e8f9f7 12767
<> 144:ef7eb2e8f9f7 12768 /*! @name UIDML - Unique Identification Register Mid Low */
<> 144:ef7eb2e8f9f7 12769 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 12770 #define SIM_UIDML_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12771 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
<> 144:ef7eb2e8f9f7 12772
<> 144:ef7eb2e8f9f7 12773 /*! @name UIDL - Unique Identification Register Low */
<> 144:ef7eb2e8f9f7 12774 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 12775 #define SIM_UIDL_UID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12776 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
<> 144:ef7eb2e8f9f7 12777
<> 144:ef7eb2e8f9f7 12778 /*! @name CLKDIV3 - System Clock Divider Register 3 */
<> 144:ef7eb2e8f9f7 12779 #define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12780 #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12781 #define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
<> 144:ef7eb2e8f9f7 12782 #define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
<> 144:ef7eb2e8f9f7 12783 #define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12784 #define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
<> 144:ef7eb2e8f9f7 12785
<> 144:ef7eb2e8f9f7 12786 /*! @name CLKDIV4 - System Clock Divider Register 4 */
<> 144:ef7eb2e8f9f7 12787 #define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12788 #define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12789 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
<> 144:ef7eb2e8f9f7 12790 #define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
<> 144:ef7eb2e8f9f7 12791 #define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12792 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
<> 144:ef7eb2e8f9f7 12793
<> 144:ef7eb2e8f9f7 12794
<> 144:ef7eb2e8f9f7 12795 /*!
<> 144:ef7eb2e8f9f7 12796 * @}
<> 144:ef7eb2e8f9f7 12797 */ /* end of group SIM_Register_Masks */
<> 144:ef7eb2e8f9f7 12798
<> 144:ef7eb2e8f9f7 12799
<> 144:ef7eb2e8f9f7 12800 /* SIM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 12801 /** Peripheral SIM base address */
<> 144:ef7eb2e8f9f7 12802 #define SIM_BASE (0x40047000u)
<> 144:ef7eb2e8f9f7 12803 /** Peripheral SIM base pointer */
<> 144:ef7eb2e8f9f7 12804 #define SIM ((SIM_Type *)SIM_BASE)
<> 144:ef7eb2e8f9f7 12805 /** Array initializer of SIM peripheral base addresses */
<> 144:ef7eb2e8f9f7 12806 #define SIM_BASE_ADDRS { SIM_BASE }
<> 144:ef7eb2e8f9f7 12807 /** Array initializer of SIM peripheral base pointers */
<> 144:ef7eb2e8f9f7 12808 #define SIM_BASE_PTRS { SIM }
<> 144:ef7eb2e8f9f7 12809
<> 144:ef7eb2e8f9f7 12810 /*!
<> 144:ef7eb2e8f9f7 12811 * @}
<> 144:ef7eb2e8f9f7 12812 */ /* end of group SIM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 12813
<> 144:ef7eb2e8f9f7 12814
<> 144:ef7eb2e8f9f7 12815 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12816 -- SMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12817 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12818
<> 144:ef7eb2e8f9f7 12819 /*!
<> 144:ef7eb2e8f9f7 12820 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12821 * @{
<> 144:ef7eb2e8f9f7 12822 */
<> 144:ef7eb2e8f9f7 12823
<> 144:ef7eb2e8f9f7 12824 /** SMC - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 12825 typedef struct {
<> 144:ef7eb2e8f9f7 12826 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 12827 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 12828 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
<> 144:ef7eb2e8f9f7 12829 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
<> 144:ef7eb2e8f9f7 12830 } SMC_Type;
<> 144:ef7eb2e8f9f7 12831
<> 144:ef7eb2e8f9f7 12832 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12833 -- SMC Register Masks
<> 144:ef7eb2e8f9f7 12834 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12835
<> 144:ef7eb2e8f9f7 12836 /*!
<> 144:ef7eb2e8f9f7 12837 * @addtogroup SMC_Register_Masks SMC Register Masks
<> 144:ef7eb2e8f9f7 12838 * @{
<> 144:ef7eb2e8f9f7 12839 */
<> 144:ef7eb2e8f9f7 12840
<> 144:ef7eb2e8f9f7 12841 /*! @name PMPROT - Power Mode Protection register */
<> 144:ef7eb2e8f9f7 12842 #define SMC_PMPROT_AVLLS_MASK (0x2U)
<> 144:ef7eb2e8f9f7 12843 #define SMC_PMPROT_AVLLS_SHIFT (1U)
<> 144:ef7eb2e8f9f7 12844 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
<> 144:ef7eb2e8f9f7 12845 #define SMC_PMPROT_ALLS_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12846 #define SMC_PMPROT_ALLS_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12847 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
<> 144:ef7eb2e8f9f7 12848 #define SMC_PMPROT_AVLP_MASK (0x20U)
<> 144:ef7eb2e8f9f7 12849 #define SMC_PMPROT_AVLP_SHIFT (5U)
<> 144:ef7eb2e8f9f7 12850 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
<> 144:ef7eb2e8f9f7 12851 #define SMC_PMPROT_AHSRUN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 12852 #define SMC_PMPROT_AHSRUN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 12853 #define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
<> 144:ef7eb2e8f9f7 12854
<> 144:ef7eb2e8f9f7 12855 /*! @name PMCTRL - Power Mode Control register */
<> 144:ef7eb2e8f9f7 12856 #define SMC_PMCTRL_STOPM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 12857 #define SMC_PMCTRL_STOPM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12858 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
<> 144:ef7eb2e8f9f7 12859 #define SMC_PMCTRL_STOPA_MASK (0x8U)
<> 144:ef7eb2e8f9f7 12860 #define SMC_PMCTRL_STOPA_SHIFT (3U)
<> 144:ef7eb2e8f9f7 12861 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
<> 144:ef7eb2e8f9f7 12862 #define SMC_PMCTRL_RUNM_MASK (0x60U)
<> 144:ef7eb2e8f9f7 12863 #define SMC_PMCTRL_RUNM_SHIFT (5U)
<> 144:ef7eb2e8f9f7 12864 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
<> 144:ef7eb2e8f9f7 12865
<> 144:ef7eb2e8f9f7 12866 /*! @name STOPCTRL - Stop Control Register */
<> 144:ef7eb2e8f9f7 12867 #define SMC_STOPCTRL_LLSM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 12868 #define SMC_STOPCTRL_LLSM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12869 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
<> 144:ef7eb2e8f9f7 12870 #define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
<> 144:ef7eb2e8f9f7 12871 #define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
<> 144:ef7eb2e8f9f7 12872 #define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
<> 144:ef7eb2e8f9f7 12873 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
<> 144:ef7eb2e8f9f7 12874 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
<> 144:ef7eb2e8f9f7 12875 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
<> 144:ef7eb2e8f9f7 12876 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 12877 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
<> 144:ef7eb2e8f9f7 12878 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
<> 144:ef7eb2e8f9f7 12879
<> 144:ef7eb2e8f9f7 12880 /*! @name PMSTAT - Power Mode Status register */
<> 144:ef7eb2e8f9f7 12881 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 12882 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12883 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
<> 144:ef7eb2e8f9f7 12884
<> 144:ef7eb2e8f9f7 12885
<> 144:ef7eb2e8f9f7 12886 /*!
<> 144:ef7eb2e8f9f7 12887 * @}
<> 144:ef7eb2e8f9f7 12888 */ /* end of group SMC_Register_Masks */
<> 144:ef7eb2e8f9f7 12889
<> 144:ef7eb2e8f9f7 12890
<> 144:ef7eb2e8f9f7 12891 /* SMC - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 12892 /** Peripheral SMC base address */
<> 144:ef7eb2e8f9f7 12893 #define SMC_BASE (0x4007E000u)
<> 144:ef7eb2e8f9f7 12894 /** Peripheral SMC base pointer */
<> 144:ef7eb2e8f9f7 12895 #define SMC ((SMC_Type *)SMC_BASE)
<> 144:ef7eb2e8f9f7 12896 /** Array initializer of SMC peripheral base addresses */
<> 144:ef7eb2e8f9f7 12897 #define SMC_BASE_ADDRS { SMC_BASE }
<> 144:ef7eb2e8f9f7 12898 /** Array initializer of SMC peripheral base pointers */
<> 144:ef7eb2e8f9f7 12899 #define SMC_BASE_PTRS { SMC }
<> 144:ef7eb2e8f9f7 12900
<> 144:ef7eb2e8f9f7 12901 /*!
<> 144:ef7eb2e8f9f7 12902 * @}
<> 144:ef7eb2e8f9f7 12903 */ /* end of group SMC_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 12904
<> 144:ef7eb2e8f9f7 12905
<> 144:ef7eb2e8f9f7 12906 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12907 -- SPI Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12908 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12909
<> 144:ef7eb2e8f9f7 12910 /*!
<> 144:ef7eb2e8f9f7 12911 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
<> 144:ef7eb2e8f9f7 12912 * @{
<> 144:ef7eb2e8f9f7 12913 */
<> 144:ef7eb2e8f9f7 12914
<> 144:ef7eb2e8f9f7 12915 /** SPI - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 12916 typedef struct {
<> 144:ef7eb2e8f9f7 12917 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 12918 uint8_t RESERVED_0[4];
<> 144:ef7eb2e8f9f7 12919 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 12920 union { /* offset: 0xC */
<> 144:ef7eb2e8f9f7 12921 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
<> 144:ef7eb2e8f9f7 12922 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
<> 144:ef7eb2e8f9f7 12923 };
<> 144:ef7eb2e8f9f7 12924 uint8_t RESERVED_1[24];
<> 144:ef7eb2e8f9f7 12925 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 12926 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 12927 union { /* offset: 0x34 */
<> 144:ef7eb2e8f9f7 12928 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
<> 144:ef7eb2e8f9f7 12929 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
<> 144:ef7eb2e8f9f7 12930 };
<> 144:ef7eb2e8f9f7 12931 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
<> 144:ef7eb2e8f9f7 12932 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
<> 144:ef7eb2e8f9f7 12933 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
<> 144:ef7eb2e8f9f7 12934 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
<> 144:ef7eb2e8f9f7 12935 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
<> 144:ef7eb2e8f9f7 12936 uint8_t RESERVED_2[48];
<> 144:ef7eb2e8f9f7 12937 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
<> 144:ef7eb2e8f9f7 12938 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
<> 144:ef7eb2e8f9f7 12939 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
<> 144:ef7eb2e8f9f7 12940 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
<> 144:ef7eb2e8f9f7 12941 } SPI_Type;
<> 144:ef7eb2e8f9f7 12942
<> 144:ef7eb2e8f9f7 12943 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12944 -- SPI Register Masks
<> 144:ef7eb2e8f9f7 12945 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 12946
<> 144:ef7eb2e8f9f7 12947 /*!
<> 144:ef7eb2e8f9f7 12948 * @addtogroup SPI_Register_Masks SPI Register Masks
<> 144:ef7eb2e8f9f7 12949 * @{
<> 144:ef7eb2e8f9f7 12950 */
<> 144:ef7eb2e8f9f7 12951
<> 144:ef7eb2e8f9f7 12952 /*! @name MCR - Module Configuration Register */
<> 144:ef7eb2e8f9f7 12953 #define SPI_MCR_HALT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 12954 #define SPI_MCR_HALT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 12955 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
<> 144:ef7eb2e8f9f7 12956 #define SPI_MCR_SMPL_PT_MASK (0x300U)
<> 144:ef7eb2e8f9f7 12957 #define SPI_MCR_SMPL_PT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 12958 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
<> 144:ef7eb2e8f9f7 12959 #define SPI_MCR_CLR_RXF_MASK (0x400U)
<> 144:ef7eb2e8f9f7 12960 #define SPI_MCR_CLR_RXF_SHIFT (10U)
<> 144:ef7eb2e8f9f7 12961 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
<> 144:ef7eb2e8f9f7 12962 #define SPI_MCR_CLR_TXF_MASK (0x800U)
<> 144:ef7eb2e8f9f7 12963 #define SPI_MCR_CLR_TXF_SHIFT (11U)
<> 144:ef7eb2e8f9f7 12964 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
<> 144:ef7eb2e8f9f7 12965 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 12966 #define SPI_MCR_DIS_RXF_SHIFT (12U)
<> 144:ef7eb2e8f9f7 12967 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
<> 144:ef7eb2e8f9f7 12968 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 12969 #define SPI_MCR_DIS_TXF_SHIFT (13U)
<> 144:ef7eb2e8f9f7 12970 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
<> 144:ef7eb2e8f9f7 12971 #define SPI_MCR_MDIS_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 12972 #define SPI_MCR_MDIS_SHIFT (14U)
<> 144:ef7eb2e8f9f7 12973 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
<> 144:ef7eb2e8f9f7 12974 #define SPI_MCR_DOZE_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 12975 #define SPI_MCR_DOZE_SHIFT (15U)
<> 144:ef7eb2e8f9f7 12976 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
<> 144:ef7eb2e8f9f7 12977 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
<> 144:ef7eb2e8f9f7 12978 #define SPI_MCR_PCSIS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 12979 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
<> 144:ef7eb2e8f9f7 12980 #define SPI_MCR_ROOE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 12981 #define SPI_MCR_ROOE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 12982 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
<> 144:ef7eb2e8f9f7 12983 #define SPI_MCR_PCSSE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 12984 #define SPI_MCR_PCSSE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 12985 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
<> 144:ef7eb2e8f9f7 12986 #define SPI_MCR_MTFE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 12987 #define SPI_MCR_MTFE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 12988 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
<> 144:ef7eb2e8f9f7 12989 #define SPI_MCR_FRZ_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 12990 #define SPI_MCR_FRZ_SHIFT (27U)
<> 144:ef7eb2e8f9f7 12991 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
<> 144:ef7eb2e8f9f7 12992 #define SPI_MCR_DCONF_MASK (0x30000000U)
<> 144:ef7eb2e8f9f7 12993 #define SPI_MCR_DCONF_SHIFT (28U)
<> 144:ef7eb2e8f9f7 12994 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
<> 144:ef7eb2e8f9f7 12995 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 12996 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 12997 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
<> 144:ef7eb2e8f9f7 12998 #define SPI_MCR_MSTR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 12999 #define SPI_MCR_MSTR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 13000 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
<> 144:ef7eb2e8f9f7 13001
<> 144:ef7eb2e8f9f7 13002 /*! @name TCR - Transfer Count Register */
<> 144:ef7eb2e8f9f7 13003 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 13004 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13005 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
<> 144:ef7eb2e8f9f7 13006
<> 144:ef7eb2e8f9f7 13007 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
<> 144:ef7eb2e8f9f7 13008 #define SPI_CTAR_BR_MASK (0xFU)
<> 144:ef7eb2e8f9f7 13009 #define SPI_CTAR_BR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13010 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
<> 144:ef7eb2e8f9f7 13011 #define SPI_CTAR_DT_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 13012 #define SPI_CTAR_DT_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13013 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
<> 144:ef7eb2e8f9f7 13014 #define SPI_CTAR_ASC_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 13015 #define SPI_CTAR_ASC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 13016 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
<> 144:ef7eb2e8f9f7 13017 #define SPI_CTAR_CSSCK_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 13018 #define SPI_CTAR_CSSCK_SHIFT (12U)
<> 144:ef7eb2e8f9f7 13019 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
<> 144:ef7eb2e8f9f7 13020 #define SPI_CTAR_PBR_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 13021 #define SPI_CTAR_PBR_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13022 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
<> 144:ef7eb2e8f9f7 13023 #define SPI_CTAR_PDT_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 13024 #define SPI_CTAR_PDT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 13025 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
<> 144:ef7eb2e8f9f7 13026 #define SPI_CTAR_PASC_MASK (0x300000U)
<> 144:ef7eb2e8f9f7 13027 #define SPI_CTAR_PASC_SHIFT (20U)
<> 144:ef7eb2e8f9f7 13028 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
<> 144:ef7eb2e8f9f7 13029 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
<> 144:ef7eb2e8f9f7 13030 #define SPI_CTAR_PCSSCK_SHIFT (22U)
<> 144:ef7eb2e8f9f7 13031 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
<> 144:ef7eb2e8f9f7 13032 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 13033 #define SPI_CTAR_LSBFE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 13034 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
<> 144:ef7eb2e8f9f7 13035 #define SPI_CTAR_CPHA_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 13036 #define SPI_CTAR_CPHA_SHIFT (25U)
<> 144:ef7eb2e8f9f7 13037 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
<> 144:ef7eb2e8f9f7 13038 #define SPI_CTAR_CPOL_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 13039 #define SPI_CTAR_CPOL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 13040 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
<> 144:ef7eb2e8f9f7 13041 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
<> 144:ef7eb2e8f9f7 13042 #define SPI_CTAR_FMSZ_SHIFT (27U)
<> 144:ef7eb2e8f9f7 13043 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
<> 144:ef7eb2e8f9f7 13044 #define SPI_CTAR_DBR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 13045 #define SPI_CTAR_DBR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 13046 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
<> 144:ef7eb2e8f9f7 13047
<> 144:ef7eb2e8f9f7 13048 /* The count of SPI_CTAR */
<> 144:ef7eb2e8f9f7 13049 #define SPI_CTAR_COUNT (2U)
<> 144:ef7eb2e8f9f7 13050
<> 144:ef7eb2e8f9f7 13051 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
<> 144:ef7eb2e8f9f7 13052 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 13053 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
<> 144:ef7eb2e8f9f7 13054 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
<> 144:ef7eb2e8f9f7 13055 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 13056 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 13057 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
<> 144:ef7eb2e8f9f7 13058 #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
<> 144:ef7eb2e8f9f7 13059 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
<> 144:ef7eb2e8f9f7 13060 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
<> 144:ef7eb2e8f9f7 13061
<> 144:ef7eb2e8f9f7 13062 /* The count of SPI_CTAR_SLAVE */
<> 144:ef7eb2e8f9f7 13063 #define SPI_CTAR_SLAVE_COUNT (1U)
<> 144:ef7eb2e8f9f7 13064
<> 144:ef7eb2e8f9f7 13065 /*! @name SR - Status Register */
<> 144:ef7eb2e8f9f7 13066 #define SPI_SR_POPNXTPTR_MASK (0xFU)
<> 144:ef7eb2e8f9f7 13067 #define SPI_SR_POPNXTPTR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13068 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
<> 144:ef7eb2e8f9f7 13069 #define SPI_SR_RXCTR_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 13070 #define SPI_SR_RXCTR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13071 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
<> 144:ef7eb2e8f9f7 13072 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 13073 #define SPI_SR_TXNXTPTR_SHIFT (8U)
<> 144:ef7eb2e8f9f7 13074 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
<> 144:ef7eb2e8f9f7 13075 #define SPI_SR_TXCTR_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 13076 #define SPI_SR_TXCTR_SHIFT (12U)
<> 144:ef7eb2e8f9f7 13077 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
<> 144:ef7eb2e8f9f7 13078 #define SPI_SR_RFDF_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 13079 #define SPI_SR_RFDF_SHIFT (17U)
<> 144:ef7eb2e8f9f7 13080 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
<> 144:ef7eb2e8f9f7 13081 #define SPI_SR_RFOF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 13082 #define SPI_SR_RFOF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 13083 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
<> 144:ef7eb2e8f9f7 13084 #define SPI_SR_TFFF_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 13085 #define SPI_SR_TFFF_SHIFT (25U)
<> 144:ef7eb2e8f9f7 13086 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
<> 144:ef7eb2e8f9f7 13087 #define SPI_SR_TFUF_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 13088 #define SPI_SR_TFUF_SHIFT (27U)
<> 144:ef7eb2e8f9f7 13089 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
<> 144:ef7eb2e8f9f7 13090 #define SPI_SR_EOQF_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 13091 #define SPI_SR_EOQF_SHIFT (28U)
<> 144:ef7eb2e8f9f7 13092 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
<> 144:ef7eb2e8f9f7 13093 #define SPI_SR_TXRXS_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 13094 #define SPI_SR_TXRXS_SHIFT (30U)
<> 144:ef7eb2e8f9f7 13095 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
<> 144:ef7eb2e8f9f7 13096 #define SPI_SR_TCF_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 13097 #define SPI_SR_TCF_SHIFT (31U)
<> 144:ef7eb2e8f9f7 13098 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
<> 144:ef7eb2e8f9f7 13099
<> 144:ef7eb2e8f9f7 13100 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
<> 144:ef7eb2e8f9f7 13101 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 13102 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13103 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
<> 144:ef7eb2e8f9f7 13104 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 13105 #define SPI_RSER_RFDF_RE_SHIFT (17U)
<> 144:ef7eb2e8f9f7 13106 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
<> 144:ef7eb2e8f9f7 13107 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 13108 #define SPI_RSER_RFOF_RE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 13109 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
<> 144:ef7eb2e8f9f7 13110 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 13111 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
<> 144:ef7eb2e8f9f7 13112 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
<> 144:ef7eb2e8f9f7 13113 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 13114 #define SPI_RSER_TFFF_RE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 13115 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
<> 144:ef7eb2e8f9f7 13116 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 13117 #define SPI_RSER_TFUF_RE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 13118 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
<> 144:ef7eb2e8f9f7 13119 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 13120 #define SPI_RSER_EOQF_RE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 13121 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
<> 144:ef7eb2e8f9f7 13122 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 13123 #define SPI_RSER_TCF_RE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 13124 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
<> 144:ef7eb2e8f9f7 13125
<> 144:ef7eb2e8f9f7 13126 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
<> 144:ef7eb2e8f9f7 13127 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13128 #define SPI_PUSHR_TXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13129 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13130 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
<> 144:ef7eb2e8f9f7 13131 #define SPI_PUSHR_PCS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13132 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
<> 144:ef7eb2e8f9f7 13133 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 13134 #define SPI_PUSHR_CTCNT_SHIFT (26U)
<> 144:ef7eb2e8f9f7 13135 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
<> 144:ef7eb2e8f9f7 13136 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 13137 #define SPI_PUSHR_EOQ_SHIFT (27U)
<> 144:ef7eb2e8f9f7 13138 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
<> 144:ef7eb2e8f9f7 13139 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
<> 144:ef7eb2e8f9f7 13140 #define SPI_PUSHR_CTAS_SHIFT (28U)
<> 144:ef7eb2e8f9f7 13141 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
<> 144:ef7eb2e8f9f7 13142 #define SPI_PUSHR_CONT_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 13143 #define SPI_PUSHR_CONT_SHIFT (31U)
<> 144:ef7eb2e8f9f7 13144 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
<> 144:ef7eb2e8f9f7 13145
<> 144:ef7eb2e8f9f7 13146 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
<> 144:ef7eb2e8f9f7 13147 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 13148 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13149 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13150
<> 144:ef7eb2e8f9f7 13151 /*! @name POPR - POP RX FIFO Register */
<> 144:ef7eb2e8f9f7 13152 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 13153 #define SPI_POPR_RXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13154 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
<> 144:ef7eb2e8f9f7 13155
<> 144:ef7eb2e8f9f7 13156 /*! @name TXFR0 - Transmit FIFO Registers */
<> 144:ef7eb2e8f9f7 13157 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13158 #define SPI_TXFR0_TXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13159 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13160 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 13161 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13162 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13163
<> 144:ef7eb2e8f9f7 13164 /*! @name TXFR1 - Transmit FIFO Registers */
<> 144:ef7eb2e8f9f7 13165 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13166 #define SPI_TXFR1_TXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13167 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13168 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 13169 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13170 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13171
<> 144:ef7eb2e8f9f7 13172 /*! @name TXFR2 - Transmit FIFO Registers */
<> 144:ef7eb2e8f9f7 13173 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13174 #define SPI_TXFR2_TXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13175 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13176 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 13177 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13178 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13179
<> 144:ef7eb2e8f9f7 13180 /*! @name TXFR3 - Transmit FIFO Registers */
<> 144:ef7eb2e8f9f7 13181 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13182 #define SPI_TXFR3_TXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13183 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13184 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 13185 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13186 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
<> 144:ef7eb2e8f9f7 13187
<> 144:ef7eb2e8f9f7 13188 /*! @name RXFR0 - Receive FIFO Registers */
<> 144:ef7eb2e8f9f7 13189 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 13190 #define SPI_RXFR0_RXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13191 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
<> 144:ef7eb2e8f9f7 13192
<> 144:ef7eb2e8f9f7 13193 /*! @name RXFR1 - Receive FIFO Registers */
<> 144:ef7eb2e8f9f7 13194 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 13195 #define SPI_RXFR1_RXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13196 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
<> 144:ef7eb2e8f9f7 13197
<> 144:ef7eb2e8f9f7 13198 /*! @name RXFR2 - Receive FIFO Registers */
<> 144:ef7eb2e8f9f7 13199 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 13200 #define SPI_RXFR2_RXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13201 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
<> 144:ef7eb2e8f9f7 13202
<> 144:ef7eb2e8f9f7 13203 /*! @name RXFR3 - Receive FIFO Registers */
<> 144:ef7eb2e8f9f7 13204 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 13205 #define SPI_RXFR3_RXDATA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13206 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
<> 144:ef7eb2e8f9f7 13207
<> 144:ef7eb2e8f9f7 13208
<> 144:ef7eb2e8f9f7 13209 /*!
<> 144:ef7eb2e8f9f7 13210 * @}
<> 144:ef7eb2e8f9f7 13211 */ /* end of group SPI_Register_Masks */
<> 144:ef7eb2e8f9f7 13212
<> 144:ef7eb2e8f9f7 13213
<> 144:ef7eb2e8f9f7 13214 /* SPI - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 13215 /** Peripheral SPI0 base address */
<> 144:ef7eb2e8f9f7 13216 #define SPI0_BASE (0x4002C000u)
<> 144:ef7eb2e8f9f7 13217 /** Peripheral SPI0 base pointer */
<> 144:ef7eb2e8f9f7 13218 #define SPI0 ((SPI_Type *)SPI0_BASE)
<> 144:ef7eb2e8f9f7 13219 /** Peripheral SPI1 base address */
<> 144:ef7eb2e8f9f7 13220 #define SPI1_BASE (0x4002D000u)
<> 144:ef7eb2e8f9f7 13221 /** Peripheral SPI1 base pointer */
<> 144:ef7eb2e8f9f7 13222 #define SPI1 ((SPI_Type *)SPI1_BASE)
<> 144:ef7eb2e8f9f7 13223 /** Peripheral SPI2 base address */
<> 144:ef7eb2e8f9f7 13224 #define SPI2_BASE (0x400AC000u)
<> 144:ef7eb2e8f9f7 13225 /** Peripheral SPI2 base pointer */
<> 144:ef7eb2e8f9f7 13226 #define SPI2 ((SPI_Type *)SPI2_BASE)
<> 144:ef7eb2e8f9f7 13227 /** Array initializer of SPI peripheral base addresses */
<> 144:ef7eb2e8f9f7 13228 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
<> 144:ef7eb2e8f9f7 13229 /** Array initializer of SPI peripheral base pointers */
<> 144:ef7eb2e8f9f7 13230 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
<> 144:ef7eb2e8f9f7 13231 /** Interrupt vectors for the SPI peripheral type */
<> 144:ef7eb2e8f9f7 13232 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
<> 144:ef7eb2e8f9f7 13233
<> 144:ef7eb2e8f9f7 13234 /*!
<> 144:ef7eb2e8f9f7 13235 * @}
<> 144:ef7eb2e8f9f7 13236 */ /* end of group SPI_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 13237
<> 144:ef7eb2e8f9f7 13238
<> 144:ef7eb2e8f9f7 13239 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13240 -- TPM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 13241 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 13242
<> 144:ef7eb2e8f9f7 13243 /*!
<> 144:ef7eb2e8f9f7 13244 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
<> 144:ef7eb2e8f9f7 13245 * @{
<> 144:ef7eb2e8f9f7 13246 */
<> 144:ef7eb2e8f9f7 13247
<> 144:ef7eb2e8f9f7 13248 /** TPM - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 13249 typedef struct {
<> 144:ef7eb2e8f9f7 13250 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
<> 144:ef7eb2e8f9f7 13251 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
<> 144:ef7eb2e8f9f7 13252 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
<> 144:ef7eb2e8f9f7 13253 struct { /* offset: 0xC, array step: 0x8 */
<> 144:ef7eb2e8f9f7 13254 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
<> 144:ef7eb2e8f9f7 13255 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
<> 144:ef7eb2e8f9f7 13256 } CONTROLS[2];
<> 144:ef7eb2e8f9f7 13257 uint8_t RESERVED_0[52];
<> 144:ef7eb2e8f9f7 13258 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
<> 144:ef7eb2e8f9f7 13259 uint8_t RESERVED_1[16];
<> 144:ef7eb2e8f9f7 13260 __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
<> 144:ef7eb2e8f9f7 13261 uint8_t RESERVED_2[8];
<> 144:ef7eb2e8f9f7 13262 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
<> 144:ef7eb2e8f9f7 13263 uint8_t RESERVED_3[4];
<> 144:ef7eb2e8f9f7 13264 __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
<> 144:ef7eb2e8f9f7 13265 uint8_t RESERVED_4[4];
<> 144:ef7eb2e8f9f7 13266 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
<> 144:ef7eb2e8f9f7 13267 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
<> 144:ef7eb2e8f9f7 13268 } TPM_Type;
<> 144:ef7eb2e8f9f7 13269
<> 144:ef7eb2e8f9f7 13270 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13271 -- TPM Register Masks
<> 144:ef7eb2e8f9f7 13272 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 13273
<> 144:ef7eb2e8f9f7 13274 /*!
<> 144:ef7eb2e8f9f7 13275 * @addtogroup TPM_Register_Masks TPM Register Masks
<> 144:ef7eb2e8f9f7 13276 * @{
<> 144:ef7eb2e8f9f7 13277 */
<> 144:ef7eb2e8f9f7 13278
<> 144:ef7eb2e8f9f7 13279 /*! @name SC - Status and Control */
<> 144:ef7eb2e8f9f7 13280 #define TPM_SC_PS_MASK (0x7U)
<> 144:ef7eb2e8f9f7 13281 #define TPM_SC_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13282 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
<> 144:ef7eb2e8f9f7 13283 #define TPM_SC_CMOD_MASK (0x18U)
<> 144:ef7eb2e8f9f7 13284 #define TPM_SC_CMOD_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13285 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
<> 144:ef7eb2e8f9f7 13286 #define TPM_SC_CPWMS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13287 #define TPM_SC_CPWMS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13288 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
<> 144:ef7eb2e8f9f7 13289 #define TPM_SC_TOIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13290 #define TPM_SC_TOIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13291 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
<> 144:ef7eb2e8f9f7 13292 #define TPM_SC_TOF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13293 #define TPM_SC_TOF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13294 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
<> 144:ef7eb2e8f9f7 13295 #define TPM_SC_DMA_MASK (0x100U)
<> 144:ef7eb2e8f9f7 13296 #define TPM_SC_DMA_SHIFT (8U)
<> 144:ef7eb2e8f9f7 13297 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
<> 144:ef7eb2e8f9f7 13298
<> 144:ef7eb2e8f9f7 13299 /*! @name CNT - Counter */
<> 144:ef7eb2e8f9f7 13300 #define TPM_CNT_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13301 #define TPM_CNT_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13302 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
<> 144:ef7eb2e8f9f7 13303
<> 144:ef7eb2e8f9f7 13304 /*! @name MOD - Modulo */
<> 144:ef7eb2e8f9f7 13305 #define TPM_MOD_MOD_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13306 #define TPM_MOD_MOD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13307 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
<> 144:ef7eb2e8f9f7 13308
<> 144:ef7eb2e8f9f7 13309 /*! @name CnSC - Channel (n) Status and Control */
<> 144:ef7eb2e8f9f7 13310 #define TPM_CnSC_DMA_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13311 #define TPM_CnSC_DMA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13312 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
<> 144:ef7eb2e8f9f7 13313 #define TPM_CnSC_ELSA_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13314 #define TPM_CnSC_ELSA_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13315 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
<> 144:ef7eb2e8f9f7 13316 #define TPM_CnSC_ELSB_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13317 #define TPM_CnSC_ELSB_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13318 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
<> 144:ef7eb2e8f9f7 13319 #define TPM_CnSC_MSA_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13320 #define TPM_CnSC_MSA_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13321 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
<> 144:ef7eb2e8f9f7 13322 #define TPM_CnSC_MSB_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13323 #define TPM_CnSC_MSB_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13324 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
<> 144:ef7eb2e8f9f7 13325 #define TPM_CnSC_CHIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13326 #define TPM_CnSC_CHIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13327 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
<> 144:ef7eb2e8f9f7 13328 #define TPM_CnSC_CHF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13329 #define TPM_CnSC_CHF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13330 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
<> 144:ef7eb2e8f9f7 13331
<> 144:ef7eb2e8f9f7 13332 /* The count of TPM_CnSC */
<> 144:ef7eb2e8f9f7 13333 #define TPM_CnSC_COUNT (2U)
<> 144:ef7eb2e8f9f7 13334
<> 144:ef7eb2e8f9f7 13335 /*! @name CnV - Channel (n) Value */
<> 144:ef7eb2e8f9f7 13336 #define TPM_CnV_VAL_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13337 #define TPM_CnV_VAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13338 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
<> 144:ef7eb2e8f9f7 13339
<> 144:ef7eb2e8f9f7 13340 /* The count of TPM_CnV */
<> 144:ef7eb2e8f9f7 13341 #define TPM_CnV_COUNT (2U)
<> 144:ef7eb2e8f9f7 13342
<> 144:ef7eb2e8f9f7 13343 /*! @name STATUS - Capture and Compare Status */
<> 144:ef7eb2e8f9f7 13344 #define TPM_STATUS_CH0F_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13345 #define TPM_STATUS_CH0F_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13346 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
<> 144:ef7eb2e8f9f7 13347 #define TPM_STATUS_CH1F_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13348 #define TPM_STATUS_CH1F_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13349 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
<> 144:ef7eb2e8f9f7 13350 #define TPM_STATUS_TOF_MASK (0x100U)
<> 144:ef7eb2e8f9f7 13351 #define TPM_STATUS_TOF_SHIFT (8U)
<> 144:ef7eb2e8f9f7 13352 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
<> 144:ef7eb2e8f9f7 13353
<> 144:ef7eb2e8f9f7 13354 /*! @name COMBINE - Combine Channel Register */
<> 144:ef7eb2e8f9f7 13355 #define TPM_COMBINE_COMBINE0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13356 #define TPM_COMBINE_COMBINE0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13357 #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
<> 144:ef7eb2e8f9f7 13358 #define TPM_COMBINE_COMSWAP0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13359 #define TPM_COMBINE_COMSWAP0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13360 #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
<> 144:ef7eb2e8f9f7 13361
<> 144:ef7eb2e8f9f7 13362 /*! @name POL - Channel Polarity */
<> 144:ef7eb2e8f9f7 13363 #define TPM_POL_POL0_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13364 #define TPM_POL_POL0_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13365 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
<> 144:ef7eb2e8f9f7 13366 #define TPM_POL_POL1_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13367 #define TPM_POL_POL1_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13368 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
<> 144:ef7eb2e8f9f7 13369
<> 144:ef7eb2e8f9f7 13370 /*! @name FILTER - Filter Control */
<> 144:ef7eb2e8f9f7 13371 #define TPM_FILTER_CH0FVAL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 13372 #define TPM_FILTER_CH0FVAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13373 #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
<> 144:ef7eb2e8f9f7 13374 #define TPM_FILTER_CH1FVAL_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 13375 #define TPM_FILTER_CH1FVAL_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13376 #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
<> 144:ef7eb2e8f9f7 13377
<> 144:ef7eb2e8f9f7 13378 /*! @name QDCTRL - Quadrature Decoder Control and Status */
<> 144:ef7eb2e8f9f7 13379 #define TPM_QDCTRL_QUADEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13380 #define TPM_QDCTRL_QUADEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13381 #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
<> 144:ef7eb2e8f9f7 13382 #define TPM_QDCTRL_TOFDIR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13383 #define TPM_QDCTRL_TOFDIR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13384 #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
<> 144:ef7eb2e8f9f7 13385 #define TPM_QDCTRL_QUADIR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13386 #define TPM_QDCTRL_QUADIR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13387 #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
<> 144:ef7eb2e8f9f7 13388 #define TPM_QDCTRL_QUADMODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13389 #define TPM_QDCTRL_QUADMODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13390 #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
<> 144:ef7eb2e8f9f7 13391
<> 144:ef7eb2e8f9f7 13392 /*! @name CONF - Configuration */
<> 144:ef7eb2e8f9f7 13393 #define TPM_CONF_DOZEEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13394 #define TPM_CONF_DOZEEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13395 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
<> 144:ef7eb2e8f9f7 13396 #define TPM_CONF_DBGMODE_MASK (0xC0U)
<> 144:ef7eb2e8f9f7 13397 #define TPM_CONF_DBGMODE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13398 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
<> 144:ef7eb2e8f9f7 13399 #define TPM_CONF_GTBSYNC_MASK (0x100U)
<> 144:ef7eb2e8f9f7 13400 #define TPM_CONF_GTBSYNC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 13401 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
<> 144:ef7eb2e8f9f7 13402 #define TPM_CONF_GTBEEN_MASK (0x200U)
<> 144:ef7eb2e8f9f7 13403 #define TPM_CONF_GTBEEN_SHIFT (9U)
<> 144:ef7eb2e8f9f7 13404 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
<> 144:ef7eb2e8f9f7 13405 #define TPM_CONF_CSOT_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 13406 #define TPM_CONF_CSOT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13407 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
<> 144:ef7eb2e8f9f7 13408 #define TPM_CONF_CSOO_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 13409 #define TPM_CONF_CSOO_SHIFT (17U)
<> 144:ef7eb2e8f9f7 13410 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
<> 144:ef7eb2e8f9f7 13411 #define TPM_CONF_CROT_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 13412 #define TPM_CONF_CROT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 13413 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
<> 144:ef7eb2e8f9f7 13414 #define TPM_CONF_CPOT_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 13415 #define TPM_CONF_CPOT_SHIFT (19U)
<> 144:ef7eb2e8f9f7 13416 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
<> 144:ef7eb2e8f9f7 13417 #define TPM_CONF_TRGPOL_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 13418 #define TPM_CONF_TRGPOL_SHIFT (22U)
<> 144:ef7eb2e8f9f7 13419 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
<> 144:ef7eb2e8f9f7 13420 #define TPM_CONF_TRGSRC_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 13421 #define TPM_CONF_TRGSRC_SHIFT (23U)
<> 144:ef7eb2e8f9f7 13422 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
<> 144:ef7eb2e8f9f7 13423 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 13424 #define TPM_CONF_TRGSEL_SHIFT (24U)
<> 144:ef7eb2e8f9f7 13425 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
<> 144:ef7eb2e8f9f7 13426
<> 144:ef7eb2e8f9f7 13427
<> 144:ef7eb2e8f9f7 13428 /*!
<> 144:ef7eb2e8f9f7 13429 * @}
<> 144:ef7eb2e8f9f7 13430 */ /* end of group TPM_Register_Masks */
<> 144:ef7eb2e8f9f7 13431
<> 144:ef7eb2e8f9f7 13432
<> 144:ef7eb2e8f9f7 13433 /* TPM - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 13434 /** Peripheral TPM1 base address */
<> 144:ef7eb2e8f9f7 13435 #define TPM1_BASE (0x400C9000u)
<> 144:ef7eb2e8f9f7 13436 /** Peripheral TPM1 base pointer */
<> 144:ef7eb2e8f9f7 13437 #define TPM1 ((TPM_Type *)TPM1_BASE)
<> 144:ef7eb2e8f9f7 13438 /** Peripheral TPM2 base address */
<> 144:ef7eb2e8f9f7 13439 #define TPM2_BASE (0x400CA000u)
<> 144:ef7eb2e8f9f7 13440 /** Peripheral TPM2 base pointer */
<> 144:ef7eb2e8f9f7 13441 #define TPM2 ((TPM_Type *)TPM2_BASE)
<> 144:ef7eb2e8f9f7 13442 /** Array initializer of TPM peripheral base addresses */
<> 144:ef7eb2e8f9f7 13443 #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
<> 144:ef7eb2e8f9f7 13444 /** Array initializer of TPM peripheral base pointers */
<> 144:ef7eb2e8f9f7 13445 #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
<> 144:ef7eb2e8f9f7 13446 /** Interrupt vectors for the TPM peripheral type */
<> 144:ef7eb2e8f9f7 13447 #define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
<> 144:ef7eb2e8f9f7 13448
<> 144:ef7eb2e8f9f7 13449 /*!
<> 144:ef7eb2e8f9f7 13450 * @}
<> 144:ef7eb2e8f9f7 13451 */ /* end of group TPM_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 13452
<> 144:ef7eb2e8f9f7 13453
<> 144:ef7eb2e8f9f7 13454 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13455 -- TSI Peripheral Access Layer
<> 144:ef7eb2e8f9f7 13456 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 13457
<> 144:ef7eb2e8f9f7 13458 /*!
<> 144:ef7eb2e8f9f7 13459 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
<> 144:ef7eb2e8f9f7 13460 * @{
<> 144:ef7eb2e8f9f7 13461 */
<> 144:ef7eb2e8f9f7 13462
<> 144:ef7eb2e8f9f7 13463 /** TSI - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 13464 typedef struct {
<> 144:ef7eb2e8f9f7 13465 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 13466 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 13467 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 13468 } TSI_Type;
<> 144:ef7eb2e8f9f7 13469
<> 144:ef7eb2e8f9f7 13470 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13471 -- TSI Register Masks
<> 144:ef7eb2e8f9f7 13472 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 13473
<> 144:ef7eb2e8f9f7 13474 /*!
<> 144:ef7eb2e8f9f7 13475 * @addtogroup TSI_Register_Masks TSI Register Masks
<> 144:ef7eb2e8f9f7 13476 * @{
<> 144:ef7eb2e8f9f7 13477 */
<> 144:ef7eb2e8f9f7 13478
<> 144:ef7eb2e8f9f7 13479 /*! @name GENCS - TSI General Control and Status Register */
<> 144:ef7eb2e8f9f7 13480 #define TSI_GENCS_EOSDMEO_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13481 #define TSI_GENCS_EOSDMEO_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13482 #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
<> 144:ef7eb2e8f9f7 13483 #define TSI_GENCS_CURSW_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13484 #define TSI_GENCS_CURSW_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13485 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
<> 144:ef7eb2e8f9f7 13486 #define TSI_GENCS_EOSF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13487 #define TSI_GENCS_EOSF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13488 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
<> 144:ef7eb2e8f9f7 13489 #define TSI_GENCS_SCNIP_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13490 #define TSI_GENCS_SCNIP_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13491 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
<> 144:ef7eb2e8f9f7 13492 #define TSI_GENCS_STM_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13493 #define TSI_GENCS_STM_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13494 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
<> 144:ef7eb2e8f9f7 13495 #define TSI_GENCS_STPE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13496 #define TSI_GENCS_STPE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13497 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
<> 144:ef7eb2e8f9f7 13498 #define TSI_GENCS_TSIIEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13499 #define TSI_GENCS_TSIIEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13500 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
<> 144:ef7eb2e8f9f7 13501 #define TSI_GENCS_TSIEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13502 #define TSI_GENCS_TSIEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13503 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
<> 144:ef7eb2e8f9f7 13504 #define TSI_GENCS_NSCN_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 13505 #define TSI_GENCS_NSCN_SHIFT (8U)
<> 144:ef7eb2e8f9f7 13506 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
<> 144:ef7eb2e8f9f7 13507 #define TSI_GENCS_PS_MASK (0xE000U)
<> 144:ef7eb2e8f9f7 13508 #define TSI_GENCS_PS_SHIFT (13U)
<> 144:ef7eb2e8f9f7 13509 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
<> 144:ef7eb2e8f9f7 13510 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
<> 144:ef7eb2e8f9f7 13511 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13512 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
<> 144:ef7eb2e8f9f7 13513 #define TSI_GENCS_DVOLT_MASK (0x180000U)
<> 144:ef7eb2e8f9f7 13514 #define TSI_GENCS_DVOLT_SHIFT (19U)
<> 144:ef7eb2e8f9f7 13515 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
<> 144:ef7eb2e8f9f7 13516 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
<> 144:ef7eb2e8f9f7 13517 #define TSI_GENCS_REFCHRG_SHIFT (21U)
<> 144:ef7eb2e8f9f7 13518 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
<> 144:ef7eb2e8f9f7 13519 #define TSI_GENCS_MODE_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 13520 #define TSI_GENCS_MODE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 13521 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
<> 144:ef7eb2e8f9f7 13522 #define TSI_GENCS_ESOR_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 13523 #define TSI_GENCS_ESOR_SHIFT (28U)
<> 144:ef7eb2e8f9f7 13524 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
<> 144:ef7eb2e8f9f7 13525 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 13526 #define TSI_GENCS_OUTRGF_SHIFT (31U)
<> 144:ef7eb2e8f9f7 13527 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
<> 144:ef7eb2e8f9f7 13528
<> 144:ef7eb2e8f9f7 13529 /*! @name DATA - TSI DATA Register */
<> 144:ef7eb2e8f9f7 13530 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13531 #define TSI_DATA_TSICNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13532 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
<> 144:ef7eb2e8f9f7 13533 #define TSI_DATA_SWTS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 13534 #define TSI_DATA_SWTS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 13535 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
<> 144:ef7eb2e8f9f7 13536 #define TSI_DATA_DMAEN_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 13537 #define TSI_DATA_DMAEN_SHIFT (23U)
<> 144:ef7eb2e8f9f7 13538 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
<> 144:ef7eb2e8f9f7 13539 #define TSI_DATA_TSICH_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 13540 #define TSI_DATA_TSICH_SHIFT (28U)
<> 144:ef7eb2e8f9f7 13541 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
<> 144:ef7eb2e8f9f7 13542
<> 144:ef7eb2e8f9f7 13543 /*! @name TSHD - TSI Threshold Register */
<> 144:ef7eb2e8f9f7 13544 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 13545 #define TSI_TSHD_THRESL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13546 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
<> 144:ef7eb2e8f9f7 13547 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 13548 #define TSI_TSHD_THRESH_SHIFT (16U)
<> 144:ef7eb2e8f9f7 13549 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
<> 144:ef7eb2e8f9f7 13550
<> 144:ef7eb2e8f9f7 13551
<> 144:ef7eb2e8f9f7 13552 /*!
<> 144:ef7eb2e8f9f7 13553 * @}
<> 144:ef7eb2e8f9f7 13554 */ /* end of group TSI_Register_Masks */
<> 144:ef7eb2e8f9f7 13555
<> 144:ef7eb2e8f9f7 13556
<> 144:ef7eb2e8f9f7 13557 /* TSI - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 13558 /** Peripheral TSI0 base address */
<> 144:ef7eb2e8f9f7 13559 #define TSI0_BASE (0x40045000u)
<> 144:ef7eb2e8f9f7 13560 /** Peripheral TSI0 base pointer */
<> 144:ef7eb2e8f9f7 13561 #define TSI0 ((TSI_Type *)TSI0_BASE)
<> 144:ef7eb2e8f9f7 13562 /** Array initializer of TSI peripheral base addresses */
<> 144:ef7eb2e8f9f7 13563 #define TSI_BASE_ADDRS { TSI0_BASE }
<> 144:ef7eb2e8f9f7 13564 /** Array initializer of TSI peripheral base pointers */
<> 144:ef7eb2e8f9f7 13565 #define TSI_BASE_PTRS { TSI0 }
<> 144:ef7eb2e8f9f7 13566 /** Interrupt vectors for the TSI peripheral type */
<> 144:ef7eb2e8f9f7 13567 #define TSI_IRQS { TSI0_IRQn }
<> 144:ef7eb2e8f9f7 13568
<> 144:ef7eb2e8f9f7 13569 /*!
<> 144:ef7eb2e8f9f7 13570 * @}
<> 144:ef7eb2e8f9f7 13571 */ /* end of group TSI_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 13572
<> 144:ef7eb2e8f9f7 13573
<> 144:ef7eb2e8f9f7 13574 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13575 -- UART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 13576 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 13577
<> 144:ef7eb2e8f9f7 13578 /*!
<> 144:ef7eb2e8f9f7 13579 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
<> 144:ef7eb2e8f9f7 13580 * @{
<> 144:ef7eb2e8f9f7 13581 */
<> 144:ef7eb2e8f9f7 13582
<> 144:ef7eb2e8f9f7 13583 /** UART - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 13584 typedef struct {
<> 144:ef7eb2e8f9f7 13585 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
<> 144:ef7eb2e8f9f7 13586 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
<> 144:ef7eb2e8f9f7 13587 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
<> 144:ef7eb2e8f9f7 13588 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
<> 144:ef7eb2e8f9f7 13589 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
<> 144:ef7eb2e8f9f7 13590 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
<> 144:ef7eb2e8f9f7 13591 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
<> 144:ef7eb2e8f9f7 13592 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
<> 144:ef7eb2e8f9f7 13593 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
<> 144:ef7eb2e8f9f7 13594 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
<> 144:ef7eb2e8f9f7 13595 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
<> 144:ef7eb2e8f9f7 13596 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
<> 144:ef7eb2e8f9f7 13597 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 13598 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
<> 144:ef7eb2e8f9f7 13599 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
<> 144:ef7eb2e8f9f7 13600 uint8_t RESERVED_0[1];
<> 144:ef7eb2e8f9f7 13601 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
<> 144:ef7eb2e8f9f7 13602 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
<> 144:ef7eb2e8f9f7 13603 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
<> 144:ef7eb2e8f9f7 13604 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
<> 144:ef7eb2e8f9f7 13605 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
<> 144:ef7eb2e8f9f7 13606 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
<> 144:ef7eb2e8f9f7 13607 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
<> 144:ef7eb2e8f9f7 13608 uint8_t RESERVED_1[1];
<> 144:ef7eb2e8f9f7 13609 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 13610 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
<> 144:ef7eb2e8f9f7 13611 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
<> 144:ef7eb2e8f9f7 13612 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
<> 144:ef7eb2e8f9f7 13613 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 13614 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
<> 144:ef7eb2e8f9f7 13615 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
<> 144:ef7eb2e8f9f7 13616 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
<> 144:ef7eb2e8f9f7 13617 uint8_t RESERVED_2[26];
<> 144:ef7eb2e8f9f7 13618 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
<> 144:ef7eb2e8f9f7 13619 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
<> 144:ef7eb2e8f9f7 13620 union { /* offset: 0x3C */
<> 144:ef7eb2e8f9f7 13621 struct { /* offset: 0x3C */
<> 144:ef7eb2e8f9f7 13622 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
<> 144:ef7eb2e8f9f7 13623 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
<> 144:ef7eb2e8f9f7 13624 } TYPE0;
<> 144:ef7eb2e8f9f7 13625 struct { /* offset: 0x3C */
<> 144:ef7eb2e8f9f7 13626 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
<> 144:ef7eb2e8f9f7 13627 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
<> 144:ef7eb2e8f9f7 13628 } TYPE1;
<> 144:ef7eb2e8f9f7 13629 };
<> 144:ef7eb2e8f9f7 13630 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
<> 144:ef7eb2e8f9f7 13631 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
<> 144:ef7eb2e8f9f7 13632 } UART_Type;
<> 144:ef7eb2e8f9f7 13633
<> 144:ef7eb2e8f9f7 13634 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13635 -- UART Register Masks
<> 144:ef7eb2e8f9f7 13636 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 13637
<> 144:ef7eb2e8f9f7 13638 /*!
<> 144:ef7eb2e8f9f7 13639 * @addtogroup UART_Register_Masks UART Register Masks
<> 144:ef7eb2e8f9f7 13640 * @{
<> 144:ef7eb2e8f9f7 13641 */
<> 144:ef7eb2e8f9f7 13642
<> 144:ef7eb2e8f9f7 13643 /*! @name BDH - UART Baud Rate Registers: High */
<> 144:ef7eb2e8f9f7 13644 #define UART_BDH_SBR_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 13645 #define UART_BDH_SBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13646 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
<> 144:ef7eb2e8f9f7 13647 #define UART_BDH_SBNS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13648 #define UART_BDH_SBNS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13649 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
<> 144:ef7eb2e8f9f7 13650 #define UART_BDH_RXEDGIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13651 #define UART_BDH_RXEDGIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13652 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
<> 144:ef7eb2e8f9f7 13653 #define UART_BDH_LBKDIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13654 #define UART_BDH_LBKDIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13655 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
<> 144:ef7eb2e8f9f7 13656
<> 144:ef7eb2e8f9f7 13657 /*! @name BDL - UART Baud Rate Registers: Low */
<> 144:ef7eb2e8f9f7 13658 #define UART_BDL_SBR_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13659 #define UART_BDL_SBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13660 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
<> 144:ef7eb2e8f9f7 13661
<> 144:ef7eb2e8f9f7 13662 /*! @name C1 - UART Control Register 1 */
<> 144:ef7eb2e8f9f7 13663 #define UART_C1_PT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13664 #define UART_C1_PT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13665 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
<> 144:ef7eb2e8f9f7 13666 #define UART_C1_PE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13667 #define UART_C1_PE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13668 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
<> 144:ef7eb2e8f9f7 13669 #define UART_C1_ILT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13670 #define UART_C1_ILT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13671 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
<> 144:ef7eb2e8f9f7 13672 #define UART_C1_WAKE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13673 #define UART_C1_WAKE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13674 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
<> 144:ef7eb2e8f9f7 13675 #define UART_C1_M_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13676 #define UART_C1_M_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13677 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
<> 144:ef7eb2e8f9f7 13678 #define UART_C1_RSRC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13679 #define UART_C1_RSRC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13680 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
<> 144:ef7eb2e8f9f7 13681 #define UART_C1_UARTSWAI_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13682 #define UART_C1_UARTSWAI_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13683 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
<> 144:ef7eb2e8f9f7 13684 #define UART_C1_LOOPS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13685 #define UART_C1_LOOPS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13686 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
<> 144:ef7eb2e8f9f7 13687
<> 144:ef7eb2e8f9f7 13688 /*! @name C2 - UART Control Register 2 */
<> 144:ef7eb2e8f9f7 13689 #define UART_C2_SBK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13690 #define UART_C2_SBK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13691 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
<> 144:ef7eb2e8f9f7 13692 #define UART_C2_RWU_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13693 #define UART_C2_RWU_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13694 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
<> 144:ef7eb2e8f9f7 13695 #define UART_C2_RE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13696 #define UART_C2_RE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13697 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
<> 144:ef7eb2e8f9f7 13698 #define UART_C2_TE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13699 #define UART_C2_TE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13700 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
<> 144:ef7eb2e8f9f7 13701 #define UART_C2_ILIE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13702 #define UART_C2_ILIE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13703 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
<> 144:ef7eb2e8f9f7 13704 #define UART_C2_RIE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13705 #define UART_C2_RIE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13706 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
<> 144:ef7eb2e8f9f7 13707 #define UART_C2_TCIE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13708 #define UART_C2_TCIE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13709 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
<> 144:ef7eb2e8f9f7 13710 #define UART_C2_TIE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13711 #define UART_C2_TIE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13712 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
<> 144:ef7eb2e8f9f7 13713
<> 144:ef7eb2e8f9f7 13714 /*! @name S1 - UART Status Register 1 */
<> 144:ef7eb2e8f9f7 13715 #define UART_S1_PF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13716 #define UART_S1_PF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13717 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
<> 144:ef7eb2e8f9f7 13718 #define UART_S1_FE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13719 #define UART_S1_FE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13720 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
<> 144:ef7eb2e8f9f7 13721 #define UART_S1_NF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13722 #define UART_S1_NF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13723 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
<> 144:ef7eb2e8f9f7 13724 #define UART_S1_OR_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13725 #define UART_S1_OR_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13726 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
<> 144:ef7eb2e8f9f7 13727 #define UART_S1_IDLE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13728 #define UART_S1_IDLE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13729 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
<> 144:ef7eb2e8f9f7 13730 #define UART_S1_RDRF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13731 #define UART_S1_RDRF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13732 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
<> 144:ef7eb2e8f9f7 13733 #define UART_S1_TC_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13734 #define UART_S1_TC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13735 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
<> 144:ef7eb2e8f9f7 13736 #define UART_S1_TDRE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13737 #define UART_S1_TDRE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13738 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
<> 144:ef7eb2e8f9f7 13739
<> 144:ef7eb2e8f9f7 13740 /*! @name S2 - UART Status Register 2 */
<> 144:ef7eb2e8f9f7 13741 #define UART_S2_RAF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13742 #define UART_S2_RAF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13743 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
<> 144:ef7eb2e8f9f7 13744 #define UART_S2_LBKDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13745 #define UART_S2_LBKDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13746 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
<> 144:ef7eb2e8f9f7 13747 #define UART_S2_BRK13_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13748 #define UART_S2_BRK13_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13749 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
<> 144:ef7eb2e8f9f7 13750 #define UART_S2_RWUID_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13751 #define UART_S2_RWUID_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13752 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
<> 144:ef7eb2e8f9f7 13753 #define UART_S2_RXINV_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13754 #define UART_S2_RXINV_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13755 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
<> 144:ef7eb2e8f9f7 13756 #define UART_S2_MSBF_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13757 #define UART_S2_MSBF_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13758 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
<> 144:ef7eb2e8f9f7 13759 #define UART_S2_RXEDGIF_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13760 #define UART_S2_RXEDGIF_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13761 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
<> 144:ef7eb2e8f9f7 13762 #define UART_S2_LBKDIF_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13763 #define UART_S2_LBKDIF_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13764 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
<> 144:ef7eb2e8f9f7 13765
<> 144:ef7eb2e8f9f7 13766 /*! @name C3 - UART Control Register 3 */
<> 144:ef7eb2e8f9f7 13767 #define UART_C3_PEIE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13768 #define UART_C3_PEIE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13769 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
<> 144:ef7eb2e8f9f7 13770 #define UART_C3_FEIE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13771 #define UART_C3_FEIE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13772 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
<> 144:ef7eb2e8f9f7 13773 #define UART_C3_NEIE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13774 #define UART_C3_NEIE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13775 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
<> 144:ef7eb2e8f9f7 13776 #define UART_C3_ORIE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13777 #define UART_C3_ORIE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13778 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
<> 144:ef7eb2e8f9f7 13779 #define UART_C3_TXINV_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13780 #define UART_C3_TXINV_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13781 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
<> 144:ef7eb2e8f9f7 13782 #define UART_C3_TXDIR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13783 #define UART_C3_TXDIR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13784 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
<> 144:ef7eb2e8f9f7 13785 #define UART_C3_T8_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13786 #define UART_C3_T8_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13787 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
<> 144:ef7eb2e8f9f7 13788 #define UART_C3_R8_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13789 #define UART_C3_R8_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13790 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
<> 144:ef7eb2e8f9f7 13791
<> 144:ef7eb2e8f9f7 13792 /*! @name D - UART Data Register */
<> 144:ef7eb2e8f9f7 13793 #define UART_D_RT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13794 #define UART_D_RT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13795 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
<> 144:ef7eb2e8f9f7 13796
<> 144:ef7eb2e8f9f7 13797 /*! @name MA1 - UART Match Address Registers 1 */
<> 144:ef7eb2e8f9f7 13798 #define UART_MA1_MA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13799 #define UART_MA1_MA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13800 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
<> 144:ef7eb2e8f9f7 13801
<> 144:ef7eb2e8f9f7 13802 /*! @name MA2 - UART Match Address Registers 2 */
<> 144:ef7eb2e8f9f7 13803 #define UART_MA2_MA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13804 #define UART_MA2_MA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13805 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
<> 144:ef7eb2e8f9f7 13806
<> 144:ef7eb2e8f9f7 13807 /*! @name C4 - UART Control Register 4 */
<> 144:ef7eb2e8f9f7 13808 #define UART_C4_BRFA_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 13809 #define UART_C4_BRFA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13810 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
<> 144:ef7eb2e8f9f7 13811 #define UART_C4_M10_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13812 #define UART_C4_M10_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13813 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
<> 144:ef7eb2e8f9f7 13814 #define UART_C4_MAEN2_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13815 #define UART_C4_MAEN2_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13816 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
<> 144:ef7eb2e8f9f7 13817 #define UART_C4_MAEN1_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13818 #define UART_C4_MAEN1_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13819 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
<> 144:ef7eb2e8f9f7 13820
<> 144:ef7eb2e8f9f7 13821 /*! @name C5 - UART Control Register 5 */
<> 144:ef7eb2e8f9f7 13822 #define UART_C5_RDMAS_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13823 #define UART_C5_RDMAS_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13824 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
<> 144:ef7eb2e8f9f7 13825 #define UART_C5_TDMAS_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13826 #define UART_C5_TDMAS_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13827 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
<> 144:ef7eb2e8f9f7 13828
<> 144:ef7eb2e8f9f7 13829 /*! @name ED - UART Extended Data Register */
<> 144:ef7eb2e8f9f7 13830 #define UART_ED_PARITYE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13831 #define UART_ED_PARITYE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13832 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
<> 144:ef7eb2e8f9f7 13833 #define UART_ED_NOISY_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13834 #define UART_ED_NOISY_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13835 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
<> 144:ef7eb2e8f9f7 13836
<> 144:ef7eb2e8f9f7 13837 /*! @name MODEM - UART Modem Register */
<> 144:ef7eb2e8f9f7 13838 #define UART_MODEM_TXCTSE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13839 #define UART_MODEM_TXCTSE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13840 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
<> 144:ef7eb2e8f9f7 13841 #define UART_MODEM_TXRTSE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13842 #define UART_MODEM_TXRTSE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13843 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
<> 144:ef7eb2e8f9f7 13844 #define UART_MODEM_TXRTSPOL_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13845 #define UART_MODEM_TXRTSPOL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13846 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
<> 144:ef7eb2e8f9f7 13847 #define UART_MODEM_RXRTSE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13848 #define UART_MODEM_RXRTSE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13849 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
<> 144:ef7eb2e8f9f7 13850
<> 144:ef7eb2e8f9f7 13851 /*! @name IR - UART Infrared Register */
<> 144:ef7eb2e8f9f7 13852 #define UART_IR_TNP_MASK (0x3U)
<> 144:ef7eb2e8f9f7 13853 #define UART_IR_TNP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13854 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
<> 144:ef7eb2e8f9f7 13855 #define UART_IR_IREN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13856 #define UART_IR_IREN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13857 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
<> 144:ef7eb2e8f9f7 13858
<> 144:ef7eb2e8f9f7 13859 /*! @name PFIFO - UART FIFO Parameters */
<> 144:ef7eb2e8f9f7 13860 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
<> 144:ef7eb2e8f9f7 13861 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13862 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
<> 144:ef7eb2e8f9f7 13863 #define UART_PFIFO_RXFE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13864 #define UART_PFIFO_RXFE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13865 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
<> 144:ef7eb2e8f9f7 13866 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
<> 144:ef7eb2e8f9f7 13867 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13868 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
<> 144:ef7eb2e8f9f7 13869 #define UART_PFIFO_TXFE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13870 #define UART_PFIFO_TXFE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13871 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
<> 144:ef7eb2e8f9f7 13872
<> 144:ef7eb2e8f9f7 13873 /*! @name CFIFO - UART FIFO Control Register */
<> 144:ef7eb2e8f9f7 13874 #define UART_CFIFO_RXUFE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13875 #define UART_CFIFO_RXUFE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13876 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
<> 144:ef7eb2e8f9f7 13877 #define UART_CFIFO_TXOFE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13878 #define UART_CFIFO_TXOFE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13879 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
<> 144:ef7eb2e8f9f7 13880 #define UART_CFIFO_RXOFE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13881 #define UART_CFIFO_RXOFE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13882 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
<> 144:ef7eb2e8f9f7 13883 #define UART_CFIFO_RXFLUSH_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13884 #define UART_CFIFO_RXFLUSH_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13885 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
<> 144:ef7eb2e8f9f7 13886 #define UART_CFIFO_TXFLUSH_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13887 #define UART_CFIFO_TXFLUSH_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13888 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
<> 144:ef7eb2e8f9f7 13889
<> 144:ef7eb2e8f9f7 13890 /*! @name SFIFO - UART FIFO Status Register */
<> 144:ef7eb2e8f9f7 13891 #define UART_SFIFO_RXUF_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13892 #define UART_SFIFO_RXUF_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13893 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
<> 144:ef7eb2e8f9f7 13894 #define UART_SFIFO_TXOF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13895 #define UART_SFIFO_TXOF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13896 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
<> 144:ef7eb2e8f9f7 13897 #define UART_SFIFO_RXOF_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13898 #define UART_SFIFO_RXOF_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13899 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
<> 144:ef7eb2e8f9f7 13900 #define UART_SFIFO_RXEMPT_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13901 #define UART_SFIFO_RXEMPT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13902 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
<> 144:ef7eb2e8f9f7 13903 #define UART_SFIFO_TXEMPT_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13904 #define UART_SFIFO_TXEMPT_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13905 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
<> 144:ef7eb2e8f9f7 13906
<> 144:ef7eb2e8f9f7 13907 /*! @name TWFIFO - UART FIFO Transmit Watermark */
<> 144:ef7eb2e8f9f7 13908 #define UART_TWFIFO_TXWATER_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13909 #define UART_TWFIFO_TXWATER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13910 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
<> 144:ef7eb2e8f9f7 13911
<> 144:ef7eb2e8f9f7 13912 /*! @name TCFIFO - UART FIFO Transmit Count */
<> 144:ef7eb2e8f9f7 13913 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13914 #define UART_TCFIFO_TXCOUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13915 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 13916
<> 144:ef7eb2e8f9f7 13917 /*! @name RWFIFO - UART FIFO Receive Watermark */
<> 144:ef7eb2e8f9f7 13918 #define UART_RWFIFO_RXWATER_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13919 #define UART_RWFIFO_RXWATER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13920 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
<> 144:ef7eb2e8f9f7 13921
<> 144:ef7eb2e8f9f7 13922 /*! @name RCFIFO - UART FIFO Receive Count */
<> 144:ef7eb2e8f9f7 13923 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13924 #define UART_RCFIFO_RXCOUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13925 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 13926
<> 144:ef7eb2e8f9f7 13927 /*! @name C7816 - UART 7816 Control Register */
<> 144:ef7eb2e8f9f7 13928 #define UART_C7816_ISO_7816E_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13929 #define UART_C7816_ISO_7816E_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13930 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
<> 144:ef7eb2e8f9f7 13931 #define UART_C7816_TTYPE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13932 #define UART_C7816_TTYPE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13933 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
<> 144:ef7eb2e8f9f7 13934 #define UART_C7816_INIT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13935 #define UART_C7816_INIT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13936 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
<> 144:ef7eb2e8f9f7 13937 #define UART_C7816_ANACK_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13938 #define UART_C7816_ANACK_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13939 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
<> 144:ef7eb2e8f9f7 13940 #define UART_C7816_ONACK_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13941 #define UART_C7816_ONACK_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13942 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
<> 144:ef7eb2e8f9f7 13943
<> 144:ef7eb2e8f9f7 13944 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 13945 #define UART_IE7816_RXTE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13946 #define UART_IE7816_RXTE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13947 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
<> 144:ef7eb2e8f9f7 13948 #define UART_IE7816_TXTE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13949 #define UART_IE7816_TXTE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13950 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
<> 144:ef7eb2e8f9f7 13951 #define UART_IE7816_GTVE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13952 #define UART_IE7816_GTVE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13953 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
<> 144:ef7eb2e8f9f7 13954 #define UART_IE7816_ADTE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13955 #define UART_IE7816_ADTE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13956 #define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
<> 144:ef7eb2e8f9f7 13957 #define UART_IE7816_INITDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13958 #define UART_IE7816_INITDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13959 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
<> 144:ef7eb2e8f9f7 13960 #define UART_IE7816_BWTE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13961 #define UART_IE7816_BWTE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13962 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
<> 144:ef7eb2e8f9f7 13963 #define UART_IE7816_CWTE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13964 #define UART_IE7816_CWTE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13965 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
<> 144:ef7eb2e8f9f7 13966 #define UART_IE7816_WTE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13967 #define UART_IE7816_WTE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13968 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
<> 144:ef7eb2e8f9f7 13969
<> 144:ef7eb2e8f9f7 13970 /*! @name IS7816 - UART 7816 Interrupt Status Register */
<> 144:ef7eb2e8f9f7 13971 #define UART_IS7816_RXT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 13972 #define UART_IS7816_RXT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13973 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
<> 144:ef7eb2e8f9f7 13974 #define UART_IS7816_TXT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 13975 #define UART_IS7816_TXT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 13976 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
<> 144:ef7eb2e8f9f7 13977 #define UART_IS7816_GTV_MASK (0x4U)
<> 144:ef7eb2e8f9f7 13978 #define UART_IS7816_GTV_SHIFT (2U)
<> 144:ef7eb2e8f9f7 13979 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
<> 144:ef7eb2e8f9f7 13980 #define UART_IS7816_ADT_MASK (0x8U)
<> 144:ef7eb2e8f9f7 13981 #define UART_IS7816_ADT_SHIFT (3U)
<> 144:ef7eb2e8f9f7 13982 #define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
<> 144:ef7eb2e8f9f7 13983 #define UART_IS7816_INITD_MASK (0x10U)
<> 144:ef7eb2e8f9f7 13984 #define UART_IS7816_INITD_SHIFT (4U)
<> 144:ef7eb2e8f9f7 13985 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
<> 144:ef7eb2e8f9f7 13986 #define UART_IS7816_BWT_MASK (0x20U)
<> 144:ef7eb2e8f9f7 13987 #define UART_IS7816_BWT_SHIFT (5U)
<> 144:ef7eb2e8f9f7 13988 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
<> 144:ef7eb2e8f9f7 13989 #define UART_IS7816_CWT_MASK (0x40U)
<> 144:ef7eb2e8f9f7 13990 #define UART_IS7816_CWT_SHIFT (6U)
<> 144:ef7eb2e8f9f7 13991 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
<> 144:ef7eb2e8f9f7 13992 #define UART_IS7816_WT_MASK (0x80U)
<> 144:ef7eb2e8f9f7 13993 #define UART_IS7816_WT_SHIFT (7U)
<> 144:ef7eb2e8f9f7 13994 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
<> 144:ef7eb2e8f9f7 13995
<> 144:ef7eb2e8f9f7 13996 /*! @name WP7816 - UART 7816 Wait Parameter Register */
<> 144:ef7eb2e8f9f7 13997 #define UART_WP7816_WTX_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 13998 #define UART_WP7816_WTX_SHIFT (0U)
<> 144:ef7eb2e8f9f7 13999 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
<> 144:ef7eb2e8f9f7 14000
<> 144:ef7eb2e8f9f7 14001 /*! @name WN7816 - UART 7816 Wait N Register */
<> 144:ef7eb2e8f9f7 14002 #define UART_WN7816_GTN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14003 #define UART_WN7816_GTN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14004 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
<> 144:ef7eb2e8f9f7 14005
<> 144:ef7eb2e8f9f7 14006 /*! @name WF7816 - UART 7816 Wait FD Register */
<> 144:ef7eb2e8f9f7 14007 #define UART_WF7816_GTFD_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14008 #define UART_WF7816_GTFD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14009 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
<> 144:ef7eb2e8f9f7 14010
<> 144:ef7eb2e8f9f7 14011 /*! @name ET7816 - UART 7816 Error Threshold Register */
<> 144:ef7eb2e8f9f7 14012 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
<> 144:ef7eb2e8f9f7 14013 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14014 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
<> 144:ef7eb2e8f9f7 14015 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 14016 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14017 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
<> 144:ef7eb2e8f9f7 14018
<> 144:ef7eb2e8f9f7 14019 /*! @name TL7816 - UART 7816 Transmit Length Register */
<> 144:ef7eb2e8f9f7 14020 #define UART_TL7816_TLEN_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14021 #define UART_TL7816_TLEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14022 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
<> 144:ef7eb2e8f9f7 14023
<> 144:ef7eb2e8f9f7 14024 /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
<> 144:ef7eb2e8f9f7 14025 #define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14026 #define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14027 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
<> 144:ef7eb2e8f9f7 14028
<> 144:ef7eb2e8f9f7 14029 /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
<> 144:ef7eb2e8f9f7 14030 #define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14031 #define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14032 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
<> 144:ef7eb2e8f9f7 14033
<> 144:ef7eb2e8f9f7 14034 /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
<> 144:ef7eb2e8f9f7 14035 #define UART_WP7816A_T0_WI_H_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14036 #define UART_WP7816A_T0_WI_H_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14037 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
<> 144:ef7eb2e8f9f7 14038
<> 144:ef7eb2e8f9f7 14039 /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
<> 144:ef7eb2e8f9f7 14040 #define UART_WP7816B_T0_WI_L_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14041 #define UART_WP7816B_T0_WI_L_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14042 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
<> 144:ef7eb2e8f9f7 14043
<> 144:ef7eb2e8f9f7 14044 /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
<> 144:ef7eb2e8f9f7 14045 #define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14046 #define UART_WP7816A_T1_BWI_H_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14047 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
<> 144:ef7eb2e8f9f7 14048
<> 144:ef7eb2e8f9f7 14049 /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
<> 144:ef7eb2e8f9f7 14050 #define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14051 #define UART_WP7816B_T1_BWI_L_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14052 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
<> 144:ef7eb2e8f9f7 14053
<> 144:ef7eb2e8f9f7 14054 /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
<> 144:ef7eb2e8f9f7 14055 #define UART_WGP7816_T1_BGI_MASK (0xFU)
<> 144:ef7eb2e8f9f7 14056 #define UART_WGP7816_T1_BGI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14057 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
<> 144:ef7eb2e8f9f7 14058 #define UART_WGP7816_T1_CWI1_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 14059 #define UART_WGP7816_T1_CWI1_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14060 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
<> 144:ef7eb2e8f9f7 14061
<> 144:ef7eb2e8f9f7 14062 /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
<> 144:ef7eb2e8f9f7 14063 #define UART_WP7816C_T1_CWI2_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 14064 #define UART_WP7816C_T1_CWI2_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14065 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
<> 144:ef7eb2e8f9f7 14066
<> 144:ef7eb2e8f9f7 14067
<> 144:ef7eb2e8f9f7 14068 /*!
<> 144:ef7eb2e8f9f7 14069 * @}
<> 144:ef7eb2e8f9f7 14070 */ /* end of group UART_Register_Masks */
<> 144:ef7eb2e8f9f7 14071
<> 144:ef7eb2e8f9f7 14072
<> 144:ef7eb2e8f9f7 14073 /* UART - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 14074 /** Peripheral UART0 base address */
<> 144:ef7eb2e8f9f7 14075 #define UART0_BASE (0x4006A000u)
<> 144:ef7eb2e8f9f7 14076 /** Peripheral UART0 base pointer */
<> 144:ef7eb2e8f9f7 14077 #define UART0 ((UART_Type *)UART0_BASE)
<> 144:ef7eb2e8f9f7 14078 /** Peripheral UART1 base address */
<> 144:ef7eb2e8f9f7 14079 #define UART1_BASE (0x4006B000u)
<> 144:ef7eb2e8f9f7 14080 /** Peripheral UART1 base pointer */
<> 144:ef7eb2e8f9f7 14081 #define UART1 ((UART_Type *)UART1_BASE)
<> 144:ef7eb2e8f9f7 14082 /** Peripheral UART2 base address */
<> 144:ef7eb2e8f9f7 14083 #define UART2_BASE (0x4006C000u)
<> 144:ef7eb2e8f9f7 14084 /** Peripheral UART2 base pointer */
<> 144:ef7eb2e8f9f7 14085 #define UART2 ((UART_Type *)UART2_BASE)
<> 144:ef7eb2e8f9f7 14086 /** Peripheral UART3 base address */
<> 144:ef7eb2e8f9f7 14087 #define UART3_BASE (0x4006D000u)
<> 144:ef7eb2e8f9f7 14088 /** Peripheral UART3 base pointer */
<> 144:ef7eb2e8f9f7 14089 #define UART3 ((UART_Type *)UART3_BASE)
<> 144:ef7eb2e8f9f7 14090 /** Peripheral UART4 base address */
<> 144:ef7eb2e8f9f7 14091 #define UART4_BASE (0x400EA000u)
<> 144:ef7eb2e8f9f7 14092 /** Peripheral UART4 base pointer */
<> 144:ef7eb2e8f9f7 14093 #define UART4 ((UART_Type *)UART4_BASE)
<> 144:ef7eb2e8f9f7 14094 /** Array initializer of UART peripheral base addresses */
<> 144:ef7eb2e8f9f7 14095 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
<> 144:ef7eb2e8f9f7 14096 /** Array initializer of UART peripheral base pointers */
<> 144:ef7eb2e8f9f7 14097 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4 }
<> 144:ef7eb2e8f9f7 14098 /** Interrupt vectors for the UART peripheral type */
<> 144:ef7eb2e8f9f7 14099 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
<> 144:ef7eb2e8f9f7 14100 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
<> 144:ef7eb2e8f9f7 14101
<> 144:ef7eb2e8f9f7 14102 /*!
<> 144:ef7eb2e8f9f7 14103 * @}
<> 144:ef7eb2e8f9f7 14104 */ /* end of group UART_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 14105
<> 144:ef7eb2e8f9f7 14106
<> 144:ef7eb2e8f9f7 14107 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14108 -- USB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 14109 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 14110
<> 144:ef7eb2e8f9f7 14111 /*!
<> 144:ef7eb2e8f9f7 14112 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
<> 144:ef7eb2e8f9f7 14113 * @{
<> 144:ef7eb2e8f9f7 14114 */
<> 144:ef7eb2e8f9f7 14115
<> 144:ef7eb2e8f9f7 14116 /** USB - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 14117 typedef struct {
<> 144:ef7eb2e8f9f7 14118 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 14119 uint8_t RESERVED_0[3];
<> 144:ef7eb2e8f9f7 14120 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 14121 uint8_t RESERVED_1[3];
<> 144:ef7eb2e8f9f7 14122 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 14123 uint8_t RESERVED_2[3];
<> 144:ef7eb2e8f9f7 14124 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
<> 144:ef7eb2e8f9f7 14125 uint8_t RESERVED_3[3];
<> 144:ef7eb2e8f9f7 14126 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 14127 uint8_t RESERVED_4[3];
<> 144:ef7eb2e8f9f7 14128 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 14129 uint8_t RESERVED_5[3];
<> 144:ef7eb2e8f9f7 14130 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 14131 uint8_t RESERVED_6[3];
<> 144:ef7eb2e8f9f7 14132 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 14133 uint8_t RESERVED_7[99];
<> 144:ef7eb2e8f9f7 14134 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 14135 uint8_t RESERVED_8[3];
<> 144:ef7eb2e8f9f7 14136 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 14137 uint8_t RESERVED_9[3];
<> 144:ef7eb2e8f9f7 14138 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
<> 144:ef7eb2e8f9f7 14139 uint8_t RESERVED_10[3];
<> 144:ef7eb2e8f9f7 14140 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
<> 144:ef7eb2e8f9f7 14141 uint8_t RESERVED_11[3];
<> 144:ef7eb2e8f9f7 14142 __I uint8_t STAT; /**< Status register, offset: 0x90 */
<> 144:ef7eb2e8f9f7 14143 uint8_t RESERVED_12[3];
<> 144:ef7eb2e8f9f7 14144 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
<> 144:ef7eb2e8f9f7 14145 uint8_t RESERVED_13[3];
<> 144:ef7eb2e8f9f7 14146 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
<> 144:ef7eb2e8f9f7 14147 uint8_t RESERVED_14[3];
<> 144:ef7eb2e8f9f7 14148 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
<> 144:ef7eb2e8f9f7 14149 uint8_t RESERVED_15[3];
<> 144:ef7eb2e8f9f7 14150 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
<> 144:ef7eb2e8f9f7 14151 uint8_t RESERVED_16[3];
<> 144:ef7eb2e8f9f7 14152 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
<> 144:ef7eb2e8f9f7 14153 uint8_t RESERVED_17[3];
<> 144:ef7eb2e8f9f7 14154 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
<> 144:ef7eb2e8f9f7 14155 uint8_t RESERVED_18[3];
<> 144:ef7eb2e8f9f7 14156 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
<> 144:ef7eb2e8f9f7 14157 uint8_t RESERVED_19[3];
<> 144:ef7eb2e8f9f7 14158 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
<> 144:ef7eb2e8f9f7 14159 uint8_t RESERVED_20[3];
<> 144:ef7eb2e8f9f7 14160 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
<> 144:ef7eb2e8f9f7 14161 uint8_t RESERVED_21[11];
<> 144:ef7eb2e8f9f7 14162 struct { /* offset: 0xC0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 14163 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
<> 144:ef7eb2e8f9f7 14164 uint8_t RESERVED_0[3];
<> 144:ef7eb2e8f9f7 14165 } ENDPOINT[16];
<> 144:ef7eb2e8f9f7 14166 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 14167 uint8_t RESERVED_22[3];
<> 144:ef7eb2e8f9f7 14168 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
<> 144:ef7eb2e8f9f7 14169 uint8_t RESERVED_23[3];
<> 144:ef7eb2e8f9f7 14170 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
<> 144:ef7eb2e8f9f7 14171 uint8_t RESERVED_24[3];
<> 144:ef7eb2e8f9f7 14172 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
<> 144:ef7eb2e8f9f7 14173 uint8_t RESERVED_25[7];
<> 144:ef7eb2e8f9f7 14174 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
<> 144:ef7eb2e8f9f7 14175 uint8_t RESERVED_26[43];
<> 144:ef7eb2e8f9f7 14176 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
<> 144:ef7eb2e8f9f7 14177 uint8_t RESERVED_27[3];
<> 144:ef7eb2e8f9f7 14178 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
<> 144:ef7eb2e8f9f7 14179 uint8_t RESERVED_28[15];
<> 144:ef7eb2e8f9f7 14180 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
<> 144:ef7eb2e8f9f7 14181 uint8_t RESERVED_29[7];
<> 144:ef7eb2e8f9f7 14182 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
<> 144:ef7eb2e8f9f7 14183 } USB_Type;
<> 144:ef7eb2e8f9f7 14184
<> 144:ef7eb2e8f9f7 14185 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14186 -- USB Register Masks
<> 144:ef7eb2e8f9f7 14187 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 14188
<> 144:ef7eb2e8f9f7 14189 /*!
<> 144:ef7eb2e8f9f7 14190 * @addtogroup USB_Register_Masks USB Register Masks
<> 144:ef7eb2e8f9f7 14191 * @{
<> 144:ef7eb2e8f9f7 14192 */
<> 144:ef7eb2e8f9f7 14193
<> 144:ef7eb2e8f9f7 14194 /*! @name PERID - Peripheral ID register */
<> 144:ef7eb2e8f9f7 14195 #define USB_PERID_ID_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 14196 #define USB_PERID_ID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14197 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
<> 144:ef7eb2e8f9f7 14198
<> 144:ef7eb2e8f9f7 14199 /*! @name IDCOMP - Peripheral ID Complement register */
<> 144:ef7eb2e8f9f7 14200 #define USB_IDCOMP_NID_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 14201 #define USB_IDCOMP_NID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14202 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
<> 144:ef7eb2e8f9f7 14203
<> 144:ef7eb2e8f9f7 14204 /*! @name REV - Peripheral Revision register */
<> 144:ef7eb2e8f9f7 14205 #define USB_REV_REV_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14206 #define USB_REV_REV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14207 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
<> 144:ef7eb2e8f9f7 14208
<> 144:ef7eb2e8f9f7 14209 /*! @name ADDINFO - Peripheral Additional Info register */
<> 144:ef7eb2e8f9f7 14210 #define USB_ADDINFO_IEHOST_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14211 #define USB_ADDINFO_IEHOST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14212 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
<> 144:ef7eb2e8f9f7 14213
<> 144:ef7eb2e8f9f7 14214 /*! @name OTGISTAT - OTG Interrupt Status register */
<> 144:ef7eb2e8f9f7 14215 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14216 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14217 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
<> 144:ef7eb2e8f9f7 14218 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14219 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14220 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
<> 144:ef7eb2e8f9f7 14221 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14222 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14223 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
<> 144:ef7eb2e8f9f7 14224 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14225 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14226 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
<> 144:ef7eb2e8f9f7 14227 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14228 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14229 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
<> 144:ef7eb2e8f9f7 14230 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14231 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14232 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
<> 144:ef7eb2e8f9f7 14233
<> 144:ef7eb2e8f9f7 14234 /*! @name OTGICR - OTG Interrupt Control register */
<> 144:ef7eb2e8f9f7 14235 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14236 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14237 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
<> 144:ef7eb2e8f9f7 14238 #define USB_OTGICR_BSESSEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14239 #define USB_OTGICR_BSESSEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14240 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
<> 144:ef7eb2e8f9f7 14241 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14242 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14243 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
<> 144:ef7eb2e8f9f7 14244 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14245 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14246 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
<> 144:ef7eb2e8f9f7 14247 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14248 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14249 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
<> 144:ef7eb2e8f9f7 14250 #define USB_OTGICR_IDEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14251 #define USB_OTGICR_IDEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14252 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
<> 144:ef7eb2e8f9f7 14253
<> 144:ef7eb2e8f9f7 14254 /*! @name OTGSTAT - OTG Status register */
<> 144:ef7eb2e8f9f7 14255 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14256 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14257 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
<> 144:ef7eb2e8f9f7 14258 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14259 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14260 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
<> 144:ef7eb2e8f9f7 14261 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14262 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14263 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
<> 144:ef7eb2e8f9f7 14264 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14265 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14266 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
<> 144:ef7eb2e8f9f7 14267 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14268 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14269 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
<> 144:ef7eb2e8f9f7 14270 #define USB_OTGSTAT_ID_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14271 #define USB_OTGSTAT_ID_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14272 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
<> 144:ef7eb2e8f9f7 14273
<> 144:ef7eb2e8f9f7 14274 /*! @name OTGCTL - OTG Control register */
<> 144:ef7eb2e8f9f7 14275 #define USB_OTGCTL_OTGEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14276 #define USB_OTGCTL_OTGEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14277 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
<> 144:ef7eb2e8f9f7 14278 #define USB_OTGCTL_DMLOW_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14279 #define USB_OTGCTL_DMLOW_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14280 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
<> 144:ef7eb2e8f9f7 14281 #define USB_OTGCTL_DPLOW_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14282 #define USB_OTGCTL_DPLOW_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14283 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
<> 144:ef7eb2e8f9f7 14284 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14285 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14286 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
<> 144:ef7eb2e8f9f7 14287
<> 144:ef7eb2e8f9f7 14288 /*! @name ISTAT - Interrupt Status register */
<> 144:ef7eb2e8f9f7 14289 #define USB_ISTAT_USBRST_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14290 #define USB_ISTAT_USBRST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14291 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
<> 144:ef7eb2e8f9f7 14292 #define USB_ISTAT_ERROR_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14293 #define USB_ISTAT_ERROR_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14294 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
<> 144:ef7eb2e8f9f7 14295 #define USB_ISTAT_SOFTOK_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14296 #define USB_ISTAT_SOFTOK_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14297 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
<> 144:ef7eb2e8f9f7 14298 #define USB_ISTAT_TOKDNE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14299 #define USB_ISTAT_TOKDNE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14300 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
<> 144:ef7eb2e8f9f7 14301 #define USB_ISTAT_SLEEP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14302 #define USB_ISTAT_SLEEP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14303 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
<> 144:ef7eb2e8f9f7 14304 #define USB_ISTAT_RESUME_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14305 #define USB_ISTAT_RESUME_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14306 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
<> 144:ef7eb2e8f9f7 14307 #define USB_ISTAT_ATTACH_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14308 #define USB_ISTAT_ATTACH_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14309 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
<> 144:ef7eb2e8f9f7 14310 #define USB_ISTAT_STALL_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14311 #define USB_ISTAT_STALL_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14312 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
<> 144:ef7eb2e8f9f7 14313
<> 144:ef7eb2e8f9f7 14314 /*! @name INTEN - Interrupt Enable register */
<> 144:ef7eb2e8f9f7 14315 #define USB_INTEN_USBRSTEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14316 #define USB_INTEN_USBRSTEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14317 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
<> 144:ef7eb2e8f9f7 14318 #define USB_INTEN_ERROREN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14319 #define USB_INTEN_ERROREN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14320 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
<> 144:ef7eb2e8f9f7 14321 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14322 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14323 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
<> 144:ef7eb2e8f9f7 14324 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14325 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14326 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
<> 144:ef7eb2e8f9f7 14327 #define USB_INTEN_SLEEPEN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14328 #define USB_INTEN_SLEEPEN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14329 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
<> 144:ef7eb2e8f9f7 14330 #define USB_INTEN_RESUMEEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14331 #define USB_INTEN_RESUMEEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14332 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
<> 144:ef7eb2e8f9f7 14333 #define USB_INTEN_ATTACHEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14334 #define USB_INTEN_ATTACHEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14335 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
<> 144:ef7eb2e8f9f7 14336 #define USB_INTEN_STALLEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14337 #define USB_INTEN_STALLEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14338 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
<> 144:ef7eb2e8f9f7 14339
<> 144:ef7eb2e8f9f7 14340 /*! @name ERRSTAT - Error Interrupt Status register */
<> 144:ef7eb2e8f9f7 14341 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14342 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14343 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
<> 144:ef7eb2e8f9f7 14344 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14345 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14346 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
<> 144:ef7eb2e8f9f7 14347 #define USB_ERRSTAT_CRC16_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14348 #define USB_ERRSTAT_CRC16_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14349 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
<> 144:ef7eb2e8f9f7 14350 #define USB_ERRSTAT_DFN8_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14351 #define USB_ERRSTAT_DFN8_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14352 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
<> 144:ef7eb2e8f9f7 14353 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14354 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14355 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
<> 144:ef7eb2e8f9f7 14356 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14357 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14358 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
<> 144:ef7eb2e8f9f7 14359 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14360 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14361 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
<> 144:ef7eb2e8f9f7 14362
<> 144:ef7eb2e8f9f7 14363 /*! @name ERREN - Error Interrupt Enable register */
<> 144:ef7eb2e8f9f7 14364 #define USB_ERREN_PIDERREN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14365 #define USB_ERREN_PIDERREN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14366 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
<> 144:ef7eb2e8f9f7 14367 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14368 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14369 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
<> 144:ef7eb2e8f9f7 14370 #define USB_ERREN_CRC16EN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14371 #define USB_ERREN_CRC16EN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14372 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
<> 144:ef7eb2e8f9f7 14373 #define USB_ERREN_DFN8EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14374 #define USB_ERREN_DFN8EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14375 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
<> 144:ef7eb2e8f9f7 14376 #define USB_ERREN_BTOERREN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14377 #define USB_ERREN_BTOERREN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14378 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
<> 144:ef7eb2e8f9f7 14379 #define USB_ERREN_DMAERREN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14380 #define USB_ERREN_DMAERREN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14381 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
<> 144:ef7eb2e8f9f7 14382 #define USB_ERREN_BTSERREN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14383 #define USB_ERREN_BTSERREN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14384 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
<> 144:ef7eb2e8f9f7 14385
<> 144:ef7eb2e8f9f7 14386 /*! @name STAT - Status register */
<> 144:ef7eb2e8f9f7 14387 #define USB_STAT_ODD_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14388 #define USB_STAT_ODD_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14389 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
<> 144:ef7eb2e8f9f7 14390 #define USB_STAT_TX_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14391 #define USB_STAT_TX_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14392 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
<> 144:ef7eb2e8f9f7 14393 #define USB_STAT_ENDP_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 14394 #define USB_STAT_ENDP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14395 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
<> 144:ef7eb2e8f9f7 14396
<> 144:ef7eb2e8f9f7 14397 /*! @name CTL - Control register */
<> 144:ef7eb2e8f9f7 14398 #define USB_CTL_USBENSOFEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14399 #define USB_CTL_USBENSOFEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14400 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
<> 144:ef7eb2e8f9f7 14401 #define USB_CTL_ODDRST_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14402 #define USB_CTL_ODDRST_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14403 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
<> 144:ef7eb2e8f9f7 14404 #define USB_CTL_RESUME_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14405 #define USB_CTL_RESUME_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14406 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
<> 144:ef7eb2e8f9f7 14407 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14408 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14409 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
<> 144:ef7eb2e8f9f7 14410 #define USB_CTL_RESET_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14411 #define USB_CTL_RESET_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14412 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
<> 144:ef7eb2e8f9f7 14413 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14414 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14415 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
<> 144:ef7eb2e8f9f7 14416 #define USB_CTL_SE0_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14417 #define USB_CTL_SE0_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14418 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
<> 144:ef7eb2e8f9f7 14419 #define USB_CTL_JSTATE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14420 #define USB_CTL_JSTATE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14421 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
<> 144:ef7eb2e8f9f7 14422
<> 144:ef7eb2e8f9f7 14423 /*! @name ADDR - Address register */
<> 144:ef7eb2e8f9f7 14424 #define USB_ADDR_ADDR_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 14425 #define USB_ADDR_ADDR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14426 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
<> 144:ef7eb2e8f9f7 14427 #define USB_ADDR_LSEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14428 #define USB_ADDR_LSEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14429 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
<> 144:ef7eb2e8f9f7 14430
<> 144:ef7eb2e8f9f7 14431 /*! @name BDTPAGE1 - BDT Page register 1 */
<> 144:ef7eb2e8f9f7 14432 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
<> 144:ef7eb2e8f9f7 14433 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14434 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
<> 144:ef7eb2e8f9f7 14435
<> 144:ef7eb2e8f9f7 14436 /*! @name FRMNUML - Frame Number register Low */
<> 144:ef7eb2e8f9f7 14437 #define USB_FRMNUML_FRM_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14438 #define USB_FRMNUML_FRM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14439 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
<> 144:ef7eb2e8f9f7 14440
<> 144:ef7eb2e8f9f7 14441 /*! @name FRMNUMH - Frame Number register High */
<> 144:ef7eb2e8f9f7 14442 #define USB_FRMNUMH_FRM_MASK (0x7U)
<> 144:ef7eb2e8f9f7 14443 #define USB_FRMNUMH_FRM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14444 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
<> 144:ef7eb2e8f9f7 14445
<> 144:ef7eb2e8f9f7 14446 /*! @name TOKEN - Token register */
<> 144:ef7eb2e8f9f7 14447 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
<> 144:ef7eb2e8f9f7 14448 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14449 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
<> 144:ef7eb2e8f9f7 14450 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 14451 #define USB_TOKEN_TOKENPID_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14452 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
<> 144:ef7eb2e8f9f7 14453
<> 144:ef7eb2e8f9f7 14454 /*! @name SOFTHLD - SOF Threshold register */
<> 144:ef7eb2e8f9f7 14455 #define USB_SOFTHLD_CNT_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14456 #define USB_SOFTHLD_CNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14457 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
<> 144:ef7eb2e8f9f7 14458
<> 144:ef7eb2e8f9f7 14459 /*! @name BDTPAGE2 - BDT Page Register 2 */
<> 144:ef7eb2e8f9f7 14460 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14461 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14462 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
<> 144:ef7eb2e8f9f7 14463
<> 144:ef7eb2e8f9f7 14464 /*! @name BDTPAGE3 - BDT Page Register 3 */
<> 144:ef7eb2e8f9f7 14465 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14466 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14467 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
<> 144:ef7eb2e8f9f7 14468
<> 144:ef7eb2e8f9f7 14469 /*! @name ENDPT - Endpoint Control register */
<> 144:ef7eb2e8f9f7 14470 #define USB_ENDPT_EPHSHK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14471 #define USB_ENDPT_EPHSHK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14472 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
<> 144:ef7eb2e8f9f7 14473 #define USB_ENDPT_EPSTALL_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14474 #define USB_ENDPT_EPSTALL_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14475 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
<> 144:ef7eb2e8f9f7 14476 #define USB_ENDPT_EPTXEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14477 #define USB_ENDPT_EPTXEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14478 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
<> 144:ef7eb2e8f9f7 14479 #define USB_ENDPT_EPRXEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 14480 #define USB_ENDPT_EPRXEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 14481 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
<> 144:ef7eb2e8f9f7 14482 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14483 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14484 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
<> 144:ef7eb2e8f9f7 14485 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14486 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14487 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
<> 144:ef7eb2e8f9f7 14488 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14489 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14490 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
<> 144:ef7eb2e8f9f7 14491
<> 144:ef7eb2e8f9f7 14492 /* The count of USB_ENDPT */
<> 144:ef7eb2e8f9f7 14493 #define USB_ENDPT_COUNT (16U)
<> 144:ef7eb2e8f9f7 14494
<> 144:ef7eb2e8f9f7 14495 /*! @name USBCTRL - USB Control register */
<> 144:ef7eb2e8f9f7 14496 #define USB_USBCTRL_PDE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14497 #define USB_USBCTRL_PDE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14498 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
<> 144:ef7eb2e8f9f7 14499 #define USB_USBCTRL_SUSP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14500 #define USB_USBCTRL_SUSP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14501 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
<> 144:ef7eb2e8f9f7 14502
<> 144:ef7eb2e8f9f7 14503 /*! @name OBSERVE - USB OTG Observe register */
<> 144:ef7eb2e8f9f7 14504 #define USB_OBSERVE_DMPD_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14505 #define USB_OBSERVE_DMPD_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14506 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
<> 144:ef7eb2e8f9f7 14507 #define USB_OBSERVE_DPPD_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14508 #define USB_OBSERVE_DPPD_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14509 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
<> 144:ef7eb2e8f9f7 14510 #define USB_OBSERVE_DPPU_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14511 #define USB_OBSERVE_DPPU_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14512 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
<> 144:ef7eb2e8f9f7 14513
<> 144:ef7eb2e8f9f7 14514 /*! @name CONTROL - USB OTG Control register */
<> 144:ef7eb2e8f9f7 14515 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14516 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14517 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
<> 144:ef7eb2e8f9f7 14518
<> 144:ef7eb2e8f9f7 14519 /*! @name USBTRC0 - USB Transceiver Control register 0 */
<> 144:ef7eb2e8f9f7 14520 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14521 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14522 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
<> 144:ef7eb2e8f9f7 14523 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14524 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14525 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
<> 144:ef7eb2e8f9f7 14526 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14527 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14528 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
<> 144:ef7eb2e8f9f7 14529 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14530 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14531 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
<> 144:ef7eb2e8f9f7 14532 #define USB_USBTRC0_USBRESET_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14533 #define USB_USBTRC0_USBRESET_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14534 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
<> 144:ef7eb2e8f9f7 14535
<> 144:ef7eb2e8f9f7 14536 /*! @name USBFRMADJUST - Frame Adjust Register */
<> 144:ef7eb2e8f9f7 14537 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14538 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14539 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
<> 144:ef7eb2e8f9f7 14540
<> 144:ef7eb2e8f9f7 14541 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
<> 144:ef7eb2e8f9f7 14542 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 14543 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 14544 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
<> 144:ef7eb2e8f9f7 14545 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 14546 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14547 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
<> 144:ef7eb2e8f9f7 14548 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14549 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14550 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
<> 144:ef7eb2e8f9f7 14551
<> 144:ef7eb2e8f9f7 14552 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
<> 144:ef7eb2e8f9f7 14553 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14554 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14555 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
<> 144:ef7eb2e8f9f7 14556 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14557 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14558 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
<> 144:ef7eb2e8f9f7 14559
<> 144:ef7eb2e8f9f7 14560 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
<> 144:ef7eb2e8f9f7 14561 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14562 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14563 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
<> 144:ef7eb2e8f9f7 14564
<> 144:ef7eb2e8f9f7 14565 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
<> 144:ef7eb2e8f9f7 14566 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14567 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14568 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
<> 144:ef7eb2e8f9f7 14569
<> 144:ef7eb2e8f9f7 14570
<> 144:ef7eb2e8f9f7 14571 /*!
<> 144:ef7eb2e8f9f7 14572 * @}
<> 144:ef7eb2e8f9f7 14573 */ /* end of group USB_Register_Masks */
<> 144:ef7eb2e8f9f7 14574
<> 144:ef7eb2e8f9f7 14575
<> 144:ef7eb2e8f9f7 14576 /* USB - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 14577 /** Peripheral USB0 base address */
<> 144:ef7eb2e8f9f7 14578 #define USB0_BASE (0x40072000u)
<> 144:ef7eb2e8f9f7 14579 /** Peripheral USB0 base pointer */
<> 144:ef7eb2e8f9f7 14580 #define USB0 ((USB_Type *)USB0_BASE)
<> 144:ef7eb2e8f9f7 14581 /** Array initializer of USB peripheral base addresses */
<> 144:ef7eb2e8f9f7 14582 #define USB_BASE_ADDRS { USB0_BASE }
<> 144:ef7eb2e8f9f7 14583 /** Array initializer of USB peripheral base pointers */
<> 144:ef7eb2e8f9f7 14584 #define USB_BASE_PTRS { USB0 }
<> 144:ef7eb2e8f9f7 14585 /** Interrupt vectors for the USB peripheral type */
<> 144:ef7eb2e8f9f7 14586 #define USB_IRQS { USB0_IRQn }
<> 144:ef7eb2e8f9f7 14587
<> 144:ef7eb2e8f9f7 14588 /*!
<> 144:ef7eb2e8f9f7 14589 * @}
<> 144:ef7eb2e8f9f7 14590 */ /* end of group USB_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 14591
<> 144:ef7eb2e8f9f7 14592
<> 144:ef7eb2e8f9f7 14593 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14594 -- USBDCD Peripheral Access Layer
<> 144:ef7eb2e8f9f7 14595 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 14596
<> 144:ef7eb2e8f9f7 14597 /*!
<> 144:ef7eb2e8f9f7 14598 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
<> 144:ef7eb2e8f9f7 14599 * @{
<> 144:ef7eb2e8f9f7 14600 */
<> 144:ef7eb2e8f9f7 14601
<> 144:ef7eb2e8f9f7 14602 /** USBDCD - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 14603 typedef struct {
<> 144:ef7eb2e8f9f7 14604 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 14605 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 14606 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 14607 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 14608 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 14609 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 14610 union { /* offset: 0x18 */
<> 144:ef7eb2e8f9f7 14611 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 14612 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 14613 };
<> 144:ef7eb2e8f9f7 14614 } USBDCD_Type;
<> 144:ef7eb2e8f9f7 14615
<> 144:ef7eb2e8f9f7 14616 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14617 -- USBDCD Register Masks
<> 144:ef7eb2e8f9f7 14618 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 14619
<> 144:ef7eb2e8f9f7 14620 /*!
<> 144:ef7eb2e8f9f7 14621 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
<> 144:ef7eb2e8f9f7 14622 * @{
<> 144:ef7eb2e8f9f7 14623 */
<> 144:ef7eb2e8f9f7 14624
<> 144:ef7eb2e8f9f7 14625 /*! @name CONTROL - Control register */
<> 144:ef7eb2e8f9f7 14626 #define USBDCD_CONTROL_IACK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14627 #define USBDCD_CONTROL_IACK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14628 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
<> 144:ef7eb2e8f9f7 14629 #define USBDCD_CONTROL_IF_MASK (0x100U)
<> 144:ef7eb2e8f9f7 14630 #define USBDCD_CONTROL_IF_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14631 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
<> 144:ef7eb2e8f9f7 14632 #define USBDCD_CONTROL_IE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 14633 #define USBDCD_CONTROL_IE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14634 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
<> 144:ef7eb2e8f9f7 14635 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 14636 #define USBDCD_CONTROL_BC12_SHIFT (17U)
<> 144:ef7eb2e8f9f7 14637 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
<> 144:ef7eb2e8f9f7 14638 #define USBDCD_CONTROL_START_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 14639 #define USBDCD_CONTROL_START_SHIFT (24U)
<> 144:ef7eb2e8f9f7 14640 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
<> 144:ef7eb2e8f9f7 14641 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 14642 #define USBDCD_CONTROL_SR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 14643 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
<> 144:ef7eb2e8f9f7 14644
<> 144:ef7eb2e8f9f7 14645 /*! @name CLOCK - Clock register */
<> 144:ef7eb2e8f9f7 14646 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14647 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14648 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
<> 144:ef7eb2e8f9f7 14649 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
<> 144:ef7eb2e8f9f7 14650 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14651 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
<> 144:ef7eb2e8f9f7 14652
<> 144:ef7eb2e8f9f7 14653 /*! @name STATUS - Status register */
<> 144:ef7eb2e8f9f7 14654 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 14655 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14656 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
<> 144:ef7eb2e8f9f7 14657 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 14658 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 14659 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
<> 144:ef7eb2e8f9f7 14660 #define USBDCD_STATUS_ERR_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 14661 #define USBDCD_STATUS_ERR_SHIFT (20U)
<> 144:ef7eb2e8f9f7 14662 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
<> 144:ef7eb2e8f9f7 14663 #define USBDCD_STATUS_TO_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 14664 #define USBDCD_STATUS_TO_SHIFT (21U)
<> 144:ef7eb2e8f9f7 14665 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
<> 144:ef7eb2e8f9f7 14666 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 14667 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
<> 144:ef7eb2e8f9f7 14668 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
<> 144:ef7eb2e8f9f7 14669
<> 144:ef7eb2e8f9f7 14670 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
<> 144:ef7eb2e8f9f7 14671 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 14672 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14673 #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
<> 144:ef7eb2e8f9f7 14674
<> 144:ef7eb2e8f9f7 14675 /*! @name TIMER0 - TIMER0 register */
<> 144:ef7eb2e8f9f7 14676 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
<> 144:ef7eb2e8f9f7 14677 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14678 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
<> 144:ef7eb2e8f9f7 14679 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 14680 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14681 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
<> 144:ef7eb2e8f9f7 14682
<> 144:ef7eb2e8f9f7 14683 /*! @name TIMER1 - TIMER1 register */
<> 144:ef7eb2e8f9f7 14684 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 14685 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14686 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
<> 144:ef7eb2e8f9f7 14687 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 14688 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14689 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
<> 144:ef7eb2e8f9f7 14690
<> 144:ef7eb2e8f9f7 14691 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
<> 144:ef7eb2e8f9f7 14692 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
<> 144:ef7eb2e8f9f7 14693 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14694 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
<> 144:ef7eb2e8f9f7 14695 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 14696 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14697 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
<> 144:ef7eb2e8f9f7 14698
<> 144:ef7eb2e8f9f7 14699 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
<> 144:ef7eb2e8f9f7 14700 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 14701 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14702 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
<> 144:ef7eb2e8f9f7 14703 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 14704 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14705 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
<> 144:ef7eb2e8f9f7 14706
<> 144:ef7eb2e8f9f7 14707
<> 144:ef7eb2e8f9f7 14708 /*!
<> 144:ef7eb2e8f9f7 14709 * @}
<> 144:ef7eb2e8f9f7 14710 */ /* end of group USBDCD_Register_Masks */
<> 144:ef7eb2e8f9f7 14711
<> 144:ef7eb2e8f9f7 14712
<> 144:ef7eb2e8f9f7 14713 /* USBDCD - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 14714 /** Peripheral USBDCD base address */
<> 144:ef7eb2e8f9f7 14715 #define USBDCD_BASE (0x40035000u)
<> 144:ef7eb2e8f9f7 14716 /** Peripheral USBDCD base pointer */
<> 144:ef7eb2e8f9f7 14717 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
<> 144:ef7eb2e8f9f7 14718 /** Array initializer of USBDCD peripheral base addresses */
<> 144:ef7eb2e8f9f7 14719 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
<> 144:ef7eb2e8f9f7 14720 /** Array initializer of USBDCD peripheral base pointers */
<> 144:ef7eb2e8f9f7 14721 #define USBDCD_BASE_PTRS { USBDCD }
<> 144:ef7eb2e8f9f7 14722 /** Interrupt vectors for the USBDCD peripheral type */
<> 144:ef7eb2e8f9f7 14723 #define USBDCD_IRQS { USBDCD_IRQn }
<> 144:ef7eb2e8f9f7 14724
<> 144:ef7eb2e8f9f7 14725 /*!
<> 144:ef7eb2e8f9f7 14726 * @}
<> 144:ef7eb2e8f9f7 14727 */ /* end of group USBDCD_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 14728
<> 144:ef7eb2e8f9f7 14729
<> 144:ef7eb2e8f9f7 14730 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14731 -- USBHS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 14732 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 14733
<> 144:ef7eb2e8f9f7 14734 /*!
<> 144:ef7eb2e8f9f7 14735 * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer
<> 144:ef7eb2e8f9f7 14736 * @{
<> 144:ef7eb2e8f9f7 14737 */
<> 144:ef7eb2e8f9f7 14738
<> 144:ef7eb2e8f9f7 14739 /** USBHS - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 14740 typedef struct {
<> 144:ef7eb2e8f9f7 14741 __I uint32_t ID; /**< Identification Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 14742 __I uint32_t HWGENERAL; /**< General Hardware Parameters Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 14743 __I uint32_t HWHOST; /**< Host Hardware Parameters Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 14744 __I uint32_t HWDEVICE; /**< Device Hardware Parameters Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 14745 __I uint32_t HWTXBUF; /**< Transmit Buffer Hardware Parameters Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 14746 __I uint32_t HWRXBUF; /**< Receive Buffer Hardware Parameters Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 14747 uint8_t RESERVED_0[104];
<> 144:ef7eb2e8f9f7 14748 __IO uint32_t GPTIMER0LD; /**< General Purpose Timer n Load Register, offset: 0x80 */
<> 144:ef7eb2e8f9f7 14749 __IO uint32_t GPTIMER0CTL; /**< General Purpose Timer n Control Register, offset: 0x84 */
<> 144:ef7eb2e8f9f7 14750 __IO uint32_t GPTIMER1LD; /**< General Purpose Timer n Load Register, offset: 0x88 */
<> 144:ef7eb2e8f9f7 14751 __IO uint32_t GPTIMER1CTL; /**< General Purpose Timer n Control Register, offset: 0x8C */
<> 144:ef7eb2e8f9f7 14752 __IO uint32_t USB_SBUSCFG; /**< System Bus Interface Configuration Register, offset: 0x90 */
<> 144:ef7eb2e8f9f7 14753 uint8_t RESERVED_1[108];
<> 144:ef7eb2e8f9f7 14754 __I uint32_t HCIVERSION; /**< Host Controller Interface Version and Capability Registers Length Register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 14755 __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters Register, offset: 0x104 */
<> 144:ef7eb2e8f9f7 14756 __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters Register, offset: 0x108 */
<> 144:ef7eb2e8f9f7 14757 uint8_t RESERVED_2[22];
<> 144:ef7eb2e8f9f7 14758 __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x122 */
<> 144:ef7eb2e8f9f7 14759 __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
<> 144:ef7eb2e8f9f7 14760 uint8_t RESERVED_3[24];
<> 144:ef7eb2e8f9f7 14761 __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
<> 144:ef7eb2e8f9f7 14762 __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
<> 144:ef7eb2e8f9f7 14763 __IO uint32_t USBINTR; /**< USB Interrupt Enable Register, offset: 0x148 */
<> 144:ef7eb2e8f9f7 14764 __IO uint32_t FRINDEX; /**< Frame Index Register, offset: 0x14C */
<> 144:ef7eb2e8f9f7 14765 uint8_t RESERVED_4[4];
<> 144:ef7eb2e8f9f7 14766 union { /* offset: 0x154 */
<> 144:ef7eb2e8f9f7 14767 __IO uint32_t DEVICEADDR; /**< Device Address Register, offset: 0x154 */
<> 144:ef7eb2e8f9f7 14768 __IO uint32_t PERIODICLISTBASE; /**< Periodic Frame List Base Address Register, offset: 0x154 */
<> 144:ef7eb2e8f9f7 14769 };
<> 144:ef7eb2e8f9f7 14770 union { /* offset: 0x158 */
<> 144:ef7eb2e8f9f7 14771 __IO uint32_t ASYNCLISTADDR; /**< Current Asynchronous List Address Register, offset: 0x158 */
<> 144:ef7eb2e8f9f7 14772 __IO uint32_t EPLISTADDR; /**< Endpoint List Address Register, offset: 0x158 */
<> 144:ef7eb2e8f9f7 14773 };
<> 144:ef7eb2e8f9f7 14774 __I uint32_t TTCTRL; /**< Host TT Asynchronous Buffer Control, offset: 0x15C */
<> 144:ef7eb2e8f9f7 14775 __IO uint32_t BURSTSIZE; /**< Master Interface Data Burst Size Register, offset: 0x160 */
<> 144:ef7eb2e8f9f7 14776 __IO uint32_t TXFILLTUNING; /**< Transmit FIFO Tuning Control Register, offset: 0x164 */
<> 144:ef7eb2e8f9f7 14777 uint8_t RESERVED_5[16];
<> 144:ef7eb2e8f9f7 14778 __IO uint32_t ENDPTNAK; /**< Endpoint NAK Register, offset: 0x178 */
<> 144:ef7eb2e8f9f7 14779 __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable Register, offset: 0x17C */
<> 144:ef7eb2e8f9f7 14780 __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
<> 144:ef7eb2e8f9f7 14781 __IO uint32_t PORTSC1; /**< Port Status and Control Registers, offset: 0x184 */
<> 144:ef7eb2e8f9f7 14782 uint8_t RESERVED_6[28];
<> 144:ef7eb2e8f9f7 14783 __IO uint32_t OTGSC; /**< On-the-Go Status and Control Register, offset: 0x1A4 */
<> 144:ef7eb2e8f9f7 14784 __IO uint32_t USBMODE; /**< USB Mode Register, offset: 0x1A8 */
<> 144:ef7eb2e8f9f7 14785 __IO uint32_t EPSETUPSR; /**< Endpoint Setup Status Register, offset: 0x1AC */
<> 144:ef7eb2e8f9f7 14786 __IO uint32_t EPPRIME; /**< Endpoint Initialization Register, offset: 0x1B0 */
<> 144:ef7eb2e8f9f7 14787 __IO uint32_t EPFLUSH; /**< Endpoint Flush Register, offset: 0x1B4 */
<> 144:ef7eb2e8f9f7 14788 __I uint32_t EPSR; /**< Endpoint Status Register, offset: 0x1B8 */
<> 144:ef7eb2e8f9f7 14789 __IO uint32_t EPCOMPLETE; /**< Endpoint Complete Register, offset: 0x1BC */
<> 144:ef7eb2e8f9f7 14790 __IO uint32_t EPCR0; /**< Endpoint Control Register 0, offset: 0x1C0 */
<> 144:ef7eb2e8f9f7 14791 __IO uint32_t EPCR[7]; /**< Endpoint Control Register n, array offset: 0x1C4, array step: 0x4 */
<> 144:ef7eb2e8f9f7 14792 uint8_t RESERVED_7[32];
<> 144:ef7eb2e8f9f7 14793 __IO uint32_t USBGENCTRL; /**< USB General Control Register, offset: 0x200 */
<> 144:ef7eb2e8f9f7 14794 } USBHS_Type;
<> 144:ef7eb2e8f9f7 14795
<> 144:ef7eb2e8f9f7 14796 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14797 -- USBHS Register Masks
<> 144:ef7eb2e8f9f7 14798 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 14799
<> 144:ef7eb2e8f9f7 14800 /*!
<> 144:ef7eb2e8f9f7 14801 * @addtogroup USBHS_Register_Masks USBHS Register Masks
<> 144:ef7eb2e8f9f7 14802 * @{
<> 144:ef7eb2e8f9f7 14803 */
<> 144:ef7eb2e8f9f7 14804
<> 144:ef7eb2e8f9f7 14805 /*! @name ID - Identification Register */
<> 144:ef7eb2e8f9f7 14806 #define USBHS_ID_ID_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 14807 #define USBHS_ID_ID_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14808 #define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
<> 144:ef7eb2e8f9f7 14809 #define USBHS_ID_NID_MASK (0x3F00U)
<> 144:ef7eb2e8f9f7 14810 #define USBHS_ID_NID_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14811 #define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
<> 144:ef7eb2e8f9f7 14812 #define USBHS_ID_TAG_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 14813 #define USBHS_ID_TAG_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14814 #define USBHS_ID_TAG(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
<> 144:ef7eb2e8f9f7 14815 #define USBHS_ID_REVISION_MASK (0x1E00000U)
<> 144:ef7eb2e8f9f7 14816 #define USBHS_ID_REVISION_SHIFT (21U)
<> 144:ef7eb2e8f9f7 14817 #define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
<> 144:ef7eb2e8f9f7 14818 #define USBHS_ID_VERSION_MASK (0x1E000000U)
<> 144:ef7eb2e8f9f7 14819 #define USBHS_ID_VERSION_SHIFT (25U)
<> 144:ef7eb2e8f9f7 14820 #define USBHS_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
<> 144:ef7eb2e8f9f7 14821 #define USBHS_ID_VERSIONID_MASK (0xE0000000U)
<> 144:ef7eb2e8f9f7 14822 #define USBHS_ID_VERSIONID_SHIFT (29U)
<> 144:ef7eb2e8f9f7 14823 #define USBHS_ID_VERSIONID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
<> 144:ef7eb2e8f9f7 14824
<> 144:ef7eb2e8f9f7 14825 /*! @name HWGENERAL - General Hardware Parameters Register */
<> 144:ef7eb2e8f9f7 14826 #define USBHS_HWGENERAL_PHYW_MASK (0x30U)
<> 144:ef7eb2e8f9f7 14827 #define USBHS_HWGENERAL_PHYW_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14828 #define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
<> 144:ef7eb2e8f9f7 14829 #define USBHS_HWGENERAL_PHYM_MASK (0x1C0U)
<> 144:ef7eb2e8f9f7 14830 #define USBHS_HWGENERAL_PHYM_SHIFT (6U)
<> 144:ef7eb2e8f9f7 14831 #define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
<> 144:ef7eb2e8f9f7 14832 #define USBHS_HWGENERAL_SM_MASK (0x600U)
<> 144:ef7eb2e8f9f7 14833 #define USBHS_HWGENERAL_SM_SHIFT (9U)
<> 144:ef7eb2e8f9f7 14834 #define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
<> 144:ef7eb2e8f9f7 14835
<> 144:ef7eb2e8f9f7 14836 /*! @name HWHOST - Host Hardware Parameters Register */
<> 144:ef7eb2e8f9f7 14837 #define USBHS_HWHOST_HC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14838 #define USBHS_HWHOST_HC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14839 #define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
<> 144:ef7eb2e8f9f7 14840 #define USBHS_HWHOST_NPORT_MASK (0xEU)
<> 144:ef7eb2e8f9f7 14841 #define USBHS_HWHOST_NPORT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14842 #define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
<> 144:ef7eb2e8f9f7 14843 #define USBHS_HWHOST_TTASY_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 14844 #define USBHS_HWHOST_TTASY_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14845 #define USBHS_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
<> 144:ef7eb2e8f9f7 14846 #define USBHS_HWHOST_TTPER_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 14847 #define USBHS_HWHOST_TTPER_SHIFT (24U)
<> 144:ef7eb2e8f9f7 14848 #define USBHS_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
<> 144:ef7eb2e8f9f7 14849
<> 144:ef7eb2e8f9f7 14850 /*! @name HWDEVICE - Device Hardware Parameters Register */
<> 144:ef7eb2e8f9f7 14851 #define USBHS_HWDEVICE_DC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14852 #define USBHS_HWDEVICE_DC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14853 #define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
<> 144:ef7eb2e8f9f7 14854 #define USBHS_HWDEVICE_DEVEP_MASK (0x3EU)
<> 144:ef7eb2e8f9f7 14855 #define USBHS_HWDEVICE_DEVEP_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14856 #define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
<> 144:ef7eb2e8f9f7 14857
<> 144:ef7eb2e8f9f7 14858 /*! @name HWTXBUF - Transmit Buffer Hardware Parameters Register */
<> 144:ef7eb2e8f9f7 14859 #define USBHS_HWTXBUF_TXBURST_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14860 #define USBHS_HWTXBUF_TXBURST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14861 #define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
<> 144:ef7eb2e8f9f7 14862 #define USBHS_HWTXBUF_TXADD_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 14863 #define USBHS_HWTXBUF_TXADD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14864 #define USBHS_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
<> 144:ef7eb2e8f9f7 14865 #define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 14866 #define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14867 #define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
<> 144:ef7eb2e8f9f7 14868 #define USBHS_HWTXBUF_TXLC_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 14869 #define USBHS_HWTXBUF_TXLC_SHIFT (31U)
<> 144:ef7eb2e8f9f7 14870 #define USBHS_HWTXBUF_TXLC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
<> 144:ef7eb2e8f9f7 14871
<> 144:ef7eb2e8f9f7 14872 /*! @name HWRXBUF - Receive Buffer Hardware Parameters Register */
<> 144:ef7eb2e8f9f7 14873 #define USBHS_HWRXBUF_RXBURST_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14874 #define USBHS_HWRXBUF_RXBURST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14875 #define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
<> 144:ef7eb2e8f9f7 14876 #define USBHS_HWRXBUF_RXADD_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 14877 #define USBHS_HWRXBUF_RXADD_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14878 #define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
<> 144:ef7eb2e8f9f7 14879
<> 144:ef7eb2e8f9f7 14880 /*! @name GPTIMER0LD - General Purpose Timer n Load Register */
<> 144:ef7eb2e8f9f7 14881 #define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
<> 144:ef7eb2e8f9f7 14882 #define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14883 #define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
<> 144:ef7eb2e8f9f7 14884
<> 144:ef7eb2e8f9f7 14885 /*! @name GPTIMER0CTL - General Purpose Timer n Control Register */
<> 144:ef7eb2e8f9f7 14886 #define USBHS_GPTIMER0CTL_GPTCNT_MASK (0xFFFFFFU)
<> 144:ef7eb2e8f9f7 14887 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14888 #define USBHS_GPTIMER0CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
<> 144:ef7eb2e8f9f7 14889 #define USBHS_GPTIMER0CTL_MODE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 14890 #define USBHS_GPTIMER0CTL_MODE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 14891 #define USBHS_GPTIMER0CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
<> 144:ef7eb2e8f9f7 14892 #define USBHS_GPTIMER0CTL_RST_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 14893 #define USBHS_GPTIMER0CTL_RST_SHIFT (30U)
<> 144:ef7eb2e8f9f7 14894 #define USBHS_GPTIMER0CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
<> 144:ef7eb2e8f9f7 14895 #define USBHS_GPTIMER0CTL_RUN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 14896 #define USBHS_GPTIMER0CTL_RUN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 14897 #define USBHS_GPTIMER0CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
<> 144:ef7eb2e8f9f7 14898
<> 144:ef7eb2e8f9f7 14899 /*! @name GPTIMER1LD - General Purpose Timer n Load Register */
<> 144:ef7eb2e8f9f7 14900 #define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
<> 144:ef7eb2e8f9f7 14901 #define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14902 #define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
<> 144:ef7eb2e8f9f7 14903
<> 144:ef7eb2e8f9f7 14904 /*! @name GPTIMER1CTL - General Purpose Timer n Control Register */
<> 144:ef7eb2e8f9f7 14905 #define USBHS_GPTIMER1CTL_GPTCNT_MASK (0xFFFFFFU)
<> 144:ef7eb2e8f9f7 14906 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14907 #define USBHS_GPTIMER1CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
<> 144:ef7eb2e8f9f7 14908 #define USBHS_GPTIMER1CTL_MODE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 14909 #define USBHS_GPTIMER1CTL_MODE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 14910 #define USBHS_GPTIMER1CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
<> 144:ef7eb2e8f9f7 14911 #define USBHS_GPTIMER1CTL_RST_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 14912 #define USBHS_GPTIMER1CTL_RST_SHIFT (30U)
<> 144:ef7eb2e8f9f7 14913 #define USBHS_GPTIMER1CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
<> 144:ef7eb2e8f9f7 14914 #define USBHS_GPTIMER1CTL_RUN_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 14915 #define USBHS_GPTIMER1CTL_RUN_SHIFT (31U)
<> 144:ef7eb2e8f9f7 14916 #define USBHS_GPTIMER1CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
<> 144:ef7eb2e8f9f7 14917
<> 144:ef7eb2e8f9f7 14918 /*! @name USB_SBUSCFG - System Bus Interface Configuration Register */
<> 144:ef7eb2e8f9f7 14919 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7U)
<> 144:ef7eb2e8f9f7 14920 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14921 #define USBHS_USB_SBUSCFG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)
<> 144:ef7eb2e8f9f7 14922
<> 144:ef7eb2e8f9f7 14923 /*! @name HCIVERSION - Host Controller Interface Version and Capability Registers Length Register */
<> 144:ef7eb2e8f9f7 14924 #define USBHS_HCIVERSION_CAPLENGTH_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 14925 #define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14926 #define USBHS_HCIVERSION_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
<> 144:ef7eb2e8f9f7 14927 #define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 14928 #define USBHS_HCIVERSION_HCIVERSION_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14929 #define USBHS_HCIVERSION_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
<> 144:ef7eb2e8f9f7 14930
<> 144:ef7eb2e8f9f7 14931 /*! @name HCSPARAMS - Host Controller Structural Parameters Register */
<> 144:ef7eb2e8f9f7 14932 #define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU)
<> 144:ef7eb2e8f9f7 14933 #define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14934 #define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
<> 144:ef7eb2e8f9f7 14935 #define USBHS_HCSPARAMS_PPC_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14936 #define USBHS_HCSPARAMS_PPC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14937 #define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
<> 144:ef7eb2e8f9f7 14938 #define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 14939 #define USBHS_HCSPARAMS_N_PCC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14940 #define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
<> 144:ef7eb2e8f9f7 14941 #define USBHS_HCSPARAMS_N_CC_MASK (0xF000U)
<> 144:ef7eb2e8f9f7 14942 #define USBHS_HCSPARAMS_N_CC_SHIFT (12U)
<> 144:ef7eb2e8f9f7 14943 #define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
<> 144:ef7eb2e8f9f7 14944 #define USBHS_HCSPARAMS_PI_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 14945 #define USBHS_HCSPARAMS_PI_SHIFT (16U)
<> 144:ef7eb2e8f9f7 14946 #define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
<> 144:ef7eb2e8f9f7 14947 #define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 14948 #define USBHS_HCSPARAMS_N_PTT_SHIFT (20U)
<> 144:ef7eb2e8f9f7 14949 #define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
<> 144:ef7eb2e8f9f7 14950 #define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 14951 #define USBHS_HCSPARAMS_N_TT_SHIFT (24U)
<> 144:ef7eb2e8f9f7 14952 #define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
<> 144:ef7eb2e8f9f7 14953
<> 144:ef7eb2e8f9f7 14954 /*! @name HCCPARAMS - Host Controller Capability Parameters Register */
<> 144:ef7eb2e8f9f7 14955 #define USBHS_HCCPARAMS_ADC_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14956 #define USBHS_HCCPARAMS_ADC_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14957 #define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
<> 144:ef7eb2e8f9f7 14958 #define USBHS_HCCPARAMS_PFL_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14959 #define USBHS_HCCPARAMS_PFL_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14960 #define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
<> 144:ef7eb2e8f9f7 14961 #define USBHS_HCCPARAMS_ASP_MASK (0x4U)
<> 144:ef7eb2e8f9f7 14962 #define USBHS_HCCPARAMS_ASP_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14963 #define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
<> 144:ef7eb2e8f9f7 14964 #define USBHS_HCCPARAMS_IST_MASK (0xF0U)
<> 144:ef7eb2e8f9f7 14965 #define USBHS_HCCPARAMS_IST_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14966 #define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
<> 144:ef7eb2e8f9f7 14967 #define USBHS_HCCPARAMS_EECP_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 14968 #define USBHS_HCCPARAMS_EECP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14969 #define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
<> 144:ef7eb2e8f9f7 14970
<> 144:ef7eb2e8f9f7 14971 /*! @name DCIVERSION - Device Controller Interface Version */
<> 144:ef7eb2e8f9f7 14972 #define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 14973 #define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14974 #define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
<> 144:ef7eb2e8f9f7 14975
<> 144:ef7eb2e8f9f7 14976 /*! @name DCCPARAMS - Device Controller Capability Parameters */
<> 144:ef7eb2e8f9f7 14977 #define USBHS_DCCPARAMS_DEN_MASK (0x1FU)
<> 144:ef7eb2e8f9f7 14978 #define USBHS_DCCPARAMS_DEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14979 #define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
<> 144:ef7eb2e8f9f7 14980 #define USBHS_DCCPARAMS_DC_MASK (0x80U)
<> 144:ef7eb2e8f9f7 14981 #define USBHS_DCCPARAMS_DC_SHIFT (7U)
<> 144:ef7eb2e8f9f7 14982 #define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
<> 144:ef7eb2e8f9f7 14983 #define USBHS_DCCPARAMS_HC_MASK (0x100U)
<> 144:ef7eb2e8f9f7 14984 #define USBHS_DCCPARAMS_HC_SHIFT (8U)
<> 144:ef7eb2e8f9f7 14985 #define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
<> 144:ef7eb2e8f9f7 14986
<> 144:ef7eb2e8f9f7 14987 /*! @name USBCMD - USB Command Register */
<> 144:ef7eb2e8f9f7 14988 #define USBHS_USBCMD_RS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 14989 #define USBHS_USBCMD_RS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 14990 #define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
<> 144:ef7eb2e8f9f7 14991 #define USBHS_USBCMD_RST_MASK (0x2U)
<> 144:ef7eb2e8f9f7 14992 #define USBHS_USBCMD_RST_SHIFT (1U)
<> 144:ef7eb2e8f9f7 14993 #define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
<> 144:ef7eb2e8f9f7 14994 #define USBHS_USBCMD_FS_MASK (0xCU)
<> 144:ef7eb2e8f9f7 14995 #define USBHS_USBCMD_FS_SHIFT (2U)
<> 144:ef7eb2e8f9f7 14996 #define USBHS_USBCMD_FS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
<> 144:ef7eb2e8f9f7 14997 #define USBHS_USBCMD_PSE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 14998 #define USBHS_USBCMD_PSE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 14999 #define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
<> 144:ef7eb2e8f9f7 15000 #define USBHS_USBCMD_ASE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15001 #define USBHS_USBCMD_ASE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15002 #define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
<> 144:ef7eb2e8f9f7 15003 #define USBHS_USBCMD_IAA_MASK (0x40U)
<> 144:ef7eb2e8f9f7 15004 #define USBHS_USBCMD_IAA_SHIFT (6U)
<> 144:ef7eb2e8f9f7 15005 #define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
<> 144:ef7eb2e8f9f7 15006 #define USBHS_USBCMD_ASP_MASK (0x300U)
<> 144:ef7eb2e8f9f7 15007 #define USBHS_USBCMD_ASP_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15008 #define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
<> 144:ef7eb2e8f9f7 15009 #define USBHS_USBCMD_ASPE_MASK (0x800U)
<> 144:ef7eb2e8f9f7 15010 #define USBHS_USBCMD_ASPE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15011 #define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
<> 144:ef7eb2e8f9f7 15012 #define USBHS_USBCMD_SUTW_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 15013 #define USBHS_USBCMD_SUTW_SHIFT (13U)
<> 144:ef7eb2e8f9f7 15014 #define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
<> 144:ef7eb2e8f9f7 15015 #define USBHS_USBCMD_ATDTW_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 15016 #define USBHS_USBCMD_ATDTW_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15017 #define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
<> 144:ef7eb2e8f9f7 15018 #define USBHS_USBCMD_FS2_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 15019 #define USBHS_USBCMD_FS2_SHIFT (15U)
<> 144:ef7eb2e8f9f7 15020 #define USBHS_USBCMD_FS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
<> 144:ef7eb2e8f9f7 15021 #define USBHS_USBCMD_ITC_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 15022 #define USBHS_USBCMD_ITC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15023 #define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
<> 144:ef7eb2e8f9f7 15024
<> 144:ef7eb2e8f9f7 15025 /*! @name USBSTS - USB Status Register */
<> 144:ef7eb2e8f9f7 15026 #define USBHS_USBSTS_UI_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15027 #define USBHS_USBSTS_UI_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15028 #define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
<> 144:ef7eb2e8f9f7 15029 #define USBHS_USBSTS_UEI_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15030 #define USBHS_USBSTS_UEI_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15031 #define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
<> 144:ef7eb2e8f9f7 15032 #define USBHS_USBSTS_PCI_MASK (0x4U)
<> 144:ef7eb2e8f9f7 15033 #define USBHS_USBSTS_PCI_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15034 #define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
<> 144:ef7eb2e8f9f7 15035 #define USBHS_USBSTS_FRI_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15036 #define USBHS_USBSTS_FRI_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15037 #define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
<> 144:ef7eb2e8f9f7 15038 #define USBHS_USBSTS_SEI_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15039 #define USBHS_USBSTS_SEI_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15040 #define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
<> 144:ef7eb2e8f9f7 15041 #define USBHS_USBSTS_AAI_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15042 #define USBHS_USBSTS_AAI_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15043 #define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
<> 144:ef7eb2e8f9f7 15044 #define USBHS_USBSTS_URI_MASK (0x40U)
<> 144:ef7eb2e8f9f7 15045 #define USBHS_USBSTS_URI_SHIFT (6U)
<> 144:ef7eb2e8f9f7 15046 #define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
<> 144:ef7eb2e8f9f7 15047 #define USBHS_USBSTS_SRI_MASK (0x80U)
<> 144:ef7eb2e8f9f7 15048 #define USBHS_USBSTS_SRI_SHIFT (7U)
<> 144:ef7eb2e8f9f7 15049 #define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
<> 144:ef7eb2e8f9f7 15050 #define USBHS_USBSTS_SLI_MASK (0x100U)
<> 144:ef7eb2e8f9f7 15051 #define USBHS_USBSTS_SLI_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15052 #define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
<> 144:ef7eb2e8f9f7 15053 #define USBHS_USBSTS_HCH_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15054 #define USBHS_USBSTS_HCH_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15055 #define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
<> 144:ef7eb2e8f9f7 15056 #define USBHS_USBSTS_RCL_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 15057 #define USBHS_USBSTS_RCL_SHIFT (13U)
<> 144:ef7eb2e8f9f7 15058 #define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
<> 144:ef7eb2e8f9f7 15059 #define USBHS_USBSTS_PS_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 15060 #define USBHS_USBSTS_PS_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15061 #define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
<> 144:ef7eb2e8f9f7 15062 #define USBHS_USBSTS_AS_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 15063 #define USBHS_USBSTS_AS_SHIFT (15U)
<> 144:ef7eb2e8f9f7 15064 #define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
<> 144:ef7eb2e8f9f7 15065 #define USBHS_USBSTS_NAKI_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 15066 #define USBHS_USBSTS_NAKI_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15067 #define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
<> 144:ef7eb2e8f9f7 15068 #define USBHS_USBSTS_UAI_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15069 #define USBHS_USBSTS_UAI_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15070 #define USBHS_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
<> 144:ef7eb2e8f9f7 15071 #define USBHS_USBSTS_UPI_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15072 #define USBHS_USBSTS_UPI_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15073 #define USBHS_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
<> 144:ef7eb2e8f9f7 15074 #define USBHS_USBSTS_TI0_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15075 #define USBHS_USBSTS_TI0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15076 #define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
<> 144:ef7eb2e8f9f7 15077 #define USBHS_USBSTS_TI1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 15078 #define USBHS_USBSTS_TI1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 15079 #define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
<> 144:ef7eb2e8f9f7 15080
<> 144:ef7eb2e8f9f7 15081 /*! @name USBINTR - USB Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 15082 #define USBHS_USBINTR_UE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15083 #define USBHS_USBINTR_UE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15084 #define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
<> 144:ef7eb2e8f9f7 15085 #define USBHS_USBINTR_UEE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15086 #define USBHS_USBINTR_UEE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15087 #define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
<> 144:ef7eb2e8f9f7 15088 #define USBHS_USBINTR_PCE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 15089 #define USBHS_USBINTR_PCE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15090 #define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
<> 144:ef7eb2e8f9f7 15091 #define USBHS_USBINTR_FRE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15092 #define USBHS_USBINTR_FRE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15093 #define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
<> 144:ef7eb2e8f9f7 15094 #define USBHS_USBINTR_SEE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15095 #define USBHS_USBINTR_SEE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15096 #define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
<> 144:ef7eb2e8f9f7 15097 #define USBHS_USBINTR_AAE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15098 #define USBHS_USBINTR_AAE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15099 #define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
<> 144:ef7eb2e8f9f7 15100 #define USBHS_USBINTR_URE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 15101 #define USBHS_USBINTR_URE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 15102 #define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
<> 144:ef7eb2e8f9f7 15103 #define USBHS_USBINTR_SRE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 15104 #define USBHS_USBINTR_SRE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 15105 #define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
<> 144:ef7eb2e8f9f7 15106 #define USBHS_USBINTR_SLE_MASK (0x100U)
<> 144:ef7eb2e8f9f7 15107 #define USBHS_USBINTR_SLE_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15108 #define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
<> 144:ef7eb2e8f9f7 15109 #define USBHS_USBINTR_NAKE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 15110 #define USBHS_USBINTR_NAKE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15111 #define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
<> 144:ef7eb2e8f9f7 15112 #define USBHS_USBINTR_UAIE_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15113 #define USBHS_USBINTR_UAIE_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15114 #define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
<> 144:ef7eb2e8f9f7 15115 #define USBHS_USBINTR_UPIE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15116 #define USBHS_USBINTR_UPIE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15117 #define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
<> 144:ef7eb2e8f9f7 15118 #define USBHS_USBINTR_TIE0_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15119 #define USBHS_USBINTR_TIE0_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15120 #define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
<> 144:ef7eb2e8f9f7 15121 #define USBHS_USBINTR_TIE1_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 15122 #define USBHS_USBINTR_TIE1_SHIFT (25U)
<> 144:ef7eb2e8f9f7 15123 #define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
<> 144:ef7eb2e8f9f7 15124
<> 144:ef7eb2e8f9f7 15125 /*! @name FRINDEX - Frame Index Register */
<> 144:ef7eb2e8f9f7 15126 #define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU)
<> 144:ef7eb2e8f9f7 15127 #define USBHS_FRINDEX_FRINDEX_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15128 #define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
<> 144:ef7eb2e8f9f7 15129 #define USBHS_FRINDEX_Reerved_MASK (0xFFFFC000U)
<> 144:ef7eb2e8f9f7 15130 #define USBHS_FRINDEX_Reerved_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15131 #define USBHS_FRINDEX_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
<> 144:ef7eb2e8f9f7 15132
<> 144:ef7eb2e8f9f7 15133 /*! @name DEVICEADDR - Device Address Register */
<> 144:ef7eb2e8f9f7 15134 #define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15135 #define USBHS_DEVICEADDR_USBADRA_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15136 #define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
<> 144:ef7eb2e8f9f7 15137 #define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U)
<> 144:ef7eb2e8f9f7 15138 #define USBHS_DEVICEADDR_USBADR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 15139 #define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
<> 144:ef7eb2e8f9f7 15140
<> 144:ef7eb2e8f9f7 15141 /*! @name PERIODICLISTBASE - Periodic Frame List Base Address Register */
<> 144:ef7eb2e8f9f7 15142 #define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xFFFFF000U)
<> 144:ef7eb2e8f9f7 15143 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15144 #define USBHS_PERIODICLISTBASE_PERBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
<> 144:ef7eb2e8f9f7 15145
<> 144:ef7eb2e8f9f7 15146 /*! @name ASYNCLISTADDR - Current Asynchronous List Address Register */
<> 144:ef7eb2e8f9f7 15147 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
<> 144:ef7eb2e8f9f7 15148 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15149 #define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
<> 144:ef7eb2e8f9f7 15150
<> 144:ef7eb2e8f9f7 15151 /*! @name EPLISTADDR - Endpoint List Address Register */
<> 144:ef7eb2e8f9f7 15152 #define USBHS_EPLISTADDR_EPBASE_MASK (0xFFFFF800U)
<> 144:ef7eb2e8f9f7 15153 #define USBHS_EPLISTADDR_EPBASE_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15154 #define USBHS_EPLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
<> 144:ef7eb2e8f9f7 15155
<> 144:ef7eb2e8f9f7 15156 /*! @name TTCTRL - Host TT Asynchronous Buffer Control */
<> 144:ef7eb2e8f9f7 15157 #define USBHS_TTCTRL_TTHA_MASK (0x7F000000U)
<> 144:ef7eb2e8f9f7 15158 #define USBHS_TTCTRL_TTHA_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15159 #define USBHS_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
<> 144:ef7eb2e8f9f7 15160 #define USBHS_TTCTRL_Reerved_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 15161 #define USBHS_TTCTRL_Reerved_SHIFT (31U)
<> 144:ef7eb2e8f9f7 15162 #define USBHS_TTCTRL_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
<> 144:ef7eb2e8f9f7 15163
<> 144:ef7eb2e8f9f7 15164 /*! @name BURSTSIZE - Master Interface Data Burst Size Register */
<> 144:ef7eb2e8f9f7 15165 #define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU)
<> 144:ef7eb2e8f9f7 15166 #define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15167 #define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
<> 144:ef7eb2e8f9f7 15168 #define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U)
<> 144:ef7eb2e8f9f7 15169 #define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15170 #define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
<> 144:ef7eb2e8f9f7 15171
<> 144:ef7eb2e8f9f7 15172 /*! @name TXFILLTUNING - Transmit FIFO Tuning Control Register */
<> 144:ef7eb2e8f9f7 15173 #define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU)
<> 144:ef7eb2e8f9f7 15174 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15175 #define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
<> 144:ef7eb2e8f9f7 15176 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
<> 144:ef7eb2e8f9f7 15177 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15178 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
<> 144:ef7eb2e8f9f7 15179 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
<> 144:ef7eb2e8f9f7 15180 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15181 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
<> 144:ef7eb2e8f9f7 15182
<> 144:ef7eb2e8f9f7 15183 /*! @name ENDPTNAK - Endpoint NAK Register */
<> 144:ef7eb2e8f9f7 15184 #define USBHS_ENDPTNAK_EPRN_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15185 #define USBHS_ENDPTNAK_EPRN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15186 #define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
<> 144:ef7eb2e8f9f7 15187 #define USBHS_ENDPTNAK_EPTN_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15188 #define USBHS_ENDPTNAK_EPTN_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15189 #define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
<> 144:ef7eb2e8f9f7 15190
<> 144:ef7eb2e8f9f7 15191 /*! @name ENDPTNAKEN - Endpoint NAK Enable Register */
<> 144:ef7eb2e8f9f7 15192 #define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15193 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15194 #define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
<> 144:ef7eb2e8f9f7 15195 #define USBHS_ENDPTNAKEN_EPTNE_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15196 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15197 #define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
<> 144:ef7eb2e8f9f7 15198
<> 144:ef7eb2e8f9f7 15199 /*! @name PORTSC1 - Port Status and Control Registers */
<> 144:ef7eb2e8f9f7 15200 #define USBHS_PORTSC1_CCS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15201 #define USBHS_PORTSC1_CCS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15202 #define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
<> 144:ef7eb2e8f9f7 15203 #define USBHS_PORTSC1_CSC_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15204 #define USBHS_PORTSC1_CSC_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15205 #define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
<> 144:ef7eb2e8f9f7 15206 #define USBHS_PORTSC1_PE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 15207 #define USBHS_PORTSC1_PE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15208 #define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
<> 144:ef7eb2e8f9f7 15209 #define USBHS_PORTSC1_PEC_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15210 #define USBHS_PORTSC1_PEC_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15211 #define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
<> 144:ef7eb2e8f9f7 15212 #define USBHS_PORTSC1_OCA_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15213 #define USBHS_PORTSC1_OCA_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15214 #define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
<> 144:ef7eb2e8f9f7 15215 #define USBHS_PORTSC1_OCC_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15216 #define USBHS_PORTSC1_OCC_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15217 #define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
<> 144:ef7eb2e8f9f7 15218 #define USBHS_PORTSC1_FPR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 15219 #define USBHS_PORTSC1_FPR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 15220 #define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
<> 144:ef7eb2e8f9f7 15221 #define USBHS_PORTSC1_SUSP_MASK (0x80U)
<> 144:ef7eb2e8f9f7 15222 #define USBHS_PORTSC1_SUSP_SHIFT (7U)
<> 144:ef7eb2e8f9f7 15223 #define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
<> 144:ef7eb2e8f9f7 15224 #define USBHS_PORTSC1_PR_MASK (0x100U)
<> 144:ef7eb2e8f9f7 15225 #define USBHS_PORTSC1_PR_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15226 #define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
<> 144:ef7eb2e8f9f7 15227 #define USBHS_PORTSC1_HSP_MASK (0x200U)
<> 144:ef7eb2e8f9f7 15228 #define USBHS_PORTSC1_HSP_SHIFT (9U)
<> 144:ef7eb2e8f9f7 15229 #define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
<> 144:ef7eb2e8f9f7 15230 #define USBHS_PORTSC1_LS_MASK (0xC00U)
<> 144:ef7eb2e8f9f7 15231 #define USBHS_PORTSC1_LS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 15232 #define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
<> 144:ef7eb2e8f9f7 15233 #define USBHS_PORTSC1_PP_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15234 #define USBHS_PORTSC1_PP_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15235 #define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
<> 144:ef7eb2e8f9f7 15236 #define USBHS_PORTSC1_PO_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 15237 #define USBHS_PORTSC1_PO_SHIFT (13U)
<> 144:ef7eb2e8f9f7 15238 #define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
<> 144:ef7eb2e8f9f7 15239 #define USBHS_PORTSC1_PIC_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 15240 #define USBHS_PORTSC1_PIC_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15241 #define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
<> 144:ef7eb2e8f9f7 15242 #define USBHS_PORTSC1_PTC_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15243 #define USBHS_PORTSC1_PTC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15244 #define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
<> 144:ef7eb2e8f9f7 15245 #define USBHS_PORTSC1_WKCN_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15246 #define USBHS_PORTSC1_WKCN_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15247 #define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
<> 144:ef7eb2e8f9f7 15248 #define USBHS_PORTSC1_WKDS_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 15249 #define USBHS_PORTSC1_WKDS_SHIFT (21U)
<> 144:ef7eb2e8f9f7 15250 #define USBHS_PORTSC1_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
<> 144:ef7eb2e8f9f7 15251 #define USBHS_PORTSC1_WKOC_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15252 #define USBHS_PORTSC1_WKOC_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15253 #define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
<> 144:ef7eb2e8f9f7 15254 #define USBHS_PORTSC1_PHCD_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 15255 #define USBHS_PORTSC1_PHCD_SHIFT (23U)
<> 144:ef7eb2e8f9f7 15256 #define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
<> 144:ef7eb2e8f9f7 15257 #define USBHS_PORTSC1_PFSC_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15258 #define USBHS_PORTSC1_PFSC_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15259 #define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
<> 144:ef7eb2e8f9f7 15260 #define USBHS_PORTSC1_PTS2_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 15261 #define USBHS_PORTSC1_PTS2_SHIFT (25U)
<> 144:ef7eb2e8f9f7 15262 #define USBHS_PORTSC1_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
<> 144:ef7eb2e8f9f7 15263 #define USBHS_PORTSC1_PSPD_MASK (0xC000000U)
<> 144:ef7eb2e8f9f7 15264 #define USBHS_PORTSC1_PSPD_SHIFT (26U)
<> 144:ef7eb2e8f9f7 15265 #define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
<> 144:ef7eb2e8f9f7 15266 #define USBHS_PORTSC1_PTS_MASK (0xC0000000U)
<> 144:ef7eb2e8f9f7 15267 #define USBHS_PORTSC1_PTS_SHIFT (30U)
<> 144:ef7eb2e8f9f7 15268 #define USBHS_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
<> 144:ef7eb2e8f9f7 15269
<> 144:ef7eb2e8f9f7 15270 /*! @name OTGSC - On-the-Go Status and Control Register */
<> 144:ef7eb2e8f9f7 15271 #define USBHS_OTGSC_VD_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15272 #define USBHS_OTGSC_VD_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15273 #define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
<> 144:ef7eb2e8f9f7 15274 #define USBHS_OTGSC_VC_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15275 #define USBHS_OTGSC_VC_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15276 #define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
<> 144:ef7eb2e8f9f7 15277 #define USBHS_OTGSC_HAAR_MASK (0x4U)
<> 144:ef7eb2e8f9f7 15278 #define USBHS_OTGSC_HAAR_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15279 #define USBHS_OTGSC_HAAR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
<> 144:ef7eb2e8f9f7 15280 #define USBHS_OTGSC_OT_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15281 #define USBHS_OTGSC_OT_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15282 #define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
<> 144:ef7eb2e8f9f7 15283 #define USBHS_OTGSC_DP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15284 #define USBHS_OTGSC_DP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15285 #define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
<> 144:ef7eb2e8f9f7 15286 #define USBHS_OTGSC_IDPU_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15287 #define USBHS_OTGSC_IDPU_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15288 #define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
<> 144:ef7eb2e8f9f7 15289 #define USBHS_OTGSC_HABA_MASK (0x80U)
<> 144:ef7eb2e8f9f7 15290 #define USBHS_OTGSC_HABA_SHIFT (7U)
<> 144:ef7eb2e8f9f7 15291 #define USBHS_OTGSC_HABA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
<> 144:ef7eb2e8f9f7 15292 #define USBHS_OTGSC_ID_MASK (0x100U)
<> 144:ef7eb2e8f9f7 15293 #define USBHS_OTGSC_ID_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15294 #define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
<> 144:ef7eb2e8f9f7 15295 #define USBHS_OTGSC_AVV_MASK (0x200U)
<> 144:ef7eb2e8f9f7 15296 #define USBHS_OTGSC_AVV_SHIFT (9U)
<> 144:ef7eb2e8f9f7 15297 #define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
<> 144:ef7eb2e8f9f7 15298 #define USBHS_OTGSC_ASV_MASK (0x400U)
<> 144:ef7eb2e8f9f7 15299 #define USBHS_OTGSC_ASV_SHIFT (10U)
<> 144:ef7eb2e8f9f7 15300 #define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
<> 144:ef7eb2e8f9f7 15301 #define USBHS_OTGSC_BSV_MASK (0x800U)
<> 144:ef7eb2e8f9f7 15302 #define USBHS_OTGSC_BSV_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15303 #define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
<> 144:ef7eb2e8f9f7 15304 #define USBHS_OTGSC_BSE_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15305 #define USBHS_OTGSC_BSE_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15306 #define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
<> 144:ef7eb2e8f9f7 15307 #define USBHS_OTGSC_MST_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 15308 #define USBHS_OTGSC_MST_SHIFT (13U)
<> 144:ef7eb2e8f9f7 15309 #define USBHS_OTGSC_MST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
<> 144:ef7eb2e8f9f7 15310 #define USBHS_OTGSC_DPS_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 15311 #define USBHS_OTGSC_DPS_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15312 #define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
<> 144:ef7eb2e8f9f7 15313 #define USBHS_OTGSC_IDIS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 15314 #define USBHS_OTGSC_IDIS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15315 #define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
<> 144:ef7eb2e8f9f7 15316 #define USBHS_OTGSC_AVVIS_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15317 #define USBHS_OTGSC_AVVIS_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15318 #define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
<> 144:ef7eb2e8f9f7 15319 #define USBHS_OTGSC_ASVIS_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15320 #define USBHS_OTGSC_ASVIS_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15321 #define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
<> 144:ef7eb2e8f9f7 15322 #define USBHS_OTGSC_BSVIS_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15323 #define USBHS_OTGSC_BSVIS_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15324 #define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
<> 144:ef7eb2e8f9f7 15325 #define USBHS_OTGSC_BSEIS_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15326 #define USBHS_OTGSC_BSEIS_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15327 #define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
<> 144:ef7eb2e8f9f7 15328 #define USBHS_OTGSC_MSS_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 15329 #define USBHS_OTGSC_MSS_SHIFT (21U)
<> 144:ef7eb2e8f9f7 15330 #define USBHS_OTGSC_MSS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
<> 144:ef7eb2e8f9f7 15331 #define USBHS_OTGSC_DPIS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15332 #define USBHS_OTGSC_DPIS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15333 #define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
<> 144:ef7eb2e8f9f7 15334 #define USBHS_OTGSC_IDIE_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15335 #define USBHS_OTGSC_IDIE_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15336 #define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
<> 144:ef7eb2e8f9f7 15337 #define USBHS_OTGSC_AVVIE_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 15338 #define USBHS_OTGSC_AVVIE_SHIFT (25U)
<> 144:ef7eb2e8f9f7 15339 #define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
<> 144:ef7eb2e8f9f7 15340 #define USBHS_OTGSC_ASVIE_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 15341 #define USBHS_OTGSC_ASVIE_SHIFT (26U)
<> 144:ef7eb2e8f9f7 15342 #define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
<> 144:ef7eb2e8f9f7 15343 #define USBHS_OTGSC_BSVIE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 15344 #define USBHS_OTGSC_BSVIE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 15345 #define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
<> 144:ef7eb2e8f9f7 15346 #define USBHS_OTGSC_BSEIE_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 15347 #define USBHS_OTGSC_BSEIE_SHIFT (28U)
<> 144:ef7eb2e8f9f7 15348 #define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
<> 144:ef7eb2e8f9f7 15349 #define USBHS_OTGSC_MSE_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 15350 #define USBHS_OTGSC_MSE_SHIFT (29U)
<> 144:ef7eb2e8f9f7 15351 #define USBHS_OTGSC_MSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
<> 144:ef7eb2e8f9f7 15352 #define USBHS_OTGSC_DPIE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 15353 #define USBHS_OTGSC_DPIE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 15354 #define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
<> 144:ef7eb2e8f9f7 15355
<> 144:ef7eb2e8f9f7 15356 /*! @name USBMODE - USB Mode Register */
<> 144:ef7eb2e8f9f7 15357 #define USBHS_USBMODE_CM_MASK (0x3U)
<> 144:ef7eb2e8f9f7 15358 #define USBHS_USBMODE_CM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15359 #define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
<> 144:ef7eb2e8f9f7 15360 #define USBHS_USBMODE_ES_MASK (0x4U)
<> 144:ef7eb2e8f9f7 15361 #define USBHS_USBMODE_ES_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15362 #define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
<> 144:ef7eb2e8f9f7 15363 #define USBHS_USBMODE_SLOM_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15364 #define USBHS_USBMODE_SLOM_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15365 #define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
<> 144:ef7eb2e8f9f7 15366 #define USBHS_USBMODE_SDIS_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15367 #define USBHS_USBMODE_SDIS_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15368 #define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
<> 144:ef7eb2e8f9f7 15369 #define USBHS_USBMODE_TXHSD_MASK (0x7000U)
<> 144:ef7eb2e8f9f7 15370 #define USBHS_USBMODE_TXHSD_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15371 #define USBHS_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
<> 144:ef7eb2e8f9f7 15372
<> 144:ef7eb2e8f9f7 15373 /*! @name EPSETUPSR - Endpoint Setup Status Register */
<> 144:ef7eb2e8f9f7 15374 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15375 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15376 #define USBHS_EPSETUPSR_EPSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
<> 144:ef7eb2e8f9f7 15377
<> 144:ef7eb2e8f9f7 15378 /*! @name EPPRIME - Endpoint Initialization Register */
<> 144:ef7eb2e8f9f7 15379 #define USBHS_EPPRIME_PERB_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15380 #define USBHS_EPPRIME_PERB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15381 #define USBHS_EPPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
<> 144:ef7eb2e8f9f7 15382 #define USBHS_EPPRIME_PETB_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15383 #define USBHS_EPPRIME_PETB_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15384 #define USBHS_EPPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
<> 144:ef7eb2e8f9f7 15385
<> 144:ef7eb2e8f9f7 15386 /*! @name EPFLUSH - Endpoint Flush Register */
<> 144:ef7eb2e8f9f7 15387 #define USBHS_EPFLUSH_FERB_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15388 #define USBHS_EPFLUSH_FERB_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15389 #define USBHS_EPFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
<> 144:ef7eb2e8f9f7 15390 #define USBHS_EPFLUSH_FETB_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15391 #define USBHS_EPFLUSH_FETB_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15392 #define USBHS_EPFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
<> 144:ef7eb2e8f9f7 15393
<> 144:ef7eb2e8f9f7 15394 /*! @name EPSR - Endpoint Status Register */
<> 144:ef7eb2e8f9f7 15395 #define USBHS_EPSR_ERBR_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15396 #define USBHS_EPSR_ERBR_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15397 #define USBHS_EPSR_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
<> 144:ef7eb2e8f9f7 15398 #define USBHS_EPSR_ETBR_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15399 #define USBHS_EPSR_ETBR_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15400 #define USBHS_EPSR_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
<> 144:ef7eb2e8f9f7 15401
<> 144:ef7eb2e8f9f7 15402 /*! @name EPCOMPLETE - Endpoint Complete Register */
<> 144:ef7eb2e8f9f7 15403 #define USBHS_EPCOMPLETE_ERCE_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15404 #define USBHS_EPCOMPLETE_ERCE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15405 #define USBHS_EPCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
<> 144:ef7eb2e8f9f7 15406 #define USBHS_EPCOMPLETE_ETCE_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15407 #define USBHS_EPCOMPLETE_ETCE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15408 #define USBHS_EPCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
<> 144:ef7eb2e8f9f7 15409
<> 144:ef7eb2e8f9f7 15410 /*! @name EPCR0 - Endpoint Control Register 0 */
<> 144:ef7eb2e8f9f7 15411 #define USBHS_EPCR0_RXS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15412 #define USBHS_EPCR0_RXS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15413 #define USBHS_EPCR0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
<> 144:ef7eb2e8f9f7 15414 #define USBHS_EPCR0_RXT_MASK (0xCU)
<> 144:ef7eb2e8f9f7 15415 #define USBHS_EPCR0_RXT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15416 #define USBHS_EPCR0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
<> 144:ef7eb2e8f9f7 15417 #define USBHS_EPCR0_RXE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 15418 #define USBHS_EPCR0_RXE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 15419 #define USBHS_EPCR0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
<> 144:ef7eb2e8f9f7 15420 #define USBHS_EPCR0_TXS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 15421 #define USBHS_EPCR0_TXS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15422 #define USBHS_EPCR0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
<> 144:ef7eb2e8f9f7 15423 #define USBHS_EPCR0_TXT_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 15424 #define USBHS_EPCR0_TXT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15425 #define USBHS_EPCR0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
<> 144:ef7eb2e8f9f7 15426 #define USBHS_EPCR0_TXE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 15427 #define USBHS_EPCR0_TXE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 15428 #define USBHS_EPCR0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
<> 144:ef7eb2e8f9f7 15429
<> 144:ef7eb2e8f9f7 15430 /*! @name EPCR - Endpoint Control Register n */
<> 144:ef7eb2e8f9f7 15431 #define USBHS_EPCR_RXS_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15432 #define USBHS_EPCR_RXS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15433 #define USBHS_EPCR_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
<> 144:ef7eb2e8f9f7 15434 #define USBHS_EPCR_RXD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15435 #define USBHS_EPCR_RXD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15436 #define USBHS_EPCR_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
<> 144:ef7eb2e8f9f7 15437 #define USBHS_EPCR_RXT_MASK (0xCU)
<> 144:ef7eb2e8f9f7 15438 #define USBHS_EPCR_RXT_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15439 #define USBHS_EPCR_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
<> 144:ef7eb2e8f9f7 15440 #define USBHS_EPCR_RXI_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15441 #define USBHS_EPCR_RXI_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15442 #define USBHS_EPCR_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
<> 144:ef7eb2e8f9f7 15443 #define USBHS_EPCR_RXR_MASK (0x40U)
<> 144:ef7eb2e8f9f7 15444 #define USBHS_EPCR_RXR_SHIFT (6U)
<> 144:ef7eb2e8f9f7 15445 #define USBHS_EPCR_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
<> 144:ef7eb2e8f9f7 15446 #define USBHS_EPCR_RXE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 15447 #define USBHS_EPCR_RXE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 15448 #define USBHS_EPCR_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
<> 144:ef7eb2e8f9f7 15449 #define USBHS_EPCR_TXS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 15450 #define USBHS_EPCR_TXS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15451 #define USBHS_EPCR_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
<> 144:ef7eb2e8f9f7 15452 #define USBHS_EPCR_TXD_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15453 #define USBHS_EPCR_TXD_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15454 #define USBHS_EPCR_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
<> 144:ef7eb2e8f9f7 15455 #define USBHS_EPCR_TXT_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 15456 #define USBHS_EPCR_TXT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15457 #define USBHS_EPCR_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
<> 144:ef7eb2e8f9f7 15458 #define USBHS_EPCR_TXI_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 15459 #define USBHS_EPCR_TXI_SHIFT (21U)
<> 144:ef7eb2e8f9f7 15460 #define USBHS_EPCR_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
<> 144:ef7eb2e8f9f7 15461 #define USBHS_EPCR_TXR_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15462 #define USBHS_EPCR_TXR_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15463 #define USBHS_EPCR_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
<> 144:ef7eb2e8f9f7 15464 #define USBHS_EPCR_TXE_MASK (0x800000U)
<> 144:ef7eb2e8f9f7 15465 #define USBHS_EPCR_TXE_SHIFT (23U)
<> 144:ef7eb2e8f9f7 15466 #define USBHS_EPCR_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
<> 144:ef7eb2e8f9f7 15467
<> 144:ef7eb2e8f9f7 15468 /* The count of USBHS_EPCR */
<> 144:ef7eb2e8f9f7 15469 #define USBHS_EPCR_COUNT (7U)
<> 144:ef7eb2e8f9f7 15470
<> 144:ef7eb2e8f9f7 15471 /*! @name USBGENCTRL - USB General Control Register */
<> 144:ef7eb2e8f9f7 15472 #define USBHS_USBGENCTRL_WU_IE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15473 #define USBHS_USBGENCTRL_WU_IE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15474 #define USBHS_USBGENCTRL_WU_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
<> 144:ef7eb2e8f9f7 15475 #define USBHS_USBGENCTRL_WU_INT_CLR_MASK (0x20U)
<> 144:ef7eb2e8f9f7 15476 #define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT (5U)
<> 144:ef7eb2e8f9f7 15477 #define USBHS_USBGENCTRL_WU_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
<> 144:ef7eb2e8f9f7 15478
<> 144:ef7eb2e8f9f7 15479
<> 144:ef7eb2e8f9f7 15480 /*!
<> 144:ef7eb2e8f9f7 15481 * @}
<> 144:ef7eb2e8f9f7 15482 */ /* end of group USBHS_Register_Masks */
<> 144:ef7eb2e8f9f7 15483
<> 144:ef7eb2e8f9f7 15484
<> 144:ef7eb2e8f9f7 15485 /* USBHS - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 15486 /** Peripheral USBHS base address */
<> 144:ef7eb2e8f9f7 15487 #define USBHS_BASE (0x400A1000u)
<> 144:ef7eb2e8f9f7 15488 /** Peripheral USBHS base pointer */
<> 144:ef7eb2e8f9f7 15489 #define USBHS ((USBHS_Type *)USBHS_BASE)
<> 144:ef7eb2e8f9f7 15490 /** Array initializer of USBHS peripheral base addresses */
<> 144:ef7eb2e8f9f7 15491 #define USBHS_BASE_ADDRS { USBHS_BASE }
<> 144:ef7eb2e8f9f7 15492 /** Array initializer of USBHS peripheral base pointers */
<> 144:ef7eb2e8f9f7 15493 #define USBHS_BASE_PTRS { USBHS }
<> 144:ef7eb2e8f9f7 15494 /** Interrupt vectors for the USBHS peripheral type */
<> 144:ef7eb2e8f9f7 15495 #define USBHS_IRQS { USBHS_IRQn }
<> 144:ef7eb2e8f9f7 15496
<> 144:ef7eb2e8f9f7 15497 /*!
<> 144:ef7eb2e8f9f7 15498 * @}
<> 144:ef7eb2e8f9f7 15499 */ /* end of group USBHS_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 15500
<> 144:ef7eb2e8f9f7 15501
<> 144:ef7eb2e8f9f7 15502 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15503 -- USBHSDCD Peripheral Access Layer
<> 144:ef7eb2e8f9f7 15504 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 15505
<> 144:ef7eb2e8f9f7 15506 /*!
<> 144:ef7eb2e8f9f7 15507 * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
<> 144:ef7eb2e8f9f7 15508 * @{
<> 144:ef7eb2e8f9f7 15509 */
<> 144:ef7eb2e8f9f7 15510
<> 144:ef7eb2e8f9f7 15511 /** USBHSDCD - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 15512 typedef struct {
<> 144:ef7eb2e8f9f7 15513 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 15514 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 15515 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 15516 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 15517 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 15518 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 15519 union { /* offset: 0x18 */
<> 144:ef7eb2e8f9f7 15520 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 15521 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 15522 };
<> 144:ef7eb2e8f9f7 15523 } USBHSDCD_Type;
<> 144:ef7eb2e8f9f7 15524
<> 144:ef7eb2e8f9f7 15525 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15526 -- USBHSDCD Register Masks
<> 144:ef7eb2e8f9f7 15527 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 15528
<> 144:ef7eb2e8f9f7 15529 /*!
<> 144:ef7eb2e8f9f7 15530 * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
<> 144:ef7eb2e8f9f7 15531 * @{
<> 144:ef7eb2e8f9f7 15532 */
<> 144:ef7eb2e8f9f7 15533
<> 144:ef7eb2e8f9f7 15534 /*! @name CONTROL - Control register */
<> 144:ef7eb2e8f9f7 15535 #define USBHSDCD_CONTROL_IACK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15536 #define USBHSDCD_CONTROL_IACK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15537 #define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
<> 144:ef7eb2e8f9f7 15538 #define USBHSDCD_CONTROL_IF_MASK (0x100U)
<> 144:ef7eb2e8f9f7 15539 #define USBHSDCD_CONTROL_IF_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15540 #define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
<> 144:ef7eb2e8f9f7 15541 #define USBHSDCD_CONTROL_IE_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 15542 #define USBHSDCD_CONTROL_IE_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15543 #define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
<> 144:ef7eb2e8f9f7 15544 #define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15545 #define USBHSDCD_CONTROL_BC12_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15546 #define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
<> 144:ef7eb2e8f9f7 15547 #define USBHSDCD_CONTROL_START_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15548 #define USBHSDCD_CONTROL_START_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15549 #define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
<> 144:ef7eb2e8f9f7 15550 #define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
<> 144:ef7eb2e8f9f7 15551 #define USBHSDCD_CONTROL_SR_SHIFT (25U)
<> 144:ef7eb2e8f9f7 15552 #define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
<> 144:ef7eb2e8f9f7 15553
<> 144:ef7eb2e8f9f7 15554 /*! @name CLOCK - Clock register */
<> 144:ef7eb2e8f9f7 15555 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 15556 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15557 #define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
<> 144:ef7eb2e8f9f7 15558 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
<> 144:ef7eb2e8f9f7 15559 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
<> 144:ef7eb2e8f9f7 15560 #define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
<> 144:ef7eb2e8f9f7 15561
<> 144:ef7eb2e8f9f7 15562 /*! @name STATUS - Status register */
<> 144:ef7eb2e8f9f7 15563 #define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 15564 #define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15565 #define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
<> 144:ef7eb2e8f9f7 15566 #define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 15567 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15568 #define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
<> 144:ef7eb2e8f9f7 15569 #define USBHSDCD_STATUS_ERR_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15570 #define USBHSDCD_STATUS_ERR_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15571 #define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
<> 144:ef7eb2e8f9f7 15572 #define USBHSDCD_STATUS_TO_MASK (0x200000U)
<> 144:ef7eb2e8f9f7 15573 #define USBHSDCD_STATUS_TO_SHIFT (21U)
<> 144:ef7eb2e8f9f7 15574 #define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
<> 144:ef7eb2e8f9f7 15575 #define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15576 #define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15577 #define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
<> 144:ef7eb2e8f9f7 15578
<> 144:ef7eb2e8f9f7 15579 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
<> 144:ef7eb2e8f9f7 15580 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
<> 144:ef7eb2e8f9f7 15581 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15582 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
<> 144:ef7eb2e8f9f7 15583
<> 144:ef7eb2e8f9f7 15584 /*! @name TIMER0 - TIMER0 register */
<> 144:ef7eb2e8f9f7 15585 #define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
<> 144:ef7eb2e8f9f7 15586 #define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15587 #define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
<> 144:ef7eb2e8f9f7 15588 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 15589 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15590 #define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
<> 144:ef7eb2e8f9f7 15591
<> 144:ef7eb2e8f9f7 15592 /*! @name TIMER1 - TIMER1 register */
<> 144:ef7eb2e8f9f7 15593 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 15594 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15595 #define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
<> 144:ef7eb2e8f9f7 15596 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 15597 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15598 #define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
<> 144:ef7eb2e8f9f7 15599
<> 144:ef7eb2e8f9f7 15600 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
<> 144:ef7eb2e8f9f7 15601 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15602 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15603 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
<> 144:ef7eb2e8f9f7 15604 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 15605 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15606 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
<> 144:ef7eb2e8f9f7 15607
<> 144:ef7eb2e8f9f7 15608 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
<> 144:ef7eb2e8f9f7 15609 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
<> 144:ef7eb2e8f9f7 15610 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15611 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
<> 144:ef7eb2e8f9f7 15612 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 15613 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15614 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
<> 144:ef7eb2e8f9f7 15615
<> 144:ef7eb2e8f9f7 15616
<> 144:ef7eb2e8f9f7 15617 /*!
<> 144:ef7eb2e8f9f7 15618 * @}
<> 144:ef7eb2e8f9f7 15619 */ /* end of group USBHSDCD_Register_Masks */
<> 144:ef7eb2e8f9f7 15620
<> 144:ef7eb2e8f9f7 15621
<> 144:ef7eb2e8f9f7 15622 /* USBHSDCD - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 15623 /** Peripheral USBHSDCD base address */
<> 144:ef7eb2e8f9f7 15624 #define USBHSDCD_BASE (0x400A3000u)
<> 144:ef7eb2e8f9f7 15625 /** Peripheral USBHSDCD base pointer */
<> 144:ef7eb2e8f9f7 15626 #define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
<> 144:ef7eb2e8f9f7 15627 /** Array initializer of USBHSDCD peripheral base addresses */
<> 144:ef7eb2e8f9f7 15628 #define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
<> 144:ef7eb2e8f9f7 15629 /** Array initializer of USBHSDCD peripheral base pointers */
<> 144:ef7eb2e8f9f7 15630 #define USBHSDCD_BASE_PTRS { USBHSDCD }
<> 144:ef7eb2e8f9f7 15631 /** Interrupt vectors for the USBHSDCD peripheral type */
<> 144:ef7eb2e8f9f7 15632 #define USBHSDCD_IRQS { USBHSDCD_IRQn }
<> 144:ef7eb2e8f9f7 15633
<> 144:ef7eb2e8f9f7 15634 /*!
<> 144:ef7eb2e8f9f7 15635 * @}
<> 144:ef7eb2e8f9f7 15636 */ /* end of group USBHSDCD_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 15637
<> 144:ef7eb2e8f9f7 15638
<> 144:ef7eb2e8f9f7 15639 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15640 -- USBPHY Peripheral Access Layer
<> 144:ef7eb2e8f9f7 15641 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 15642
<> 144:ef7eb2e8f9f7 15643 /*!
<> 144:ef7eb2e8f9f7 15644 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
<> 144:ef7eb2e8f9f7 15645 * @{
<> 144:ef7eb2e8f9f7 15646 */
<> 144:ef7eb2e8f9f7 15647
<> 144:ef7eb2e8f9f7 15648 /** USBPHY - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 15649 typedef struct {
<> 144:ef7eb2e8f9f7 15650 __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 15651 __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
<> 144:ef7eb2e8f9f7 15652 __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
<> 144:ef7eb2e8f9f7 15653 __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
<> 144:ef7eb2e8f9f7 15654 __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
<> 144:ef7eb2e8f9f7 15655 __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 15656 __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
<> 144:ef7eb2e8f9f7 15657 __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
<> 144:ef7eb2e8f9f7 15658 __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
<> 144:ef7eb2e8f9f7 15659 __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
<> 144:ef7eb2e8f9f7 15660 __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
<> 144:ef7eb2e8f9f7 15661 __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
<> 144:ef7eb2e8f9f7 15662 __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
<> 144:ef7eb2e8f9f7 15663 __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
<> 144:ef7eb2e8f9f7 15664 __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
<> 144:ef7eb2e8f9f7 15665 __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
<> 144:ef7eb2e8f9f7 15666 __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
<> 144:ef7eb2e8f9f7 15667 uint8_t RESERVED_0[12];
<> 144:ef7eb2e8f9f7 15668 __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
<> 144:ef7eb2e8f9f7 15669 __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
<> 144:ef7eb2e8f9f7 15670 __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
<> 144:ef7eb2e8f9f7 15671 __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
<> 144:ef7eb2e8f9f7 15672 __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
<> 144:ef7eb2e8f9f7 15673 uint8_t RESERVED_1[12];
<> 144:ef7eb2e8f9f7 15674 __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
<> 144:ef7eb2e8f9f7 15675 __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
<> 144:ef7eb2e8f9f7 15676 __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
<> 144:ef7eb2e8f9f7 15677 __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
<> 144:ef7eb2e8f9f7 15678 __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
<> 144:ef7eb2e8f9f7 15679 uint8_t RESERVED_2[28];
<> 144:ef7eb2e8f9f7 15680 __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
<> 144:ef7eb2e8f9f7 15681 __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
<> 144:ef7eb2e8f9f7 15682 __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
<> 144:ef7eb2e8f9f7 15683 __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
<> 144:ef7eb2e8f9f7 15684 uint8_t RESERVED_3[16];
<> 144:ef7eb2e8f9f7 15685 __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
<> 144:ef7eb2e8f9f7 15686 __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
<> 144:ef7eb2e8f9f7 15687 __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
<> 144:ef7eb2e8f9f7 15688 __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
<> 144:ef7eb2e8f9f7 15689 __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
<> 144:ef7eb2e8f9f7 15690 uint8_t RESERVED_4[28];
<> 144:ef7eb2e8f9f7 15691 __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
<> 144:ef7eb2e8f9f7 15692 uint8_t RESERVED_5[12];
<> 144:ef7eb2e8f9f7 15693 __IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */
<> 144:ef7eb2e8f9f7 15694 __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
<> 144:ef7eb2e8f9f7 15695 __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
<> 144:ef7eb2e8f9f7 15696 __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
<> 144:ef7eb2e8f9f7 15697 __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
<> 144:ef7eb2e8f9f7 15698 __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
<> 144:ef7eb2e8f9f7 15699 __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
<> 144:ef7eb2e8f9f7 15700 __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
<> 144:ef7eb2e8f9f7 15701 __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
<> 144:ef7eb2e8f9f7 15702 __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
<> 144:ef7eb2e8f9f7 15703 __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
<> 144:ef7eb2e8f9f7 15704 __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
<> 144:ef7eb2e8f9f7 15705 __IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */
<> 144:ef7eb2e8f9f7 15706 __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */
<> 144:ef7eb2e8f9f7 15707 __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */
<> 144:ef7eb2e8f9f7 15708 __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */
<> 144:ef7eb2e8f9f7 15709 } USBPHY_Type;
<> 144:ef7eb2e8f9f7 15710
<> 144:ef7eb2e8f9f7 15711 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15712 -- USBPHY Register Masks
<> 144:ef7eb2e8f9f7 15713 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 15714
<> 144:ef7eb2e8f9f7 15715 /*!
<> 144:ef7eb2e8f9f7 15716 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
<> 144:ef7eb2e8f9f7 15717 * @{
<> 144:ef7eb2e8f9f7 15718 */
<> 144:ef7eb2e8f9f7 15719
<> 144:ef7eb2e8f9f7 15720 /*! @name PWD - USB PHY Power-Down Register */
<> 144:ef7eb2e8f9f7 15721 #define USBPHY_PWD_TXPWDFS_MASK (0x400U)
<> 144:ef7eb2e8f9f7 15722 #define USBPHY_PWD_TXPWDFS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 15723 #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
<> 144:ef7eb2e8f9f7 15724 #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
<> 144:ef7eb2e8f9f7 15725 #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15726 #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
<> 144:ef7eb2e8f9f7 15727 #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15728 #define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15729 #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
<> 144:ef7eb2e8f9f7 15730 #define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15731 #define USBPHY_PWD_RXPWDENV_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15732 #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
<> 144:ef7eb2e8f9f7 15733 #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15734 #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15735 #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
<> 144:ef7eb2e8f9f7 15736 #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15737 #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15738 #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
<> 144:ef7eb2e8f9f7 15739 #define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15740 #define USBPHY_PWD_RXPWDRX_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15741 #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
<> 144:ef7eb2e8f9f7 15742
<> 144:ef7eb2e8f9f7 15743 /*! @name PWD_SET - USB PHY Power-Down Register */
<> 144:ef7eb2e8f9f7 15744 #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
<> 144:ef7eb2e8f9f7 15745 #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 15746 #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
<> 144:ef7eb2e8f9f7 15747 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
<> 144:ef7eb2e8f9f7 15748 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15749 #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
<> 144:ef7eb2e8f9f7 15750 #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15751 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15752 #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
<> 144:ef7eb2e8f9f7 15753 #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15754 #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15755 #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
<> 144:ef7eb2e8f9f7 15756 #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15757 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15758 #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
<> 144:ef7eb2e8f9f7 15759 #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15760 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15761 #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
<> 144:ef7eb2e8f9f7 15762 #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15763 #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15764 #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
<> 144:ef7eb2e8f9f7 15765
<> 144:ef7eb2e8f9f7 15766 /*! @name PWD_CLR - USB PHY Power-Down Register */
<> 144:ef7eb2e8f9f7 15767 #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
<> 144:ef7eb2e8f9f7 15768 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 15769 #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
<> 144:ef7eb2e8f9f7 15770 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
<> 144:ef7eb2e8f9f7 15771 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15772 #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
<> 144:ef7eb2e8f9f7 15773 #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15774 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15775 #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
<> 144:ef7eb2e8f9f7 15776 #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15777 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15778 #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
<> 144:ef7eb2e8f9f7 15779 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15780 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15781 #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
<> 144:ef7eb2e8f9f7 15782 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15783 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15784 #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
<> 144:ef7eb2e8f9f7 15785 #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15786 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15787 #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
<> 144:ef7eb2e8f9f7 15788
<> 144:ef7eb2e8f9f7 15789 /*! @name PWD_TOG - USB PHY Power-Down Register */
<> 144:ef7eb2e8f9f7 15790 #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
<> 144:ef7eb2e8f9f7 15791 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 15792 #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
<> 144:ef7eb2e8f9f7 15793 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
<> 144:ef7eb2e8f9f7 15794 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
<> 144:ef7eb2e8f9f7 15795 #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
<> 144:ef7eb2e8f9f7 15796 #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15797 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15798 #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
<> 144:ef7eb2e8f9f7 15799 #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
<> 144:ef7eb2e8f9f7 15800 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
<> 144:ef7eb2e8f9f7 15801 #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
<> 144:ef7eb2e8f9f7 15802 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15803 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15804 #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
<> 144:ef7eb2e8f9f7 15805 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15806 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15807 #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
<> 144:ef7eb2e8f9f7 15808 #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15809 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15810 #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
<> 144:ef7eb2e8f9f7 15811
<> 144:ef7eb2e8f9f7 15812 /*! @name TX - USB PHY Transmitter Control Register */
<> 144:ef7eb2e8f9f7 15813 #define USBPHY_TX_D_CAL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15814 #define USBPHY_TX_D_CAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15815 #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 15816 #define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 15817 #define USBPHY_TX_TXCAL45DM_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15818 #define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
<> 144:ef7eb2e8f9f7 15819 #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15820 #define USBPHY_TX_TXCAL45DP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15821 #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
<> 144:ef7eb2e8f9f7 15822 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
<> 144:ef7eb2e8f9f7 15823 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 15824 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
<> 144:ef7eb2e8f9f7 15825
<> 144:ef7eb2e8f9f7 15826 /*! @name TX_SET - USB PHY Transmitter Control Register */
<> 144:ef7eb2e8f9f7 15827 #define USBPHY_TX_SET_D_CAL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15828 #define USBPHY_TX_SET_D_CAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15829 #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 15830 #define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 15831 #define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15832 #define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
<> 144:ef7eb2e8f9f7 15833 #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15834 #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15835 #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
<> 144:ef7eb2e8f9f7 15836 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
<> 144:ef7eb2e8f9f7 15837 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 15838 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
<> 144:ef7eb2e8f9f7 15839
<> 144:ef7eb2e8f9f7 15840 /*! @name TX_CLR - USB PHY Transmitter Control Register */
<> 144:ef7eb2e8f9f7 15841 #define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15842 #define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15843 #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 15844 #define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 15845 #define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15846 #define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
<> 144:ef7eb2e8f9f7 15847 #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15848 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15849 #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
<> 144:ef7eb2e8f9f7 15850 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
<> 144:ef7eb2e8f9f7 15851 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 15852 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
<> 144:ef7eb2e8f9f7 15853
<> 144:ef7eb2e8f9f7 15854 /*! @name TX_TOG - USB PHY Transmitter Control Register */
<> 144:ef7eb2e8f9f7 15855 #define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
<> 144:ef7eb2e8f9f7 15856 #define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15857 #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 15858 #define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 15859 #define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
<> 144:ef7eb2e8f9f7 15860 #define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
<> 144:ef7eb2e8f9f7 15861 #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
<> 144:ef7eb2e8f9f7 15862 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
<> 144:ef7eb2e8f9f7 15863 #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
<> 144:ef7eb2e8f9f7 15864 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
<> 144:ef7eb2e8f9f7 15865 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
<> 144:ef7eb2e8f9f7 15866 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
<> 144:ef7eb2e8f9f7 15867
<> 144:ef7eb2e8f9f7 15868 /*! @name RX - USB PHY Receiver Control Register */
<> 144:ef7eb2e8f9f7 15869 #define USBPHY_RX_ENVADJ_MASK (0x7U)
<> 144:ef7eb2e8f9f7 15870 #define USBPHY_RX_ENVADJ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15871 #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
<> 144:ef7eb2e8f9f7 15872 #define USBPHY_RX_DISCONADJ_MASK (0x70U)
<> 144:ef7eb2e8f9f7 15873 #define USBPHY_RX_DISCONADJ_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15874 #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
<> 144:ef7eb2e8f9f7 15875 #define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15876 #define USBPHY_RX_RXDBYPASS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15877 #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
<> 144:ef7eb2e8f9f7 15878
<> 144:ef7eb2e8f9f7 15879 /*! @name RX_SET - USB PHY Receiver Control Register */
<> 144:ef7eb2e8f9f7 15880 #define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
<> 144:ef7eb2e8f9f7 15881 #define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15882 #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
<> 144:ef7eb2e8f9f7 15883 #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
<> 144:ef7eb2e8f9f7 15884 #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15885 #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
<> 144:ef7eb2e8f9f7 15886 #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15887 #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15888 #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
<> 144:ef7eb2e8f9f7 15889
<> 144:ef7eb2e8f9f7 15890 /*! @name RX_CLR - USB PHY Receiver Control Register */
<> 144:ef7eb2e8f9f7 15891 #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
<> 144:ef7eb2e8f9f7 15892 #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15893 #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
<> 144:ef7eb2e8f9f7 15894 #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
<> 144:ef7eb2e8f9f7 15895 #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15896 #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
<> 144:ef7eb2e8f9f7 15897 #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15898 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15899 #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
<> 144:ef7eb2e8f9f7 15900
<> 144:ef7eb2e8f9f7 15901 /*! @name RX_TOG - USB PHY Receiver Control Register */
<> 144:ef7eb2e8f9f7 15902 #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
<> 144:ef7eb2e8f9f7 15903 #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
<> 144:ef7eb2e8f9f7 15904 #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
<> 144:ef7eb2e8f9f7 15905 #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
<> 144:ef7eb2e8f9f7 15906 #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15907 #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
<> 144:ef7eb2e8f9f7 15908 #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
<> 144:ef7eb2e8f9f7 15909 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
<> 144:ef7eb2e8f9f7 15910 #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
<> 144:ef7eb2e8f9f7 15911
<> 144:ef7eb2e8f9f7 15912 /*! @name CTRL - USB PHY General Control Register */
<> 144:ef7eb2e8f9f7 15913 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15914 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15915 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
<> 144:ef7eb2e8f9f7 15916 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15917 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15918 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
<> 144:ef7eb2e8f9f7 15919 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15920 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15921 #define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
<> 144:ef7eb2e8f9f7 15922 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15923 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15924 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
<> 144:ef7eb2e8f9f7 15925 #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 15926 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15927 #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
<> 144:ef7eb2e8f9f7 15928 #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 15929 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
<> 144:ef7eb2e8f9f7 15930 #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
<> 144:ef7eb2e8f9f7 15931 #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15932 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15933 #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
<> 144:ef7eb2e8f9f7 15934 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15935 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15936 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 15937 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15938 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15939 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
<> 144:ef7eb2e8f9f7 15940 #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15941 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15942 #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
<> 144:ef7eb2e8f9f7 15943 #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 15944 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 15945 #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
<> 144:ef7eb2e8f9f7 15946 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 15947 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 15948 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
<> 144:ef7eb2e8f9f7 15949 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 15950 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
<> 144:ef7eb2e8f9f7 15951 #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
<> 144:ef7eb2e8f9f7 15952 #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 15953 #define USBPHY_CTRL_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 15954 #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 15955 #define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 15956 #define USBPHY_CTRL_SFTRST_SHIFT (31U)
<> 144:ef7eb2e8f9f7 15957 #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
<> 144:ef7eb2e8f9f7 15958
<> 144:ef7eb2e8f9f7 15959 /*! @name CTRL_SET - USB PHY General Control Register */
<> 144:ef7eb2e8f9f7 15960 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 15961 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 15962 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
<> 144:ef7eb2e8f9f7 15963 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 15964 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 15965 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
<> 144:ef7eb2e8f9f7 15966 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
<> 144:ef7eb2e8f9f7 15967 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
<> 144:ef7eb2e8f9f7 15968 #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
<> 144:ef7eb2e8f9f7 15969 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 15970 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
<> 144:ef7eb2e8f9f7 15971 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
<> 144:ef7eb2e8f9f7 15972 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 15973 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
<> 144:ef7eb2e8f9f7 15974 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
<> 144:ef7eb2e8f9f7 15975 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 15976 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
<> 144:ef7eb2e8f9f7 15977 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
<> 144:ef7eb2e8f9f7 15978 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 15979 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 15980 #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
<> 144:ef7eb2e8f9f7 15981 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 15982 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 15983 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 15984 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 15985 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
<> 144:ef7eb2e8f9f7 15986 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
<> 144:ef7eb2e8f9f7 15987 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 15988 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 15989 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
<> 144:ef7eb2e8f9f7 15990 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 15991 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 15992 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
<> 144:ef7eb2e8f9f7 15993 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 15994 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 15995 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
<> 144:ef7eb2e8f9f7 15996 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 15997 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
<> 144:ef7eb2e8f9f7 15998 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
<> 144:ef7eb2e8f9f7 15999 #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16000 #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16001 #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16002 #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16003 #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16004 #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
<> 144:ef7eb2e8f9f7 16005
<> 144:ef7eb2e8f9f7 16006 /*! @name CTRL_CLR - USB PHY General Control Register */
<> 144:ef7eb2e8f9f7 16007 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16008 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16009 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
<> 144:ef7eb2e8f9f7 16010 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16011 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16012 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
<> 144:ef7eb2e8f9f7 16013 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16014 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16015 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
<> 144:ef7eb2e8f9f7 16016 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16017 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16018 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
<> 144:ef7eb2e8f9f7 16019 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 16020 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
<> 144:ef7eb2e8f9f7 16021 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
<> 144:ef7eb2e8f9f7 16022 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 16023 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
<> 144:ef7eb2e8f9f7 16024 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
<> 144:ef7eb2e8f9f7 16025 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 16026 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16027 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
<> 144:ef7eb2e8f9f7 16028 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 16029 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 16030 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16031 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 16032 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16033 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
<> 144:ef7eb2e8f9f7 16034 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 16035 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16036 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
<> 144:ef7eb2e8f9f7 16037 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 16038 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 16039 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
<> 144:ef7eb2e8f9f7 16040 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 16041 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 16042 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
<> 144:ef7eb2e8f9f7 16043 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 16044 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
<> 144:ef7eb2e8f9f7 16045 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
<> 144:ef7eb2e8f9f7 16046 #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16047 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16048 #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16049 #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16050 #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16051 #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
<> 144:ef7eb2e8f9f7 16052
<> 144:ef7eb2e8f9f7 16053 /*! @name CTRL_TOG - USB PHY General Control Register */
<> 144:ef7eb2e8f9f7 16054 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16055 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16056 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
<> 144:ef7eb2e8f9f7 16057 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16058 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16059 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
<> 144:ef7eb2e8f9f7 16060 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16061 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16062 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
<> 144:ef7eb2e8f9f7 16063 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16064 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16065 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
<> 144:ef7eb2e8f9f7 16066 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 16067 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
<> 144:ef7eb2e8f9f7 16068 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
<> 144:ef7eb2e8f9f7 16069 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 16070 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
<> 144:ef7eb2e8f9f7 16071 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
<> 144:ef7eb2e8f9f7 16072 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 16073 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16074 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
<> 144:ef7eb2e8f9f7 16075 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
<> 144:ef7eb2e8f9f7 16076 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
<> 144:ef7eb2e8f9f7 16077 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16078 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 16079 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16080 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
<> 144:ef7eb2e8f9f7 16081 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 16082 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16083 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
<> 144:ef7eb2e8f9f7 16084 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
<> 144:ef7eb2e8f9f7 16085 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
<> 144:ef7eb2e8f9f7 16086 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
<> 144:ef7eb2e8f9f7 16087 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
<> 144:ef7eb2e8f9f7 16088 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
<> 144:ef7eb2e8f9f7 16089 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
<> 144:ef7eb2e8f9f7 16090 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 16091 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
<> 144:ef7eb2e8f9f7 16092 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
<> 144:ef7eb2e8f9f7 16093 #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16094 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16095 #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16096 #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16097 #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16098 #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
<> 144:ef7eb2e8f9f7 16099
<> 144:ef7eb2e8f9f7 16100 /*! @name STATUS - USB PHY Status Register */
<> 144:ef7eb2e8f9f7 16101 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16102 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16103 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
<> 144:ef7eb2e8f9f7 16104 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16105 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16106 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
<> 144:ef7eb2e8f9f7 16107 #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16108 #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16109 #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
<> 144:ef7eb2e8f9f7 16110 #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
<> 144:ef7eb2e8f9f7 16111 #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
<> 144:ef7eb2e8f9f7 16112 #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
<> 144:ef7eb2e8f9f7 16113
<> 144:ef7eb2e8f9f7 16114 /*! @name DEBUG - USB PHY Debug Register */
<> 144:ef7eb2e8f9f7 16115 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16116 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16117 #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
<> 144:ef7eb2e8f9f7 16118 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16119 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16120 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
<> 144:ef7eb2e8f9f7 16121 #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16122 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16123 #define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16124 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 16125 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16126 #define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16127 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 16128 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16129 #define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16130 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16131 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16132 #define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16133 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 16134 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16135 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16136 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 16137 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16138 #define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
<> 144:ef7eb2e8f9f7 16139 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
<> 144:ef7eb2e8f9f7 16140 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
<> 144:ef7eb2e8f9f7 16141 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
<> 144:ef7eb2e8f9f7 16142 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 16143 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
<> 144:ef7eb2e8f9f7 16144 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
<> 144:ef7eb2e8f9f7 16145 #define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16146 #define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16147 #define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16148
<> 144:ef7eb2e8f9f7 16149 /*! @name DEBUG_SET - USB PHY Debug Register */
<> 144:ef7eb2e8f9f7 16150 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16151 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16152 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
<> 144:ef7eb2e8f9f7 16153 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16154 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16155 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
<> 144:ef7eb2e8f9f7 16156 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16157 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16158 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16159 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 16160 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16161 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16162 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 16163 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16164 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16165 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16166 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16167 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16168 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 16169 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16170 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16171 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 16172 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16173 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
<> 144:ef7eb2e8f9f7 16174 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
<> 144:ef7eb2e8f9f7 16175 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
<> 144:ef7eb2e8f9f7 16176 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
<> 144:ef7eb2e8f9f7 16177 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 16178 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
<> 144:ef7eb2e8f9f7 16179 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
<> 144:ef7eb2e8f9f7 16180 #define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16181 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16182 #define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16183
<> 144:ef7eb2e8f9f7 16184 /*! @name DEBUG_CLR - USB PHY Debug Register */
<> 144:ef7eb2e8f9f7 16185 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16186 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16187 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
<> 144:ef7eb2e8f9f7 16188 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16189 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16190 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
<> 144:ef7eb2e8f9f7 16191 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16192 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16193 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16194 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 16195 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16196 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16197 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 16198 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16199 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16200 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16201 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16202 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16203 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 16204 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16205 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16206 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 16207 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16208 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
<> 144:ef7eb2e8f9f7 16209 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
<> 144:ef7eb2e8f9f7 16210 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
<> 144:ef7eb2e8f9f7 16211 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
<> 144:ef7eb2e8f9f7 16212 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 16213 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
<> 144:ef7eb2e8f9f7 16214 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
<> 144:ef7eb2e8f9f7 16215 #define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16216 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16217 #define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16218
<> 144:ef7eb2e8f9f7 16219 /*! @name DEBUG_TOG - USB PHY Debug Register */
<> 144:ef7eb2e8f9f7 16220 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16221 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16222 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
<> 144:ef7eb2e8f9f7 16223 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16224 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16225 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
<> 144:ef7eb2e8f9f7 16226 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16227 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16228 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16229 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
<> 144:ef7eb2e8f9f7 16230 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16231 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16232 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
<> 144:ef7eb2e8f9f7 16233 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16234 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16235 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16236 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16237 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16238 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
<> 144:ef7eb2e8f9f7 16239 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16240 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
<> 144:ef7eb2e8f9f7 16241 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
<> 144:ef7eb2e8f9f7 16242 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16243 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
<> 144:ef7eb2e8f9f7 16244 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
<> 144:ef7eb2e8f9f7 16245 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
<> 144:ef7eb2e8f9f7 16246 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
<> 144:ef7eb2e8f9f7 16247 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
<> 144:ef7eb2e8f9f7 16248 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
<> 144:ef7eb2e8f9f7 16249 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
<> 144:ef7eb2e8f9f7 16250 #define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
<> 144:ef7eb2e8f9f7 16251 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
<> 144:ef7eb2e8f9f7 16252 #define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16253
<> 144:ef7eb2e8f9f7 16254 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
<> 144:ef7eb2e8f9f7 16255 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 16256 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16257 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
<> 144:ef7eb2e8f9f7 16258 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
<> 144:ef7eb2e8f9f7 16259 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16260 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
<> 144:ef7eb2e8f9f7 16261 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
<> 144:ef7eb2e8f9f7 16262 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
<> 144:ef7eb2e8f9f7 16263 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
<> 144:ef7eb2e8f9f7 16264
<> 144:ef7eb2e8f9f7 16265 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
<> 144:ef7eb2e8f9f7 16266 #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
<> 144:ef7eb2e8f9f7 16267 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16268 #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
<> 144:ef7eb2e8f9f7 16269
<> 144:ef7eb2e8f9f7 16270 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
<> 144:ef7eb2e8f9f7 16271 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
<> 144:ef7eb2e8f9f7 16272 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16273 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
<> 144:ef7eb2e8f9f7 16274
<> 144:ef7eb2e8f9f7 16275 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
<> 144:ef7eb2e8f9f7 16276 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
<> 144:ef7eb2e8f9f7 16277 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16278 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
<> 144:ef7eb2e8f9f7 16279
<> 144:ef7eb2e8f9f7 16280 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
<> 144:ef7eb2e8f9f7 16281 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
<> 144:ef7eb2e8f9f7 16282 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16283 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
<> 144:ef7eb2e8f9f7 16284
<> 144:ef7eb2e8f9f7 16285 /*! @name VERSION - UTMI RTL Version */
<> 144:ef7eb2e8f9f7 16286 #define USBPHY_VERSION_STEP_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 16287 #define USBPHY_VERSION_STEP_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16288 #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
<> 144:ef7eb2e8f9f7 16289 #define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 16290 #define USBPHY_VERSION_MINOR_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16291 #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
<> 144:ef7eb2e8f9f7 16292 #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 16293 #define USBPHY_VERSION_MAJOR_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16294 #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
<> 144:ef7eb2e8f9f7 16295
<> 144:ef7eb2e8f9f7 16296 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
<> 144:ef7eb2e8f9f7 16297 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 16298 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16299 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16300 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16301 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16302 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
<> 144:ef7eb2e8f9f7 16303 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK (0x800U)
<> 144:ef7eb2e8f9f7 16304 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16305 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
<> 144:ef7eb2e8f9f7 16306 #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16307 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16308 #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
<> 144:ef7eb2e8f9f7 16309 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16310 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16311 #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
<> 144:ef7eb2e8f9f7 16312 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 16313 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16314 #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
<> 144:ef7eb2e8f9f7 16315 #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16316 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16317 #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
<> 144:ef7eb2e8f9f7 16318
<> 144:ef7eb2e8f9f7 16319 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
<> 144:ef7eb2e8f9f7 16320 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 16321 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16322 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16323 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16324 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16325 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
<> 144:ef7eb2e8f9f7 16326 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
<> 144:ef7eb2e8f9f7 16327 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16328 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
<> 144:ef7eb2e8f9f7 16329 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16330 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16331 #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
<> 144:ef7eb2e8f9f7 16332 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16333 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16334 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
<> 144:ef7eb2e8f9f7 16335 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 16336 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16337 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
<> 144:ef7eb2e8f9f7 16338 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16339 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16340 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
<> 144:ef7eb2e8f9f7 16341
<> 144:ef7eb2e8f9f7 16342 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
<> 144:ef7eb2e8f9f7 16343 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 16344 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16345 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16346 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16347 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16348 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
<> 144:ef7eb2e8f9f7 16349 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
<> 144:ef7eb2e8f9f7 16350 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16351 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
<> 144:ef7eb2e8f9f7 16352 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16353 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16354 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
<> 144:ef7eb2e8f9f7 16355 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16356 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16357 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
<> 144:ef7eb2e8f9f7 16358 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 16359 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16360 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
<> 144:ef7eb2e8f9f7 16361 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16362 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16363 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
<> 144:ef7eb2e8f9f7 16364
<> 144:ef7eb2e8f9f7 16365 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
<> 144:ef7eb2e8f9f7 16366 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x3U)
<> 144:ef7eb2e8f9f7 16367 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16368 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16369 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16370 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16371 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
<> 144:ef7eb2e8f9f7 16372 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
<> 144:ef7eb2e8f9f7 16373 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16374 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
<> 144:ef7eb2e8f9f7 16375 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
<> 144:ef7eb2e8f9f7 16376 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
<> 144:ef7eb2e8f9f7 16377 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
<> 144:ef7eb2e8f9f7 16378 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16379 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16380 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
<> 144:ef7eb2e8f9f7 16381 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
<> 144:ef7eb2e8f9f7 16382 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16383 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
<> 144:ef7eb2e8f9f7 16384 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16385 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16386 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
<> 144:ef7eb2e8f9f7 16387
<> 144:ef7eb2e8f9f7 16388 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
<> 144:ef7eb2e8f9f7 16389 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
<> 144:ef7eb2e8f9f7 16390 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16391 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
<> 144:ef7eb2e8f9f7 16392 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16393 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16394 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
<> 144:ef7eb2e8f9f7 16395 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16396 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16397 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16398 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16399 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16400 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16401 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16402 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16403 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16404 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16405 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16406 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16407 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16408 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16409 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
<> 144:ef7eb2e8f9f7 16410 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
<> 144:ef7eb2e8f9f7 16411 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
<> 144:ef7eb2e8f9f7 16412 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
<> 144:ef7eb2e8f9f7 16413 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 16414 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16415 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
<> 144:ef7eb2e8f9f7 16416 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 16417 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16418 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
<> 144:ef7eb2e8f9f7 16419 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 16420 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
<> 144:ef7eb2e8f9f7 16421 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
<> 144:ef7eb2e8f9f7 16422 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16423 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16424 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
<> 144:ef7eb2e8f9f7 16425
<> 144:ef7eb2e8f9f7 16426 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
<> 144:ef7eb2e8f9f7 16427 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
<> 144:ef7eb2e8f9f7 16428 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16429 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
<> 144:ef7eb2e8f9f7 16430 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16431 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16432 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
<> 144:ef7eb2e8f9f7 16433 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16434 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16435 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16436 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16437 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16438 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16439 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16440 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16441 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16442 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16443 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16444 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16445 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16446 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16447 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
<> 144:ef7eb2e8f9f7 16448 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
<> 144:ef7eb2e8f9f7 16449 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
<> 144:ef7eb2e8f9f7 16450 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
<> 144:ef7eb2e8f9f7 16451 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 16452 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16453 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
<> 144:ef7eb2e8f9f7 16454 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 16455 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16456 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
<> 144:ef7eb2e8f9f7 16457 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 16458 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
<> 144:ef7eb2e8f9f7 16459 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
<> 144:ef7eb2e8f9f7 16460 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16461 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16462 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
<> 144:ef7eb2e8f9f7 16463
<> 144:ef7eb2e8f9f7 16464 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
<> 144:ef7eb2e8f9f7 16465 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
<> 144:ef7eb2e8f9f7 16466 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16467 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
<> 144:ef7eb2e8f9f7 16468 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16469 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16470 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
<> 144:ef7eb2e8f9f7 16471 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16472 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16473 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16474 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16475 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16476 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16477 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16478 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16479 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16480 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16481 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16482 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16483 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16484 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16485 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
<> 144:ef7eb2e8f9f7 16486 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
<> 144:ef7eb2e8f9f7 16487 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
<> 144:ef7eb2e8f9f7 16488 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
<> 144:ef7eb2e8f9f7 16489 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 16490 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16491 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
<> 144:ef7eb2e8f9f7 16492 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 16493 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16494 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
<> 144:ef7eb2e8f9f7 16495 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 16496 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
<> 144:ef7eb2e8f9f7 16497 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
<> 144:ef7eb2e8f9f7 16498 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16499 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16500 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
<> 144:ef7eb2e8f9f7 16501
<> 144:ef7eb2e8f9f7 16502 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
<> 144:ef7eb2e8f9f7 16503 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
<> 144:ef7eb2e8f9f7 16504 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16505 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
<> 144:ef7eb2e8f9f7 16506 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16507 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16508 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
<> 144:ef7eb2e8f9f7 16509 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16510 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16511 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16512 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16513 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16514 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16515 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16516 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16517 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16518 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16519 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16520 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16521 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16522 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16523 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
<> 144:ef7eb2e8f9f7 16524 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
<> 144:ef7eb2e8f9f7 16525 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
<> 144:ef7eb2e8f9f7 16526 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
<> 144:ef7eb2e8f9f7 16527 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
<> 144:ef7eb2e8f9f7 16528 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16529 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
<> 144:ef7eb2e8f9f7 16530 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
<> 144:ef7eb2e8f9f7 16531 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16532 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
<> 144:ef7eb2e8f9f7 16533 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
<> 144:ef7eb2e8f9f7 16534 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
<> 144:ef7eb2e8f9f7 16535 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
<> 144:ef7eb2e8f9f7 16536 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16537 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16538 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
<> 144:ef7eb2e8f9f7 16539
<> 144:ef7eb2e8f9f7 16540 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
<> 144:ef7eb2e8f9f7 16541 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16542 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16543 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
<> 144:ef7eb2e8f9f7 16544 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16545 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16546 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
<> 144:ef7eb2e8f9f7 16547 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16548 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16549 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
<> 144:ef7eb2e8f9f7 16550 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16551 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16552 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
<> 144:ef7eb2e8f9f7 16553 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16554 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16555 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
<> 144:ef7eb2e8f9f7 16556
<> 144:ef7eb2e8f9f7 16557 /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
<> 144:ef7eb2e8f9f7 16558 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16559 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16560 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
<> 144:ef7eb2e8f9f7 16561 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16562 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16563 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
<> 144:ef7eb2e8f9f7 16564 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16565 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16566 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
<> 144:ef7eb2e8f9f7 16567 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16568 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16569 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
<> 144:ef7eb2e8f9f7 16570 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16571 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16572 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
<> 144:ef7eb2e8f9f7 16573
<> 144:ef7eb2e8f9f7 16574 /*! @name ANACTRL - USB PHY Analog Control Register */
<> 144:ef7eb2e8f9f7 16575 #define USBPHY_ANACTRL_TESTCLK_SEL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16576 #define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16577 #define USBPHY_ANACTRL_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16578 #define USBPHY_ANACTRL_PFD_CLKGATE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16579 #define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16580 #define USBPHY_ANACTRL_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16581 #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16582 #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16583 #define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16584 #define USBPHY_ANACTRL_PFD_FRAC_MASK (0x3F0U)
<> 144:ef7eb2e8f9f7 16585 #define USBPHY_ANACTRL_PFD_FRAC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16586 #define USBPHY_ANACTRL_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
<> 144:ef7eb2e8f9f7 16587 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
<> 144:ef7eb2e8f9f7 16588 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
<> 144:ef7eb2e8f9f7 16589 #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16590 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK (0x1800U)
<> 144:ef7eb2e8f9f7 16591 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16592 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16593 #define USBPHY_ANACTRL_EMPH_EN_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16594 #define USBPHY_ANACTRL_EMPH_EN_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16595 #define USBPHY_ANACTRL_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
<> 144:ef7eb2e8f9f7 16596 #define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 16597 #define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT (14U)
<> 144:ef7eb2e8f9f7 16598 #define USBPHY_ANACTRL_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16599 #define USBPHY_ANACTRL_PFD_STABLE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16600 #define USBPHY_ANACTRL_PFD_STABLE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16601 #define USBPHY_ANACTRL_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
<> 144:ef7eb2e8f9f7 16602
<> 144:ef7eb2e8f9f7 16603 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
<> 144:ef7eb2e8f9f7 16604 #define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16605 #define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16606 #define USBPHY_ANACTRL_SET_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16607 #define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16608 #define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16609 #define USBPHY_ANACTRL_SET_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16610 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16611 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16612 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16613 #define USBPHY_ANACTRL_SET_PFD_FRAC_MASK (0x3F0U)
<> 144:ef7eb2e8f9f7 16614 #define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16615 #define USBPHY_ANACTRL_SET_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
<> 144:ef7eb2e8f9f7 16616 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
<> 144:ef7eb2e8f9f7 16617 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
<> 144:ef7eb2e8f9f7 16618 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16619 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK (0x1800U)
<> 144:ef7eb2e8f9f7 16620 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16621 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16622 #define USBPHY_ANACTRL_SET_EMPH_EN_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16623 #define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16624 #define USBPHY_ANACTRL_SET_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
<> 144:ef7eb2e8f9f7 16625 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 16626 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT (14U)
<> 144:ef7eb2e8f9f7 16627 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16628 #define USBPHY_ANACTRL_SET_PFD_STABLE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16629 #define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16630 #define USBPHY_ANACTRL_SET_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
<> 144:ef7eb2e8f9f7 16631
<> 144:ef7eb2e8f9f7 16632 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
<> 144:ef7eb2e8f9f7 16633 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16634 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16635 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16636 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16637 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16638 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16639 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16640 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16641 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16642 #define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK (0x3F0U)
<> 144:ef7eb2e8f9f7 16643 #define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16644 #define USBPHY_ANACTRL_CLR_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
<> 144:ef7eb2e8f9f7 16645 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
<> 144:ef7eb2e8f9f7 16646 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
<> 144:ef7eb2e8f9f7 16647 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16648 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK (0x1800U)
<> 144:ef7eb2e8f9f7 16649 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16650 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16651 #define USBPHY_ANACTRL_CLR_EMPH_EN_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16652 #define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16653 #define USBPHY_ANACTRL_CLR_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
<> 144:ef7eb2e8f9f7 16654 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 16655 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT (14U)
<> 144:ef7eb2e8f9f7 16656 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16657 #define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16658 #define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16659 #define USBPHY_ANACTRL_CLR_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
<> 144:ef7eb2e8f9f7 16660
<> 144:ef7eb2e8f9f7 16661 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
<> 144:ef7eb2e8f9f7 16662 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16663 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16664 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16665 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16666 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16667 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
<> 144:ef7eb2e8f9f7 16668 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
<> 144:ef7eb2e8f9f7 16669 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16670 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
<> 144:ef7eb2e8f9f7 16671 #define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK (0x3F0U)
<> 144:ef7eb2e8f9f7 16672 #define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16673 #define USBPHY_ANACTRL_TOG_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
<> 144:ef7eb2e8f9f7 16674 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
<> 144:ef7eb2e8f9f7 16675 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
<> 144:ef7eb2e8f9f7 16676 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
<> 144:ef7eb2e8f9f7 16677 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK (0x1800U)
<> 144:ef7eb2e8f9f7 16678 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
<> 144:ef7eb2e8f9f7 16679 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16680 #define USBPHY_ANACTRL_TOG_EMPH_EN_MASK (0x2000U)
<> 144:ef7eb2e8f9f7 16681 #define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT (13U)
<> 144:ef7eb2e8f9f7 16682 #define USBPHY_ANACTRL_TOG_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
<> 144:ef7eb2e8f9f7 16683 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK (0xC000U)
<> 144:ef7eb2e8f9f7 16684 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT (14U)
<> 144:ef7eb2e8f9f7 16685 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
<> 144:ef7eb2e8f9f7 16686 #define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK (0x80000000U)
<> 144:ef7eb2e8f9f7 16687 #define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT (31U)
<> 144:ef7eb2e8f9f7 16688 #define USBPHY_ANACTRL_TOG_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
<> 144:ef7eb2e8f9f7 16689
<> 144:ef7eb2e8f9f7 16690 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
<> 144:ef7eb2e8f9f7 16691 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16692 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16693 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
<> 144:ef7eb2e8f9f7 16694 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16695 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16696 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16697 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16698 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16699 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16700 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16701 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16702 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16703 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16704 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16705 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16706 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16707 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16708 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
<> 144:ef7eb2e8f9f7 16709 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16710 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16711 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
<> 144:ef7eb2e8f9f7 16712 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16713 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16714 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16715 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16716 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16717 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16718 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 16719 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 16720 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
<> 144:ef7eb2e8f9f7 16721 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 16722 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16723 #define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
<> 144:ef7eb2e8f9f7 16724
<> 144:ef7eb2e8f9f7 16725 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
<> 144:ef7eb2e8f9f7 16726 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16727 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16728 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
<> 144:ef7eb2e8f9f7 16729 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16730 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16731 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16732 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16733 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16734 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16735 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16736 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16737 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16738 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16739 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16740 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16741 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16742 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16743 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
<> 144:ef7eb2e8f9f7 16744 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16745 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16746 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
<> 144:ef7eb2e8f9f7 16747 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16748 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16749 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16750 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16751 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16752 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16753 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 16754 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 16755 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
<> 144:ef7eb2e8f9f7 16756 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 16757 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16758 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
<> 144:ef7eb2e8f9f7 16759
<> 144:ef7eb2e8f9f7 16760 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
<> 144:ef7eb2e8f9f7 16761 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16762 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16763 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
<> 144:ef7eb2e8f9f7 16764 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16765 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16766 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16767 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16768 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16769 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16770 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16771 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16772 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16773 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16774 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16775 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16776 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16777 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16778 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
<> 144:ef7eb2e8f9f7 16779 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16780 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16781 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
<> 144:ef7eb2e8f9f7 16782 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16783 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16784 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16785 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16786 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16787 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16788 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 16789 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 16790 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
<> 144:ef7eb2e8f9f7 16791 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 16792 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16793 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
<> 144:ef7eb2e8f9f7 16794
<> 144:ef7eb2e8f9f7 16795 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
<> 144:ef7eb2e8f9f7 16796 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16797 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16798 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
<> 144:ef7eb2e8f9f7 16799 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16800 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16801 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16802 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16803 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16804 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16805 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16806 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16807 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16808 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16809 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16810 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
<> 144:ef7eb2e8f9f7 16811 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 16812 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 16813 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
<> 144:ef7eb2e8f9f7 16814 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
<> 144:ef7eb2e8f9f7 16815 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
<> 144:ef7eb2e8f9f7 16816 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
<> 144:ef7eb2e8f9f7 16817 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
<> 144:ef7eb2e8f9f7 16818 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
<> 144:ef7eb2e8f9f7 16819 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
<> 144:ef7eb2e8f9f7 16820 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
<> 144:ef7eb2e8f9f7 16821 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
<> 144:ef7eb2e8f9f7 16822 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
<> 144:ef7eb2e8f9f7 16823 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 16824 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
<> 144:ef7eb2e8f9f7 16825 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
<> 144:ef7eb2e8f9f7 16826 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
<> 144:ef7eb2e8f9f7 16827 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16828 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
<> 144:ef7eb2e8f9f7 16829
<> 144:ef7eb2e8f9f7 16830 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
<> 144:ef7eb2e8f9f7 16831 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 16832 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16833 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16834 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 16835 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16836 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16837
<> 144:ef7eb2e8f9f7 16838 /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
<> 144:ef7eb2e8f9f7 16839 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 16840 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16841 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16842 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 16843 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16844 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16845
<> 144:ef7eb2e8f9f7 16846 /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
<> 144:ef7eb2e8f9f7 16847 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 16848 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16849 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16850 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 16851 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16852 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16853
<> 144:ef7eb2e8f9f7 16854 /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
<> 144:ef7eb2e8f9f7 16855 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 16856 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16857 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16858 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
<> 144:ef7eb2e8f9f7 16859 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16860 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
<> 144:ef7eb2e8f9f7 16861
<> 144:ef7eb2e8f9f7 16862 /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
<> 144:ef7eb2e8f9f7 16863 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16864 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16865 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16866 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16867 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16868 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16869 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16870 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16871 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16872 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16873 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16874 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16875 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16876 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16877 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16878 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 16879 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16880 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16881 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 16882 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16883 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
<> 144:ef7eb2e8f9f7 16884 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 16885 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16886 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 16887 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 16888 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16889 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
<> 144:ef7eb2e8f9f7 16890 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 16891 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
<> 144:ef7eb2e8f9f7 16892 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
<> 144:ef7eb2e8f9f7 16893
<> 144:ef7eb2e8f9f7 16894 /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
<> 144:ef7eb2e8f9f7 16895 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16896 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16897 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16898 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16899 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16900 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16901 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16902 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16903 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16904 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16905 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16906 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16907 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16908 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16909 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16910 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 16911 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16912 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16913 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 16914 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16915 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
<> 144:ef7eb2e8f9f7 16916 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 16917 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16918 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 16919 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 16920 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16921 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
<> 144:ef7eb2e8f9f7 16922 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 16923 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
<> 144:ef7eb2e8f9f7 16924 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
<> 144:ef7eb2e8f9f7 16925
<> 144:ef7eb2e8f9f7 16926 /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
<> 144:ef7eb2e8f9f7 16927 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16928 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16929 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16930 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16931 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16932 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16933 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16934 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16935 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16936 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16937 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16938 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16939 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16940 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16941 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16942 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 16943 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16944 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16945 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 16946 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16947 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
<> 144:ef7eb2e8f9f7 16948 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 16949 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16950 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 16951 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 16952 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16953 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
<> 144:ef7eb2e8f9f7 16954 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 16955 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
<> 144:ef7eb2e8f9f7 16956 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
<> 144:ef7eb2e8f9f7 16957
<> 144:ef7eb2e8f9f7 16958 /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
<> 144:ef7eb2e8f9f7 16959 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
<> 144:ef7eb2e8f9f7 16960 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
<> 144:ef7eb2e8f9f7 16961 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16962 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
<> 144:ef7eb2e8f9f7 16963 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
<> 144:ef7eb2e8f9f7 16964 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16965 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
<> 144:ef7eb2e8f9f7 16966 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
<> 144:ef7eb2e8f9f7 16967 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16968 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
<> 144:ef7eb2e8f9f7 16969 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
<> 144:ef7eb2e8f9f7 16970 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16971 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 16972 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 16973 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
<> 144:ef7eb2e8f9f7 16974 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
<> 144:ef7eb2e8f9f7 16975 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
<> 144:ef7eb2e8f9f7 16976 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
<> 144:ef7eb2e8f9f7 16977 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
<> 144:ef7eb2e8f9f7 16978 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
<> 144:ef7eb2e8f9f7 16979 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
<> 144:ef7eb2e8f9f7 16980 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
<> 144:ef7eb2e8f9f7 16981 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
<> 144:ef7eb2e8f9f7 16982 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
<> 144:ef7eb2e8f9f7 16983 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
<> 144:ef7eb2e8f9f7 16984 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
<> 144:ef7eb2e8f9f7 16985 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
<> 144:ef7eb2e8f9f7 16986 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
<> 144:ef7eb2e8f9f7 16987 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
<> 144:ef7eb2e8f9f7 16988 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
<> 144:ef7eb2e8f9f7 16989
<> 144:ef7eb2e8f9f7 16990
<> 144:ef7eb2e8f9f7 16991 /*!
<> 144:ef7eb2e8f9f7 16992 * @}
<> 144:ef7eb2e8f9f7 16993 */ /* end of group USBPHY_Register_Masks */
<> 144:ef7eb2e8f9f7 16994
<> 144:ef7eb2e8f9f7 16995
<> 144:ef7eb2e8f9f7 16996 /* USBPHY - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 16997 /** Peripheral USBPHY base address */
<> 144:ef7eb2e8f9f7 16998 #define USBPHY_BASE (0x400A2000u)
<> 144:ef7eb2e8f9f7 16999 /** Peripheral USBPHY base pointer */
<> 144:ef7eb2e8f9f7 17000 #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
<> 144:ef7eb2e8f9f7 17001 /** Array initializer of USBPHY peripheral base addresses */
<> 144:ef7eb2e8f9f7 17002 #define USBPHY_BASE_ADDRS { USBPHY_BASE }
<> 144:ef7eb2e8f9f7 17003 /** Array initializer of USBPHY peripheral base pointers */
<> 144:ef7eb2e8f9f7 17004 #define USBPHY_BASE_PTRS { USBPHY }
<> 144:ef7eb2e8f9f7 17005
<> 144:ef7eb2e8f9f7 17006 /*!
<> 144:ef7eb2e8f9f7 17007 * @}
<> 144:ef7eb2e8f9f7 17008 */ /* end of group USBPHY_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 17009
<> 144:ef7eb2e8f9f7 17010
<> 144:ef7eb2e8f9f7 17011 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17012 -- VREF Peripheral Access Layer
<> 144:ef7eb2e8f9f7 17013 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 17014
<> 144:ef7eb2e8f9f7 17015 /*!
<> 144:ef7eb2e8f9f7 17016 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
<> 144:ef7eb2e8f9f7 17017 * @{
<> 144:ef7eb2e8f9f7 17018 */
<> 144:ef7eb2e8f9f7 17019
<> 144:ef7eb2e8f9f7 17020 /** VREF - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 17021 typedef struct {
<> 144:ef7eb2e8f9f7 17022 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
<> 144:ef7eb2e8f9f7 17023 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
<> 144:ef7eb2e8f9f7 17024 } VREF_Type;
<> 144:ef7eb2e8f9f7 17025
<> 144:ef7eb2e8f9f7 17026 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17027 -- VREF Register Masks
<> 144:ef7eb2e8f9f7 17028 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 17029
<> 144:ef7eb2e8f9f7 17030 /*!
<> 144:ef7eb2e8f9f7 17031 * @addtogroup VREF_Register_Masks VREF Register Masks
<> 144:ef7eb2e8f9f7 17032 * @{
<> 144:ef7eb2e8f9f7 17033 */
<> 144:ef7eb2e8f9f7 17034
<> 144:ef7eb2e8f9f7 17035 /*! @name TRM - VREF Trim Register */
<> 144:ef7eb2e8f9f7 17036 #define VREF_TRM_TRIM_MASK (0x3FU)
<> 144:ef7eb2e8f9f7 17037 #define VREF_TRM_TRIM_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17038 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
<> 144:ef7eb2e8f9f7 17039 #define VREF_TRM_CHOPEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 17040 #define VREF_TRM_CHOPEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 17041 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
<> 144:ef7eb2e8f9f7 17042
<> 144:ef7eb2e8f9f7 17043 /*! @name SC - VREF Status and Control Register */
<> 144:ef7eb2e8f9f7 17044 #define VREF_SC_MODE_LV_MASK (0x3U)
<> 144:ef7eb2e8f9f7 17045 #define VREF_SC_MODE_LV_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17046 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
<> 144:ef7eb2e8f9f7 17047 #define VREF_SC_VREFST_MASK (0x4U)
<> 144:ef7eb2e8f9f7 17048 #define VREF_SC_VREFST_SHIFT (2U)
<> 144:ef7eb2e8f9f7 17049 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
<> 144:ef7eb2e8f9f7 17050 #define VREF_SC_ICOMPEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 17051 #define VREF_SC_ICOMPEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 17052 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
<> 144:ef7eb2e8f9f7 17053 #define VREF_SC_REGEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 17054 #define VREF_SC_REGEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 17055 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
<> 144:ef7eb2e8f9f7 17056 #define VREF_SC_VREFEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 17057 #define VREF_SC_VREFEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 17058 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
<> 144:ef7eb2e8f9f7 17059
<> 144:ef7eb2e8f9f7 17060
<> 144:ef7eb2e8f9f7 17061 /*!
<> 144:ef7eb2e8f9f7 17062 * @}
<> 144:ef7eb2e8f9f7 17063 */ /* end of group VREF_Register_Masks */
<> 144:ef7eb2e8f9f7 17064
<> 144:ef7eb2e8f9f7 17065
<> 144:ef7eb2e8f9f7 17066 /* VREF - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 17067 /** Peripheral VREF base address */
<> 144:ef7eb2e8f9f7 17068 #define VREF_BASE (0x40074000u)
<> 144:ef7eb2e8f9f7 17069 /** Peripheral VREF base pointer */
<> 144:ef7eb2e8f9f7 17070 #define VREF ((VREF_Type *)VREF_BASE)
<> 144:ef7eb2e8f9f7 17071 /** Array initializer of VREF peripheral base addresses */
<> 144:ef7eb2e8f9f7 17072 #define VREF_BASE_ADDRS { VREF_BASE }
<> 144:ef7eb2e8f9f7 17073 /** Array initializer of VREF peripheral base pointers */
<> 144:ef7eb2e8f9f7 17074 #define VREF_BASE_PTRS { VREF }
<> 144:ef7eb2e8f9f7 17075
<> 144:ef7eb2e8f9f7 17076 /*!
<> 144:ef7eb2e8f9f7 17077 * @}
<> 144:ef7eb2e8f9f7 17078 */ /* end of group VREF_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 17079
<> 144:ef7eb2e8f9f7 17080
<> 144:ef7eb2e8f9f7 17081 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17082 -- WDOG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 17083 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 17084
<> 144:ef7eb2e8f9f7 17085 /*!
<> 144:ef7eb2e8f9f7 17086 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
<> 144:ef7eb2e8f9f7 17087 * @{
<> 144:ef7eb2e8f9f7 17088 */
<> 144:ef7eb2e8f9f7 17089
<> 144:ef7eb2e8f9f7 17090 /** WDOG - Register Layout Typedef */
<> 144:ef7eb2e8f9f7 17091 typedef struct {
<> 144:ef7eb2e8f9f7 17092 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
<> 144:ef7eb2e8f9f7 17093 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
<> 144:ef7eb2e8f9f7 17094 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
<> 144:ef7eb2e8f9f7 17095 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
<> 144:ef7eb2e8f9f7 17096 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
<> 144:ef7eb2e8f9f7 17097 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
<> 144:ef7eb2e8f9f7 17098 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
<> 144:ef7eb2e8f9f7 17099 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
<> 144:ef7eb2e8f9f7 17100 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
<> 144:ef7eb2e8f9f7 17101 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
<> 144:ef7eb2e8f9f7 17102 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
<> 144:ef7eb2e8f9f7 17103 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
<> 144:ef7eb2e8f9f7 17104 } WDOG_Type;
<> 144:ef7eb2e8f9f7 17105
<> 144:ef7eb2e8f9f7 17106 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17107 -- WDOG Register Masks
<> 144:ef7eb2e8f9f7 17108 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 17109
<> 144:ef7eb2e8f9f7 17110 /*!
<> 144:ef7eb2e8f9f7 17111 * @addtogroup WDOG_Register_Masks WDOG Register Masks
<> 144:ef7eb2e8f9f7 17112 * @{
<> 144:ef7eb2e8f9f7 17113 */
<> 144:ef7eb2e8f9f7 17114
<> 144:ef7eb2e8f9f7 17115 /*! @name STCTRLH - Watchdog Status and Control Register High */
<> 144:ef7eb2e8f9f7 17116 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
<> 144:ef7eb2e8f9f7 17117 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17118 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
<> 144:ef7eb2e8f9f7 17119 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
<> 144:ef7eb2e8f9f7 17120 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
<> 144:ef7eb2e8f9f7 17121 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
<> 144:ef7eb2e8f9f7 17122 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
<> 144:ef7eb2e8f9f7 17123 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
<> 144:ef7eb2e8f9f7 17124 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
<> 144:ef7eb2e8f9f7 17125 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
<> 144:ef7eb2e8f9f7 17126 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
<> 144:ef7eb2e8f9f7 17127 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
<> 144:ef7eb2e8f9f7 17128 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
<> 144:ef7eb2e8f9f7 17129 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
<> 144:ef7eb2e8f9f7 17130 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
<> 144:ef7eb2e8f9f7 17131 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
<> 144:ef7eb2e8f9f7 17132 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
<> 144:ef7eb2e8f9f7 17133 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
<> 144:ef7eb2e8f9f7 17134 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
<> 144:ef7eb2e8f9f7 17135 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
<> 144:ef7eb2e8f9f7 17136 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
<> 144:ef7eb2e8f9f7 17137 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
<> 144:ef7eb2e8f9f7 17138 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
<> 144:ef7eb2e8f9f7 17139 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
<> 144:ef7eb2e8f9f7 17140 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
<> 144:ef7eb2e8f9f7 17141 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
<> 144:ef7eb2e8f9f7 17142 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
<> 144:ef7eb2e8f9f7 17143 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
<> 144:ef7eb2e8f9f7 17144 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
<> 144:ef7eb2e8f9f7 17145 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
<> 144:ef7eb2e8f9f7 17146 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
<> 144:ef7eb2e8f9f7 17147 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
<> 144:ef7eb2e8f9f7 17148 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
<> 144:ef7eb2e8f9f7 17149 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
<> 144:ef7eb2e8f9f7 17150 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
<> 144:ef7eb2e8f9f7 17151 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
<> 144:ef7eb2e8f9f7 17152
<> 144:ef7eb2e8f9f7 17153 /*! @name STCTRLL - Watchdog Status and Control Register Low */
<> 144:ef7eb2e8f9f7 17154 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
<> 144:ef7eb2e8f9f7 17155 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
<> 144:ef7eb2e8f9f7 17156 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
<> 144:ef7eb2e8f9f7 17157
<> 144:ef7eb2e8f9f7 17158 /*! @name TOVALH - Watchdog Time-out Value Register High */
<> 144:ef7eb2e8f9f7 17159 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17160 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17161 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
<> 144:ef7eb2e8f9f7 17162
<> 144:ef7eb2e8f9f7 17163 /*! @name TOVALL - Watchdog Time-out Value Register Low */
<> 144:ef7eb2e8f9f7 17164 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17165 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17166 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
<> 144:ef7eb2e8f9f7 17167
<> 144:ef7eb2e8f9f7 17168 /*! @name WINH - Watchdog Window Register High */
<> 144:ef7eb2e8f9f7 17169 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17170 #define WDOG_WINH_WINHIGH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17171 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
<> 144:ef7eb2e8f9f7 17172
<> 144:ef7eb2e8f9f7 17173 /*! @name WINL - Watchdog Window Register Low */
<> 144:ef7eb2e8f9f7 17174 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17175 #define WDOG_WINL_WINLOW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17176 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
<> 144:ef7eb2e8f9f7 17177
<> 144:ef7eb2e8f9f7 17178 /*! @name REFRESH - Watchdog Refresh register */
<> 144:ef7eb2e8f9f7 17179 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17180 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17181 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
<> 144:ef7eb2e8f9f7 17182
<> 144:ef7eb2e8f9f7 17183 /*! @name UNLOCK - Watchdog Unlock register */
<> 144:ef7eb2e8f9f7 17184 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17185 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17186 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
<> 144:ef7eb2e8f9f7 17187
<> 144:ef7eb2e8f9f7 17188 /*! @name TMROUTH - Watchdog Timer Output Register High */
<> 144:ef7eb2e8f9f7 17189 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17190 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17191 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
<> 144:ef7eb2e8f9f7 17192
<> 144:ef7eb2e8f9f7 17193 /*! @name TMROUTL - Watchdog Timer Output Register Low */
<> 144:ef7eb2e8f9f7 17194 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17195 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17196 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
<> 144:ef7eb2e8f9f7 17197
<> 144:ef7eb2e8f9f7 17198 /*! @name RSTCNT - Watchdog Reset Count register */
<> 144:ef7eb2e8f9f7 17199 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
<> 144:ef7eb2e8f9f7 17200 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
<> 144:ef7eb2e8f9f7 17201 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
<> 144:ef7eb2e8f9f7 17202
<> 144:ef7eb2e8f9f7 17203 /*! @name PRESC - Watchdog Prescaler register */
<> 144:ef7eb2e8f9f7 17204 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
<> 144:ef7eb2e8f9f7 17205 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
<> 144:ef7eb2e8f9f7 17206 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
<> 144:ef7eb2e8f9f7 17207
<> 144:ef7eb2e8f9f7 17208
<> 144:ef7eb2e8f9f7 17209 /*!
<> 144:ef7eb2e8f9f7 17210 * @}
<> 144:ef7eb2e8f9f7 17211 */ /* end of group WDOG_Register_Masks */
<> 144:ef7eb2e8f9f7 17212
<> 144:ef7eb2e8f9f7 17213
<> 144:ef7eb2e8f9f7 17214 /* WDOG - Peripheral instance base addresses */
<> 144:ef7eb2e8f9f7 17215 /** Peripheral WDOG base address */
<> 144:ef7eb2e8f9f7 17216 #define WDOG_BASE (0x40052000u)
<> 144:ef7eb2e8f9f7 17217 /** Peripheral WDOG base pointer */
<> 144:ef7eb2e8f9f7 17218 #define WDOG ((WDOG_Type *)WDOG_BASE)
<> 144:ef7eb2e8f9f7 17219 /** Array initializer of WDOG peripheral base addresses */
<> 144:ef7eb2e8f9f7 17220 #define WDOG_BASE_ADDRS { WDOG_BASE }
<> 144:ef7eb2e8f9f7 17221 /** Array initializer of WDOG peripheral base pointers */
<> 144:ef7eb2e8f9f7 17222 #define WDOG_BASE_PTRS { WDOG }
<> 144:ef7eb2e8f9f7 17223 /** Interrupt vectors for the WDOG peripheral type */
<> 144:ef7eb2e8f9f7 17224 #define WDOG_IRQS { WDOG_EWM_IRQn }
<> 144:ef7eb2e8f9f7 17225
<> 144:ef7eb2e8f9f7 17226 /*!
<> 144:ef7eb2e8f9f7 17227 * @}
<> 144:ef7eb2e8f9f7 17228 */ /* end of group WDOG_Peripheral_Access_Layer */
<> 144:ef7eb2e8f9f7 17229
<> 144:ef7eb2e8f9f7 17230
<> 144:ef7eb2e8f9f7 17231 /*
<> 144:ef7eb2e8f9f7 17232 ** End of section using anonymous unions
<> 144:ef7eb2e8f9f7 17233 */
<> 144:ef7eb2e8f9f7 17234
<> 144:ef7eb2e8f9f7 17235 #if defined(__ARMCC_VERSION)
<> 144:ef7eb2e8f9f7 17236 #pragma pop
<> 144:ef7eb2e8f9f7 17237 #elif defined(__CWCC__)
<> 144:ef7eb2e8f9f7 17238 #pragma pop
<> 144:ef7eb2e8f9f7 17239 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 17240 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 17241 #elif defined(__IAR_SYSTEMS_ICC__)
<> 144:ef7eb2e8f9f7 17242 #pragma language=default
<> 144:ef7eb2e8f9f7 17243 #else
<> 144:ef7eb2e8f9f7 17244 #error Not supported compiler type
<> 144:ef7eb2e8f9f7 17245 #endif
<> 144:ef7eb2e8f9f7 17246
<> 144:ef7eb2e8f9f7 17247 /*!
<> 144:ef7eb2e8f9f7 17248 * @}
<> 144:ef7eb2e8f9f7 17249 */ /* end of group Peripheral_access_layer */
<> 144:ef7eb2e8f9f7 17250
<> 144:ef7eb2e8f9f7 17251
<> 144:ef7eb2e8f9f7 17252 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17253 -- SDK Compatibility
<> 144:ef7eb2e8f9f7 17254 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 17255
<> 144:ef7eb2e8f9f7 17256 /*!
<> 144:ef7eb2e8f9f7 17257 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
<> 144:ef7eb2e8f9f7 17258 * @{
<> 144:ef7eb2e8f9f7 17259 */
<> 144:ef7eb2e8f9f7 17260
<> 144:ef7eb2e8f9f7 17261 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
<> 144:ef7eb2e8f9f7 17262 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
<> 144:ef7eb2e8f9f7 17263 #define FMC_PFB0CR_RFU_MASK FMC_PFB01CR_RFU_MASK
<> 144:ef7eb2e8f9f7 17264 #define FMC_PFB0CR_RFU_SHIFT FMC_PFB01CR_RFU_SHIFT
<> 144:ef7eb2e8f9f7 17265 #define FMC_PFB0CR_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
<> 144:ef7eb2e8f9f7 17266 #define FMC_PFB0CR_B0IPE_SHIFT FMC_PFB01CR_B0IPE_SHIFT
<> 144:ef7eb2e8f9f7 17267 #define FMC_PFB0CR_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
<> 144:ef7eb2e8f9f7 17268 #define FMC_PFB0CR_B0DPE_SHIFT FMC_PFB01CR_B0DPE_SHIFT
<> 144:ef7eb2e8f9f7 17269 #define FMC_PFB0CR_B0ICE_MASK FMC_PFB01CR_B0ICE_MASK
<> 144:ef7eb2e8f9f7 17270 #define FMC_PFB0CR_B0ICE_SHIFT FMC_PFB01CR_B0ICE_SHIFT
<> 144:ef7eb2e8f9f7 17271 #define FMC_PFB0CR_B0DCE_MASK FMC_PFB01CR_B0DCE_MASK
<> 144:ef7eb2e8f9f7 17272 #define FMC_PFB0CR_B0DCE_SHIFT FMC_PFB01CR_B0DCE_SHIFT
<> 144:ef7eb2e8f9f7 17273 #define FMC_PFB0CR_CRC_MASK FMC_PFB01CR_CRC_MASK
<> 144:ef7eb2e8f9f7 17274 #define FMC_PFB0CR_CRC_SHIFT FMC_PFB01CR_CRC_SHIFT
<> 144:ef7eb2e8f9f7 17275 #define FMC_PFB0CR_CRC(x) FMC_PFB01CR_CRC(x)
<> 144:ef7eb2e8f9f7 17276 #define FMC_PFB0CR_B0MW_MASK FMC_PFB01CR_B0MW_MASK
<> 144:ef7eb2e8f9f7 17277 #define FMC_PFB0CR_B0MW_SHIFT FMC_PFB01CR_B0MW_SHIFT
<> 144:ef7eb2e8f9f7 17278 #define FMC_PFB0CR_B0MW(x) FMC_PFB01CR_B0MW(x)
<> 144:ef7eb2e8f9f7 17279 #define FMC_PFB0CR_S_B_INV_MASK FMC_PFB01CR_S_B_INV_MASK
<> 144:ef7eb2e8f9f7 17280 #define FMC_PFB0CR_S_B_INV_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
<> 144:ef7eb2e8f9f7 17281 #define FMC_PFB0CR_CINV_WAY_MASK FMC_PFB01CR_CINV_WAY_MASK
<> 144:ef7eb2e8f9f7 17282 #define FMC_PFB0CR_CINV_WAY_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
<> 144:ef7eb2e8f9f7 17283 #define FMC_PFB0CR_CINV_WAY(x) FMC_PFB01CR_CINV_WAY(x)
<> 144:ef7eb2e8f9f7 17284 #define FMC_PFB0CR_CLCK_WAY_MASK FMC_PFB01CR_CLCK_WAY_MASK
<> 144:ef7eb2e8f9f7 17285 #define FMC_PFB0CR_CLCK_WAY_SHIFT FMC_PFB01CR_CLCK_WAY_SHIFT
<> 144:ef7eb2e8f9f7 17286 #define FMC_PFB0CR_CLCK_WAY(x) FMC_PFB01CR_CLCK_WAY(x)
<> 144:ef7eb2e8f9f7 17287 #define FMC_PFB0CR_B0RWSC_MASK FMC_PFB01CR_B0RWSC_MASK
<> 144:ef7eb2e8f9f7 17288 #define FMC_PFB0CR_B0RWSC_SHIFT FMC_PFB01CR_B0RWSC_SHIFT
<> 144:ef7eb2e8f9f7 17289 #define FMC_PFB0CR_B0RWSC(x) FMC_PFB01CR_B0RWSC(x)
<> 144:ef7eb2e8f9f7 17290 #define FMC_PFB1CR_RFU_MASK FMC_PFB23CR_RFU_MASK
<> 144:ef7eb2e8f9f7 17291 #define FMC_PFB1CR_RFU_SHIFT FMC_PFB23CR_RFU_SHIFT
<> 144:ef7eb2e8f9f7 17292 #define FMC_PFB1CR_B1IPE_MASK FMC_PFB23CR_B1IPE_MASK
<> 144:ef7eb2e8f9f7 17293 #define FMC_PFB1CR_B1IPE_SHIFT FMC_PFB23CR_B1IPE_SHIFT
<> 144:ef7eb2e8f9f7 17294 #define FMC_PFB1CR_B1DPE_MASK FMC_PFB23CR_B1DPE_MASK
<> 144:ef7eb2e8f9f7 17295 #define FMC_PFB1CR_B1DPE_SHIFT FMC_PFB23CR_B1DPE_SHIFT
<> 144:ef7eb2e8f9f7 17296 #define FMC_PFB1CR_B1ICE_MASK FMC_PFB23CR_B1ICE_MASK
<> 144:ef7eb2e8f9f7 17297 #define FMC_PFB1CR_B1ICE_SHIFT FMC_PFB23CR_B1ICE_SHIFT
<> 144:ef7eb2e8f9f7 17298 #define FMC_PFB1CR_B1DCE_MASK FMC_PFB23CR_B1DCE_MASK
<> 144:ef7eb2e8f9f7 17299 #define FMC_PFB1CR_B1DCE_SHIFT FMC_PFB23CR_B1DCE_SHIFT
<> 144:ef7eb2e8f9f7 17300 #define FMC_PFB1CR_B1MW_MASK FMC_PFB23CR_B1MW_MASK
<> 144:ef7eb2e8f9f7 17301 #define FMC_PFB1CR_B1MW_SHIFT FMC_PFB23CR_B1MW_SHIFT
<> 144:ef7eb2e8f9f7 17302 #define FMC_PFB1CR_B1MW(x) FMC_PFB23CR_B1MW(x)
<> 144:ef7eb2e8f9f7 17303 #define FMC_PFB1CR_B1RWSC_MASK FMC_PFB23CR_B1RWSC_MASK
<> 144:ef7eb2e8f9f7 17304 #define FMC_PFB1CR_B1RWSC_SHIFT FMC_PFB23CR_B1RWSC_SHIFT
<> 144:ef7eb2e8f9f7 17305 #define FMC_PFB1CR_B1RWSC(x) FMC_PFB23CR_B1RWSC(x)
<> 144:ef7eb2e8f9f7 17306 #define LLWU_PE8_WUPE130_MASK LLWU_PE8_WUPE30_MASK
<> 144:ef7eb2e8f9f7 17307 #define LLWU_PE8_WUPE130_SHIFT LLWU_PE8_WUPE30_SHIFT
<> 144:ef7eb2e8f9f7 17308 #define LLWU_PE8_WUPE130(x) LLWU_PE8_WUPE30(x)
<> 144:ef7eb2e8f9f7 17309 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
<> 144:ef7eb2e8f9f7 17310 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
<> 144:ef7eb2e8f9f7 17311 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
<> 144:ef7eb2e8f9f7 17312 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
<> 144:ef7eb2e8f9f7 17313 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
<> 144:ef7eb2e8f9f7 17314 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
<> 144:ef7eb2e8f9f7 17315 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
<> 144:ef7eb2e8f9f7 17316 #define PMC_REGSC_BGBDS_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17317 #define PMC_REGSC_BGBDS_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17318 #define SDHC_VENDOR_EXTDMAEN_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17319 #define SDHC_VENDOR_EXTDMAEN_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17320 #define SDRAM_CTRL_COC_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17321 #define SDRAM_CTRL_COC_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17322 #define SDRAM_CTRL_NAM_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17323 #define SDRAM_CTRL_NAM_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17324 #define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17325 #define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17326 #define UART_C6_CP_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17327 #define UART_C6_CP_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17328 #define UART_C6_CE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17329 #define UART_C6_CE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17330 #define UART_C6_TX709_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17331 #define UART_C6_TX709_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17332 #define UART_C6_EN709_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17333 #define UART_C6_EN709_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17334 #define UART_PCTH_PCTH_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17335 #define UART_PCTH_PCTH_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17336 #define UART_PCTH_PCTH(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17337 #define UART_PCTL_PCTL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17338 #define UART_PCTL_PCTL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17339 #define UART_PCTL_PCTL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17340 #define UART_IE0_CPTXIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17341 #define UART_IE0_CPTXIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17342 #define UART_IE0_CTXDIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17343 #define UART_IE0_CTXDIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17344 #define UART_IE0_RPLOFIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17345 #define UART_IE0_RPLOFIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17346 #define UART_SDTH_SDTH_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17347 #define UART_SDTH_SDTH_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17348 #define UART_SDTH_SDTH(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17349 #define UART_SDTL_SDTL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17350 #define UART_SDTL_SDTL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17351 #define UART_SDTL_SDTL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17352 #define UART_PRE_PREAMBLE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17353 #define UART_PRE_PREAMBLE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17354 #define UART_PRE_PREAMBLE(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17355 #define UART_TPL_TPL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17356 #define UART_TPL_TPL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17357 #define UART_TPL_TPL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17358 #define UART_IE_TXDIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17359 #define UART_IE_TXDIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17360 #define UART_IE_PSIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17361 #define UART_IE_PSIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17362 #define UART_IE_PCTEIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17363 #define UART_IE_PCTEIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17364 #define UART_IE_PTXIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17365 #define UART_IE_PTXIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17366 #define UART_IE_PRXIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17367 #define UART_IE_PRXIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17368 #define UART_IE_ISDIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17369 #define UART_IE_ISDIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17370 #define UART_IE_WBEIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17371 #define UART_IE_WBEIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17372 #define UART_IE_PEIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17373 #define UART_IE_PEIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17374 #define UART_WB_WBASE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17375 #define UART_WB_WBASE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17376 #define UART_WB_WBASE(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17377 #define UART_S3_TXFF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17378 #define UART_S3_TXFF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17379 #define UART_S3_PSF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17380 #define UART_S3_PSF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17381 #define UART_S3_PCTEF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17382 #define UART_S3_PCTEF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17383 #define UART_S3_PTXF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17384 #define UART_S3_PTXF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17385 #define UART_S3_PRXF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17386 #define UART_S3_PRXF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17387 #define UART_S3_ISD_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17388 #define UART_S3_ISD_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17389 #define UART_S3_WBEF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17390 #define UART_S3_WBEF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17391 #define UART_S3_PEF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17392 #define UART_S3_PEF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17393 #define UART_S4_FE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17394 #define UART_S4_FE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17395 #define UART_S4_TXDF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17396 #define UART_S4_TXDF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17397 #define UART_S4_CDET_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17398 #define UART_S4_CDET_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17399 #define UART_S4_CDET(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17400 #define UART_S4_RPLOF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17401 #define UART_S4_RPLOF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17402 #define UART_S4_LNF_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17403 #define UART_S4_LNF_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17404 #define UART_RPL_RPL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17405 #define UART_RPL_RPL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17406 #define UART_RPL_RPL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17407 #define UART_RPREL_RPREL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17408 #define UART_RPREL_RPREL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17409 #define UART_RPREL_RPREL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17410 #define UART_CPW_CPW_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17411 #define UART_CPW_CPW_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17412 #define UART_CPW_CPW(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17413 #define UART_RIDTH_RIDTH_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17414 #define UART_RIDTH_RIDTH_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17415 #define UART_RIDTH_RIDTH(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17416 #define UART_RIDTL_RIDTL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17417 #define UART_RIDTL_RIDTL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17418 #define UART_RIDTL_RIDTL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17419 #define UART_TIDTH_TIDTH_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17420 #define UART_TIDTH_TIDTH_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17421 #define UART_TIDTH_TIDTH(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17422 #define UART_TIDTL_TIDTL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17423 #define UART_TIDTL_TIDTL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17424 #define UART_TIDTL_TIDTL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17425 #define UART_RB1TH_RB1TH_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17426 #define UART_RB1TH_RB1TH_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17427 #define UART_RB1TH_RB1TH(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17428 #define UART_RB1TL_RB1TL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17429 #define UART_RB1TL_RB1TL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17430 #define UART_RB1TL_RB1TL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17431 #define UART_TB1TH_TB1TH_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17432 #define UART_TB1TH_TB1TH_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17433 #define UART_TB1TH_TB1TH(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17434 #define UART_TB1TL_TB1TL_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17435 #define UART_TB1TL_TB1TL_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17436 #define UART_TB1TL_TB1TL(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17437 #define UART_PROG_REG_MIN_DMC1_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17438 #define UART_PROG_REG_MIN_DMC1_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17439 #define UART_PROG_REG_MIN_DMC1(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17440 #define UART_PROG_REG_LCV_LEN_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17441 #define UART_PROG_REG_LCV_LEN_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17442 #define UART_PROG_REG_LCV_LEN(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17443 #define UART_STATE_REG_SM_STATE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17444 #define UART_STATE_REG_SM_STATE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17445 #define UART_STATE_REG_SM_STATE(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17446 #define UART_STATE_REG_TX_STATE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17447 #define UART_STATE_REG_TX_STATE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17448 #define UART_STATE_REG_TX_STATE(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17449 #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17450 #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17451 #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17452 #define USBHS_USBSTS_ULPII_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17453 #define USBHS_USBSTS_ULPII_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17454 #define USBHS_USBINTR_ULPIE_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17455 #define USBHS_USBINTR_ULPIE_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17456 #define USBPHY_CTRL_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17457 #define USBPHY_CTRL_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17458 #define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17459 #define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17460 #define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17461 #define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17462 #define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17463 #define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17464 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
<> 144:ef7eb2e8f9f7 17465 #define MCM_ISR_IRQ_MASK MCM_ISCR_IRQ_MASK
<> 144:ef7eb2e8f9f7 17466 #define MCM_ISR_IRQ_SHIFT MCM_ISCR_IRQ_SHIFT
<> 144:ef7eb2e8f9f7 17467 #define MCM_ISR_NMI_MASK MCM_ISCR_NMI_MASK
<> 144:ef7eb2e8f9f7 17468 #define MCM_ISR_NMI_SHIFT MCM_ISCR_NMI_SHIFT
<> 144:ef7eb2e8f9f7 17469 #define MCM_ISR_DHREQ_MASK MCM_ISCR_DHREQ_MASK
<> 144:ef7eb2e8f9f7 17470 #define MCM_ISR_DHREQ_SHIFT MCM_ISCR_DHREQ_SHIFT
<> 144:ef7eb2e8f9f7 17471 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
<> 144:ef7eb2e8f9f7 17472 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
<> 144:ef7eb2e8f9f7 17473 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
<> 144:ef7eb2e8f9f7 17474 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
<> 144:ef7eb2e8f9f7 17475 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
<> 144:ef7eb2e8f9f7 17476 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
<> 144:ef7eb2e8f9f7 17477 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
<> 144:ef7eb2e8f9f7 17478 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
<> 144:ef7eb2e8f9f7 17479 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
<> 144:ef7eb2e8f9f7 17480 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
<> 144:ef7eb2e8f9f7 17481 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
<> 144:ef7eb2e8f9f7 17482 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
<> 144:ef7eb2e8f9f7 17483 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
<> 144:ef7eb2e8f9f7 17484 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
<> 144:ef7eb2e8f9f7 17485 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
<> 144:ef7eb2e8f9f7 17486 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
<> 144:ef7eb2e8f9f7 17487 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
<> 144:ef7eb2e8f9f7 17488 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
<> 144:ef7eb2e8f9f7 17489 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
<> 144:ef7eb2e8f9f7 17490 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
<> 144:ef7eb2e8f9f7 17491 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
<> 144:ef7eb2e8f9f7 17492 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
<> 144:ef7eb2e8f9f7 17493 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
<> 144:ef7eb2e8f9f7 17494 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
<> 144:ef7eb2e8f9f7 17495 #define DMAMUX0 DMAMUX
<> 144:ef7eb2e8f9f7 17496 #define DSPI0 SPI0
<> 144:ef7eb2e8f9f7 17497 #define DSPI1 SPI1
<> 144:ef7eb2e8f9f7 17498 #define DSPI2 SPI2
<> 144:ef7eb2e8f9f7 17499 #define FLEXCAN0 CAN0
<> 144:ef7eb2e8f9f7 17500 #define FLEXCAN1 CAN1
<> 144:ef7eb2e8f9f7 17501 #define GPIOA_BASE PTA_BASE
<> 144:ef7eb2e8f9f7 17502 #define GPIOA PTA
<> 144:ef7eb2e8f9f7 17503 #define GPIOB_BASE PTB_BASE
<> 144:ef7eb2e8f9f7 17504 #define GPIOB PTB
<> 144:ef7eb2e8f9f7 17505 #define GPIOC_BASE PTC_BASE
<> 144:ef7eb2e8f9f7 17506 #define GPIOC PTC
<> 144:ef7eb2e8f9f7 17507 #define GPIOD_BASE PTD_BASE
<> 144:ef7eb2e8f9f7 17508 #define GPIOD PTD
<> 144:ef7eb2e8f9f7 17509 #define GPIOE_BASE PTE_BASE
<> 144:ef7eb2e8f9f7 17510 #define GPIOE PTE
<> 144:ef7eb2e8f9f7 17511 #define Watchdog_IRQn WDOG_EWM_IRQn
<> 144:ef7eb2e8f9f7 17512 #define Watchdog_IRQHandler WDOG_EWM_IRQHandler
<> 144:ef7eb2e8f9f7 17513 #define LPTimer_IRQn LPTMR0_IRQn
<> 144:ef7eb2e8f9f7 17514 #define LPTimer_IRQHandler LPTMR0_IRQHandler
<> 144:ef7eb2e8f9f7 17515 #define UART0_LON_IRQn This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17516 #define UART0_LON_IRQHandler This_symbol_has_been_deprecated
<> 144:ef7eb2e8f9f7 17517 #define LLW_IRQn LLWU_IRQn
<> 144:ef7eb2e8f9f7 17518 #define LLW_IRQHandler LLWU_IRQHandler
<> 144:ef7eb2e8f9f7 17519
<> 144:ef7eb2e8f9f7 17520 /*!
<> 144:ef7eb2e8f9f7 17521 * @}
<> 144:ef7eb2e8f9f7 17522 */ /* end of group SDK_Compatibility_Symbols */
<> 144:ef7eb2e8f9f7 17523
<> 144:ef7eb2e8f9f7 17524
<> 144:ef7eb2e8f9f7 17525 #endif /* _MK66F18_H_ */
<> 144:ef7eb2e8f9f7 17526