Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MK22FN512CAP12
<> 144:ef7eb2e8f9f7 4 ** MK22FN512VDC12
<> 144:ef7eb2e8f9f7 5 ** MK22FN512VLH12
<> 144:ef7eb2e8f9f7 6 ** MK22FN512VLL12
<> 144:ef7eb2e8f9f7 7 ** MK22FN512VMP12
<> 144:ef7eb2e8f9f7 8 **
<> 144:ef7eb2e8f9f7 9 ** Compiler: IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 10 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
<> 144:ef7eb2e8f9f7 11 ** Version: rev. 2.8, 2015-02-19
<> 144:ef7eb2e8f9f7 12 ** Build: b151009
<> 144:ef7eb2e8f9f7 13 **
<> 144:ef7eb2e8f9f7 14 ** Abstract:
<> 144:ef7eb2e8f9f7 15 ** Linker file for the IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 18 ** All rights reserved.
<> 144:ef7eb2e8f9f7 19 **
<> 144:ef7eb2e8f9f7 20 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 21 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 22 **
<> 144:ef7eb2e8f9f7 23 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 24 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 27 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 28 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 29 **
<> 144:ef7eb2e8f9f7 30 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 31 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 32 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 33 **
<> 144:ef7eb2e8f9f7 34 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 35 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 36 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 37 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 38 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 39 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 40 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 41 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 42 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 43 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 44 **
<> 144:ef7eb2e8f9f7 45 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 46 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 47 **
<> 144:ef7eb2e8f9f7 48 ** ###################################################################
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50 define symbol __ram_vector_table__ = 1;
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* Heap 1/4 of ram and stack 1/8 */
<> 144:ef7eb2e8f9f7 53 define symbol __stack_size__=0x4000;
<> 144:ef7eb2e8f9f7 54 define symbol __heap_size__=0x8000;
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
<> 144:ef7eb2e8f9f7 57 define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 define symbol m_interrupts_start = 0x00000000;
<> 144:ef7eb2e8f9f7 60 define symbol m_interrupts_end = 0x000003FF;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 define symbol m_flash_config_start = 0x00000400;
<> 144:ef7eb2e8f9f7 63 define symbol m_flash_config_end = 0x0000040F;
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 define symbol m_text_start = 0x00000410;
<> 144:ef7eb2e8f9f7 66 define symbol m_text_end = 0x0007FFFF;
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 define symbol m_interrupts_ram_start = 0x1FFF0000;
<> 144:ef7eb2e8f9f7 69 define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
<> 144:ef7eb2e8f9f7 72 define symbol m_data_end = 0x1FFFFFFF;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 define symbol m_data_2_start = 0x20000000;
<> 144:ef7eb2e8f9f7 75 define symbol m_data_2_end = 0x2000FFFF;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* Sizes */
<> 144:ef7eb2e8f9f7 78 if (isdefinedsymbol(__stack_size__)) {
<> 144:ef7eb2e8f9f7 79 define symbol __size_cstack__ = __stack_size__;
<> 144:ef7eb2e8f9f7 80 } else {
<> 144:ef7eb2e8f9f7 81 define symbol __size_cstack__ = 0x0400;
<> 144:ef7eb2e8f9f7 82 }
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 if (isdefinedsymbol(__heap_size__)) {
<> 144:ef7eb2e8f9f7 85 define symbol __size_heap__ = __heap_size__;
<> 144:ef7eb2e8f9f7 86 } else {
<> 144:ef7eb2e8f9f7 87 define symbol __size_heap__ = 0x0400;
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 define exported symbol __VECTOR_TABLE = m_interrupts_start;
<> 144:ef7eb2e8f9f7 91 define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
<> 144:ef7eb2e8f9f7 92 define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 define memory mem with size = 4G;
<> 144:ef7eb2e8f9f7 95 define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
<> 144:ef7eb2e8f9f7 96 define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
<> 144:ef7eb2e8f9f7 97 | mem:[from m_text_start to m_text_end];
<> 144:ef7eb2e8f9f7 98 define region DATA_region = mem:[from m_data_start to m_data_end]
<> 144:ef7eb2e8f9f7 99 | mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
<> 144:ef7eb2e8f9f7 100 define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
<> 144:ef7eb2e8f9f7 101 define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 define block CSTACK with alignment = 8, size = __size_cstack__ { };
<> 144:ef7eb2e8f9f7 104 define block HEAP with alignment = 8, size = __size_heap__ { };
<> 144:ef7eb2e8f9f7 105 define block RW { readwrite };
<> 144:ef7eb2e8f9f7 106 define block ZI { zi };
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 initialize by copy { readwrite, section .textrw };
<> 144:ef7eb2e8f9f7 109 do not initialize { section .noinit };
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 place at address mem: m_interrupts_start { readonly section .intvec };
<> 144:ef7eb2e8f9f7 112 place in m_flash_config_region { section FlashConfig };
<> 144:ef7eb2e8f9f7 113 place in TEXT_region { readonly };
<> 144:ef7eb2e8f9f7 114 place in DATA_region { block RW };
<> 144:ef7eb2e8f9f7 115 place in DATA_region { block ZI };
<> 144:ef7eb2e8f9f7 116 place in DATA_region { last block HEAP };
<> 144:ef7eb2e8f9f7 117 place in CSTACK_region { block CSTACK };
<> 144:ef7eb2e8f9f7 118 place in m_interrupts_ram_region { section m_interrupts_ram };
<> 144:ef7eb2e8f9f7 119