Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* MPS2 CMSIS Library
<> 144:ef7eb2e8f9f7 2 *
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2006-2016 ARM Limited
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 13 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 14 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * 3. Neither the name of the copyright holder nor the names of its contributors
<> 144:ef7eb2e8f9f7 17 * may be used to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 18 * specific prior written permission.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 30 * POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 * @file CMSDK_CM0plus.h
<> 144:ef7eb2e8f9f7 33 * @brief CMSIS Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 34 * CMSDK_CM0plus Device
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 *******************************************************************************/
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifndef CMSDK_CM0plus_H
<> 144:ef7eb2e8f9f7 40 #define CMSDK_CM0plus_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 typedef enum IRQn
<> 144:ef7eb2e8f9f7 50 {
<> 144:ef7eb2e8f9f7 51 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
<> 144:ef7eb2e8f9f7 54 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 55 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 56 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 57 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 58 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
<> 144:ef7eb2e8f9f7 61 UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
<> 144:ef7eb2e8f9f7 62 UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
<> 144:ef7eb2e8f9f7 63 UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
<> 144:ef7eb2e8f9f7 64 UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
<> 144:ef7eb2e8f9f7 65 UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
<> 144:ef7eb2e8f9f7 66 UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
<> 144:ef7eb2e8f9f7 67 PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
<> 144:ef7eb2e8f9f7 68 PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
<> 144:ef7eb2e8f9f7 69 TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
<> 144:ef7eb2e8f9f7 70 TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
<> 144:ef7eb2e8f9f7 71 DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
<> 144:ef7eb2e8f9f7 72 SPI_IRQn = 11, /*!< SPI Interrupt */
<> 144:ef7eb2e8f9f7 73 UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
<> 144:ef7eb2e8f9f7 74 ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
<> 144:ef7eb2e8f9f7 75 I2S_IRQn = 14, /*!< I2S Interrupt */
<> 144:ef7eb2e8f9f7 76 TSC_IRQn = 15, /*!< Touch Screen Interrupt */
<> 144:ef7eb2e8f9f7 77 PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
<> 144:ef7eb2e8f9f7 78 PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
<> 144:ef7eb2e8f9f7 79 UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
<> 144:ef7eb2e8f9f7 80 UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
<> 144:ef7eb2e8f9f7 81 UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
<> 144:ef7eb2e8f9f7 82 UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
<> 144:ef7eb2e8f9f7 83 ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
<> 144:ef7eb2e8f9f7 84 SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
<> 144:ef7eb2e8f9f7 85 PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
<> 144:ef7eb2e8f9f7 86 PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
<> 144:ef7eb2e8f9f7 87 PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
<> 144:ef7eb2e8f9f7 88 PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
<> 144:ef7eb2e8f9f7 89 PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
<> 144:ef7eb2e8f9f7 90 PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
<> 144:ef7eb2e8f9f7 91 PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
<> 144:ef7eb2e8f9f7 92 PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
<> 144:ef7eb2e8f9f7 93 } IRQn_Type;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 97 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 98 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
<> 144:ef7eb2e8f9f7 101 #define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */
<> 144:ef7eb2e8f9f7 102 #define __MPU_PRESENT 1 /* MPU present or not */
<> 144:ef7eb2e8f9f7 103 #define __VTOR_PRESENT 1 /* VTOR present or not */
<> 144:ef7eb2e8f9f7 104 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 105 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #include <core_cm0plus.h> /* Processor and core peripherals */
<> 144:ef7eb2e8f9f7 108 #include "system_CMSDK_CM0plus.h" /* System Header */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 112 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 113 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* ------------------- Start of section using anonymous unions ------------------ */
<> 144:ef7eb2e8f9f7 116 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 117 #pragma push
<> 144:ef7eb2e8f9f7 118 #pragma anon_unions
<> 144:ef7eb2e8f9f7 119 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 120 #pragma language=extended
<> 144:ef7eb2e8f9f7 121 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 122 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 123 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 124 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 125 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 126 #pragma warning 586
<> 144:ef7eb2e8f9f7 127 #else
<> 144:ef7eb2e8f9f7 128 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 129 #endif
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
<> 144:ef7eb2e8f9f7 132 typedef struct
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
<> 144:ef7eb2e8f9f7 135 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
<> 144:ef7eb2e8f9f7 136 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
<> 144:ef7eb2e8f9f7 137 union {
<> 144:ef7eb2e8f9f7 138 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 139 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 140 };
<> 144:ef7eb2e8f9f7 141 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 } CMSDK_UART_TypeDef;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* CMSDK_UART DATA Register Definitions */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
<> 144:ef7eb2e8f9f7 148 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
<> 144:ef7eb2e8f9f7 151 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
<> 144:ef7eb2e8f9f7 154 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
<> 144:ef7eb2e8f9f7 157 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
<> 144:ef7eb2e8f9f7 160 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
<> 144:ef7eb2e8f9f7 163 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
<> 144:ef7eb2e8f9f7 166 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
<> 144:ef7eb2e8f9f7 169 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
<> 144:ef7eb2e8f9f7 172 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
<> 144:ef7eb2e8f9f7 175 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
<> 144:ef7eb2e8f9f7 178 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
<> 144:ef7eb2e8f9f7 181 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
<> 144:ef7eb2e8f9f7 184 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
<> 144:ef7eb2e8f9f7 187 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
<> 144:ef7eb2e8f9f7 190 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
<> 144:ef7eb2e8f9f7 193 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
<> 144:ef7eb2e8f9f7 196 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /*----------------------------- Timer (TIMER) -------------------------------*/
<> 144:ef7eb2e8f9f7 200 typedef struct
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
<> 144:ef7eb2e8f9f7 203 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
<> 144:ef7eb2e8f9f7 204 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
<> 144:ef7eb2e8f9f7 205 union {
<> 144:ef7eb2e8f9f7 206 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 207 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 208 };
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 } CMSDK_TIMER_TypeDef;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* CMSDK_TIMER CTRL Register Definitions */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
<> 144:ef7eb2e8f9f7 215 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
<> 144:ef7eb2e8f9f7 218 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
<> 144:ef7eb2e8f9f7 221 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
<> 144:ef7eb2e8f9f7 224 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
<> 144:ef7eb2e8f9f7 227 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
<> 144:ef7eb2e8f9f7 230 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
<> 144:ef7eb2e8f9f7 233 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
<> 144:ef7eb2e8f9f7 236 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /*------------- Timer (TIM) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 240 typedef struct
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
<> 144:ef7eb2e8f9f7 243 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
<> 144:ef7eb2e8f9f7 244 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
<> 144:ef7eb2e8f9f7 245 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
<> 144:ef7eb2e8f9f7 246 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 247 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 248 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 249 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 250 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
<> 144:ef7eb2e8f9f7 251 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
<> 144:ef7eb2e8f9f7 252 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
<> 144:ef7eb2e8f9f7 253 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
<> 144:ef7eb2e8f9f7 254 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 255 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 256 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 257 uint32_t RESERVED1[945];
<> 144:ef7eb2e8f9f7 258 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
<> 144:ef7eb2e8f9f7 259 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
<> 144:ef7eb2e8f9f7 260 } CMSDK_DUALTIMER_BOTH_TypeDef;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 263 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 266 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 269 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 272 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 275 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 278 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 281 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 284 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 287 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 290 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 293 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 296 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 299 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 302 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 305 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 308 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 311 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 314 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 317 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 320 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 323 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 326 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 329 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 332 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 typedef struct
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
<> 144:ef7eb2e8f9f7 338 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
<> 144:ef7eb2e8f9f7 340 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
<> 144:ef7eb2e8f9f7 341 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 342 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 343 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 344 } CMSDK_DUALTIMER_SINGLE_TypeDef;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 347 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 350 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 353 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 356 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 359 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 362 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 365 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 368 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 371 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 374 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 377 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 380 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
<> 144:ef7eb2e8f9f7 384 typedef struct
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
<> 144:ef7eb2e8f9f7 387 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
<> 144:ef7eb2e8f9f7 388 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 389 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
<> 144:ef7eb2e8f9f7 390 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
<> 144:ef7eb2e8f9f7 391 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
<> 144:ef7eb2e8f9f7 392 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
<> 144:ef7eb2e8f9f7 393 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
<> 144:ef7eb2e8f9f7 394 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
<> 144:ef7eb2e8f9f7 395 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
<> 144:ef7eb2e8f9f7 396 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
<> 144:ef7eb2e8f9f7 397 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
<> 144:ef7eb2e8f9f7 398 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
<> 144:ef7eb2e8f9f7 399 union {
<> 144:ef7eb2e8f9f7 400 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 401 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 402 };
<> 144:ef7eb2e8f9f7 403 uint32_t RESERVED1[241];
<> 144:ef7eb2e8f9f7 404 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
<> 144:ef7eb2e8f9f7 405 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
<> 144:ef7eb2e8f9f7 406 } CMSDK_GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
<> 144:ef7eb2e8f9f7 409 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
<> 144:ef7eb2e8f9f7 412 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
<> 144:ef7eb2e8f9f7 415 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
<> 144:ef7eb2e8f9f7 418 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
<> 144:ef7eb2e8f9f7 421 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
<> 144:ef7eb2e8f9f7 424 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 427 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 430 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
<> 144:ef7eb2e8f9f7 433 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
<> 144:ef7eb2e8f9f7 436 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
<> 144:ef7eb2e8f9f7 439 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
<> 144:ef7eb2e8f9f7 442 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
<> 144:ef7eb2e8f9f7 445 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
<> 144:ef7eb2e8f9f7 448 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
<> 144:ef7eb2e8f9f7 451 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
<> 144:ef7eb2e8f9f7 454 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /*------------- System Control (SYSCON) --------------------------------------*/
<> 144:ef7eb2e8f9f7 458 typedef struct
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
<> 144:ef7eb2e8f9f7 462 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
<> 144:ef7eb2e8f9f7 464 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
<> 144:ef7eb2e8f9f7 465 } CMSDK_SYSCON_TypeDef;
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #define CMSDK_SYSCON_REMAP_Pos 0
<> 144:ef7eb2e8f9f7 468 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
<> 144:ef7eb2e8f9f7 471 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
<> 144:ef7eb2e8f9f7 474 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
<> 144:ef7eb2e8f9f7 477 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
<> 144:ef7eb2e8f9f7 480 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
<> 144:ef7eb2e8f9f7 483 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
<> 144:ef7eb2e8f9f7 486 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
<> 144:ef7eb2e8f9f7 489 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
<> 144:ef7eb2e8f9f7 492 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
<> 144:ef7eb2e8f9f7 495 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /*------------- PL230 uDMA (PL230) --------------------------------------*/
<> 144:ef7eb2e8f9f7 499 typedef struct
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
<> 144:ef7eb2e8f9f7 502 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
<> 144:ef7eb2e8f9f7 503 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
<> 144:ef7eb2e8f9f7 504 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
<> 144:ef7eb2e8f9f7 505 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
<> 144:ef7eb2e8f9f7 506 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
<> 144:ef7eb2e8f9f7 508 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
<> 144:ef7eb2e8f9f7 510 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
<> 144:ef7eb2e8f9f7 512 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
<> 144:ef7eb2e8f9f7 513 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
<> 144:ef7eb2e8f9f7 514 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
<> 144:ef7eb2e8f9f7 515 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
<> 144:ef7eb2e8f9f7 516 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
<> 144:ef7eb2e8f9f7 517 uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 518 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 } CMSDK_PL230_TypeDef;
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 #define PL230_DMA_CHNL_BITS 0
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
<> 144:ef7eb2e8f9f7 525 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
<> 144:ef7eb2e8f9f7 528 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
<> 144:ef7eb2e8f9f7 531 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
<> 144:ef7eb2e8f9f7 534 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
<> 144:ef7eb2e8f9f7 537 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
<> 144:ef7eb2e8f9f7 540 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
<> 144:ef7eb2e8f9f7 543 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
<> 144:ef7eb2e8f9f7 546 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
<> 144:ef7eb2e8f9f7 549 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
<> 144:ef7eb2e8f9f7 552 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
<> 144:ef7eb2e8f9f7 555 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
<> 144:ef7eb2e8f9f7 558 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
<> 144:ef7eb2e8f9f7 561 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
<> 144:ef7eb2e8f9f7 564 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
<> 144:ef7eb2e8f9f7 567 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
<> 144:ef7eb2e8f9f7 570 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
<> 144:ef7eb2e8f9f7 573 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
<> 144:ef7eb2e8f9f7 576 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
<> 144:ef7eb2e8f9f7 579 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
<> 144:ef7eb2e8f9f7 582 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
<> 144:ef7eb2e8f9f7 585 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
<> 144:ef7eb2e8f9f7 588 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
<> 144:ef7eb2e8f9f7 591 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /*------------------- Watchdog ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 595 typedef struct
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
<> 144:ef7eb2e8f9f7 599 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
<> 144:ef7eb2e8f9f7 600 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
<> 144:ef7eb2e8f9f7 601 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
<> 144:ef7eb2e8f9f7 602 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
<> 144:ef7eb2e8f9f7 603 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
<> 144:ef7eb2e8f9f7 604 uint32_t RESERVED0[762];
<> 144:ef7eb2e8f9f7 605 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
<> 144:ef7eb2e8f9f7 606 uint32_t RESERVED1[191];
<> 144:ef7eb2e8f9f7 607 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
<> 144:ef7eb2e8f9f7 608 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
<> 144:ef7eb2e8f9f7 609 }CMSDK_WATCHDOG_TypeDef;
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 612 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 615 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
<> 144:ef7eb2e8f9f7 618 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
<> 144:ef7eb2e8f9f7 621 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
<> 144:ef7eb2e8f9f7 624 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 627 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 630 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
<> 144:ef7eb2e8f9f7 633 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
<> 144:ef7eb2e8f9f7 636 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
<> 144:ef7eb2e8f9f7 639 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* -------------------- End of section using anonymous unions ------------------- */
<> 144:ef7eb2e8f9f7 644 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 645 #pragma pop
<> 144:ef7eb2e8f9f7 646 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 647 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 648 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 649 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 650 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 651 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 652 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 653 #pragma warning restore
<> 144:ef7eb2e8f9f7 654 #else
<> 144:ef7eb2e8f9f7 655 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 656 #endif
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 662 /* ================ Peripheral memory map ================ */
<> 144:ef7eb2e8f9f7 663 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Peripheral and SRAM base address */
<> 144:ef7eb2e8f9f7 666 #define CMSDK_FLASH_BASE (0x00000000UL)
<> 144:ef7eb2e8f9f7 667 #define CMSDK_SRAM_BASE (0x20000000UL)
<> 144:ef7eb2e8f9f7 668 #define CMSDK_PERIPH_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 #define CMSDK_RAM_BASE (0x20000000UL)
<> 144:ef7eb2e8f9f7 671 #define CMSDK_APB_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 672 #define CMSDK_AHB_BASE (0x40010000UL)
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* APB peripherals */
<> 144:ef7eb2e8f9f7 675 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 676 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
<> 144:ef7eb2e8f9f7 677 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
<> 144:ef7eb2e8f9f7 678 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
<> 144:ef7eb2e8f9f7 679 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
<> 144:ef7eb2e8f9f7 680 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
<> 144:ef7eb2e8f9f7 681 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
<> 144:ef7eb2e8f9f7 682 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
<> 144:ef7eb2e8f9f7 683 #define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
<> 144:ef7eb2e8f9f7 684 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
<> 144:ef7eb2e8f9f7 685 #define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
<> 144:ef7eb2e8f9f7 686 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* AHB peripherals */
<> 144:ef7eb2e8f9f7 689 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 690 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
<> 144:ef7eb2e8f9f7 691 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
<> 144:ef7eb2e8f9f7 692 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
<> 144:ef7eb2e8f9f7 693 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 697 /* ================ Peripheral declaration ================ */
<> 144:ef7eb2e8f9f7 698 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
<> 144:ef7eb2e8f9f7 701 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
<> 144:ef7eb2e8f9f7 702 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
<> 144:ef7eb2e8f9f7 703 #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
<> 144:ef7eb2e8f9f7 704 #define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
<> 144:ef7eb2e8f9f7 705 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
<> 144:ef7eb2e8f9f7 706 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
<> 144:ef7eb2e8f9f7 707 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
<> 144:ef7eb2e8f9f7 708 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
<> 144:ef7eb2e8f9f7 709 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
<> 144:ef7eb2e8f9f7 710 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
<> 144:ef7eb2e8f9f7 711 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
<> 144:ef7eb2e8f9f7 712 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
<> 144:ef7eb2e8f9f7 713 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
<> 144:ef7eb2e8f9f7 714 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
<> 144:ef7eb2e8f9f7 715 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
<> 144:ef7eb2e8f9f7 716 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 #endif
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 #endif /* CMSDK_CM0plus_H */