Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ; MPS2 CMSIS Library
<> 144:ef7eb2e8f9f7 2 ;
<> 144:ef7eb2e8f9f7 3 ; Copyright (c) 2006-2016 ARM Limited
<> 144:ef7eb2e8f9f7 4 ; All rights reserved.
<> 144:ef7eb2e8f9f7 5 ;
<> 144:ef7eb2e8f9f7 6 ; Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 ; modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 ;
<> 144:ef7eb2e8f9f7 9 ; 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 ; this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 ;
<> 144:ef7eb2e8f9f7 12 ; 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 13 ; this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 14 ; and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ; 3. Neither the name of the copyright holder nor the names of its contributors
<> 144:ef7eb2e8f9f7 17 ; may be used to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 18 ; specific prior written permission.
<> 144:ef7eb2e8f9f7 19 ;
<> 144:ef7eb2e8f9f7 20 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 21 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 22 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 23 ; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 24 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 25 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 26 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 27 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 28 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 29 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 30 ; POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 31 ;******************************************************************************
<> 144:ef7eb2e8f9f7 32 ; @file startup_CMSDK_CM0.s
<> 144:ef7eb2e8f9f7 33 ; @brief CMSIS Core Device Startup File for
<> 144:ef7eb2e8f9f7 34 ; CMSDK_CM0 Device
<> 144:ef7eb2e8f9f7 35 ;
<> 144:ef7eb2e8f9f7 36 ;******************************************************************************
<> 144:ef7eb2e8f9f7 37 ;
<> 144:ef7eb2e8f9f7 38 ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 39 ;
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 44 ; </h>
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 Stack_Size EQU 0x00004000
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 49 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 50 __initial_sp
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 54 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 55 ; </h>
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 Heap_Size EQU 0x00001000
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 60 __heap_base
<> 144:ef7eb2e8f9f7 61 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 62 __heap_limit
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 PRESERVE8
<> 144:ef7eb2e8f9f7 66 THUMB
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 72 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 73 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 74 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 77 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 78 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 79 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 80 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 81 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 82 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 83 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 84 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 85 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 86 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 87 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 91 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 ; External Interrupts
<> 144:ef7eb2e8f9f7 94 DCD UARTRX0_Handler ; UART 0 RX Handler
<> 144:ef7eb2e8f9f7 95 DCD UARTTX0_Handler ; UART 0 TX Handler
<> 144:ef7eb2e8f9f7 96 DCD UARTRX1_Handler ; UART 1 RX Handler
<> 144:ef7eb2e8f9f7 97 DCD UARTTX1_Handler ; UART 1 TX Handler
<> 144:ef7eb2e8f9f7 98 DCD UARTRX2_Handler ; UART 2 RX Handler
<> 144:ef7eb2e8f9f7 99 DCD UARTTX2_Handler ; UART 2 TX Handler
<> 144:ef7eb2e8f9f7 100 DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
<> 144:ef7eb2e8f9f7 101 DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
<> 144:ef7eb2e8f9f7 102 DCD TIMER0_Handler ; TIMER 0 handler
<> 144:ef7eb2e8f9f7 103 DCD TIMER1_Handler ; TIMER 1 handler
<> 144:ef7eb2e8f9f7 104 DCD DUALTIMER_HANDLER ; Dual timer handler
<> 144:ef7eb2e8f9f7 105 DCD SPI_Handler ; SPI exceptions Handler
<> 144:ef7eb2e8f9f7 106 DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
<> 144:ef7eb2e8f9f7 107 DCD ETHERNET_Handler ; Ethernet Overflow Handler
<> 144:ef7eb2e8f9f7 108 DCD I2S_Handler ; I2S Handler
<> 144:ef7eb2e8f9f7 109 DCD TSC_Handler ; Touch Screen handler
<> 144:ef7eb2e8f9f7 110 DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
<> 144:ef7eb2e8f9f7 111 DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
<> 144:ef7eb2e8f9f7 112 DCD UARTRX3_Handler ; UART 3 RX Handler
<> 144:ef7eb2e8f9f7 113 DCD UARTTX3_Handler ; UART 3 TX Handler
<> 144:ef7eb2e8f9f7 114 DCD UARTRX4_Handler ; UART 4 RX Handler
<> 144:ef7eb2e8f9f7 115 DCD UARTTX4_Handler ; UART 4 TX Handler
<> 144:ef7eb2e8f9f7 116 DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
<> 144:ef7eb2e8f9f7 117 DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
<> 144:ef7eb2e8f9f7 118 DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
<> 144:ef7eb2e8f9f7 119 DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
<> 144:ef7eb2e8f9f7 120 DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
<> 144:ef7eb2e8f9f7 121 DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
<> 144:ef7eb2e8f9f7 122 DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
<> 144:ef7eb2e8f9f7 123 DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
<> 144:ef7eb2e8f9f7 124 DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
<> 144:ef7eb2e8f9f7 125 DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
<> 144:ef7eb2e8f9f7 126 __Vectors_End
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 ; Reset Handler
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 136 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 137 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 138 IMPORT __main
<> 144:ef7eb2e8f9f7 139 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 140 BLX R0
<> 144:ef7eb2e8f9f7 141 LDR R0, =__main
<> 144:ef7eb2e8f9f7 142 BX R0
<> 144:ef7eb2e8f9f7 143 ENDP
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 149 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 150 B .
<> 144:ef7eb2e8f9f7 151 ENDP
<> 144:ef7eb2e8f9f7 152 HardFault_Handler\
<> 144:ef7eb2e8f9f7 153 PROC
<> 144:ef7eb2e8f9f7 154 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 155 B .
<> 144:ef7eb2e8f9f7 156 ENDP
<> 144:ef7eb2e8f9f7 157 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 158 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 159 B .
<> 144:ef7eb2e8f9f7 160 ENDP
<> 144:ef7eb2e8f9f7 161 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 162 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 163 B .
<> 144:ef7eb2e8f9f7 164 ENDP
<> 144:ef7eb2e8f9f7 165 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 166 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 167 B .
<> 144:ef7eb2e8f9f7 168 ENDP
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 Default_Handler PROC
<> 144:ef7eb2e8f9f7 171 EXPORT UARTRX0_Handler [WEAK]
<> 144:ef7eb2e8f9f7 172 EXPORT UARTTX0_Handler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT UARTRX1_Handler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT UARTTX1_Handler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT UARTRX2_Handler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT UARTTX2_Handler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT PORT0_COMB_Handler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT PORT1_COMB_Handler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT TIMER0_Handler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT TIMER1_Handler [WEAK]
<> 144:ef7eb2e8f9f7 181 EXPORT DUALTIMER_HANDLER [WEAK]
<> 144:ef7eb2e8f9f7 182 EXPORT SPI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 183 EXPORT UARTOVF_Handler [WEAK]
<> 144:ef7eb2e8f9f7 184 EXPORT ETHERNET_Handler [WEAK]
<> 144:ef7eb2e8f9f7 185 EXPORT I2S_Handler [WEAK]
<> 144:ef7eb2e8f9f7 186 EXPORT TSC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 187 EXPORT PORT2_COMB_Handler [WEAK]
<> 144:ef7eb2e8f9f7 188 EXPORT PORT3_COMB_Handler [WEAK]
<> 144:ef7eb2e8f9f7 189 EXPORT UARTRX3_Handler [WEAK]
<> 144:ef7eb2e8f9f7 190 EXPORT UARTTX3_Handler [WEAK]
<> 144:ef7eb2e8f9f7 191 EXPORT UARTRX4_Handler [WEAK]
<> 144:ef7eb2e8f9f7 192 EXPORT UARTTX4_Handler [WEAK]
<> 144:ef7eb2e8f9f7 193 EXPORT ADCSPI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 194 EXPORT SHIELDSPI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 195 EXPORT PORT0_0_Handler [WEAK]
<> 144:ef7eb2e8f9f7 196 EXPORT PORT0_1_Handler [WEAK]
<> 144:ef7eb2e8f9f7 197 EXPORT PORT0_2_Handler [WEAK]
<> 144:ef7eb2e8f9f7 198 EXPORT PORT0_3_Handler [WEAK]
<> 144:ef7eb2e8f9f7 199 EXPORT PORT0_4_Handler [WEAK]
<> 144:ef7eb2e8f9f7 200 EXPORT PORT0_5_Handler [WEAK]
<> 144:ef7eb2e8f9f7 201 EXPORT PORT0_6_Handler [WEAK]
<> 144:ef7eb2e8f9f7 202 EXPORT PORT0_7_Handler [WEAK]
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 UARTRX0_Handler
<> 144:ef7eb2e8f9f7 205 UARTTX0_Handler
<> 144:ef7eb2e8f9f7 206 UARTRX1_Handler
<> 144:ef7eb2e8f9f7 207 UARTTX1_Handler
<> 144:ef7eb2e8f9f7 208 UARTRX2_Handler
<> 144:ef7eb2e8f9f7 209 UARTTX2_Handler
<> 144:ef7eb2e8f9f7 210 PORT0_COMB_Handler
<> 144:ef7eb2e8f9f7 211 PORT1_COMB_Handler
<> 144:ef7eb2e8f9f7 212 TIMER0_Handler
<> 144:ef7eb2e8f9f7 213 TIMER1_Handler
<> 144:ef7eb2e8f9f7 214 DUALTIMER_HANDLER
<> 144:ef7eb2e8f9f7 215 SPI_Handler
<> 144:ef7eb2e8f9f7 216 UARTOVF_Handler
<> 144:ef7eb2e8f9f7 217 ETHERNET_Handler
<> 144:ef7eb2e8f9f7 218 I2S_Handler
<> 144:ef7eb2e8f9f7 219 TSC_Handler
<> 144:ef7eb2e8f9f7 220 PORT2_COMB_Handler
<> 144:ef7eb2e8f9f7 221 PORT3_COMB_Handler
<> 144:ef7eb2e8f9f7 222 UARTRX3_Handler
<> 144:ef7eb2e8f9f7 223 UARTTX3_Handler
<> 144:ef7eb2e8f9f7 224 UARTRX4_Handler
<> 144:ef7eb2e8f9f7 225 UARTTX4_Handler
<> 144:ef7eb2e8f9f7 226 ADCSPI_Handler
<> 144:ef7eb2e8f9f7 227 SHIELDSPI_Handler
<> 144:ef7eb2e8f9f7 228 PORT0_0_Handler
<> 144:ef7eb2e8f9f7 229 PORT0_1_Handler
<> 144:ef7eb2e8f9f7 230 PORT0_2_Handler
<> 144:ef7eb2e8f9f7 231 PORT0_3_Handler
<> 144:ef7eb2e8f9f7 232 PORT0_4_Handler
<> 144:ef7eb2e8f9f7 233 PORT0_5_Handler
<> 144:ef7eb2e8f9f7 234 PORT0_6_Handler
<> 144:ef7eb2e8f9f7 235 PORT0_7_Handler
<> 144:ef7eb2e8f9f7 236 B .
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 ENDP
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 ALIGN
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 ; User Initial Stack & Heap
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 IF :DEF:__MICROLIB
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 249 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 250 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 ELSE
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 IMPORT __use_two_region_memory
<> 144:ef7eb2e8f9f7 255 EXPORT __user_initial_stackheap
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 __user_initial_stackheap PROC
<> 144:ef7eb2e8f9f7 258 LDR R0, = Heap_Mem
<> 144:ef7eb2e8f9f7 259 LDR R1, =(Stack_Mem + Stack_Size)
<> 144:ef7eb2e8f9f7 260 LDR R2, = (Heap_Mem + Heap_Size)
<> 144:ef7eb2e8f9f7 261 LDR R3, = Stack_Mem
<> 144:ef7eb2e8f9f7 262 BX LR
<> 144:ef7eb2e8f9f7 263 ENDP
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 ALIGN
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 ENDIF
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 END