Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * PackageLicenseDeclared: Apache-2.0
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 6 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 7 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 12 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 14 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 15 * limitations under the License.
<> 144:ef7eb2e8f9f7 16 */
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include "CMSDK_BEETLE.h"
<> 144:ef7eb2e8f9f7 19 #include "system_core_beetle.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 /*
<> 144:ef7eb2e8f9f7 22 * SystemCoreConfig(): Configure the System Core
<> 144:ef7eb2e8f9f7 23 */
<> 144:ef7eb2e8f9f7 24 void SystemCoreConfig()
<> 144:ef7eb2e8f9f7 25 {
<> 144:ef7eb2e8f9f7 26 /* Set GPIO Alternate Functions */
<> 144:ef7eb2e8f9f7 27 CMSDK_GPIO0->ALTFUNCSET = (1<<0); /* Sheild 0 UART 0 RXD */
<> 144:ef7eb2e8f9f7 28 CMSDK_GPIO0->ALTFUNCSET |= (1<<1); /* Sheild 0 UART 0 TXD */
<> 144:ef7eb2e8f9f7 29 CMSDK_GPIO0->ALTFUNCSET |= (1<<14); /* Sheild 0 I2C SDA SBCON2 */
<> 144:ef7eb2e8f9f7 30 CMSDK_GPIO0->ALTFUNCSET |= (1<<15); /* Sheild 0 I2C SCL SBCON2 */
<> 144:ef7eb2e8f9f7 31 CMSDK_GPIO0->ALTFUNCSET |= (1<<10); /* Sheild 0 SPI_3 nCS */
<> 144:ef7eb2e8f9f7 32 CMSDK_GPIO0->ALTFUNCSET |= (1<<11); /* Sheild 0 SPI_3 MOSI */
<> 144:ef7eb2e8f9f7 33 CMSDK_GPIO0->ALTFUNCSET |= (1<<12); /* Sheild 0 SPI_3 MISO */
<> 144:ef7eb2e8f9f7 34 CMSDK_GPIO0->ALTFUNCSET |= (1<<13); /* Sheild 0 SPI_3 SCK */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 CMSDK_GPIO1->ALTFUNCSET = (1<<0); /* UART 1 RXD */
<> 144:ef7eb2e8f9f7 37 CMSDK_GPIO1->ALTFUNCSET |= (1<<1); /* UART 1 TXD */
<> 144:ef7eb2e8f9f7 38 CMSDK_GPIO1->ALTFUNCSET |= (1<<6); /* Sheild 1 I2C SDA */
<> 144:ef7eb2e8f9f7 39 CMSDK_GPIO1->ALTFUNCSET |= (1<<7); /* Sheild 1 I2C SCL */
<> 144:ef7eb2e8f9f7 40 CMSDK_GPIO1->ALTFUNCSET |= (1<<2); /* ADC SPI_2 nCS */
<> 144:ef7eb2e8f9f7 41 CMSDK_GPIO1->ALTFUNCSET |= (1<<3); /* ADC SPI_2 MOSI */
<> 144:ef7eb2e8f9f7 42 CMSDK_GPIO1->ALTFUNCSET |= (1<<4); /* ADC SPI_2 MISO */
<> 144:ef7eb2e8f9f7 43 CMSDK_GPIO1->ALTFUNCSET |= (1<<5); /* ADC SPI_2 SCK */
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 CMSDK_GPIO1->ALTFUNCSET |= (1<<8); /* QSPI CS 2 */
<> 144:ef7eb2e8f9f7 46 CMSDK_GPIO1->ALTFUNCSET |= (1<<9); /* QSPI CS 1 */
<> 144:ef7eb2e8f9f7 47 CMSDK_GPIO1->ALTFUNCSET |= (1<<10); /* QSPI IO 0 */
<> 144:ef7eb2e8f9f7 48 CMSDK_GPIO1->ALTFUNCSET |= (1<<11); /* QSPI IO 1 */
<> 144:ef7eb2e8f9f7 49 CMSDK_GPIO1->ALTFUNCSET |= (1<<12); /* QSPI IO 2 */
<> 144:ef7eb2e8f9f7 50 CMSDK_GPIO1->ALTFUNCSET |= (1<<13); /* QSPI IO 3 */
<> 144:ef7eb2e8f9f7 51 CMSDK_GPIO1->ALTFUNCSET |= (1<<14); /* QSPI SCK */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /* Set the ARD_PWR_EN GPIO1[15] as an output */
<> 144:ef7eb2e8f9f7 54 CMSDK_GPIO1->OUTENABLESET |= (0x1 << 15);
<> 144:ef7eb2e8f9f7 55 /* Set on 3v3 (for ARDUINO HDR compliancy) */
<> 144:ef7eb2e8f9f7 56 CMSDK_GPIO1->DATA |= (0x1 << 15);
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* POWER MANAGEMENT */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*
<> 144:ef7eb2e8f9f7 62 * SystemPowerConfig(): Configures the System Power Modes
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 void SystemPowerConfig()
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 /* Configure APB Peripheral Clock in sleep state */
<> 144:ef7eb2e8f9f7 67 CMSDK_SYSCON->APBCLKCFG1SET = SYSTEM_CORE_TIMER0
<> 144:ef7eb2e8f9f7 68 | SYSTEM_CORE_TIMER1
<> 144:ef7eb2e8f9f7 69 | SYSTEM_CORE_DUALTIMER0
<> 144:ef7eb2e8f9f7 70 | SYSTEM_CORE_UART1
<> 144:ef7eb2e8f9f7 71 | SYSTEM_CORE_I2C0
<> 144:ef7eb2e8f9f7 72 | SYSTEM_CORE_QSPI
<> 144:ef7eb2e8f9f7 73 | SYSTEM_CORE_SPI0
<> 144:ef7eb2e8f9f7 74 | SYSTEM_CORE_SPI1
<> 144:ef7eb2e8f9f7 75 | SYSTEM_CORE_I2C1;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* Configure APB Peripheral Clock in deep sleep state */
<> 144:ef7eb2e8f9f7 78 CMSDK_SYSCON->APBCLKCFG2SET = SYSTEM_CORE_TIMER0
<> 144:ef7eb2e8f9f7 79 | SYSTEM_CORE_TIMER1
<> 144:ef7eb2e8f9f7 80 | SYSTEM_CORE_DUALTIMER0
<> 144:ef7eb2e8f9f7 81 | SYSTEM_CORE_UART1
<> 144:ef7eb2e8f9f7 82 | SYSTEM_CORE_I2C0
<> 144:ef7eb2e8f9f7 83 | SYSTEM_CORE_QSPI
<> 144:ef7eb2e8f9f7 84 | SYSTEM_CORE_SPI0
<> 144:ef7eb2e8f9f7 85 | SYSTEM_CORE_SPI1
<> 144:ef7eb2e8f9f7 86 | SYSTEM_CORE_I2C1;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Configure Wakeup Sources */
<> 144:ef7eb2e8f9f7 89 CMSDK_SYSCON->PWRDNCFG1SET = SYSTEM_CORE_DUALTIMER0;
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*
<> 144:ef7eb2e8f9f7 93 * SystemPowerSuspend(): Enters in System Suspend
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 void SystemPowerSuspend(power_mode_t mode)
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97 if (mode == POWER_MODE_DEEP_SLEEP) {
<> 144:ef7eb2e8f9f7 98 /* Enable deepsleep */
<> 144:ef7eb2e8f9f7 99 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 100 /* Ensure effect of last store takes effect */
<> 144:ef7eb2e8f9f7 101 __DSB();
<> 144:ef7eb2e8f9f7 102 /* Enter sleep mode */
<> 144:ef7eb2e8f9f7 103 __WFI();
<> 144:ef7eb2e8f9f7 104 } else {
<> 144:ef7eb2e8f9f7 105 /* Enter sleep mode */
<> 144:ef7eb2e8f9f7 106 __WFI();
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /*
<> 144:ef7eb2e8f9f7 111 * SystemPowerResume(): Returns from System Suspend
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 void SystemPowerResume(power_mode_t mode)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 if (mode == POWER_MODE_DEEP_SLEEP) {
<> 144:ef7eb2e8f9f7 116 /* Disable sleeponexit */
<> 144:ef7eb2e8f9f7 117 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
<> 144:ef7eb2e8f9f7 118 /* Ensure effect of last store takes effect */
<> 144:ef7eb2e8f9f7 119 __DSB();
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /*
<> 144:ef7eb2e8f9f7 125 * System config data storage functions
<> 144:ef7eb2e8f9f7 126 * Reserved as the data is not strictly persistent
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /*
<> 144:ef7eb2e8f9f7 130 * __System_Config_GetBDAddr(): Address for the BLE device on the air.
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 void __System_Config_GetBDAddr(uint8_t *addr, uint8_t byte_len)
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 SystemCoreConfigData *p;
<> 144:ef7eb2e8f9f7 135 int bank1addr = EFlash_ReturnBank1BaseAddress();
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 if (byte_len > 6)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 return;
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if (bank1addr < 0)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 memset(addr, 0xFF, byte_len);
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 else
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /* 2x bank1 address is the top as banks have to be symmetric sizes */
<> 144:ef7eb2e8f9f7 149 /* The data is stored at the end.*/
<> 144:ef7eb2e8f9f7 150 p = (SystemCoreConfigData *) ((2 * bank1addr) - SYSTEM_CORE_CONFIG_DATA_SIZE);
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 memcpy(addr, p->BD_ADDR, byte_len);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154 }