Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/CMSDK_BEETLE.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * SPDX-License-Identifier: Apache-2.0
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Licensed under the Apache License, Version 2.0 (the License); you may
<> 144:ef7eb2e8f9f7 7 * not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 8 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
<> 144:ef7eb2e8f9f7 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 15 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 16 * limitations under the License.
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 /*
<> 144:ef7eb2e8f9f7 19 * This file is derivative of CMSIS V5.00 ARMCM3.h
<> 144:ef7eb2e8f9f7 20 */
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 #ifndef CMSDK_BEETLE_H
<> 144:ef7eb2e8f9f7 24 #define CMSDK_BEETLE_H
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 27 extern "C" {
<> 144:ef7eb2e8f9f7 28 #endif
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 typedef enum IRQn
<> 144:ef7eb2e8f9f7 34 {
<> 144:ef7eb2e8f9f7 35 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
<> 144:ef7eb2e8f9f7 36 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 37 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
<> 144:ef7eb2e8f9f7 38 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 39 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 40 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 41 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 42 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 43 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 44 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */
<> 144:ef7eb2e8f9f7 47 UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
<> 144:ef7eb2e8f9f7 48 Spare_IRQn = 1, /* Undefined */
<> 144:ef7eb2e8f9f7 49 UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
<> 144:ef7eb2e8f9f7 50 I2C0_IRQn = 3, /* I2C 0 Interrupt */
<> 144:ef7eb2e8f9f7 51 I2C1_IRQn = 4, /* I2C 1 Interrupt */
<> 144:ef7eb2e8f9f7 52 RTC_IRQn = 5, /* RTC Interrupt */
<> 144:ef7eb2e8f9f7 53 PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
<> 144:ef7eb2e8f9f7 54 PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
<> 144:ef7eb2e8f9f7 55 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
<> 144:ef7eb2e8f9f7 56 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
<> 144:ef7eb2e8f9f7 57 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
<> 144:ef7eb2e8f9f7 58 SPI0_IRQn = 11, /* SPI 0 Interrupt */
<> 144:ef7eb2e8f9f7 59 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
<> 144:ef7eb2e8f9f7 60 SPI1_IRQn = 13, /* SPI 1 Interrupt */
<> 144:ef7eb2e8f9f7 61 QSPI_IRQn = 14, /* QUAD SPI Interrupt */
<> 144:ef7eb2e8f9f7 62 DMA_IRQn = 15, /* Reserved for DMA Interrup */
<> 144:ef7eb2e8f9f7 63 PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
<> 144:ef7eb2e8f9f7 64 PORT0_1_IRQn = 17, /* There are 16 pins in total */
<> 144:ef7eb2e8f9f7 65 PORT0_2_IRQn = 18,
<> 144:ef7eb2e8f9f7 66 PORT0_3_IRQn = 19,
<> 144:ef7eb2e8f9f7 67 PORT0_4_IRQn = 20,
<> 144:ef7eb2e8f9f7 68 PORT0_5_IRQn = 21,
<> 144:ef7eb2e8f9f7 69 PORT0_6_IRQn = 22,
<> 144:ef7eb2e8f9f7 70 PORT0_7_IRQn = 23,
<> 144:ef7eb2e8f9f7 71 PORT0_8_IRQn = 24,
<> 144:ef7eb2e8f9f7 72 PORT0_9_IRQn = 25,
<> 144:ef7eb2e8f9f7 73 PORT0_10_IRQn = 26,
<> 144:ef7eb2e8f9f7 74 PORT0_11_IRQn = 27,
<> 144:ef7eb2e8f9f7 75 PORT0_12_IRQn = 28,
<> 144:ef7eb2e8f9f7 76 PORT0_13_IRQn = 29,
<> 144:ef7eb2e8f9f7 77 PORT0_14_IRQn = 30,
<> 144:ef7eb2e8f9f7 78 PORT0_15_IRQn = 31,
<> 144:ef7eb2e8f9f7 79 SYSERROR_IRQn = 32, /* System Error Interrupt */
<> 144:ef7eb2e8f9f7 80 EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
<> 144:ef7eb2e8f9f7 81 LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */
<> 144:ef7eb2e8f9f7 82 LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */
<> 144:ef7eb2e8f9f7 83 LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */
<> 144:ef7eb2e8f9f7 84 LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */
<> 144:ef7eb2e8f9f7 85 LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */
<> 144:ef7eb2e8f9f7 86 LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */
<> 144:ef7eb2e8f9f7 87 LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */
<> 144:ef7eb2e8f9f7 88 LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */
<> 144:ef7eb2e8f9f7 89 PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
<> 144:ef7eb2e8f9f7 90 PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
<> 144:ef7eb2e8f9f7 91 TRNG_IRQn = 44, /* Random number generator Interrupt */
<> 144:ef7eb2e8f9f7 92 } IRQn_Type;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 96 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 97 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
<> 144:ef7eb2e8f9f7 100 #define __CM3_REV 0x0201U /* Core revision r2p1 */
<> 144:ef7eb2e8f9f7 101 #define __MPU_PRESENT 1 /* MPU present */
<> 144:ef7eb2e8f9f7 102 #define __VTOR_PRESENT 1 /* VTOR present or not */
<> 144:ef7eb2e8f9f7 103 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 104 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #include <core_cm3.h> /* Processor and core peripherals */
<> 144:ef7eb2e8f9f7 107 #include "system_CMSDK_BEETLE.h" /* System Header */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 111 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 112 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* ------------------- Start of section using anonymous unions ------------------ */
<> 144:ef7eb2e8f9f7 115 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 116 #pragma push
<> 144:ef7eb2e8f9f7 117 #pragma anon_unions
<> 144:ef7eb2e8f9f7 118 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 119 #pragma language=extended
<> 144:ef7eb2e8f9f7 120 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 121 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 122 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 123 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 124 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 125 #pragma warning 586
<> 144:ef7eb2e8f9f7 126 #else
<> 144:ef7eb2e8f9f7 127 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 128 #endif
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* ======================================================================== */
<> 144:ef7eb2e8f9f7 131 /* ============ LLCC/DMAC v1 ============ */
<> 144:ef7eb2e8f9f7 132 /* ======================================================================== */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 typedef struct
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 __IO uint32_t BUF_STATE; // +0x00
<> 144:ef7eb2e8f9f7 137 __I uint32_t STATUS; // +0x00
<> 144:ef7eb2e8f9f7 138 __IO uint32_t PTR_ADDR; // +0x08
<> 144:ef7eb2e8f9f7 139 __IO uint32_t PTR_CTRL; // +0x0c
<> 144:ef7eb2e8f9f7 140 __O uint32_t NXT_ADDR; // +0x10
<> 144:ef7eb2e8f9f7 141 __O uint32_t NXT_CTRL; // +0x14
<> 144:ef7eb2e8f9f7 142 __I uint32_t rsvd_18[2]; // +0x18
<> 144:ef7eb2e8f9f7 143 __IO uint32_t BUF0_ADDR; // +0x20
<> 144:ef7eb2e8f9f7 144 __IO uint32_t BUF0_CTRL; // +0x24
<> 144:ef7eb2e8f9f7 145 __I uint32_t rsvd_28[2]; // +0x28
<> 144:ef7eb2e8f9f7 146 __IO uint32_t BUF1_ADDR; // +0x30
<> 144:ef7eb2e8f9f7 147 __IO uint32_t BUF1_CTRL; // +0x34
<> 144:ef7eb2e8f9f7 148 __IO uint32_t INTEN; // +0x38
<> 144:ef7eb2e8f9f7 149 __IO uint32_t IRQSTATUS; // +0x3c
<> 144:ef7eb2e8f9f7 150 } DMAC_CHAN_TypeDef;
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 // DMA buffer control state machine
<> 144:ef7eb2e8f9f7 153 #define DMAC_BUFSTATE_MT 0
<> 144:ef7eb2e8f9f7 154 #define DMAC_BUFSTATE_A 1
<> 144:ef7eb2e8f9f7 155 #define DMAC_BUFSTATE_AB 5
<> 144:ef7eb2e8f9f7 156 #define DMAC_BUFSTATE_B 2
<> 144:ef7eb2e8f9f7 157 #define DMAC_BUFSTATE_BA 6
<> 144:ef7eb2e8f9f7 158 #define DMAC_BUFSTATE_FULL_IDX 2
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 // DMA Control structure MASKs
<> 144:ef7eb2e8f9f7 161 #define DMAC_CHAN_ADDR_MASK 0xfffffffc
<> 144:ef7eb2e8f9f7 162 #define DMAC_CHAN_COUNT_MASK 0x0000ffff
<> 144:ef7eb2e8f9f7 163 #define DMAC_CHAN_SIZE_MASK 0x00030000
<> 144:ef7eb2e8f9f7 164 #define DMAC_CHAN_AFIX_MASK 0x00040000
<> 144:ef7eb2e8f9f7 165 #define DMAC_CHAN_LOOP_MASK 0x00080000
<> 144:ef7eb2e8f9f7 166 #define DMAC_CHAN_ATTR_MASK 0xfff00000
<> 144:ef7eb2e8f9f7 167 #define DMAC_CHAN_COUNT_IDX_LO 0
<> 144:ef7eb2e8f9f7 168 #define DMAC_CHAN_COUNT_IDX_HI 15
<> 144:ef7eb2e8f9f7 169 #define DMAC_CHAN_SIZE_IDX_LO 16
<> 144:ef7eb2e8f9f7 170 #define DMAC_CHAN_SIZE_IDX_HI 17
<> 144:ef7eb2e8f9f7 171 #define DMAC_CHAN_AFIX_IDX 18
<> 144:ef7eb2e8f9f7 172 #define DMAC_CHAN_LOOP_IDX 19
<> 144:ef7eb2e8f9f7 173 #define DMAC_CHAN_TRIG_IDX_LO 20
<> 144:ef7eb2e8f9f7 174 #define DMAC_CHAN_TRIG_IDX_HI 23
<> 144:ef7eb2e8f9f7 175 #define DMAC_CHAN_ATTR_IDX_LO 24
<> 144:ef7eb2e8f9f7 176 #define DMAC_CHAN_ATTR_IDX_HI 31
<> 144:ef7eb2e8f9f7 177 #define DMAC_CHAN_IRQ_IDX 0
<> 144:ef7eb2e8f9f7 178 #define DMAC_CHAN_ERR_IDX 1
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 typedef struct
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 __I uint32_t ID_MAIN; // +0x0000
<> 144:ef7eb2e8f9f7 183 __I uint32_t ID_REV; // +0x0004
<> 144:ef7eb2e8f9f7 184 __I uint32_t rsvd_0008[30]; // +0x0008
<> 144:ef7eb2e8f9f7 185 __IO uint32_t STANDBY_CTRL; // +0x0080
<> 144:ef7eb2e8f9f7 186 } LLCC_CTL_TypeDef;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 typedef struct
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 __I uint32_t CMD_DATA0; // +0x2000
<> 144:ef7eb2e8f9f7 191 __I uint32_t CMD_DATA1; // +0x2004
<> 144:ef7eb2e8f9f7 192 __I uint32_t rsvd_008[14]; // +0x2008
<> 144:ef7eb2e8f9f7 193 __I uint32_t DMAH_DATA0; // +0x2040
<> 144:ef7eb2e8f9f7 194 __I uint32_t DMAH_DATA1; // +0x2044
<> 144:ef7eb2e8f9f7 195 __I uint32_t rsvd_048[6]; // +0x2048
<> 144:ef7eb2e8f9f7 196 __I uint32_t DMAL_DATA0; // +0x2060
<> 144:ef7eb2e8f9f7 197 __I uint32_t DMAL_DATA1; // +0x2064
<> 144:ef7eb2e8f9f7 198 __I uint32_t rsvd_068[6]; // +0x2068
<> 144:ef7eb2e8f9f7 199 __I uint32_t EVT_DATA0; // +0x2080
<> 144:ef7eb2e8f9f7 200 __I uint32_t EVT_DATA1; // +0x2084
<> 144:ef7eb2e8f9f7 201 __I uint32_t rsvd_088[14]; // +0x2088
<> 144:ef7eb2e8f9f7 202 __I uint32_t INTERRUPT; // +0x20c0
<> 144:ef7eb2e8f9f7 203 __IO uint32_t INTENMASK; // +0x20c4
<> 144:ef7eb2e8f9f7 204 __IO uint32_t INTENMASK_SET; // +0x20c8
<> 144:ef7eb2e8f9f7 205 __IO uint32_t INTENMASK_CLR; // +0x20cc
<> 144:ef7eb2e8f9f7 206 __I uint32_t REQUEST; // +0x20d0
<> 144:ef7eb2e8f9f7 207 __I uint32_t rsvd_0d4[3]; // +0x20d4
<> 144:ef7eb2e8f9f7 208 __I uint32_t XFERREQ; // +0x20e0
<> 144:ef7eb2e8f9f7 209 __I uint32_t XFERACK; // +0x20e4
<> 144:ef7eb2e8f9f7 210 __I uint32_t rsvd_0e8[6]; // +0x20e8
<> 144:ef7eb2e8f9f7 211 } LLCC_RXD_TypeDef;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 typedef struct
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 __IO uint32_t CMD_DATA0; // +0x3000
<> 144:ef7eb2e8f9f7 216 __IO uint32_t CMD_DATA1; // +0x3004
<> 144:ef7eb2e8f9f7 217 __I uint32_t rsvd_008[14]; // +0x3008
<> 144:ef7eb2e8f9f7 218 __IO uint32_t DMAH_DATA0; // +0x3040
<> 144:ef7eb2e8f9f7 219 __IO uint32_t DMAH_DATA1; // +0x3044
<> 144:ef7eb2e8f9f7 220 __I uint32_t rsvd_048[6]; // +0x3048
<> 144:ef7eb2e8f9f7 221 __IO uint32_t DMAL_DATA0; // +0x3060
<> 144:ef7eb2e8f9f7 222 __IO uint32_t DMAL_DATA1; // +0x3064
<> 144:ef7eb2e8f9f7 223 __I uint32_t rsvd_068[6]; // +0x3068
<> 144:ef7eb2e8f9f7 224 __IO uint32_t EVT_DATA0; // +0x3080
<> 144:ef7eb2e8f9f7 225 __IO uint32_t EVT_DATA1; // +0x3084
<> 144:ef7eb2e8f9f7 226 __I uint32_t rsvd_088[14]; // +0x3088
<> 144:ef7eb2e8f9f7 227 __I uint32_t INTERRUPT; // +0x30c0
<> 144:ef7eb2e8f9f7 228 __IO uint32_t INTENMASK; // +0x30c4
<> 144:ef7eb2e8f9f7 229 __IO uint32_t INTENMASK_SET; // +0x30c8
<> 144:ef7eb2e8f9f7 230 __IO uint32_t INTENMASK_CLR; // +0x30cc
<> 144:ef7eb2e8f9f7 231 __I uint32_t REQUEST; // +0x30d0
<> 144:ef7eb2e8f9f7 232 __I uint32_t ACTIVE; // +0x30d4
<> 144:ef7eb2e8f9f7 233 __I uint32_t VCREADY; // +0x30d8
<> 144:ef7eb2e8f9f7 234 __I uint32_t rsvd_0dc; // +0x30dc
<> 144:ef7eb2e8f9f7 235 __IO uint32_t XFERREQ; // +0x30e0
<> 144:ef7eb2e8f9f7 236 __I uint32_t XFERACK; // +0x30e4
<> 144:ef7eb2e8f9f7 237 __I uint32_t rsvd_0e8[6]; // +0x30e8
<> 144:ef7eb2e8f9f7 238 } LLCC_TXD_TypeDef;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 // TX?RX buffer handshake/interrupt fields
<> 144:ef7eb2e8f9f7 241 #define LLCC_CMD0_MASK 0x01
<> 144:ef7eb2e8f9f7 242 #define LLCC_CMD1_MASK 0x02
<> 144:ef7eb2e8f9f7 243 #define LLCC_CMD_MASK 0x03
<> 144:ef7eb2e8f9f7 244 #define LLCC_CMD_IRQ_MASK LLCC_CMD_MASK
<> 144:ef7eb2e8f9f7 245 #define LLCC_DMAH1_MASK 0x04
<> 144:ef7eb2e8f9f7 246 #define LLCC_DMAH2_MASK 0x08
<> 144:ef7eb2e8f9f7 247 #define LLCC_DMAH_MASK 0x0c
<> 144:ef7eb2e8f9f7 248 #define LLCC_DMAL1_MASK 0x10
<> 144:ef7eb2e8f9f7 249 #define LLCC_DMAL2_MASK 0x20
<> 144:ef7eb2e8f9f7 250 #define LLCC_DMAL_MASK 0x30
<> 144:ef7eb2e8f9f7 251 #define LLCC_EVT0_MASK 0x40
<> 144:ef7eb2e8f9f7 252 #define LLCC_EVT1_MASK 0x80
<> 144:ef7eb2e8f9f7 253 #define LLCC_EVT_IRQ_MASK LLCC_EVT1_MASK
<> 144:ef7eb2e8f9f7 254 #define LLCC_EVT_MASK 0xc0
<> 144:ef7eb2e8f9f7 255 #define LLCC_CMD0_IDX 0
<> 144:ef7eb2e8f9f7 256 #define LLCC_CMD1_IDX 1
<> 144:ef7eb2e8f9f7 257 #define LLCC_CMD_IDX LLCC_CMD1_IDX
<> 144:ef7eb2e8f9f7 258 #define LLCC_CMD_IRQ_IDX 1
<> 144:ef7eb2e8f9f7 259 #define LLCC_DMAH1_IDX 2
<> 144:ef7eb2e8f9f7 260 #define LLCC_DMAH2_IDX 3
<> 144:ef7eb2e8f9f7 261 #define LLCC_DMAL1_IDX 4
<> 144:ef7eb2e8f9f7 262 #define LLCC_DMAL2_IDX 5
<> 144:ef7eb2e8f9f7 263 #define LLCC_EVT0_IDX 6
<> 144:ef7eb2e8f9f7 264 #define LLCC_EVT1_IDX 7
<> 144:ef7eb2e8f9f7 265 #define LLCC_EVT_IDX LLCC_EVT1_IDX
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
<> 144:ef7eb2e8f9f7 268 typedef struct
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
<> 144:ef7eb2e8f9f7 271 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
<> 144:ef7eb2e8f9f7 272 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
<> 144:ef7eb2e8f9f7 273 union {
<> 144:ef7eb2e8f9f7 274 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 275 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 276 };
<> 144:ef7eb2e8f9f7 277 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 } CMSDK_UART_TypeDef;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* CMSDK_UART DATA Register Definitions */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
<> 144:ef7eb2e8f9f7 284 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
<> 144:ef7eb2e8f9f7 287 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
<> 144:ef7eb2e8f9f7 290 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
<> 144:ef7eb2e8f9f7 293 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
<> 144:ef7eb2e8f9f7 296 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
<> 144:ef7eb2e8f9f7 299 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
<> 144:ef7eb2e8f9f7 302 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
<> 144:ef7eb2e8f9f7 305 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
<> 144:ef7eb2e8f9f7 308 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
<> 144:ef7eb2e8f9f7 311 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
<> 144:ef7eb2e8f9f7 314 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
<> 144:ef7eb2e8f9f7 317 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
<> 144:ef7eb2e8f9f7 320 #define CMSDK_UART_INTSTATUS_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #define CMSDK_UART_INTSTATUS_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
<> 144:ef7eb2e8f9f7 323 #define CMSDK_UART_INTSTATUS_TXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 #define CMSDK_UART_INTSTATUS_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
<> 144:ef7eb2e8f9f7 326 #define CMSDK_UART_INTSTATUS_RXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #define CMSDK_UART_INTSTATUS_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
<> 144:ef7eb2e8f9f7 329 #define CMSDK_UART_INTSTATUS_TXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
<> 144:ef7eb2e8f9f7 332 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /*----------------------------- Timer (TIMER) -------------------------------*/
<> 144:ef7eb2e8f9f7 336 typedef struct
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
<> 144:ef7eb2e8f9f7 340 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
<> 144:ef7eb2e8f9f7 341 union {
<> 144:ef7eb2e8f9f7 342 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 343 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 344 };
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 } CMSDK_TIMER_TypeDef;
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* CMSDK_TIMER CTRL Register Definitions */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
<> 144:ef7eb2e8f9f7 351 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
<> 144:ef7eb2e8f9f7 354 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
<> 144:ef7eb2e8f9f7 357 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
<> 144:ef7eb2e8f9f7 360 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
<> 144:ef7eb2e8f9f7 363 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
<> 144:ef7eb2e8f9f7 366 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
<> 144:ef7eb2e8f9f7 369 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
<> 144:ef7eb2e8f9f7 372 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /*------------- Timer (TIM) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 376 typedef struct
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
<> 144:ef7eb2e8f9f7 379 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
<> 144:ef7eb2e8f9f7 381 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
<> 144:ef7eb2e8f9f7 382 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 383 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 384 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 385 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 386 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
<> 144:ef7eb2e8f9f7 387 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
<> 144:ef7eb2e8f9f7 389 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
<> 144:ef7eb2e8f9f7 390 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 391 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 392 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 393 uint32_t RESERVED1[945];
<> 144:ef7eb2e8f9f7 394 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
<> 144:ef7eb2e8f9f7 395 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
<> 144:ef7eb2e8f9f7 396 } CMSDK_DUALTIMER_BOTH_TypeDef;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 399 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 402 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 405 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 408 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 411 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 414 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 417 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 420 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 423 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 426 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 429 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 432 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 435 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 438 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 441 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 444 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 447 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 450 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 453 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 456 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 459 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 462 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 465 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 468 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 typedef struct
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
<> 144:ef7eb2e8f9f7 474 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
<> 144:ef7eb2e8f9f7 476 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
<> 144:ef7eb2e8f9f7 477 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 478 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 479 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 480 } CMSDK_DUALTIMER_SINGLE_TypeDef;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 483 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 486 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 489 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 492 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 495 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 498 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 501 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 504 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 507 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 510 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 513 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 516 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
<> 144:ef7eb2e8f9f7 520 typedef struct
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
<> 144:ef7eb2e8f9f7 523 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
<> 144:ef7eb2e8f9f7 524 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 525 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
<> 144:ef7eb2e8f9f7 526 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
<> 144:ef7eb2e8f9f7 527 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
<> 144:ef7eb2e8f9f7 528 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
<> 144:ef7eb2e8f9f7 529 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
<> 144:ef7eb2e8f9f7 530 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
<> 144:ef7eb2e8f9f7 531 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
<> 144:ef7eb2e8f9f7 532 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
<> 144:ef7eb2e8f9f7 533 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
<> 144:ef7eb2e8f9f7 534 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
<> 144:ef7eb2e8f9f7 535 union {
<> 144:ef7eb2e8f9f7 536 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 537 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 538 };
<> 144:ef7eb2e8f9f7 539 uint32_t RESERVED1[241];
<> 144:ef7eb2e8f9f7 540 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
<> 144:ef7eb2e8f9f7 541 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
<> 144:ef7eb2e8f9f7 542 } CMSDK_GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
<> 144:ef7eb2e8f9f7 545 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
<> 144:ef7eb2e8f9f7 548 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
<> 144:ef7eb2e8f9f7 551 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
<> 144:ef7eb2e8f9f7 554 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
<> 144:ef7eb2e8f9f7 557 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
<> 144:ef7eb2e8f9f7 560 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 563 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 566 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
<> 144:ef7eb2e8f9f7 569 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
<> 144:ef7eb2e8f9f7 572 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
<> 144:ef7eb2e8f9f7 575 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
<> 144:ef7eb2e8f9f7 578 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
<> 144:ef7eb2e8f9f7 581 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
<> 144:ef7eb2e8f9f7 584 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
<> 144:ef7eb2e8f9f7 587 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
<> 144:ef7eb2e8f9f7 590 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /*------------- System Control (SYSCON) --------------------------------------*/
<> 144:ef7eb2e8f9f7 594 typedef struct
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
<> 144:ef7eb2e8f9f7 597 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
<> 144:ef7eb2e8f9f7 598 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
<> 144:ef7eb2e8f9f7 599 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
<> 144:ef7eb2e8f9f7 600 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
<> 144:ef7eb2e8f9f7 601 uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 602 __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
<> 144:ef7eb2e8f9f7 603 __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
<> 144:ef7eb2e8f9f7 604 uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 605 __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
<> 144:ef7eb2e8f9f7 606 __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
<> 144:ef7eb2e8f9f7 607 uint32_t RESERVED2[2];
<> 144:ef7eb2e8f9f7 608 __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
<> 144:ef7eb2e8f9f7 609 __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
<> 144:ef7eb2e8f9f7 610 __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
<> 144:ef7eb2e8f9f7 611 __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
<> 144:ef7eb2e8f9f7 612 __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
<> 144:ef7eb2e8f9f7 613 __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
<> 144:ef7eb2e8f9f7 614 uint32_t RESERVED3[10];
<> 144:ef7eb2e8f9f7 615 __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
<> 144:ef7eb2e8f9f7 616 __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
<> 144:ef7eb2e8f9f7 617 __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
<> 144:ef7eb2e8f9f7 618 __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
<> 144:ef7eb2e8f9f7 619 __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
<> 144:ef7eb2e8f9f7 620 __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
<> 144:ef7eb2e8f9f7 621 uint32_t RESERVED4[2];
<> 144:ef7eb2e8f9f7 622 __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
<> 144:ef7eb2e8f9f7 623 __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
<> 144:ef7eb2e8f9f7 624 __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
<> 144:ef7eb2e8f9f7 625 __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
<> 144:ef7eb2e8f9f7 626 __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
<> 144:ef7eb2e8f9f7 627 __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
<> 144:ef7eb2e8f9f7 628 uint32_t RESERVED5[2];
<> 144:ef7eb2e8f9f7 629 __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
<> 144:ef7eb2e8f9f7 630 __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
<> 144:ef7eb2e8f9f7 631 __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
<> 144:ef7eb2e8f9f7 632 __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
<> 144:ef7eb2e8f9f7 633 __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
<> 144:ef7eb2e8f9f7 634 __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
<> 144:ef7eb2e8f9f7 635 __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
<> 144:ef7eb2e8f9f7 636 __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
<> 144:ef7eb2e8f9f7 637 __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
<> 144:ef7eb2e8f9f7 638 __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
<> 144:ef7eb2e8f9f7 639 uint32_t RESERVED6[2];
<> 144:ef7eb2e8f9f7 640 __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
<> 144:ef7eb2e8f9f7 641 __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
<> 144:ef7eb2e8f9f7 642 __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
<> 144:ef7eb2e8f9f7 643 uint32_t RESERVED7[1];
<> 144:ef7eb2e8f9f7 644 __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
<> 144:ef7eb2e8f9f7 645 __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
<> 144:ef7eb2e8f9f7 646 __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
<> 144:ef7eb2e8f9f7 647 } CMSDK_SYSCON_TypeDef;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #define CMSDK_SYSCON_REMAP_Pos 0
<> 144:ef7eb2e8f9f7 650 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
<> 144:ef7eb2e8f9f7 653 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
<> 144:ef7eb2e8f9f7 656 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
<> 144:ef7eb2e8f9f7 659 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
<> 144:ef7eb2e8f9f7 662 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
<> 144:ef7eb2e8f9f7 665 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
<> 144:ef7eb2e8f9f7 668 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
<> 144:ef7eb2e8f9f7 671 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
<> 144:ef7eb2e8f9f7 674 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
<> 144:ef7eb2e8f9f7 677 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /*------------- PL230 uDMA (PL230) --------------------------------------*/
<> 144:ef7eb2e8f9f7 681 typedef struct
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
<> 144:ef7eb2e8f9f7 684 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
<> 144:ef7eb2e8f9f7 685 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
<> 144:ef7eb2e8f9f7 686 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
<> 144:ef7eb2e8f9f7 687 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
<> 144:ef7eb2e8f9f7 688 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
<> 144:ef7eb2e8f9f7 689 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
<> 144:ef7eb2e8f9f7 690 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
<> 144:ef7eb2e8f9f7 691 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
<> 144:ef7eb2e8f9f7 692 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
<> 144:ef7eb2e8f9f7 693 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
<> 144:ef7eb2e8f9f7 694 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
<> 144:ef7eb2e8f9f7 695 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
<> 144:ef7eb2e8f9f7 696 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
<> 144:ef7eb2e8f9f7 697 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
<> 144:ef7eb2e8f9f7 698 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
<> 144:ef7eb2e8f9f7 699 uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 700 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 } CMSDK_PL230_TypeDef;
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #define PL230_DMA_CHNL_BITS 0
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
<> 144:ef7eb2e8f9f7 707 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
<> 144:ef7eb2e8f9f7 710 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
<> 144:ef7eb2e8f9f7 713 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
<> 144:ef7eb2e8f9f7 716 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
<> 144:ef7eb2e8f9f7 719 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
<> 144:ef7eb2e8f9f7 722 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
<> 144:ef7eb2e8f9f7 725 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
<> 144:ef7eb2e8f9f7 728 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
<> 144:ef7eb2e8f9f7 731 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
<> 144:ef7eb2e8f9f7 734 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
<> 144:ef7eb2e8f9f7 737 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
<> 144:ef7eb2e8f9f7 740 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
<> 144:ef7eb2e8f9f7 743 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
<> 144:ef7eb2e8f9f7 746 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
<> 144:ef7eb2e8f9f7 749 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
<> 144:ef7eb2e8f9f7 752 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
<> 144:ef7eb2e8f9f7 755 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
<> 144:ef7eb2e8f9f7 758 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
<> 144:ef7eb2e8f9f7 761 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
<> 144:ef7eb2e8f9f7 764 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
<> 144:ef7eb2e8f9f7 767 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
<> 144:ef7eb2e8f9f7 770 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
<> 144:ef7eb2e8f9f7 773 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /*------------------- Watchdog ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 777 typedef struct
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
<> 144:ef7eb2e8f9f7 781 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
<> 144:ef7eb2e8f9f7 782 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
<> 144:ef7eb2e8f9f7 783 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
<> 144:ef7eb2e8f9f7 784 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
<> 144:ef7eb2e8f9f7 785 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
<> 144:ef7eb2e8f9f7 786 uint32_t RESERVED0[762];
<> 144:ef7eb2e8f9f7 787 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
<> 144:ef7eb2e8f9f7 788 uint32_t RESERVED1[191];
<> 144:ef7eb2e8f9f7 789 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
<> 144:ef7eb2e8f9f7 790 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
<> 144:ef7eb2e8f9f7 791 }CMSDK_WATCHDOG_TypeDef;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 794 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 797 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
<> 144:ef7eb2e8f9f7 800 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
<> 144:ef7eb2e8f9f7 803 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
<> 144:ef7eb2e8f9f7 806 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 809 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 812 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
<> 144:ef7eb2e8f9f7 815 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
<> 144:ef7eb2e8f9f7 818 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
<> 144:ef7eb2e8f9f7 821 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* -------------------- End of section using anonymous unions ------------------- */
<> 144:ef7eb2e8f9f7 826 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 827 #pragma pop
<> 144:ef7eb2e8f9f7 828 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 829 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 830 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 831 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 832 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 833 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 834 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 835 #pragma warning restore
<> 144:ef7eb2e8f9f7 836 #else
<> 144:ef7eb2e8f9f7 837 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 838 #endif
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 844 /* ================ Peripheral memory map ================ */
<> 144:ef7eb2e8f9f7 845 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Peripheral and SRAM base address */
<> 144:ef7eb2e8f9f7 848 #define CMSDK_FLASH_BASE (0x00000000UL)
<> 144:ef7eb2e8f9f7 849 #define CMSDK_SRAM_BASE (0x20000000UL)
<> 144:ef7eb2e8f9f7 850 #define CMSDK_PERIPH_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 #define CMSDK_RAM_BASE (0x20000000UL)
<> 144:ef7eb2e8f9f7 853 #define CMSDK_APB_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 854 #define CMSDK_AHB_BASE (0x40010000UL)
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 #define LLCC_CONT_BASE (0xA0000000UL)
<> 144:ef7eb2e8f9f7 857 #define LLCC_CTRL_BASE (LLCC_CONT_BASE)
<> 144:ef7eb2e8f9f7 858 #define LLCC_RXD_BASE (LLCC_CONT_BASE+0x2000)
<> 144:ef7eb2e8f9f7 859 #define LLCC_TXD_BASE (LLCC_CONT_BASE+0x3000)
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 #define DMAC_CONT_BASE (0xA0001000UL)
<> 144:ef7eb2e8f9f7 862 #define DMAC_DMARH_BASE (DMAC_CONT_BASE+0x00)
<> 144:ef7eb2e8f9f7 863 #define DMAC_DMARL_BASE (DMAC_CONT_BASE+0x40)
<> 144:ef7eb2e8f9f7 864 #define DMAC_DMAWH_BASE (DMAC_CONT_BASE+0x80)
<> 144:ef7eb2e8f9f7 865 #define DMAC_DMAWL_BASE (DMAC_CONT_BASE+0xC0)
<> 144:ef7eb2e8f9f7 866 #define DMAC_HCIR_BASE DMAC_DMARL_BASE
<> 144:ef7eb2e8f9f7 867 #define DMAC_HCIW_BASE DMAC_DMAWL_BASE
<> 144:ef7eb2e8f9f7 868 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 869 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
<> 144:ef7eb2e8f9f7 870 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
<> 144:ef7eb2e8f9f7 871 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
<> 144:ef7eb2e8f9f7 872 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
<> 144:ef7eb2e8f9f7 873 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
<> 144:ef7eb2e8f9f7 874 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
<> 144:ef7eb2e8f9f7 875 #define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL)
<> 144:ef7eb2e8f9f7 876 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* AHB peripherals */
<> 144:ef7eb2e8f9f7 879 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 880 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
<> 144:ef7eb2e8f9f7 881 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
<> 144:ef7eb2e8f9f7 882 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
<> 144:ef7eb2e8f9f7 883 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 887 /* ================ Peripheral declaration ================ */
<> 144:ef7eb2e8f9f7 888 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
<> 144:ef7eb2e8f9f7 891 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
<> 144:ef7eb2e8f9f7 892 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
<> 144:ef7eb2e8f9f7 893 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
<> 144:ef7eb2e8f9f7 894 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
<> 144:ef7eb2e8f9f7 895 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
<> 144:ef7eb2e8f9f7 896 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
<> 144:ef7eb2e8f9f7 897 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
<> 144:ef7eb2e8f9f7 898 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
<> 144:ef7eb2e8f9f7 899 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
<> 144:ef7eb2e8f9f7 900 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
<> 144:ef7eb2e8f9f7 901 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
<> 144:ef7eb2e8f9f7 902 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
<> 144:ef7eb2e8f9f7 903 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #define LLCC_CTL ((LLCC_CTL_TypeDef *) LLCC_CTRL_BASE)
<> 144:ef7eb2e8f9f7 906 #define LLCC_RXD ((LLCC_RXD_TypeDef *) LLCC_RXD_BASE)
<> 144:ef7eb2e8f9f7 907 #define LLCC_TXD ((LLCC_TXD_TypeDef *) LLCC_TXD_BASE)
<> 144:ef7eb2e8f9f7 908 #define DMAC_DMARH ((DMAC_CHAN_TypeDef *) DMAC_DMARH_BASE)
<> 144:ef7eb2e8f9f7 909 #define DMAC_DMARL ((DMAC_CHAN_TypeDef *) DMAC_DMARL_BASE)
<> 144:ef7eb2e8f9f7 910 #define DMAC_DMAWH ((DMAC_CHAN_TypeDef *) DMAC_DMAWH_BASE)
<> 144:ef7eb2e8f9f7 911 #define DMAC_DMAWL ((DMAC_CHAN_TypeDef *) DMAC_DMAWL_BASE)
<> 144:ef7eb2e8f9f7 912 #define DMAC_HCIR DMAC_DMAWL
<> 144:ef7eb2e8f9f7 913 #define DMAC_HCIW DMAC_DMARL
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /*********************************************************************
<> 144:ef7eb2e8f9f7 916 * GPIO 2 / 3 BIT FEILD POS, OUTPUTS
<> 144:ef7eb2e8f9f7 917 *************************************************************************/
<> 144:ef7eb2e8f9f7 918 /* GPIO 2 */
<> 144:ef7eb2e8f9f7 919 #define CORDIO_LLCCTRL_RESETX_BIT (1<<0)
<> 144:ef7eb2e8f9f7 920 #define CORDIO_LLCCTRL_SYSTEM_RESET_BIT (1<<1)
<> 144:ef7eb2e8f9f7 921 #define CORDIO_LLCCTRL_LLC_RESET_BIT (1<<2)
<> 144:ef7eb2e8f9f7 922 #define CORDIO_LLCCTRL_WAKE_REQ_BIT (1<<3)
<> 144:ef7eb2e8f9f7 923 #define CORDIO_LLCCTRL_SLEEP_REQ_BIT (1<<4)
<> 144:ef7eb2e8f9f7 924 #define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT (1<<5)
<> 144:ef7eb2e8f9f7 925 #define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT (1<<6)
<> 144:ef7eb2e8f9f7 926 #define CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT (1<<7)
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* GPIO 3 */
<> 144:ef7eb2e8f9f7 929 #define CORDIO_LLCCTRL_VMEM_ON_BIT ((1<<10) | (1 << 11))
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /*********************************************************************
<> 144:ef7eb2e8f9f7 932 * GPIO 2 / 3 BIT FEILD POS, INPUTS
<> 144:ef7eb2e8f9f7 933 *************************************************************************/
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 #define CORDIO_LLCCTRL_RESET_SYNDROME_MSK (3<<0)
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT (1<<2)
<> 144:ef7eb2e8f9f7 938 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT (1<<3)
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 #define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT (1<<4)
<> 144:ef7eb2e8f9f7 941 #define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT (1<<5)
<> 144:ef7eb2e8f9f7 942 #define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT (1<<6)
<> 144:ef7eb2e8f9f7 943 #define CORDIO_LLCCTRL_STATUS_AWAKE_BIT (1<<7)
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /**************************************************************/
<> 144:ef7eb2e8f9f7 946 // RESET LOW
<> 144:ef7eb2e8f9f7 947 #define CORDIO_LLCCTRL_RESETX_ASSERT() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_RESETX_BIT)
<> 144:ef7eb2e8f9f7 948 #define CORDIO_LLCCTRL_RESETX_NEGATE() (CMSDK_GPIO2->DATAOUT |= CORDIO_LLCCTRL_RESETX_BIT)
<> 144:ef7eb2e8f9f7 949 // RESET HIGH
<> 144:ef7eb2e8f9f7 950 #define CORDIO_LLCCTRL_SYSTEM_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SYSTEM_RESET_BIT)
<> 144:ef7eb2e8f9f7 951 #define CORDIO_LLCCTRL_SYSTEM_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SYSTEM_RESET_BIT)
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 // RESET HIGH
<> 144:ef7eb2e8f9f7 954 #define CORDIO_LLCCTRL_LLC_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_LLC_RESET_BIT)
<> 144:ef7eb2e8f9f7 955 #define CORDIO_LLCCTRL_LLC_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_LLC_RESET_BIT)
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 958 #define CORDIO_LLCCTRL_WAKE_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_WAKE_REQ_BIT)
<> 144:ef7eb2e8f9f7 959 #define CORDIO_LLCCTRL_WAKE_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_WAKE_REQ_BIT)
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 962 #define CORDIO_LLCCTRL_SLEEP_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SLEEP_REQ_BIT)
<> 144:ef7eb2e8f9f7 963 #define CORDIO_LLCCTRL_SLEEP_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SLEEP_REQ_BIT)
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 966 #define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT)
<> 144:ef7eb2e8f9f7 967 #define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT)
<> 144:ef7eb2e8f9f7 968 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 969 #define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT)
<> 144:ef7eb2e8f9f7 970 #define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT)
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 973 #define CORDIO_LLCCTRL_32M_XTAL_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT)
<> 144:ef7eb2e8f9f7 974 #define CORDIO_LLCCTRL_32M_XTAL_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT)
<> 144:ef7eb2e8f9f7 975 // ASSERTS HIGH
<> 144:ef7eb2e8f9f7 976 #define CORDIO_LLCCTRL_VMEM_ON_ASSERT() (CMSDK_GPIO3->DATAOUT |=CORDIO_LLCCTRL_VMEM_ON_BIT)
<> 144:ef7eb2e8f9f7 977 #define CORDIO_LLCCTRL_VMEM_ON_NEGATE() (CMSDK_GPIO3->DATAOUT &=~CORDIO_LLCCTRL_VMEM_ON_BIT)
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /************ READ STATUS ********************/
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 // ACTIVE HIGH, BIT INDEPANDENT
<> 144:ef7eb2e8f9f7 983 #define CORDIO_LLCCTRL_RESET_SYNDROME_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_RESET_SYNDROME_MSK)
<> 144:ef7eb2e8f9f7 984 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 985 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT)
<> 144:ef7eb2e8f9f7 986 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 987 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT)
<> 144:ef7eb2e8f9f7 988 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 989 #define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT)
<> 144:ef7eb2e8f9f7 990 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 991 #define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT)
<> 144:ef7eb2e8f9f7 992 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 993 #define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT)
<> 144:ef7eb2e8f9f7 994 // ACTIVE HIGH
<> 144:ef7eb2e8f9f7 995 #define CORDIO_LLCCTRL_STATUS_AWAKE_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_AWAKE_BIT)
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* ---- DEBUG MASK & VALUE BITs used for diagnosis ---- */
<> 144:ef7eb2e8f9f7 999 #define INSTALL_DEBUG__GPIO_TOGGLES
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 #ifdef INSTALL_DEBUG__GPIO_TOGGLES
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 #define GPIO_TOGGLES_MSK (0xFC)
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 #define BIT_0 (1<<0)
<> 144:ef7eb2e8f9f7 1006 #define BIT_1 (1<<1)
<> 144:ef7eb2e8f9f7 1007 #define BIT_2 (1<<2)
<> 144:ef7eb2e8f9f7 1008 #define BIT_3 (1<<3)
<> 144:ef7eb2e8f9f7 1009 #define BIT_4 (1<<4)
<> 144:ef7eb2e8f9f7 1010 #define BIT_5 (1<<5)
<> 144:ef7eb2e8f9f7 1011 #define BIT_6 (1<<6)
<> 144:ef7eb2e8f9f7 1012 #define BIT_7 (1<<7)
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 #define BIT_SET(B) (CMSDK_GPIO0->DATAOUT |= ((B) & (GPIO_TOGGLES_MSK)))
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 #define BIT_CLR(B) (CMSDK_GPIO0->DATAOUT &= ~((B) & (GPIO_TOGGLES_MSK)))
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* BIT TOGGLE, XOR */
<> 144:ef7eb2e8f9f7 1019 #define BIT_TGL(B) (CMSDK_GPIO0->DATAOUT ^= ((B) & (GPIO_TOGGLES_MSK)))
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 #endif
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 #endif
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 #endif /* CMSDK_BEETLE_H */