Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c@50:a417edff4437, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 07:45:16 2016 +0000
Revision:
50:a417edff4437
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9



Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/



Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file em_emu.c
bogdanm 0:9b334a45a8ff 3 * @brief Energy Management Unit (EMU) Peripheral API
mbed_official 50:a417edff4437 4 * @version 4.2.1
bogdanm 0:9b334a45a8ff 5 *******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
mbed_official 50:a417edff4437 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 *******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 21 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 22 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 23 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 24 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 25 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 28 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 29 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 ******************************************************************************/
bogdanm 0:9b334a45a8ff 32
mbed_official 50:a417edff4437 33 #include <limits.h>
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 #include "em_emu.h"
bogdanm 0:9b334a45a8ff 36 #if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 #include "em_cmu.h"
bogdanm 0:9b334a45a8ff 39 #include "em_system.h"
bogdanm 0:9b334a45a8ff 40 #include "em_assert.h"
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 43 * @addtogroup EM_Library
bogdanm 0:9b334a45a8ff 44 * @{
bogdanm 0:9b334a45a8ff 45 ******************************************************************************/
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 48 * @addtogroup EMU
bogdanm 0:9b334a45a8ff 49 * @brief Energy Management Unit (EMU) Peripheral API
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 ******************************************************************************/
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /* Consistency check, since restoring assumes similar bitpositions in */
bogdanm 0:9b334a45a8ff 54 /* CMU OSCENCMD and STATUS regs */
bogdanm 0:9b334a45a8ff 55 #if (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN)
bogdanm 0:9b334a45a8ff 56 #error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions
bogdanm 0:9b334a45a8ff 57 #endif
bogdanm 0:9b334a45a8ff 58 #if (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN)
bogdanm 0:9b334a45a8ff 59 #error Conflict in HFXOENS and HFXOEN bitpositions
bogdanm 0:9b334a45a8ff 60 #endif
bogdanm 0:9b334a45a8ff 61 #if (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN)
bogdanm 0:9b334a45a8ff 62 #error Conflict in LFRCOENS and LFRCOEN bitpositions
bogdanm 0:9b334a45a8ff 63 #endif
bogdanm 0:9b334a45a8ff 64 #if (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN)
bogdanm 0:9b334a45a8ff 65 #error Conflict in LFXOENS and LFXOEN bitpositions
bogdanm 0:9b334a45a8ff 66 #endif
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 70 /* Fix for errata EMU_E107 - non-WIC interrupt masks. */
mbed_official 50:a417edff4437 71 #if defined( _EFM32_GECKO_FAMILY )
mbed_official 50:a417edff4437 72 #define ERRATA_FIX_EMU_E107_EN
mbed_official 50:a417edff4437 73 #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))
mbed_official 50:a417edff4437 74 #define NON_WIC_INT_MASK_1 (~(0x0U))
mbed_official 50:a417edff4437 75
mbed_official 50:a417edff4437 76 #elif defined( _EFM32_TINY_FAMILY )
mbed_official 50:a417edff4437 77 #define ERRATA_FIX_EMU_E107_EN
mbed_official 50:a417edff4437 78 #define NON_WIC_INT_MASK_0 (~(0x001be323U))
mbed_official 50:a417edff4437 79 #define NON_WIC_INT_MASK_1 (~(0x0U))
mbed_official 50:a417edff4437 80
mbed_official 50:a417edff4437 81 #elif defined( _EFM32_GIANT_FAMILY )
mbed_official 50:a417edff4437 82 #define ERRATA_FIX_EMU_E107_EN
mbed_official 50:a417edff4437 83 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
mbed_official 50:a417edff4437 84 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
mbed_official 50:a417edff4437 85
mbed_official 50:a417edff4437 86 #elif defined( _EFM32_WONDER_FAMILY )
mbed_official 50:a417edff4437 87 #define ERRATA_FIX_EMU_E107_EN
mbed_official 50:a417edff4437 88 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
mbed_official 50:a417edff4437 89 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
mbed_official 50:a417edff4437 90
bogdanm 0:9b334a45a8ff 91 #else
bogdanm 0:9b334a45a8ff 92 /* Zero Gecko and future families are not affected by errata EMU_E107 */
bogdanm 0:9b334a45a8ff 93 #endif
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */
mbed_official 50:a417edff4437 96 #if defined( _EFM32_HAPPY_FAMILY )
bogdanm 0:9b334a45a8ff 97 #define ERRATA_FIX_EMU_E108_EN
bogdanm 0:9b334a45a8ff 98 #endif
bogdanm 0:9b334a45a8ff 99 /** @endcond */
bogdanm 0:9b334a45a8ff 100
mbed_official 50:a417edff4437 101
mbed_official 50:a417edff4437 102 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 103 /* DCDCTODVDD output range min/max */
mbed_official 50:a417edff4437 104 #define PWRCFG_DCDCTODVDD_VMIN 1200
mbed_official 50:a417edff4437 105 #define PWRCFG_DCDCTODVDD_VMAX 3000
mbed_official 50:a417edff4437 106 typedef enum
mbed_official 50:a417edff4437 107 {
mbed_official 50:a417edff4437 108 errataFixDcdcHsInit,
mbed_official 50:a417edff4437 109 errataFixDcdcHsTrimSet,
mbed_official 50:a417edff4437 110 errataFixDcdcHsLnWaitDone
mbed_official 50:a417edff4437 111 } errataFixDcdcHs_TypeDef;
mbed_official 50:a417edff4437 112 errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit;
mbed_official 50:a417edff4437 113 #endif
mbed_official 50:a417edff4437 114
bogdanm 0:9b334a45a8ff 115 /*******************************************************************************
bogdanm 0:9b334a45a8ff 116 ************************** LOCAL VARIABLES ********************************
bogdanm 0:9b334a45a8ff 117 ******************************************************************************/
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 120 /**
bogdanm 0:9b334a45a8ff 121 * CMU configured oscillator selection and oscillator enable status. When a
bogdanm 0:9b334a45a8ff 122 * user configures oscillators, this varaiable shall shadow the configuration.
bogdanm 0:9b334a45a8ff 123 * It is used by the EMU module in order to be able to restore the oscillator
bogdanm 0:9b334a45a8ff 124 * config after having been in certain energy modes (since HW may automatically
bogdanm 0:9b334a45a8ff 125 * alter config when going into an energy mode). It is the responsibility of
bogdanm 0:9b334a45a8ff 126 * the CMU module to keep it up-to-date (or a user if not using the CMU API
bogdanm 0:9b334a45a8ff 127 * for oscillator control).
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129 static uint32_t cmuStatus;
mbed_official 50:a417edff4437 130 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
mbed_official 50:a417edff4437 131 static uint16_t cmuHfclkStatus;
mbed_official 50:a417edff4437 132 #endif
mbed_official 50:a417edff4437 133 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 134 static uint16_t dcdcMaxCurrent_mA;
mbed_official 50:a417edff4437 135 static uint16_t dcdcOutput_mVout;
mbed_official 50:a417edff4437 136 #endif
mbed_official 50:a417edff4437 137
bogdanm 0:9b334a45a8ff 138 /** @endcond */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /*******************************************************************************
bogdanm 0:9b334a45a8ff 142 ************************** LOCAL FUNCTIONS ********************************
bogdanm 0:9b334a45a8ff 143 ******************************************************************************/
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 148 * @brief
bogdanm 0:9b334a45a8ff 149 * Restore oscillators and core clock after having been in EM2 or EM3.
bogdanm 0:9b334a45a8ff 150 ******************************************************************************/
mbed_official 50:a417edff4437 151 static void emuRestore(void)
bogdanm 0:9b334a45a8ff 152 {
bogdanm 0:9b334a45a8ff 153 uint32_t oscEnCmd;
bogdanm 0:9b334a45a8ff 154 uint32_t cmuLocked;
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /* Although we could use the CMU API for most of the below handling, we */
bogdanm 0:9b334a45a8ff 157 /* would like this function to be as efficient as possible. */
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* CMU registers may be locked */
bogdanm 0:9b334a45a8ff 160 cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED;
bogdanm 0:9b334a45a8ff 161 CMU_Unlock();
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* AUXHFRCO are automatically disabled (except if using debugger). */
bogdanm 0:9b334a45a8ff 164 /* HFRCO, USHFRCO and HFXO are automatically disabled. */
bogdanm 0:9b334a45a8ff 165 /* LFRCO/LFXO may be disabled by SW in EM3. */
bogdanm 0:9b334a45a8ff 166 /* Restore according to status prior to entering energy mode. */
bogdanm 0:9b334a45a8ff 167 oscEnCmd = 0;
bogdanm 0:9b334a45a8ff 168 oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0);
bogdanm 0:9b334a45a8ff 169 oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0);
bogdanm 0:9b334a45a8ff 170 oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0);
bogdanm 0:9b334a45a8ff 171 oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0);
bogdanm 0:9b334a45a8ff 172 oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0);
bogdanm 0:9b334a45a8ff 173 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
bogdanm 0:9b334a45a8ff 174 oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0);
bogdanm 0:9b334a45a8ff 175 #endif
bogdanm 0:9b334a45a8ff 176 CMU->OSCENCMD = oscEnCmd;
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178
mbed_official 50:a417edff4437 179 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
bogdanm 0:9b334a45a8ff 180 /* Restore oscillator used for clocking core */
mbed_official 50:a417edff4437 181 switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
bogdanm 0:9b334a45a8ff 182 {
mbed_official 50:a417edff4437 183 case CMU_HFCLKSTATUS_SELECTED_LFRCO:
mbed_official 50:a417edff4437 184 /* HFRCO could only be selected if the autostart HFXO feature is not
mbed_official 50:a417edff4437 185 * enabled, otherwise the HFXO would be started and selected automatically.
mbed_official 50:a417edff4437 186 * Note: this error hook helps catching erroneous oscillator configurations,
mbed_official 50:a417edff4437 187 * when the AUTOSTARTSELEM0EM1 is set in CMU_HFXOCTRL. */
mbed_official 50:a417edff4437 188 if (!(CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1))
mbed_official 50:a417edff4437 189 {
mbed_official 50:a417edff4437 190 /* Wait for LFRCO to stabilize */
mbed_official 50:a417edff4437 191 while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))
mbed_official 50:a417edff4437 192 ;
mbed_official 50:a417edff4437 193 CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO;
mbed_official 50:a417edff4437 194 }
mbed_official 50:a417edff4437 195 else
mbed_official 50:a417edff4437 196 {
mbed_official 50:a417edff4437 197 EFM_ASSERT(0);
mbed_official 50:a417edff4437 198 }
mbed_official 50:a417edff4437 199 break;
mbed_official 50:a417edff4437 200
mbed_official 50:a417edff4437 201 case CMU_HFCLKSTATUS_SELECTED_LFXO:
mbed_official 50:a417edff4437 202 /* Wait for LFXO to stabilize */
mbed_official 50:a417edff4437 203 while (!(CMU->STATUS & CMU_STATUS_LFXORDY))
mbed_official 50:a417edff4437 204 ;
mbed_official 50:a417edff4437 205 CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO;
mbed_official 50:a417edff4437 206 break;
mbed_official 50:a417edff4437 207
mbed_official 50:a417edff4437 208 case CMU_HFCLKSTATUS_SELECTED_HFXO:
mbed_official 50:a417edff4437 209 /* Wait for HFXO to stabilize */
mbed_official 50:a417edff4437 210 while (!(CMU->STATUS & CMU_STATUS_HFXORDY))
mbed_official 50:a417edff4437 211 ;
mbed_official 50:a417edff4437 212 CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
mbed_official 50:a417edff4437 213 break;
bogdanm 0:9b334a45a8ff 214
mbed_official 50:a417edff4437 215 default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
mbed_official 50:a417edff4437 216 /* If core clock was HFRCO core clock, it is automatically restored to */
mbed_official 50:a417edff4437 217 /* state prior to entering energy mode. No need for further action. */
mbed_official 50:a417edff4437 218 break;
mbed_official 50:a417edff4437 219 }
mbed_official 50:a417edff4437 220 #else
mbed_official 50:a417edff4437 221 switch (cmuStatus & (CMU_STATUS_HFRCOSEL
mbed_official 50:a417edff4437 222 | CMU_STATUS_HFXOSEL
mbed_official 50:a417edff4437 223 | CMU_STATUS_LFRCOSEL
mbed_official 50:a417edff4437 224 #if defined( CMU_STATUS_USHFRCODIV2SEL )
mbed_official 50:a417edff4437 225 | CMU_STATUS_USHFRCODIV2SEL
mbed_official 50:a417edff4437 226 #endif
mbed_official 50:a417edff4437 227 | CMU_STATUS_LFXOSEL))
mbed_official 50:a417edff4437 228 {
mbed_official 50:a417edff4437 229 case CMU_STATUS_LFRCOSEL:
mbed_official 50:a417edff4437 230 /* Wait for LFRCO to stabilize */
mbed_official 50:a417edff4437 231 while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))
mbed_official 50:a417edff4437 232 ;
mbed_official 50:a417edff4437 233 CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO;
mbed_official 50:a417edff4437 234 break;
bogdanm 0:9b334a45a8ff 235
mbed_official 50:a417edff4437 236 case CMU_STATUS_LFXOSEL:
mbed_official 50:a417edff4437 237 /* Wait for LFXO to stabilize */
mbed_official 50:a417edff4437 238 while (!(CMU->STATUS & CMU_STATUS_LFXORDY))
mbed_official 50:a417edff4437 239 ;
mbed_official 50:a417edff4437 240 CMU->CMD = CMU_CMD_HFCLKSEL_LFXO;
mbed_official 50:a417edff4437 241 break;
mbed_official 50:a417edff4437 242
mbed_official 50:a417edff4437 243 case CMU_STATUS_HFXOSEL:
mbed_official 50:a417edff4437 244 /* Wait for HFXO to stabilize */
mbed_official 50:a417edff4437 245 while (!(CMU->STATUS & CMU_STATUS_HFXORDY))
mbed_official 50:a417edff4437 246 ;
mbed_official 50:a417edff4437 247 CMU->CMD = CMU_CMD_HFCLKSEL_HFXO;
mbed_official 50:a417edff4437 248 break;
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 #if defined( CMU_STATUS_USHFRCODIV2SEL )
mbed_official 50:a417edff4437 251 case CMU_STATUS_USHFRCODIV2SEL:
mbed_official 50:a417edff4437 252 /* Wait for USHFRCO to stabilize */
mbed_official 50:a417edff4437 253 while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY))
mbed_official 50:a417edff4437 254 ;
mbed_official 50:a417edff4437 255 CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;
mbed_official 50:a417edff4437 256 break;
bogdanm 0:9b334a45a8ff 257 #endif
bogdanm 0:9b334a45a8ff 258
mbed_official 50:a417edff4437 259 default: /* CMU_STATUS_HFRCOSEL */
mbed_official 50:a417edff4437 260 /* If core clock was HFRCO core clock, it is automatically restored to */
mbed_official 50:a417edff4437 261 /* state prior to entering energy mode. No need for further action. */
mbed_official 50:a417edff4437 262 break;
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /* If HFRCO was disabled before entering Energy Mode, turn it off again */
bogdanm 0:9b334a45a8ff 266 /* as it is automatically enabled by wake up */
bogdanm 0:9b334a45a8ff 267 if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) )
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS;
bogdanm 0:9b334a45a8ff 270 }
mbed_official 50:a417edff4437 271 #endif
bogdanm 0:9b334a45a8ff 272 /* Restore CMU register locking */
bogdanm 0:9b334a45a8ff 273 if (cmuLocked)
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 CMU_Lock();
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279
mbed_official 50:a417edff4437 280 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 281 /* Get enable conditions for errata EMU_E107 fix. */
bogdanm 0:9b334a45a8ff 282 static __INLINE bool getErrataFixEmuE107En(void)
bogdanm 0:9b334a45a8ff 283 {
mbed_official 50:a417edff4437 284 /* SYSTEM_ChipRevisionGet could have been used here, but we would like a
mbed_official 50:a417edff4437 285 * faster implementation in this case.
mbed_official 50:a417edff4437 286 */
bogdanm 0:9b334a45a8ff 287 uint16_t majorMinorRev;
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /* CHIP MAJOR bit [3:0] */
mbed_official 50:a417edff4437 290 majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
mbed_official 50:a417edff4437 291 >> _ROMTABLE_PID0_REVMAJOR_SHIFT)
mbed_official 50:a417edff4437 292 << 8;
bogdanm 0:9b334a45a8ff 293 /* CHIP MINOR bit [7:4] */
mbed_official 50:a417edff4437 294 majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
mbed_official 50:a417edff4437 295 >> _ROMTABLE_PID2_REVMINORMSB_SHIFT)
mbed_official 50:a417edff4437 296 << 4;
bogdanm 0:9b334a45a8ff 297 /* CHIP MINOR bit [3:0] */
mbed_official 50:a417edff4437 298 majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
mbed_official 50:a417edff4437 299 >> _ROMTABLE_PID3_REVMINORLSB_SHIFT;
bogdanm 0:9b334a45a8ff 300
mbed_official 50:a417edff4437 301 #if defined( _EFM32_GECKO_FAMILY )
bogdanm 0:9b334a45a8ff 302 return (majorMinorRev <= 0x0103);
mbed_official 50:a417edff4437 303 #elif defined( _EFM32_TINY_FAMILY )
bogdanm 0:9b334a45a8ff 304 return (majorMinorRev <= 0x0102);
mbed_official 50:a417edff4437 305 #elif defined( _EFM32_GIANT_FAMILY )
bogdanm 0:9b334a45a8ff 306 return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);
mbed_official 50:a417edff4437 307 #elif defined( _EFM32_WONDER_FAMILY )
bogdanm 0:9b334a45a8ff 308 return (majorMinorRev == 0x0100);
bogdanm 0:9b334a45a8ff 309 #else
bogdanm 0:9b334a45a8ff 310 /* Zero Gecko and future families are not affected by errata EMU_E107 */
bogdanm 0:9b334a45a8ff 311 return false;
bogdanm 0:9b334a45a8ff 312 #endif
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314 #endif
bogdanm 0:9b334a45a8ff 315
mbed_official 50:a417edff4437 316
mbed_official 50:a417edff4437 317 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 318 /* LP prepare / LN restore P/NFET count */
mbed_official 50:a417edff4437 319 static void maxCurrentUpdate(void);
mbed_official 50:a417edff4437 320 #define DCDC_LP_PFET_CNT 7
mbed_official 50:a417edff4437 321 #define DCDC_LP_NFET_CNT 15
mbed_official 50:a417edff4437 322 void dcdcFetCntSet(bool lpModeSet)
mbed_official 50:a417edff4437 323 {
mbed_official 50:a417edff4437 324 uint32_t tmp;
mbed_official 50:a417edff4437 325 static uint32_t emuDcdcMiscCtrlReg;
mbed_official 50:a417edff4437 326
mbed_official 50:a417edff4437 327 if (lpModeSet)
mbed_official 50:a417edff4437 328 {
mbed_official 50:a417edff4437 329 emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL;
mbed_official 50:a417edff4437 330 tmp = EMU->DCDCMISCCTRL
mbed_official 50:a417edff4437 331 & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK);
mbed_official 50:a417edff4437 332 tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT)
mbed_official 50:a417edff4437 333 | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
mbed_official 50:a417edff4437 334 EMU->DCDCMISCCTRL = tmp;
mbed_official 50:a417edff4437 335 maxCurrentUpdate();
mbed_official 50:a417edff4437 336 }
mbed_official 50:a417edff4437 337 else
mbed_official 50:a417edff4437 338 {
mbed_official 50:a417edff4437 339 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;
mbed_official 50:a417edff4437 340 maxCurrentUpdate();
mbed_official 50:a417edff4437 341 }
mbed_official 50:a417edff4437 342 }
mbed_official 50:a417edff4437 343
mbed_official 50:a417edff4437 344 void dcdcHsFixLnBlock(void)
mbed_official 50:a417edff4437 345 {
mbed_official 50:a417edff4437 346 #define EMU_DCDCSTATUS (* (volatile uint32_t *)(EMU_BASE + 0x7C))
mbed_official 50:a417edff4437 347 if (errataFixDcdcHsState == errataFixDcdcHsTrimSet)
mbed_official 50:a417edff4437 348 {
mbed_official 50:a417edff4437 349 /* Wait for LNRUNNING */
mbed_official 50:a417edff4437 350 if ((EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
mbed_official 50:a417edff4437 351 {
mbed_official 50:a417edff4437 352 while (!(EMU_DCDCSTATUS & (0x1 << 16)));
mbed_official 50:a417edff4437 353 }
mbed_official 50:a417edff4437 354 errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;
mbed_official 50:a417edff4437 355 }
mbed_official 50:a417edff4437 356 }
mbed_official 50:a417edff4437 357 #endif
mbed_official 50:a417edff4437 358
mbed_official 50:a417edff4437 359
bogdanm 0:9b334a45a8ff 360 /** @endcond */
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /*******************************************************************************
bogdanm 0:9b334a45a8ff 364 ************************** GLOBAL FUNCTIONS *******************************
bogdanm 0:9b334a45a8ff 365 ******************************************************************************/
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 368 * @brief
bogdanm 0:9b334a45a8ff 369 * Enter energy mode 2 (EM2).
bogdanm 0:9b334a45a8ff 370 *
bogdanm 0:9b334a45a8ff 371 * @details
bogdanm 0:9b334a45a8ff 372 * When entering EM2, the high frequency clocks are disabled, ie HFXO, HFRCO
bogdanm 0:9b334a45a8ff 373 * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering
bogdanm 0:9b334a45a8ff 374 * EM0, HFRCO is re-enabled and the core will be clocked by the configured
bogdanm 0:9b334a45a8ff 375 * HFRCO band. This ensures a quick wakeup from EM2.
bogdanm 0:9b334a45a8ff 376 *
bogdanm 0:9b334a45a8ff 377 * However, prior to entering EM2, the core may have been using another
bogdanm 0:9b334a45a8ff 378 * oscillator than HFRCO. The @p restore parameter gives the user the option
bogdanm 0:9b334a45a8ff 379 * to restore all HF oscillators according to state prior to entering EM2,
bogdanm 0:9b334a45a8ff 380 * as well as the clock used to clock the core. This restore procedure is
bogdanm 0:9b334a45a8ff 381 * handled by SW. However, since handled by SW, it will not be restored
bogdanm 0:9b334a45a8ff 382 * before completing the interrupt function(s) waking up the core!
bogdanm 0:9b334a45a8ff 383 *
bogdanm 0:9b334a45a8ff 384 * @note
bogdanm 0:9b334a45a8ff 385 * If restoring core clock to use the HFXO oscillator, which has been
bogdanm 0:9b334a45a8ff 386 * disabled during EM2 mode, this function will stall until the oscillator
bogdanm 0:9b334a45a8ff 387 * has stabilized. Stalling time can be reduced by adding interrupt
bogdanm 0:9b334a45a8ff 388 * support detecting stable oscillator, and an asynchronous switch to the
bogdanm 0:9b334a45a8ff 389 * original oscillator. See CMU documentation. Such a feature is however
bogdanm 0:9b334a45a8ff 390 * outside the scope of the implementation in this function.
bogdanm 0:9b334a45a8ff 391 * @par
bogdanm 0:9b334a45a8ff 392 * If HFXO is re-enabled by this function, and NOT used to clock the core,
bogdanm 0:9b334a45a8ff 393 * this function will not wait for HFXO to stabilize. This must be considered
bogdanm 0:9b334a45a8ff 394 * by the application if trying to use features relying on that oscillator
bogdanm 0:9b334a45a8ff 395 * upon return.
bogdanm 0:9b334a45a8ff 396 * @par
bogdanm 0:9b334a45a8ff 397 * If a debugger is attached, the AUXHFRCO will not be disabled if enabled
bogdanm 0:9b334a45a8ff 398 * upon entering EM2. It will thus remain enabled when returning to EM0
bogdanm 0:9b334a45a8ff 399 * regardless of the @p restore parameter.
mbed_official 50:a417edff4437 400 * @par
mbed_official 50:a417edff4437 401 * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(),
mbed_official 50:a417edff4437 402 * the starting and selecting of the core clocks will be identical to the user
mbed_official 50:a417edff4437 403 * independently of the value of the @p restore parameter when waking up on
mbed_official 50:a417edff4437 404 * the wakeup sources corresponding to the autostart and select setting.
bogdanm 0:9b334a45a8ff 405 *
bogdanm 0:9b334a45a8ff 406 * @param[in] restore
bogdanm 0:9b334a45a8ff 407 * @li true - restore oscillators and clocks, see function details.
bogdanm 0:9b334a45a8ff 408 * @li false - do not restore oscillators and clocks, see function details.
bogdanm 0:9b334a45a8ff 409 * @par
bogdanm 0:9b334a45a8ff 410 * The @p restore option should only be used if all clock control is done
bogdanm 0:9b334a45a8ff 411 * via the CMU API.
bogdanm 0:9b334a45a8ff 412 ******************************************************************************/
bogdanm 0:9b334a45a8ff 413 void EMU_EnterEM2(bool restore)
bogdanm 0:9b334a45a8ff 414 {
mbed_official 50:a417edff4437 415 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 416 bool errataFixEmuE107En;
bogdanm 0:9b334a45a8ff 417 uint32_t nonWicIntEn[2];
bogdanm 0:9b334a45a8ff 418 #endif
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /* Auto-update CMU status just in case before entering energy mode. */
bogdanm 0:9b334a45a8ff 421 /* This variable is normally kept up-to-date by the CMU API. */
bogdanm 0:9b334a45a8ff 422 cmuStatus = CMU->STATUS;
mbed_official 50:a417edff4437 423 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
mbed_official 50:a417edff4437 424 cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);
mbed_official 50:a417edff4437 425 #endif
bogdanm 0:9b334a45a8ff 426
mbed_official 50:a417edff4437 427 /* Enter Cortex deep sleep mode */
bogdanm 0:9b334a45a8ff 428 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.
bogdanm 0:9b334a45a8ff 431 Disable the enabled non-WIC interrupts. */
mbed_official 50:a417edff4437 432 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 433 errataFixEmuE107En = getErrataFixEmuE107En();
bogdanm 0:9b334a45a8ff 434 if (errataFixEmuE107En)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
bogdanm 0:9b334a45a8ff 437 NVIC->ICER[0] = nonWicIntEn[0];
bogdanm 0:9b334a45a8ff 438 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
bogdanm 0:9b334a45a8ff 439 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
bogdanm 0:9b334a45a8ff 440 NVIC->ICER[1] = nonWicIntEn[1];
bogdanm 0:9b334a45a8ff 441 #endif
bogdanm 0:9b334a45a8ff 442 }
bogdanm 0:9b334a45a8ff 443 #endif
bogdanm 0:9b334a45a8ff 444
mbed_official 50:a417edff4437 445 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 446 dcdcFetCntSet(true);
mbed_official 50:a417edff4437 447 dcdcHsFixLnBlock();
mbed_official 50:a417edff4437 448 #endif
mbed_official 50:a417edff4437 449
bogdanm 0:9b334a45a8ff 450 __WFI();
bogdanm 0:9b334a45a8ff 451
mbed_official 50:a417edff4437 452 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 453 dcdcFetCntSet(false);
mbed_official 50:a417edff4437 454 #endif
mbed_official 50:a417edff4437 455
bogdanm 0:9b334a45a8ff 456 /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */
mbed_official 50:a417edff4437 457 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 458 if (errataFixEmuE107En)
bogdanm 0:9b334a45a8ff 459 {
bogdanm 0:9b334a45a8ff 460 NVIC->ISER[0] = nonWicIntEn[0];
bogdanm 0:9b334a45a8ff 461 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
bogdanm 0:9b334a45a8ff 462 NVIC->ISER[1] = nonWicIntEn[1];
bogdanm 0:9b334a45a8ff 463 #endif
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465 #endif
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /* Restore oscillators/clocks if specified */
bogdanm 0:9b334a45a8ff 468 if (restore)
bogdanm 0:9b334a45a8ff 469 {
mbed_official 50:a417edff4437 470 emuRestore();
bogdanm 0:9b334a45a8ff 471 }
bogdanm 0:9b334a45a8ff 472 /* If not restoring, and original clock was not HFRCO, we have to */
bogdanm 0:9b334a45a8ff 473 /* update CMSIS core clock variable since core clock has changed */
bogdanm 0:9b334a45a8ff 474 /* to using HFRCO. */
mbed_official 50:a417edff4437 475 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
mbed_official 50:a417edff4437 476 else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
mbed_official 50:a417edff4437 477 != CMU_HFCLKSTATUS_SELECTED_HFRCO)
mbed_official 50:a417edff4437 478 #else
bogdanm 0:9b334a45a8ff 479 else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))
mbed_official 50:a417edff4437 480 #endif
bogdanm 0:9b334a45a8ff 481 {
bogdanm 0:9b334a45a8ff 482 SystemCoreClockUpdate();
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 488 * @brief
bogdanm 0:9b334a45a8ff 489 * Enter energy mode 3 (EM3).
bogdanm 0:9b334a45a8ff 490 *
bogdanm 0:9b334a45a8ff 491 * @details
bogdanm 0:9b334a45a8ff 492 * When entering EM3, the high frequency clocks are disabled by HW, ie HFXO,
bogdanm 0:9b334a45a8ff 493 * HFRCO and AUXHFRCO (for AUXHFRCO, see exception note below). In addition,
bogdanm 0:9b334a45a8ff 494 * the low frequency clocks, ie LFXO and LFRCO are disabled by SW. When
bogdanm 0:9b334a45a8ff 495 * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the
bogdanm 0:9b334a45a8ff 496 * configured HFRCO band. This ensures a quick wakeup from EM3.
bogdanm 0:9b334a45a8ff 497 *
bogdanm 0:9b334a45a8ff 498 * However, prior to entering EM3, the core may have been using another
bogdanm 0:9b334a45a8ff 499 * oscillator than HFRCO. The @p restore parameter gives the user the option
bogdanm 0:9b334a45a8ff 500 * to restore all HF/LF oscillators according to state prior to entering EM3,
bogdanm 0:9b334a45a8ff 501 * as well as the clock used to clock the core. This restore procedure is
bogdanm 0:9b334a45a8ff 502 * handled by SW. However, since handled by SW, it will not be restored
bogdanm 0:9b334a45a8ff 503 * before completing the interrupt function(s) waking up the core!
bogdanm 0:9b334a45a8ff 504 *
bogdanm 0:9b334a45a8ff 505 * @note
bogdanm 0:9b334a45a8ff 506 * If restoring core clock to use an oscillator other than HFRCO, this
bogdanm 0:9b334a45a8ff 507 * function will stall until the oscillator has stabilized. Stalling time
bogdanm 0:9b334a45a8ff 508 * can be reduced by adding interrupt support detecting stable oscillator,
bogdanm 0:9b334a45a8ff 509 * and an asynchronous switch to the original oscillator. See CMU
bogdanm 0:9b334a45a8ff 510 * documentation. Such a feature is however outside the scope of the
bogdanm 0:9b334a45a8ff 511 * implementation in this function.
bogdanm 0:9b334a45a8ff 512 * @par
bogdanm 0:9b334a45a8ff 513 * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock
bogdanm 0:9b334a45a8ff 514 * the core, this function will not wait for those oscillators to stabilize.
bogdanm 0:9b334a45a8ff 515 * This must be considered by the application if trying to use features
bogdanm 0:9b334a45a8ff 516 * relying on those oscillators upon return.
bogdanm 0:9b334a45a8ff 517 * @par
bogdanm 0:9b334a45a8ff 518 * If a debugger is attached, the AUXHFRCO will not be disabled if enabled
bogdanm 0:9b334a45a8ff 519 * upon entering EM3. It will thus remain enabled when returning to EM0
bogdanm 0:9b334a45a8ff 520 * regardless of the @p restore parameter.
bogdanm 0:9b334a45a8ff 521 *
bogdanm 0:9b334a45a8ff 522 * @param[in] restore
bogdanm 0:9b334a45a8ff 523 * @li true - restore oscillators and clocks, see function details.
bogdanm 0:9b334a45a8ff 524 * @li false - do not restore oscillators and clocks, see function details.
bogdanm 0:9b334a45a8ff 525 * @par
bogdanm 0:9b334a45a8ff 526 * The @p restore option should only be used if all clock control is done
bogdanm 0:9b334a45a8ff 527 * via the CMU API.
bogdanm 0:9b334a45a8ff 528 ******************************************************************************/
bogdanm 0:9b334a45a8ff 529 void EMU_EnterEM3(bool restore)
bogdanm 0:9b334a45a8ff 530 {
bogdanm 0:9b334a45a8ff 531 uint32_t cmuLocked;
bogdanm 0:9b334a45a8ff 532
mbed_official 50:a417edff4437 533 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 534 bool errataFixEmuE107En;
bogdanm 0:9b334a45a8ff 535 uint32_t nonWicIntEn[2];
bogdanm 0:9b334a45a8ff 536 #endif
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 /* Auto-update CMU status just in case before entering energy mode. */
bogdanm 0:9b334a45a8ff 539 /* This variable is normally kept up-to-date by the CMU API. */
bogdanm 0:9b334a45a8ff 540 cmuStatus = CMU->STATUS;
mbed_official 50:a417edff4437 541 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
mbed_official 50:a417edff4437 542 cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);
mbed_official 50:a417edff4437 543 #endif
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* CMU registers may be locked */
bogdanm 0:9b334a45a8ff 546 cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED;
bogdanm 0:9b334a45a8ff 547 CMU_Unlock();
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /* Disable LF oscillators */
bogdanm 0:9b334a45a8ff 550 CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS;
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /* Restore CMU register locking */
bogdanm 0:9b334a45a8ff 553 if (cmuLocked)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 CMU_Lock();
bogdanm 0:9b334a45a8ff 556 }
bogdanm 0:9b334a45a8ff 557
mbed_official 50:a417edff4437 558 /* Enter Cortex deep sleep mode */
bogdanm 0:9b334a45a8ff 559 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.
bogdanm 0:9b334a45a8ff 562 Disable the enabled non-WIC interrupts. */
mbed_official 50:a417edff4437 563 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 564 errataFixEmuE107En = getErrataFixEmuE107En();
bogdanm 0:9b334a45a8ff 565 if (errataFixEmuE107En)
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
bogdanm 0:9b334a45a8ff 568 NVIC->ICER[0] = nonWicIntEn[0];
bogdanm 0:9b334a45a8ff 569 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
bogdanm 0:9b334a45a8ff 570 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
bogdanm 0:9b334a45a8ff 571 NVIC->ICER[1] = nonWicIntEn[1];
bogdanm 0:9b334a45a8ff 572 #endif
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 #endif
bogdanm 0:9b334a45a8ff 576
mbed_official 50:a417edff4437 577 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 578 dcdcFetCntSet(true);
mbed_official 50:a417edff4437 579 dcdcHsFixLnBlock();
mbed_official 50:a417edff4437 580 #endif
mbed_official 50:a417edff4437 581
bogdanm 0:9b334a45a8ff 582 __WFI();
bogdanm 0:9b334a45a8ff 583
mbed_official 50:a417edff4437 584 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 585 dcdcFetCntSet(false);
mbed_official 50:a417edff4437 586 #endif
mbed_official 50:a417edff4437 587
bogdanm 0:9b334a45a8ff 588 /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */
mbed_official 50:a417edff4437 589 #if defined( ERRATA_FIX_EMU_E107_EN )
bogdanm 0:9b334a45a8ff 590 if (errataFixEmuE107En)
bogdanm 0:9b334a45a8ff 591 {
bogdanm 0:9b334a45a8ff 592 NVIC->ISER[0] = nonWicIntEn[0];
bogdanm 0:9b334a45a8ff 593 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
bogdanm 0:9b334a45a8ff 594 NVIC->ISER[1] = nonWicIntEn[1];
bogdanm 0:9b334a45a8ff 595 #endif
bogdanm 0:9b334a45a8ff 596 }
bogdanm 0:9b334a45a8ff 597 #endif
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /* Restore oscillators/clocks if specified */
bogdanm 0:9b334a45a8ff 600 if (restore)
bogdanm 0:9b334a45a8ff 601 {
mbed_official 50:a417edff4437 602 emuRestore();
bogdanm 0:9b334a45a8ff 603 }
bogdanm 0:9b334a45a8ff 604 /* If not restoring, and original clock was not HFRCO, we have to */
bogdanm 0:9b334a45a8ff 605 /* update CMSIS core clock variable since core clock has changed */
bogdanm 0:9b334a45a8ff 606 /* to using HFRCO. */
mbed_official 50:a417edff4437 607 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
mbed_official 50:a417edff4437 608 else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
mbed_official 50:a417edff4437 609 != CMU_HFCLKSTATUS_SELECTED_HFRCO)
mbed_official 50:a417edff4437 610 #else
bogdanm 0:9b334a45a8ff 611 else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))
mbed_official 50:a417edff4437 612 #endif
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 SystemCoreClockUpdate();
bogdanm 0:9b334a45a8ff 615 }
bogdanm 0:9b334a45a8ff 616 }
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 620 * @brief
bogdanm 0:9b334a45a8ff 621 * Enter energy mode 4 (EM4).
bogdanm 0:9b334a45a8ff 622 *
bogdanm 0:9b334a45a8ff 623 * @note
bogdanm 0:9b334a45a8ff 624 * Only a power on reset or external reset pin can wake the device from EM4.
bogdanm 0:9b334a45a8ff 625 ******************************************************************************/
bogdanm 0:9b334a45a8ff 626 void EMU_EnterEM4(void)
bogdanm 0:9b334a45a8ff 627 {
bogdanm 0:9b334a45a8ff 628 int i;
bogdanm 0:9b334a45a8ff 629
mbed_official 50:a417edff4437 630 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
mbed_official 50:a417edff4437 631 uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
mbed_official 50:a417edff4437 632 | (2 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
mbed_official 50:a417edff4437 633 uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
mbed_official 50:a417edff4437 634 | (3 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
mbed_official 50:a417edff4437 635 #else
mbed_official 50:a417edff4437 636 uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)
mbed_official 50:a417edff4437 637 | (2 << _EMU_CTRL_EM4CTRL_SHIFT);
mbed_official 50:a417edff4437 638 uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)
mbed_official 50:a417edff4437 639 | (3 << _EMU_CTRL_EM4CTRL_SHIFT);
mbed_official 50:a417edff4437 640 #endif
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 /* Make sure register write lock is disabled */
bogdanm 0:9b334a45a8ff 643 EMU_Unlock();
bogdanm 0:9b334a45a8ff 644
mbed_official 50:a417edff4437 645 #if defined( ERRATA_FIX_EMU_E108_EN )
bogdanm 0:9b334a45a8ff 646 /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */
bogdanm 0:9b334a45a8ff 647 __disable_irq();
bogdanm 0:9b334a45a8ff 648 *(volatile uint32_t *)0x400C80E4 = 0;
bogdanm 0:9b334a45a8ff 649 #endif
bogdanm 0:9b334a45a8ff 650
mbed_official 50:a417edff4437 651 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 652 dcdcFetCntSet(true);
mbed_official 50:a417edff4437 653 dcdcHsFixLnBlock();
mbed_official 50:a417edff4437 654 #endif
mbed_official 50:a417edff4437 655
bogdanm 0:9b334a45a8ff 656 for (i = 0; i < 4; i++)
bogdanm 0:9b334a45a8ff 657 {
mbed_official 50:a417edff4437 658 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
mbed_official 50:a417edff4437 659 EMU->EM4CTRL = em4seq2;
mbed_official 50:a417edff4437 660 EMU->EM4CTRL = em4seq3;
mbed_official 50:a417edff4437 661 }
mbed_official 50:a417edff4437 662 EMU->EM4CTRL = em4seq2;
mbed_official 50:a417edff4437 663 #else
bogdanm 0:9b334a45a8ff 664 EMU->CTRL = em4seq2;
bogdanm 0:9b334a45a8ff 665 EMU->CTRL = em4seq3;
bogdanm 0:9b334a45a8ff 666 }
bogdanm 0:9b334a45a8ff 667 EMU->CTRL = em4seq2;
mbed_official 50:a417edff4437 668 #endif
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 673 * @brief
bogdanm 0:9b334a45a8ff 674 * Power down memory block.
bogdanm 0:9b334a45a8ff 675 *
bogdanm 0:9b334a45a8ff 676 * @param[in] blocks
bogdanm 0:9b334a45a8ff 677 * Specifies a logical OR of bits indicating memory blocks to power down.
bogdanm 0:9b334a45a8ff 678 * Bit 0 selects block 1, bit 1 selects block 2, etc. Memory block 0 cannot
mbed_official 50:a417edff4437 679 * be disabled. Please refer to the reference manual for available
bogdanm 0:9b334a45a8ff 680 * memory blocks for a device.
bogdanm 0:9b334a45a8ff 681 *
bogdanm 0:9b334a45a8ff 682 * @note
bogdanm 0:9b334a45a8ff 683 * Only a reset can make the specified memory block(s) available for use
bogdanm 0:9b334a45a8ff 684 * after having been powered down. Function will be void for devices not
bogdanm 0:9b334a45a8ff 685 * supporting this feature.
bogdanm 0:9b334a45a8ff 686 ******************************************************************************/
bogdanm 0:9b334a45a8ff 687 void EMU_MemPwrDown(uint32_t blocks)
bogdanm 0:9b334a45a8ff 688 {
mbed_official 50:a417edff4437 689 #if defined( _EMU_MEMCTRL_POWERDOWN_MASK )
mbed_official 50:a417edff4437 690 EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK
mbed_official 50:a417edff4437 691 >> _EMU_MEMCTRL_POWERDOWN_SHIFT));
mbed_official 50:a417edff4437 692 EMU->MEMCTRL = blocks;
bogdanm 0:9b334a45a8ff 693
mbed_official 50:a417edff4437 694 #elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \
mbed_official 50:a417edff4437 695 && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \
mbed_official 50:a417edff4437 696 && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK )
mbed_official 50:a417edff4437 697 EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK
mbed_official 50:a417edff4437 698 | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK
mbed_official 50:a417edff4437 699 | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK))
mbed_official 50:a417edff4437 700 == blocks);
bogdanm 0:9b334a45a8ff 701 EMU->MEMCTRL = blocks;
mbed_official 50:a417edff4437 702
mbed_official 50:a417edff4437 703 #elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK )
mbed_official 50:a417edff4437 704 EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks);
mbed_official 50:a417edff4437 705 EMU->MEMCTRL = blocks;
mbed_official 50:a417edff4437 706
mbed_official 50:a417edff4437 707 #elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK )
mbed_official 50:a417edff4437 708 EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks);
mbed_official 50:a417edff4437 709 EMU->RAM0CTRL = blocks;
mbed_official 50:a417edff4437 710
bogdanm 0:9b334a45a8ff 711 #else
bogdanm 0:9b334a45a8ff 712 (void)blocks;
bogdanm 0:9b334a45a8ff 713 #endif
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 718 * @brief
bogdanm 0:9b334a45a8ff 719 * Update EMU module with CMU oscillator selection/enable status.
bogdanm 0:9b334a45a8ff 720 *
bogdanm 0:9b334a45a8ff 721 * @details
bogdanm 0:9b334a45a8ff 722 * When entering EM2 and EM3, the HW may change the core clock oscillator
bogdanm 0:9b334a45a8ff 723 * used, as well as disabling some oscillators. The user may optionally select
bogdanm 0:9b334a45a8ff 724 * to restore the oscillators after waking up from EM2 and EM3 through the
bogdanm 0:9b334a45a8ff 725 * SW API.
bogdanm 0:9b334a45a8ff 726 *
bogdanm 0:9b334a45a8ff 727 * However, in order to support this in a safe way, the EMU module must
bogdanm 0:9b334a45a8ff 728 * be kept up-to-date on the actual selected configuration. The CMU
bogdanm 0:9b334a45a8ff 729 * module must keep the EMU module up-to-date.
bogdanm 0:9b334a45a8ff 730 *
bogdanm 0:9b334a45a8ff 731 * This function is mainly intended for internal use by the CMU module,
bogdanm 0:9b334a45a8ff 732 * but if the applications changes oscillator configurations without
bogdanm 0:9b334a45a8ff 733 * using the CMU API, this function can be used to keep the EMU module
bogdanm 0:9b334a45a8ff 734 * up-to-date.
bogdanm 0:9b334a45a8ff 735 ******************************************************************************/
bogdanm 0:9b334a45a8ff 736 void EMU_UpdateOscConfig(void)
bogdanm 0:9b334a45a8ff 737 {
bogdanm 0:9b334a45a8ff 738 /* Fetch current configuration */
bogdanm 0:9b334a45a8ff 739 cmuStatus = CMU->STATUS;
mbed_official 50:a417edff4437 740 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
mbed_official 50:a417edff4437 741 cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);
mbed_official 50:a417edff4437 742 #endif
bogdanm 0:9b334a45a8ff 743 }
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 747 * @brief
bogdanm 0:9b334a45a8ff 748 * Update EMU module with Energy Mode 2 and 3 configuration
bogdanm 0:9b334a45a8ff 749 *
bogdanm 0:9b334a45a8ff 750 * @param[in] em23Init
bogdanm 0:9b334a45a8ff 751 * Energy Mode 2 and 3 configuration structure
bogdanm 0:9b334a45a8ff 752 ******************************************************************************/
bogdanm 0:9b334a45a8ff 753 void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 #if defined( _EMU_CTRL_EMVREG_MASK )
mbed_official 50:a417edff4437 756 EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG)
mbed_official 50:a417edff4437 757 : (EMU->CTRL & ~EMU_CTRL_EMVREG);
bogdanm 0:9b334a45a8ff 758 #elif defined( _EMU_CTRL_EM23VREG_MASK )
mbed_official 50:a417edff4437 759 EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG)
mbed_official 50:a417edff4437 760 : (EMU->CTRL & ~EMU_CTRL_EM23VREG);
mbed_official 50:a417edff4437 761 #else
mbed_official 50:a417edff4437 762 (void)em23Init;
bogdanm 0:9b334a45a8ff 763 #endif
bogdanm 0:9b334a45a8ff 764 }
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766
mbed_official 50:a417edff4437 767 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
bogdanm 0:9b334a45a8ff 768 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 769 * @brief
bogdanm 0:9b334a45a8ff 770 * Update EMU module with Energy Mode 4 configuration
bogdanm 0:9b334a45a8ff 771 *
bogdanm 0:9b334a45a8ff 772 * @param[in] em4Init
bogdanm 0:9b334a45a8ff 773 * Energy Mode 4 configuration structure
bogdanm 0:9b334a45a8ff 774 ******************************************************************************/
bogdanm 0:9b334a45a8ff 775 void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)
bogdanm 0:9b334a45a8ff 776 {
mbed_official 50:a417edff4437 777 #if defined( _EMU_EM4CONF_MASK )
mbed_official 50:a417edff4437 778 /* Init for platforms with EMU->EM4CONF register */
bogdanm 0:9b334a45a8ff 779 uint32_t em4conf = EMU->EM4CONF;
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /* Clear fields that will be reconfigured */
mbed_official 50:a417edff4437 782 em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK
mbed_official 50:a417edff4437 783 | _EMU_EM4CONF_OSC_MASK
mbed_official 50:a417edff4437 784 | _EMU_EM4CONF_BURTCWU_MASK
mbed_official 50:a417edff4437 785 | _EMU_EM4CONF_VREGEN_MASK);
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 /* Configure new settings */
mbed_official 50:a417edff4437 788 em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)
mbed_official 50:a417edff4437 789 | (em4Init->osc)
mbed_official 50:a417edff4437 790 | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)
mbed_official 50:a417edff4437 791 | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /* Apply configuration. Note that lock can be set after this stage. */
bogdanm 0:9b334a45a8ff 794 EMU->EM4CONF = em4conf;
mbed_official 50:a417edff4437 795
mbed_official 50:a417edff4437 796 #elif defined( _EMU_EM4CTRL_MASK )
mbed_official 50:a417edff4437 797 /* Init for platforms with EMU->EM4CTRL register */
mbed_official 50:a417edff4437 798
mbed_official 50:a417edff4437 799 uint32_t em4ctrl = EMU->EM4CTRL;
mbed_official 50:a417edff4437 800
mbed_official 50:a417edff4437 801 em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK
mbed_official 50:a417edff4437 802 | _EMU_EM4CTRL_RETAINLFRCO_MASK
mbed_official 50:a417edff4437 803 | _EMU_EM4CTRL_RETAINULFRCO_MASK
mbed_official 50:a417edff4437 804 | _EMU_EM4CTRL_EM4STATE_MASK
mbed_official 50:a417edff4437 805 | _EMU_EM4CTRL_EM4IORETMODE_MASK);
mbed_official 50:a417edff4437 806
mbed_official 50:a417edff4437 807 em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0)
mbed_official 50:a417edff4437 808 | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0)
mbed_official 50:a417edff4437 809 | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)
mbed_official 50:a417edff4437 810 | (em4Init->em4State ? EMU_EM4CTRL_EM4STATE_EM4H : 0)
mbed_official 50:a417edff4437 811 | (em4Init->pinRetentionMode);
mbed_official 50:a417edff4437 812
mbed_official 50:a417edff4437 813 EMU->EM4CTRL = em4ctrl;
mbed_official 50:a417edff4437 814 #endif
bogdanm 0:9b334a45a8ff 815 }
bogdanm 0:9b334a45a8ff 816 #endif
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818
bogdanm 0:9b334a45a8ff 819 #if defined( BU_PRESENT )
bogdanm 0:9b334a45a8ff 820 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 821 * @brief
bogdanm 0:9b334a45a8ff 822 * Configure Backup Power Domain settings
bogdanm 0:9b334a45a8ff 823 *
bogdanm 0:9b334a45a8ff 824 * @param[in] bupdInit
bogdanm 0:9b334a45a8ff 825 * Backup power domain initialization structure
bogdanm 0:9b334a45a8ff 826 ******************************************************************************/
bogdanm 0:9b334a45a8ff 827 void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
bogdanm 0:9b334a45a8ff 828 {
bogdanm 0:9b334a45a8ff 829 uint32_t reg;
bogdanm 0:9b334a45a8ff 830
bogdanm 0:9b334a45a8ff 831 /* Set power connection configuration */
mbed_official 50:a417edff4437 832 reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK
mbed_official 50:a417edff4437 833 | _EMU_PWRCONF_VOUTSTRONG_MASK
mbed_official 50:a417edff4437 834 | _EMU_PWRCONF_VOUTMED_MASK
mbed_official 50:a417edff4437 835 | _EMU_PWRCONF_VOUTWEAK_MASK);
bogdanm 0:9b334a45a8ff 836
mbed_official 50:a417edff4437 837 reg |= bupdInit->resistor
mbed_official 50:a417edff4437 838 | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)
mbed_official 50:a417edff4437 839 | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)
mbed_official 50:a417edff4437 840 | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT);
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842 EMU->PWRCONF = reg;
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Set backup domain inactive mode configuration */
bogdanm 0:9b334a45a8ff 845 reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
bogdanm 0:9b334a45a8ff 846 reg |= (bupdInit->inactivePower);
bogdanm 0:9b334a45a8ff 847 EMU->BUINACT = reg;
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 /* Set backup domain active mode configuration */
bogdanm 0:9b334a45a8ff 850 reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK);
bogdanm 0:9b334a45a8ff 851 reg |= (bupdInit->activePower);
bogdanm 0:9b334a45a8ff 852 EMU->BUACT = reg;
bogdanm 0:9b334a45a8ff 853
bogdanm 0:9b334a45a8ff 854 /* Set power control configuration */
mbed_official 50:a417edff4437 855 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK
mbed_official 50:a417edff4437 856 | _EMU_BUCTRL_BODCAL_MASK
mbed_official 50:a417edff4437 857 | _EMU_BUCTRL_STATEN_MASK
mbed_official 50:a417edff4437 858 | _EMU_BUCTRL_EN_MASK);
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
bogdanm 0:9b334a45a8ff 861 release reset */
mbed_official 50:a417edff4437 862 reg |= bupdInit->probe
mbed_official 50:a417edff4437 863 | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)
mbed_official 50:a417edff4437 864 | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)
mbed_official 50:a417edff4437 865 | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT);
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867 /* Enable configuration */
bogdanm 0:9b334a45a8ff 868 EMU->BUCTRL = reg;
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* If enable is true, enable BU_VIN input power pin, if not disable it */
bogdanm 0:9b334a45a8ff 871 EMU_BUPinEnable(bupdInit->enable);
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873 /* If enable is true, release BU reset, if not keep reset asserted */
mbed_official 50:a417edff4437 874 BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);
bogdanm 0:9b334a45a8ff 875 }
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 879 * @brief
bogdanm 0:9b334a45a8ff 880 * Configure Backup Power Domain BOD Threshold value
bogdanm 0:9b334a45a8ff 881 * @note
bogdanm 0:9b334a45a8ff 882 * These values are precalibrated
bogdanm 0:9b334a45a8ff 883 * @param[in] mode Active or Inactive mode
bogdanm 0:9b334a45a8ff 884 * @param[in] value
bogdanm 0:9b334a45a8ff 885 ******************************************************************************/
bogdanm 0:9b334a45a8ff 886 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
bogdanm 0:9b334a45a8ff 887 {
mbed_official 50:a417edff4437 888 EFM_ASSERT(value<8);
bogdanm 0:9b334a45a8ff 889 EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 switch(mode)
bogdanm 0:9b334a45a8ff 892 {
mbed_official 50:a417edff4437 893 case emuBODMode_Active:
mbed_official 50:a417edff4437 894 EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)
mbed_official 50:a417edff4437 895 | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);
mbed_official 50:a417edff4437 896 break;
mbed_official 50:a417edff4437 897 case emuBODMode_Inactive:
mbed_official 50:a417edff4437 898 EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)
mbed_official 50:a417edff4437 899 | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);
mbed_official 50:a417edff4437 900 break;
bogdanm 0:9b334a45a8ff 901 }
bogdanm 0:9b334a45a8ff 902 }
bogdanm 0:9b334a45a8ff 903
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 906 * @brief
bogdanm 0:9b334a45a8ff 907 * Configure Backup Power Domain BOD Threshold Range
bogdanm 0:9b334a45a8ff 908 * @note
bogdanm 0:9b334a45a8ff 909 * These values are precalibrated
bogdanm 0:9b334a45a8ff 910 * @param[in] mode Active or Inactive mode
bogdanm 0:9b334a45a8ff 911 * @param[in] value
bogdanm 0:9b334a45a8ff 912 ******************************************************************************/
bogdanm 0:9b334a45a8ff 913 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value)
bogdanm 0:9b334a45a8ff 914 {
mbed_official 50:a417edff4437 915 EFM_ASSERT(value < 4);
bogdanm 0:9b334a45a8ff 916 EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));
bogdanm 0:9b334a45a8ff 917
bogdanm 0:9b334a45a8ff 918 switch(mode)
bogdanm 0:9b334a45a8ff 919 {
mbed_official 50:a417edff4437 920 case emuBODMode_Active:
mbed_official 50:a417edff4437 921 EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)
mbed_official 50:a417edff4437 922 | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);
mbed_official 50:a417edff4437 923 break;
mbed_official 50:a417edff4437 924 case emuBODMode_Inactive:
mbed_official 50:a417edff4437 925 EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)
mbed_official 50:a417edff4437 926 | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);
mbed_official 50:a417edff4437 927 break;
mbed_official 50:a417edff4437 928 }
mbed_official 50:a417edff4437 929 }
mbed_official 50:a417edff4437 930 #endif
mbed_official 50:a417edff4437 931
mbed_official 50:a417edff4437 932
mbed_official 50:a417edff4437 933 #if defined( _EMU_DCDCCTRL_MASK )
mbed_official 50:a417edff4437 934
mbed_official 50:a417edff4437 935 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
mbed_official 50:a417edff4437 936
mbed_official 50:a417edff4437 937 /***************************************************************************//**
mbed_official 50:a417edff4437 938 * @brief
mbed_official 50:a417edff4437 939 * Load DCDC calibration constants from DI page. Const means calibration
mbed_official 50:a417edff4437 940 * data that does not change depending on other configuration parameters.
mbed_official 50:a417edff4437 941 *
mbed_official 50:a417edff4437 942 * @return
mbed_official 50:a417edff4437 943 * False if calibration registers are locked
mbed_official 50:a417edff4437 944 ******************************************************************************/
mbed_official 50:a417edff4437 945 static bool ConstCalibrationLoad(void)
mbed_official 50:a417edff4437 946 {
mbed_official 50:a417edff4437 947 uint32_t val;
mbed_official 50:a417edff4437 948 volatile uint32_t *reg;
mbed_official 50:a417edff4437 949
mbed_official 50:a417edff4437 950 /* DI calib data in flash */
mbed_official 50:a417edff4437 951 volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038);
mbed_official 50:a417edff4437 952 volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040);
mbed_official 50:a417edff4437 953 volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048);
mbed_official 50:a417edff4437 954 volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050);
mbed_official 50:a417edff4437 955 volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058);
mbed_official 50:a417edff4437 956 volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060);
mbed_official 50:a417edff4437 957
mbed_official 50:a417edff4437 958 if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX)
mbed_official 50:a417edff4437 959 {
mbed_official 50:a417edff4437 960 val = *(diCal_EMU_DCDCLNFREQCTRL + 1);
mbed_official 50:a417edff4437 961 reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;
mbed_official 50:a417edff4437 962 *reg = val;
mbed_official 50:a417edff4437 963
mbed_official 50:a417edff4437 964 val = *(diCal_EMU_DCDCLNVCTRL + 1);
mbed_official 50:a417edff4437 965 reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL;
mbed_official 50:a417edff4437 966 *reg = val;
mbed_official 50:a417edff4437 967
mbed_official 50:a417edff4437 968 val = *(diCal_EMU_DCDCLPCTRL + 1);
mbed_official 50:a417edff4437 969 reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL;
mbed_official 50:a417edff4437 970 *reg = val;
mbed_official 50:a417edff4437 971
mbed_official 50:a417edff4437 972 val = *(diCal_EMU_DCDCLPVCTRL + 1);
mbed_official 50:a417edff4437 973 reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL;
mbed_official 50:a417edff4437 974 *reg = val;
mbed_official 50:a417edff4437 975
mbed_official 50:a417edff4437 976 val = *(diCal_EMU_DCDCTRIM0 + 1);
mbed_official 50:a417edff4437 977 reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0;
mbed_official 50:a417edff4437 978 *reg = val;
mbed_official 50:a417edff4437 979
mbed_official 50:a417edff4437 980 val = *(diCal_EMU_DCDCTRIM1 + 1);
mbed_official 50:a417edff4437 981 reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1;
mbed_official 50:a417edff4437 982 *reg = val;
mbed_official 50:a417edff4437 983
mbed_official 50:a417edff4437 984 return true;
mbed_official 50:a417edff4437 985 }
mbed_official 50:a417edff4437 986 EFM_ASSERT(false);
mbed_official 50:a417edff4437 987 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 988 return false;
mbed_official 50:a417edff4437 989 }
mbed_official 50:a417edff4437 990
mbed_official 50:a417edff4437 991
mbed_official 50:a417edff4437 992 /***************************************************************************//**
mbed_official 50:a417edff4437 993 * @brief
mbed_official 50:a417edff4437 994 * Set recommended and validated current optimization settings
mbed_official 50:a417edff4437 995 *
mbed_official 50:a417edff4437 996 ******************************************************************************/
mbed_official 50:a417edff4437 997 void ValidatedConfigSet(void)
mbed_official 50:a417edff4437 998 {
mbed_official 50:a417edff4437 999 #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44))
mbed_official 50:a417edff4437 1000
mbed_official 50:a417edff4437 1001 uint32_t dcdcTiming;
mbed_official 50:a417edff4437 1002 SYSTEM_PartFamily_TypeDef family;
mbed_official 50:a417edff4437 1003 SYSTEM_ChipRevision_TypeDef rev;
mbed_official 50:a417edff4437 1004
mbed_official 50:a417edff4437 1005 /* Enable duty cycling of the bias */
mbed_official 50:a417edff4437 1006 EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;
mbed_official 50:a417edff4437 1007
mbed_official 50:a417edff4437 1008 /* Set low-noise RCO for EFM32 and EFR32 */
mbed_official 50:a417edff4437 1009 #if defined( _EFR_DEVICE )
mbed_official 50:a417edff4437 1010 /* 7MHz is recommended for all EFR32 parts with DCDC */
mbed_official 50:a417edff4437 1011 EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
mbed_official 50:a417edff4437 1012 | (EMU_DcdcLnRcoBand_7MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
mbed_official 50:a417edff4437 1013 #else
mbed_official 50:a417edff4437 1014 /* 3MHz is recommended for all EFM32 parts with DCDC */
mbed_official 50:a417edff4437 1015 EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
mbed_official 50:a417edff4437 1016 | (EMU_DcdcLnRcoBand_3MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
mbed_official 50:a417edff4437 1017 #endif
mbed_official 50:a417edff4437 1018
mbed_official 50:a417edff4437 1019 EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
mbed_official 50:a417edff4437 1020
mbed_official 50:a417edff4437 1021 family = SYSTEM_GetFamily();
mbed_official 50:a417edff4437 1022 SYSTEM_ChipRevisionGet(&rev);
mbed_official 50:a417edff4437 1023 if ((((family >= systemPartFamilyMighty1P)
mbed_official 50:a417edff4437 1024 && (family <= systemPartFamilyFlex1V))
mbed_official 50:a417edff4437 1025 || (family == systemPartFamilyEfm32Pearl1B)
mbed_official 50:a417edff4437 1026 || (family == systemPartFamilyEfm32Jade1B))
mbed_official 50:a417edff4437 1027 && ((rev.major == 1) && (rev.minor < 3))
mbed_official 50:a417edff4437 1028 && (errataFixDcdcHsState == errataFixDcdcHsInit))
mbed_official 50:a417edff4437 1029 {
mbed_official 50:a417edff4437 1030 /* LPCMPWAITDIS = 1 */
mbed_official 50:a417edff4437 1031 EMU_DCDCSMCTRL |= 1;
mbed_official 50:a417edff4437 1032
mbed_official 50:a417edff4437 1033 dcdcTiming = EMU->DCDCTIMING;
mbed_official 50:a417edff4437 1034 dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
mbed_official 50:a417edff4437 1035 |_EMU_DCDCTIMING_LNWAIT_MASK
mbed_official 50:a417edff4437 1036 |_EMU_DCDCTIMING_BYPWAIT_MASK);
mbed_official 50:a417edff4437 1037
mbed_official 50:a417edff4437 1038 dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
mbed_official 50:a417edff4437 1039 | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
mbed_official 50:a417edff4437 1040 | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));
mbed_official 50:a417edff4437 1041 EMU->DCDCTIMING = dcdcTiming;
mbed_official 50:a417edff4437 1042
mbed_official 50:a417edff4437 1043 errataFixDcdcHsState = errataFixDcdcHsTrimSet;
bogdanm 0:9b334a45a8ff 1044 }
bogdanm 0:9b334a45a8ff 1045 }
bogdanm 0:9b334a45a8ff 1046
mbed_official 50:a417edff4437 1047
mbed_official 50:a417edff4437 1048 /***************************************************************************//**
mbed_official 50:a417edff4437 1049 * @brief
mbed_official 50:a417edff4437 1050 * Calculate and update EMU->DCDCMISCCTRL for maximum DCDC current based
mbed_official 50:a417edff4437 1051 * on the slice configuration and user set maximum.
mbed_official 50:a417edff4437 1052 ******************************************************************************/
mbed_official 50:a417edff4437 1053 static void maxCurrentUpdate(void)
mbed_official 50:a417edff4437 1054 {
mbed_official 50:a417edff4437 1055 uint32_t lncLimImSel;
mbed_official 50:a417edff4437 1056 uint32_t lpcLimImSel;
mbed_official 50:a417edff4437 1057 uint32_t pFetCnt;
mbed_official 50:a417edff4437 1058
mbed_official 50:a417edff4437 1059 pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK)
mbed_official 50:a417edff4437 1060 >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;
mbed_official 50:a417edff4437 1061
mbed_official 50:a417edff4437 1062 /* Equation from Reference Manual section 11.5.20, in the register
mbed_official 50:a417edff4437 1063 field description for LNCLIMILIMSEL and LPCLIMILIMSEL. */
mbed_official 50:a417edff4437 1064 lncLimImSel = (dcdcMaxCurrent_mA / (5 * (pFetCnt + 1))) - 1;
mbed_official 50:a417edff4437 1065 /* 80mA as recommended in Application Note AN0948 */
mbed_official 50:a417edff4437 1066 lpcLimImSel = (80 / (5 * (pFetCnt + 1))) - 1;
mbed_official 50:a417edff4437 1067
mbed_official 50:a417edff4437 1068 lncLimImSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT;
mbed_official 50:a417edff4437 1069 lpcLimImSel <<= _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT;
mbed_official 50:a417edff4437 1070 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
mbed_official 50:a417edff4437 1071 | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK))
mbed_official 50:a417edff4437 1072 | (lncLimImSel | lpcLimImSel);
mbed_official 50:a417edff4437 1073 }
mbed_official 50:a417edff4437 1074
mbed_official 50:a417edff4437 1075
mbed_official 50:a417edff4437 1076 /***************************************************************************//**
mbed_official 50:a417edff4437 1077 * @brief
mbed_official 50:a417edff4437 1078 * Set static variable that holds the user set maximum current. Update
mbed_official 50:a417edff4437 1079 * DCDC configuration.
mbed_official 50:a417edff4437 1080 *
mbed_official 50:a417edff4437 1081 * @param[in] mAmaxCurrent
mbed_official 50:a417edff4437 1082 * Maximum allowed current drawn by the DCDC from VREGVDD in mA.
mbed_official 50:a417edff4437 1083 ******************************************************************************/
mbed_official 50:a417edff4437 1084 static void maxCurrentSet(uint32_t mAmaxCurrent)
mbed_official 50:a417edff4437 1085 {
mbed_official 50:a417edff4437 1086 dcdcMaxCurrent_mA = mAmaxCurrent;
mbed_official 50:a417edff4437 1087 maxCurrentUpdate();
mbed_official 50:a417edff4437 1088 }
mbed_official 50:a417edff4437 1089
mbed_official 50:a417edff4437 1090
mbed_official 50:a417edff4437 1091 /***************************************************************************//**
mbed_official 50:a417edff4437 1092 * @brief
mbed_official 50:a417edff4437 1093 * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback
mbed_official 50:a417edff4437 1094 * attenuation and DEVINFOREV.
mbed_official 50:a417edff4437 1095 *
mbed_official 50:a417edff4437 1096 * @param[in] attSet
mbed_official 50:a417edff4437 1097 * LP feedback attenuation.
mbed_official 50:a417edff4437 1098 * @param[in] lpCmpBias
mbed_official 50:a417edff4437 1099 * lpCmpBias selection
mbed_official 50:a417edff4437 1100 ******************************************************************************/
mbed_official 50:a417edff4437 1101 static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias)
mbed_official 50:a417edff4437 1102 {
mbed_official 50:a417edff4437 1103 uint8_t devinfoRev;
mbed_official 50:a417edff4437 1104 uint32_t lpcmpHystSel;
mbed_official 50:a417edff4437 1105
mbed_official 50:a417edff4437 1106 /* Get calib data revision */
mbed_official 50:a417edff4437 1107 devinfoRev = SYSTEM_GetDevinfoRev();
mbed_official 50:a417edff4437 1108
mbed_official 50:a417edff4437 1109 /* Load LPATT indexed calibration data */
mbed_official 50:a417edff4437 1110 if (devinfoRev < 4)
mbed_official 50:a417edff4437 1111 {
mbed_official 50:a417edff4437 1112 lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0;
mbed_official 50:a417edff4437 1113
mbed_official 50:a417edff4437 1114 if (lpAttenuation)
mbed_official 50:a417edff4437 1115 {
mbed_official 50:a417edff4437 1116 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK)
mbed_official 50:a417edff4437 1117 >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;
mbed_official 50:a417edff4437 1118 }
mbed_official 50:a417edff4437 1119 else
mbed_official 50:a417edff4437 1120 {
mbed_official 50:a417edff4437 1121 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)
mbed_official 50:a417edff4437 1122 >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;
mbed_official 50:a417edff4437 1123 }
mbed_official 50:a417edff4437 1124 }
mbed_official 50:a417edff4437 1125 /* devinfoRev >= 4
mbed_official 50:a417edff4437 1126 Load LPCMPBIAS indexed calibration data */
mbed_official 50:a417edff4437 1127 else
mbed_official 50:a417edff4437 1128 {
mbed_official 50:a417edff4437 1129 lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1;
mbed_official 50:a417edff4437 1130 switch (lpCmpBias)
mbed_official 50:a417edff4437 1131 {
mbed_official 50:a417edff4437 1132 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
mbed_official 50:a417edff4437 1133 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK)
mbed_official 50:a417edff4437 1134 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;
mbed_official 50:a417edff4437 1135 break;
mbed_official 50:a417edff4437 1136
mbed_official 50:a417edff4437 1137 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
mbed_official 50:a417edff4437 1138 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK)
mbed_official 50:a417edff4437 1139 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;
mbed_official 50:a417edff4437 1140 break;
mbed_official 50:a417edff4437 1141
mbed_official 50:a417edff4437 1142 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
mbed_official 50:a417edff4437 1143 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK)
mbed_official 50:a417edff4437 1144 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;
mbed_official 50:a417edff4437 1145 break;
mbed_official 50:a417edff4437 1146
mbed_official 50:a417edff4437 1147 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
mbed_official 50:a417edff4437 1148 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK)
mbed_official 50:a417edff4437 1149 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;
mbed_official 50:a417edff4437 1150 break;
mbed_official 50:a417edff4437 1151
mbed_official 50:a417edff4437 1152 default:
mbed_official 50:a417edff4437 1153 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1154 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1155 return false;
mbed_official 50:a417edff4437 1156 }
mbed_official 50:a417edff4437 1157 }
mbed_official 50:a417edff4437 1158
mbed_official 50:a417edff4437 1159 /* Make sure the sel value is within the field range. */
mbed_official 50:a417edff4437 1160 lpcmpHystSel <<= _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT;
mbed_official 50:a417edff4437 1161 if (lpcmpHystSel & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK)
mbed_official 50:a417edff4437 1162 {
mbed_official 50:a417edff4437 1163 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1164 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1165 return false;
mbed_official 50:a417edff4437 1166 }
mbed_official 50:a417edff4437 1167 EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) | lpcmpHystSel;
mbed_official 50:a417edff4437 1168
mbed_official 50:a417edff4437 1169 return true;
mbed_official 50:a417edff4437 1170 }
mbed_official 50:a417edff4437 1171
mbed_official 50:a417edff4437 1172
mbed_official 50:a417edff4437 1173 /** @endcond */
mbed_official 50:a417edff4437 1174
mbed_official 50:a417edff4437 1175 /***************************************************************************//**
mbed_official 50:a417edff4437 1176 * @brief
mbed_official 50:a417edff4437 1177 * Set DCDC regulator operating mode
mbed_official 50:a417edff4437 1178 *
mbed_official 50:a417edff4437 1179 * @param[in] dcdcMode
mbed_official 50:a417edff4437 1180 * DCDC mode
mbed_official 50:a417edff4437 1181 ******************************************************************************/
mbed_official 50:a417edff4437 1182 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
mbed_official 50:a417edff4437 1183 {
mbed_official 50:a417edff4437 1184 while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
mbed_official 50:a417edff4437 1185 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);
mbed_official 50:a417edff4437 1186 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode;
mbed_official 50:a417edff4437 1187 }
mbed_official 50:a417edff4437 1188
mbed_official 50:a417edff4437 1189
mbed_official 50:a417edff4437 1190 /***************************************************************************//**
mbed_official 50:a417edff4437 1191 * @brief
mbed_official 50:a417edff4437 1192 * Configure DCDC regulator
mbed_official 50:a417edff4437 1193 *
mbed_official 50:a417edff4437 1194 * @note
mbed_official 50:a417edff4437 1195 * Use the function EMU_DCDCPowerDown() to if the power circuit is configured
mbed_official 50:a417edff4437 1196 * for NODCDC as decribed in Section 11.3.4.3 in the Reference Manual.
mbed_official 50:a417edff4437 1197 *
mbed_official 50:a417edff4437 1198 * @param[in] dcdcInit
mbed_official 50:a417edff4437 1199 * DCDC initialization structure
mbed_official 50:a417edff4437 1200 *
mbed_official 50:a417edff4437 1201 * @return
mbed_official 50:a417edff4437 1202 * True if initialization parameters are valid
mbed_official 50:a417edff4437 1203 ******************************************************************************/
mbed_official 50:a417edff4437 1204 bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit)
mbed_official 50:a417edff4437 1205 {
mbed_official 50:a417edff4437 1206 uint32_t lpCmpBiasSel;
mbed_official 50:a417edff4437 1207
mbed_official 50:a417edff4437 1208 /* Set external power configuration. This enables writing to the other
mbed_official 50:a417edff4437 1209 DCDC registers. */
mbed_official 50:a417edff4437 1210 EMU->PWRCFG = dcdcInit->powerConfig;
mbed_official 50:a417edff4437 1211
mbed_official 50:a417edff4437 1212 /* EMU->PWRCFG is write-once and POR reset only. Check that
mbed_official 50:a417edff4437 1213 we could set the desired power configuration. */
mbed_official 50:a417edff4437 1214 if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig)
mbed_official 50:a417edff4437 1215 {
mbed_official 50:a417edff4437 1216 /* If this assert triggers unexpectedly, please power cycle the
mbed_official 50:a417edff4437 1217 kit to reset the power configuration. */
mbed_official 50:a417edff4437 1218 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1219 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1220 return false;
mbed_official 50:a417edff4437 1221 }
mbed_official 50:a417edff4437 1222
mbed_official 50:a417edff4437 1223 /* Load DCDC calibration data from the DI page */
mbed_official 50:a417edff4437 1224 ConstCalibrationLoad();
mbed_official 50:a417edff4437 1225
mbed_official 50:a417edff4437 1226 /* Check current parameters */
mbed_official 50:a417edff4437 1227 EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200);
mbed_official 50:a417edff4437 1228 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA);
mbed_official 50:a417edff4437 1229
mbed_official 50:a417edff4437 1230 /* DCDC low-noise supports max 200mA */
mbed_official 50:a417edff4437 1231 if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise)
mbed_official 50:a417edff4437 1232 {
mbed_official 50:a417edff4437 1233 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200);
mbed_official 50:a417edff4437 1234 }
mbed_official 50:a417edff4437 1235
mbed_official 50:a417edff4437 1236 /* EM2, 3 and 4 current above 100uA is not supported */
mbed_official 50:a417edff4437 1237 EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 100);
mbed_official 50:a417edff4437 1238
mbed_official 50:a417edff4437 1239 /* Decode LP comparator bias for EM0/1 and EM2/3 */
mbed_official 50:a417edff4437 1240 lpCmpBiasSel = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1;
mbed_official 50:a417edff4437 1241 if (dcdcInit->em234LoadCurrent_uA <= 10)
mbed_official 50:a417edff4437 1242 {
mbed_official 50:a417edff4437 1243 lpCmpBiasSel = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0;
mbed_official 50:a417edff4437 1244 }
mbed_official 50:a417edff4437 1245
mbed_official 50:a417edff4437 1246 /* Set DCDC low-power mode comparator bias selection */
mbed_official 50:a417edff4437 1247 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK
mbed_official 50:a417edff4437 1248 | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK))
mbed_official 50:a417edff4437 1249 | ((uint32_t)lpCmpBiasSel
mbed_official 50:a417edff4437 1250 | (uint32_t)dcdcInit->lnTransientMode);
mbed_official 50:a417edff4437 1251
mbed_official 50:a417edff4437 1252 /* Set recommended and validated current optimization settings */
mbed_official 50:a417edff4437 1253 ValidatedConfigSet();
mbed_official 50:a417edff4437 1254
mbed_official 50:a417edff4437 1255 /* Set the maximum current that the DCDC can draw from the power source */
mbed_official 50:a417edff4437 1256 maxCurrentSet(dcdcInit->maxCurrent_mA);
mbed_official 50:a417edff4437 1257
mbed_official 50:a417edff4437 1258 /* Optimize LN slice based on given load current estimate */
mbed_official 50:a417edff4437 1259 EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA);
mbed_official 50:a417edff4437 1260
mbed_official 50:a417edff4437 1261 /* Set DCDC output voltage */
mbed_official 50:a417edff4437 1262 dcdcOutput_mVout = dcdcInit->mVout;
mbed_official 50:a417edff4437 1263 if (!EMU_DCDCOutputVoltageSet(dcdcOutput_mVout, true, true))
mbed_official 50:a417edff4437 1264 {
mbed_official 50:a417edff4437 1265 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1266 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1267 return false;
mbed_official 50:a417edff4437 1268 }
mbed_official 50:a417edff4437 1269
mbed_official 50:a417edff4437 1270 /* Set EM0 DCDC operating mode. Output voltage set in EMU_DCDCOutputVoltageSet()
mbed_official 50:a417edff4437 1271 above takes effect if mode is changed from bypass here. */
mbed_official 50:a417edff4437 1272 EMU_DCDCModeSet(dcdcInit->dcdcMode);
mbed_official 50:a417edff4437 1273
mbed_official 50:a417edff4437 1274 /* Select analog peripheral power supply */
mbed_official 50:a417edff4437 1275 BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0);
mbed_official 50:a417edff4437 1276
mbed_official 50:a417edff4437 1277 return true;
mbed_official 50:a417edff4437 1278 }
mbed_official 50:a417edff4437 1279
mbed_official 50:a417edff4437 1280
mbed_official 50:a417edff4437 1281 /***************************************************************************//**
mbed_official 50:a417edff4437 1282 * @brief
mbed_official 50:a417edff4437 1283 * Set DCDC output voltage
mbed_official 50:a417edff4437 1284 *
mbed_official 50:a417edff4437 1285 * @param[in] mV
mbed_official 50:a417edff4437 1286 * Target DCDC output voltage in mV
mbed_official 50:a417edff4437 1287 *
mbed_official 50:a417edff4437 1288 * @return
mbed_official 50:a417edff4437 1289 * True if the mV parameter is valid
mbed_official 50:a417edff4437 1290 ******************************************************************************/
mbed_official 50:a417edff4437 1291 bool EMU_DCDCOutputVoltageSet(uint32_t mV,
mbed_official 50:a417edff4437 1292 bool setLpVoltage,
mbed_official 50:a417edff4437 1293 bool setLnVoltage)
mbed_official 50:a417edff4437 1294 {
mbed_official 50:a417edff4437 1295 #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )
mbed_official 50:a417edff4437 1296
mbed_official 50:a417edff4437 1297 bool validOutVoltage;
mbed_official 50:a417edff4437 1298 uint8_t lnMode;
mbed_official 50:a417edff4437 1299 bool attSet;
mbed_official 50:a417edff4437 1300 uint32_t attMask;
mbed_official 50:a417edff4437 1301 uint32_t vrefLow = 0;
mbed_official 50:a417edff4437 1302 uint32_t vrefHigh = 0;
mbed_official 50:a417edff4437 1303 uint32_t vrefVal = 0;
mbed_official 50:a417edff4437 1304 uint32_t mVlow = 0;
mbed_official 50:a417edff4437 1305 uint32_t mVhigh = 0;
mbed_official 50:a417edff4437 1306 uint32_t vrefShift;
mbed_official 50:a417edff4437 1307 uint32_t lpcmpBias;
mbed_official 50:a417edff4437 1308 volatile uint32_t* ctrlReg;
mbed_official 50:a417edff4437 1309
mbed_official 50:a417edff4437 1310 /* Check that the set voltage is within valid range.
mbed_official 50:a417edff4437 1311 Voltages are obtained from the datasheet. */
mbed_official 50:a417edff4437 1312 validOutVoltage = false;
mbed_official 50:a417edff4437 1313 if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD)
mbed_official 50:a417edff4437 1314 {
mbed_official 50:a417edff4437 1315 validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)
mbed_official 50:a417edff4437 1316 && (mV <= PWRCFG_DCDCTODVDD_VMAX));
mbed_official 50:a417edff4437 1317 }
mbed_official 50:a417edff4437 1318
mbed_official 50:a417edff4437 1319 if (!validOutVoltage)
mbed_official 50:a417edff4437 1320 {
mbed_official 50:a417edff4437 1321 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1322 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1323 return false;
mbed_official 50:a417edff4437 1324 }
mbed_official 50:a417edff4437 1325
mbed_official 50:a417edff4437 1326 /* Populate both LP and LN registers, set control reg pointer and VREF shift. */
mbed_official 50:a417edff4437 1327 for (lnMode = 0; lnMode <= 1; lnMode++)
mbed_official 50:a417edff4437 1328 {
mbed_official 50:a417edff4437 1329 if (((lnMode == 0) && !setLpVoltage)
mbed_official 50:a417edff4437 1330 || ((lnMode == 1) && !setLnVoltage))
mbed_official 50:a417edff4437 1331 {
mbed_official 50:a417edff4437 1332 continue;
mbed_official 50:a417edff4437 1333 }
mbed_official 50:a417edff4437 1334
mbed_official 50:a417edff4437 1335 ctrlReg = (lnMode ? &EMU->DCDCLNVCTRL : &EMU->DCDCLPVCTRL);
mbed_official 50:a417edff4437 1336 vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT
mbed_official 50:a417edff4437 1337 : _EMU_DCDCLPVCTRL_LPVREF_SHIFT);
mbed_official 50:a417edff4437 1338
mbed_official 50:a417edff4437 1339 /* Set attenuation to use */
mbed_official 50:a417edff4437 1340 attSet = (mV > 1800);
mbed_official 50:a417edff4437 1341 if (attSet)
mbed_official 50:a417edff4437 1342 {
mbed_official 50:a417edff4437 1343 mVlow = 1800;
mbed_official 50:a417edff4437 1344 mVhigh = 3000;
mbed_official 50:a417edff4437 1345 attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT);
mbed_official 50:a417edff4437 1346 }
mbed_official 50:a417edff4437 1347 else
mbed_official 50:a417edff4437 1348 {
mbed_official 50:a417edff4437 1349 mVlow = 1200;
mbed_official 50:a417edff4437 1350 mVhigh = 1800;
mbed_official 50:a417edff4437 1351 attMask = 0;
mbed_official 50:a417edff4437 1352 }
mbed_official 50:a417edff4437 1353
mbed_official 50:a417edff4437 1354 /* Get 2-point calib data from DEVINFO, calculate trimming and set voltege */
mbed_official 50:a417edff4437 1355 if (lnMode)
mbed_official 50:a417edff4437 1356 {
mbed_official 50:a417edff4437 1357 /* Set low-noise DCDC output voltage tuning */
mbed_official 50:a417edff4437 1358 if (attSet)
mbed_official 50:a417edff4437 1359 {
mbed_official 50:a417edff4437 1360 vrefLow = DEVINFO->DCDCLNVCTRL0;
mbed_official 50:a417edff4437 1361 vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
mbed_official 50:a417edff4437 1362 >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
mbed_official 50:a417edff4437 1363 vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)
mbed_official 50:a417edff4437 1364 >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
mbed_official 50:a417edff4437 1365 }
mbed_official 50:a417edff4437 1366 else
mbed_official 50:a417edff4437 1367 {
mbed_official 50:a417edff4437 1368 vrefLow = DEVINFO->DCDCLNVCTRL0;
mbed_official 50:a417edff4437 1369 vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)
mbed_official 50:a417edff4437 1370 >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
mbed_official 50:a417edff4437 1371 vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)
mbed_official 50:a417edff4437 1372 >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
mbed_official 50:a417edff4437 1373 }
mbed_official 50:a417edff4437 1374 }
mbed_official 50:a417edff4437 1375 else
mbed_official 50:a417edff4437 1376 {
mbed_official 50:a417edff4437 1377 /* Set low-power DCDC output voltage tuning */
mbed_official 50:a417edff4437 1378
mbed_official 50:a417edff4437 1379 /* Get LPCMPBIAS and make sure masks are not overlayed */
mbed_official 50:a417edff4437 1380 lpcmpBias = EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK;
mbed_official 50:a417edff4437 1381 EFM_ASSERT(!(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK & attMask));
mbed_official 50:a417edff4437 1382 switch (attMask | lpcmpBias)
mbed_official 50:a417edff4437 1383 {
mbed_official 50:a417edff4437 1384 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
mbed_official 50:a417edff4437 1385 vrefLow = DEVINFO->DCDCLPVCTRL2;
mbed_official 50:a417edff4437 1386 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK)
mbed_official 50:a417edff4437 1387 >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
mbed_official 50:a417edff4437 1388 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK)
mbed_official 50:a417edff4437 1389 >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
mbed_official 50:a417edff4437 1390 break;
mbed_official 50:a417edff4437 1391
mbed_official 50:a417edff4437 1392 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
mbed_official 50:a417edff4437 1393 vrefLow = DEVINFO->DCDCLPVCTRL2;
mbed_official 50:a417edff4437 1394 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK)
mbed_official 50:a417edff4437 1395 >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
mbed_official 50:a417edff4437 1396 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK)
mbed_official 50:a417edff4437 1397 >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
mbed_official 50:a417edff4437 1398 break;
mbed_official 50:a417edff4437 1399
mbed_official 50:a417edff4437 1400 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
mbed_official 50:a417edff4437 1401 vrefLow = DEVINFO->DCDCLPVCTRL3;
mbed_official 50:a417edff4437 1402 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK)
mbed_official 50:a417edff4437 1403 >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
mbed_official 50:a417edff4437 1404 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK)
mbed_official 50:a417edff4437 1405 >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
mbed_official 50:a417edff4437 1406 break;
mbed_official 50:a417edff4437 1407
mbed_official 50:a417edff4437 1408 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
mbed_official 50:a417edff4437 1409 vrefLow = DEVINFO->DCDCLPVCTRL3;
mbed_official 50:a417edff4437 1410 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK)
mbed_official 50:a417edff4437 1411 >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
mbed_official 50:a417edff4437 1412 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK)
mbed_official 50:a417edff4437 1413 >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
mbed_official 50:a417edff4437 1414 break;
mbed_official 50:a417edff4437 1415
mbed_official 50:a417edff4437 1416 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
mbed_official 50:a417edff4437 1417 vrefLow = DEVINFO->DCDCLPVCTRL0;
mbed_official 50:a417edff4437 1418 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK)
mbed_official 50:a417edff4437 1419 >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT;
mbed_official 50:a417edff4437 1420 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK)
mbed_official 50:a417edff4437 1421 >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT;
mbed_official 50:a417edff4437 1422 break;
mbed_official 50:a417edff4437 1423
mbed_official 50:a417edff4437 1424 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
mbed_official 50:a417edff4437 1425 vrefLow = DEVINFO->DCDCLPVCTRL0;
mbed_official 50:a417edff4437 1426 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK)
mbed_official 50:a417edff4437 1427 >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT;
mbed_official 50:a417edff4437 1428 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK)
mbed_official 50:a417edff4437 1429 >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT;
mbed_official 50:a417edff4437 1430 break;
mbed_official 50:a417edff4437 1431
mbed_official 50:a417edff4437 1432 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
mbed_official 50:a417edff4437 1433 vrefLow = DEVINFO->DCDCLPVCTRL1;
mbed_official 50:a417edff4437 1434 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK)
mbed_official 50:a417edff4437 1435 >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT;
mbed_official 50:a417edff4437 1436 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK)
mbed_official 50:a417edff4437 1437 >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT;
mbed_official 50:a417edff4437 1438 break;
mbed_official 50:a417edff4437 1439
mbed_official 50:a417edff4437 1440 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
mbed_official 50:a417edff4437 1441 vrefLow = DEVINFO->DCDCLPVCTRL1;
mbed_official 50:a417edff4437 1442 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK)
mbed_official 50:a417edff4437 1443 >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT;
mbed_official 50:a417edff4437 1444 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK)
mbed_official 50:a417edff4437 1445 >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT;
mbed_official 50:a417edff4437 1446 break;
mbed_official 50:a417edff4437 1447
mbed_official 50:a417edff4437 1448 default:
mbed_official 50:a417edff4437 1449 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1450 break;
mbed_official 50:a417edff4437 1451 }
mbed_official 50:a417edff4437 1452
mbed_official 50:a417edff4437 1453 /* Load LP comparator hysteresis calibration */
mbed_official 50:a417edff4437 1454 if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias >> _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT)))
mbed_official 50:a417edff4437 1455 {
mbed_official 50:a417edff4437 1456 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1457 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1458 return false;
mbed_official 50:a417edff4437 1459 }
mbed_official 50:a417edff4437 1460 } /* Low-nise / low-power mode */
mbed_official 50:a417edff4437 1461
mbed_official 50:a417edff4437 1462
mbed_official 50:a417edff4437 1463 /* Check for valid 2-point trim values */
mbed_official 50:a417edff4437 1464 if ((vrefLow == 0xFF) && (vrefHigh == 0xFF))
mbed_official 50:a417edff4437 1465 {
mbed_official 50:a417edff4437 1466 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1467 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1468 return false;
mbed_official 50:a417edff4437 1469 }
mbed_official 50:a417edff4437 1470
mbed_official 50:a417edff4437 1471 /* Calculate and set voltage trim */
mbed_official 50:a417edff4437 1472 vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow);
mbed_official 50:a417edff4437 1473 vrefVal += vrefLow;
mbed_official 50:a417edff4437 1474
mbed_official 50:a417edff4437 1475 /* Range check */
mbed_official 50:a417edff4437 1476 if ((vrefVal > vrefHigh) || (vrefVal < vrefLow))
mbed_official 50:a417edff4437 1477 {
mbed_official 50:a417edff4437 1478 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1479 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1480 return false;
mbed_official 50:a417edff4437 1481 }
mbed_official 50:a417edff4437 1482
mbed_official 50:a417edff4437 1483 /* Update DCDCLNVCTRL/DCDCLPVCTRL */
mbed_official 50:a417edff4437 1484 *ctrlReg = (vrefVal << vrefShift) | attMask;
mbed_official 50:a417edff4437 1485 }
mbed_official 50:a417edff4437 1486 #endif
mbed_official 50:a417edff4437 1487 return true;
mbed_official 50:a417edff4437 1488 }
mbed_official 50:a417edff4437 1489
mbed_official 50:a417edff4437 1490
mbed_official 50:a417edff4437 1491 /***************************************************************************//**
mbed_official 50:a417edff4437 1492 * @brief
mbed_official 50:a417edff4437 1493 * Optimize DCDC slice count based on the estimated average load current
mbed_official 50:a417edff4437 1494 * in EM0
mbed_official 50:a417edff4437 1495 *
mbed_official 50:a417edff4437 1496 * @param[in] mAEm0LoadCurrent
mbed_official 50:a417edff4437 1497 * Estimated average EM0 load current in mA.
mbed_official 50:a417edff4437 1498 ******************************************************************************/
mbed_official 50:a417edff4437 1499 void EMU_DCDCOptimizeSlice(uint32_t mAEm0LoadCurrent)
mbed_official 50:a417edff4437 1500 {
mbed_official 50:a417edff4437 1501 uint32_t sliceCount = 0;
mbed_official 50:a417edff4437 1502 uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
mbed_official 50:a417edff4437 1503 >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;
mbed_official 50:a417edff4437 1504
mbed_official 50:a417edff4437 1505 /* Set recommended slice count */
mbed_official 50:a417edff4437 1506 if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= EMU_DcdcLnRcoBand_5MHz))
mbed_official 50:a417edff4437 1507 {
mbed_official 50:a417edff4437 1508 if (mAEm0LoadCurrent < 20)
mbed_official 50:a417edff4437 1509 {
mbed_official 50:a417edff4437 1510 sliceCount = 4;
mbed_official 50:a417edff4437 1511 }
mbed_official 50:a417edff4437 1512 else if ((mAEm0LoadCurrent >= 20) && (mAEm0LoadCurrent < 40))
mbed_official 50:a417edff4437 1513 {
mbed_official 50:a417edff4437 1514 sliceCount = 8;
mbed_official 50:a417edff4437 1515 }
mbed_official 50:a417edff4437 1516 else
mbed_official 50:a417edff4437 1517 {
mbed_official 50:a417edff4437 1518 sliceCount = 16;
mbed_official 50:a417edff4437 1519 }
mbed_official 50:a417edff4437 1520 }
mbed_official 50:a417edff4437 1521 else if ((!(EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))
mbed_official 50:a417edff4437 1522 {
mbed_official 50:a417edff4437 1523 if (mAEm0LoadCurrent < 10)
mbed_official 50:a417edff4437 1524 {
mbed_official 50:a417edff4437 1525 sliceCount = 4;
mbed_official 50:a417edff4437 1526 }
mbed_official 50:a417edff4437 1527 else if ((mAEm0LoadCurrent >= 10) && (mAEm0LoadCurrent < 20))
mbed_official 50:a417edff4437 1528 {
mbed_official 50:a417edff4437 1529 sliceCount = 8;
mbed_official 50:a417edff4437 1530 }
mbed_official 50:a417edff4437 1531 else
mbed_official 50:a417edff4437 1532 {
mbed_official 50:a417edff4437 1533 sliceCount = 16;
mbed_official 50:a417edff4437 1534 }
mbed_official 50:a417edff4437 1535 }
mbed_official 50:a417edff4437 1536 else if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))
mbed_official 50:a417edff4437 1537 {
mbed_official 50:a417edff4437 1538 if (mAEm0LoadCurrent < 40)
mbed_official 50:a417edff4437 1539 {
mbed_official 50:a417edff4437 1540 sliceCount = 8;
mbed_official 50:a417edff4437 1541 }
mbed_official 50:a417edff4437 1542 else
mbed_official 50:a417edff4437 1543 {
mbed_official 50:a417edff4437 1544 sliceCount = 16;
mbed_official 50:a417edff4437 1545 }
mbed_official 50:a417edff4437 1546 }
mbed_official 50:a417edff4437 1547 else
mbed_official 50:a417edff4437 1548 {
mbed_official 50:a417edff4437 1549 /* This configuration is not recommended. EMU_DCDCInit() applies a recommended
mbed_official 50:a417edff4437 1550 configuration. */
mbed_official 50:a417edff4437 1551 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1552 }
mbed_official 50:a417edff4437 1553
mbed_official 50:a417edff4437 1554 /* The selected silices are PSLICESEL + 1 */
mbed_official 50:a417edff4437 1555 sliceCount--;
mbed_official 50:a417edff4437 1556
mbed_official 50:a417edff4437 1557 /* Apply slice count to both N and P slice */
mbed_official 50:a417edff4437 1558 sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT
mbed_official 50:a417edff4437 1559 | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
mbed_official 50:a417edff4437 1560 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK
mbed_official 50:a417edff4437 1561 | _EMU_DCDCMISCCTRL_NFETCNT_MASK))
mbed_official 50:a417edff4437 1562 | sliceCount;
mbed_official 50:a417edff4437 1563
mbed_official 50:a417edff4437 1564 /* Update current limit configuration as it depends on the slice configuration. */
mbed_official 50:a417edff4437 1565 maxCurrentUpdate();
mbed_official 50:a417edff4437 1566 }
mbed_official 50:a417edff4437 1567
mbed_official 50:a417edff4437 1568 /***************************************************************************//**
mbed_official 50:a417edff4437 1569 * @brief
mbed_official 50:a417edff4437 1570 * Set DCDC Low-noise RCO band.
mbed_official 50:a417edff4437 1571 *
mbed_official 50:a417edff4437 1572 * @param[in] band
mbed_official 50:a417edff4437 1573 * RCO band to set.
mbed_official 50:a417edff4437 1574 ******************************************************************************/
mbed_official 50:a417edff4437 1575 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
mbed_official 50:a417edff4437 1576 {
mbed_official 50:a417edff4437 1577 EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
mbed_official 50:a417edff4437 1578 | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
mbed_official 50:a417edff4437 1579 }
mbed_official 50:a417edff4437 1580
mbed_official 50:a417edff4437 1581 /***************************************************************************//**
mbed_official 50:a417edff4437 1582 * @brief
mbed_official 50:a417edff4437 1583 * Power off the DCDC regulator.
mbed_official 50:a417edff4437 1584 *
mbed_official 50:a417edff4437 1585 * @details
mbed_official 50:a417edff4437 1586 * This function powers off the DCDC controller. This function should only be
mbed_official 50:a417edff4437 1587 * used if the external power circuit is wired for no DCDC. If the external power
mbed_official 50:a417edff4437 1588 * circuit is wired for DCDC usage, then use EMU_DCDCInit() and set the
mbed_official 50:a417edff4437 1589 * DCDC in bypass mode to disable DCDC.
mbed_official 50:a417edff4437 1590 *
mbed_official 50:a417edff4437 1591 * @return
mbed_official 50:a417edff4437 1592 * Return false if the DCDC could not be disabled.
mbed_official 50:a417edff4437 1593 ******************************************************************************/
mbed_official 50:a417edff4437 1594 bool EMU_DCDCPowerOff(void)
mbed_official 50:a417edff4437 1595 {
mbed_official 50:a417edff4437 1596 /* Set power configuration to hard bypass */
mbed_official 50:a417edff4437 1597 EMU->PWRCFG = 0xF;
mbed_official 50:a417edff4437 1598 if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != 0xF)
mbed_official 50:a417edff4437 1599 {
mbed_official 50:a417edff4437 1600 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1601 /* Return when assertions are disabled */
mbed_official 50:a417edff4437 1602 return false;
mbed_official 50:a417edff4437 1603 }
mbed_official 50:a417edff4437 1604
mbed_official 50:a417edff4437 1605 /* Set DCDC to OFF and disable LP in EM2/3/4 */
mbed_official 50:a417edff4437 1606 EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF;
mbed_official 50:a417edff4437 1607 return true;
mbed_official 50:a417edff4437 1608 }
bogdanm 0:9b334a45a8ff 1609 #endif
bogdanm 0:9b334a45a8ff 1610
bogdanm 0:9b334a45a8ff 1611
mbed_official 50:a417edff4437 1612 #if defined( EMU_STATUS_VMONRDY )
mbed_official 50:a417edff4437 1613 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
mbed_official 50:a417edff4437 1614 __STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(int mV)
mbed_official 50:a417edff4437 1615 {
mbed_official 50:a417edff4437 1616 return (mV - 1200) / 200;
mbed_official 50:a417edff4437 1617 }
mbed_official 50:a417edff4437 1618
mbed_official 50:a417edff4437 1619 __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThreshold)
mbed_official 50:a417edff4437 1620 {
mbed_official 50:a417edff4437 1621 return (mV - 1200 - (coarseThreshold * 200)) / 20;
mbed_official 50:a417edff4437 1622 }
mbed_official 50:a417edff4437 1623 /** @endcond */
mbed_official 50:a417edff4437 1624
mbed_official 50:a417edff4437 1625 /***************************************************************************//**
mbed_official 50:a417edff4437 1626 * @brief
mbed_official 50:a417edff4437 1627 * Initialize VMON channel.
mbed_official 50:a417edff4437 1628 *
mbed_official 50:a417edff4437 1629 * @details
mbed_official 50:a417edff4437 1630 * Initialize a VMON channel without hysteresis. If the channel supports
mbed_official 50:a417edff4437 1631 * separate rise and fall triggers, both thresholds will be set to the same
mbed_official 50:a417edff4437 1632 * value.
mbed_official 50:a417edff4437 1633 *
mbed_official 50:a417edff4437 1634 * @param[in] vmonInit
mbed_official 50:a417edff4437 1635 * VMON initialization struct
mbed_official 50:a417edff4437 1636 ******************************************************************************/
mbed_official 50:a417edff4437 1637 void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit)
mbed_official 50:a417edff4437 1638 {
mbed_official 50:a417edff4437 1639 uint32_t thresholdCoarse, thresholdFine;
mbed_official 50:a417edff4437 1640 EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980));
mbed_official 50:a417edff4437 1641
mbed_official 50:a417edff4437 1642 thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->threshold);
mbed_official 50:a417edff4437 1643 thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->threshold, thresholdCoarse);
mbed_official 50:a417edff4437 1644
mbed_official 50:a417edff4437 1645 switch(vmonInit->channel)
mbed_official 50:a417edff4437 1646 {
mbed_official 50:a417edff4437 1647 case emuVmonChannel_AVDD:
mbed_official 50:a417edff4437 1648 EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1649 | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
mbed_official 50:a417edff4437 1650 | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1651 | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
mbed_official 50:a417edff4437 1652 | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
mbed_official 50:a417edff4437 1653 | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
mbed_official 50:a417edff4437 1654 | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
mbed_official 50:a417edff4437 1655 break;
mbed_official 50:a417edff4437 1656 case emuVmonChannel_ALTAVDD:
mbed_official 50:a417edff4437 1657 EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1658 | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)
mbed_official 50:a417edff4437 1659 | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)
mbed_official 50:a417edff4437 1660 | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)
mbed_official 50:a417edff4437 1661 | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0);
mbed_official 50:a417edff4437 1662 break;
mbed_official 50:a417edff4437 1663 case emuVmonChannel_DVDD:
mbed_official 50:a417edff4437 1664 EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1665 | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)
mbed_official 50:a417edff4437 1666 | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)
mbed_official 50:a417edff4437 1667 | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)
mbed_official 50:a417edff4437 1668 | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0);
mbed_official 50:a417edff4437 1669 break;
mbed_official 50:a417edff4437 1670 case emuVmonChannel_IOVDD0:
mbed_official 50:a417edff4437 1671 EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1672 | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)
mbed_official 50:a417edff4437 1673 | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)
mbed_official 50:a417edff4437 1674 | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)
mbed_official 50:a417edff4437 1675 | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)
mbed_official 50:a417edff4437 1676 | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0);
mbed_official 50:a417edff4437 1677 break;
mbed_official 50:a417edff4437 1678 default:
mbed_official 50:a417edff4437 1679 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1680 return;
mbed_official 50:a417edff4437 1681 }
mbed_official 50:a417edff4437 1682 }
mbed_official 50:a417edff4437 1683
mbed_official 50:a417edff4437 1684 /***************************************************************************//**
mbed_official 50:a417edff4437 1685 * @brief
mbed_official 50:a417edff4437 1686 * Initialize VMON channel with hysteresis (separate rise and fall triggers).
mbed_official 50:a417edff4437 1687 *
mbed_official 50:a417edff4437 1688 * @details
mbed_official 50:a417edff4437 1689 * Initialize a VMON channel which supports hysteresis. The AVDD channel is
mbed_official 50:a417edff4437 1690 * the only channel to support separate rise and fall triggers.
mbed_official 50:a417edff4437 1691 *
mbed_official 50:a417edff4437 1692 * @param[in] vmonInit
mbed_official 50:a417edff4437 1693 * VMON Hysteresis initialization struct
mbed_official 50:a417edff4437 1694 ******************************************************************************/
mbed_official 50:a417edff4437 1695 void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit)
mbed_official 50:a417edff4437 1696 {
mbed_official 50:a417edff4437 1697 uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;
mbed_official 50:a417edff4437 1698 /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */
mbed_official 50:a417edff4437 1699 EFM_ASSERT((vmonInit->riseThreshold >= 1200) && (vmonInit->riseThreshold < 4000));
mbed_official 50:a417edff4437 1700 EFM_ASSERT((vmonInit->fallThreshold >= 1200) && (vmonInit->fallThreshold < 4000));
mbed_official 50:a417edff4437 1701 /* Fall threshold has to be lower than rise threshold */
mbed_official 50:a417edff4437 1702 EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold);
mbed_official 50:a417edff4437 1703
mbed_official 50:a417edff4437 1704 riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->riseThreshold);
mbed_official 50:a417edff4437 1705 riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->riseThreshold, riseThresholdCoarse);
mbed_official 50:a417edff4437 1706 fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->fallThreshold);
mbed_official 50:a417edff4437 1707 fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->fallThreshold, fallThresholdCoarse);
mbed_official 50:a417edff4437 1708
mbed_official 50:a417edff4437 1709 switch(vmonInit->channel)
mbed_official 50:a417edff4437 1710 {
mbed_official 50:a417edff4437 1711 case emuVmonChannel_AVDD:
mbed_official 50:a417edff4437 1712 EMU->VMONAVDDCTRL = (riseThresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1713 | (riseThresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
mbed_official 50:a417edff4437 1714 | (fallThresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
mbed_official 50:a417edff4437 1715 | (fallThresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
mbed_official 50:a417edff4437 1716 | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
mbed_official 50:a417edff4437 1717 | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
mbed_official 50:a417edff4437 1718 | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
mbed_official 50:a417edff4437 1719 break;
mbed_official 50:a417edff4437 1720 default:
mbed_official 50:a417edff4437 1721 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1722 return;
mbed_official 50:a417edff4437 1723 }
mbed_official 50:a417edff4437 1724 }
mbed_official 50:a417edff4437 1725
mbed_official 50:a417edff4437 1726 /***************************************************************************//**
mbed_official 50:a417edff4437 1727 * @brief
mbed_official 50:a417edff4437 1728 * Enable or disable a VMON channel
mbed_official 50:a417edff4437 1729 *
mbed_official 50:a417edff4437 1730 * @param[in] channel
mbed_official 50:a417edff4437 1731 * VMON channel to enable/disable
mbed_official 50:a417edff4437 1732 *
mbed_official 50:a417edff4437 1733 * @param[in] enable
mbed_official 50:a417edff4437 1734 * Whether to enable or disable
mbed_official 50:a417edff4437 1735 ******************************************************************************/
mbed_official 50:a417edff4437 1736 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable)
mbed_official 50:a417edff4437 1737 {
mbed_official 50:a417edff4437 1738 uint32_t volatile * reg;
mbed_official 50:a417edff4437 1739 uint32_t bit;
mbed_official 50:a417edff4437 1740
mbed_official 50:a417edff4437 1741 switch(channel)
mbed_official 50:a417edff4437 1742 {
mbed_official 50:a417edff4437 1743 case emuVmonChannel_AVDD:
mbed_official 50:a417edff4437 1744 reg = &(EMU->VMONAVDDCTRL);
mbed_official 50:a417edff4437 1745 bit = _EMU_VMONAVDDCTRL_EN_SHIFT;
mbed_official 50:a417edff4437 1746 break;
mbed_official 50:a417edff4437 1747 case emuVmonChannel_ALTAVDD:
mbed_official 50:a417edff4437 1748 reg = &(EMU->VMONALTAVDDCTRL);
mbed_official 50:a417edff4437 1749 bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;
mbed_official 50:a417edff4437 1750 break;
mbed_official 50:a417edff4437 1751 case emuVmonChannel_DVDD:
mbed_official 50:a417edff4437 1752 reg = &(EMU->VMONDVDDCTRL);
mbed_official 50:a417edff4437 1753 bit = _EMU_VMONDVDDCTRL_EN_SHIFT;
mbed_official 50:a417edff4437 1754 break;
mbed_official 50:a417edff4437 1755 case emuVmonChannel_IOVDD0:
mbed_official 50:a417edff4437 1756 reg = &(EMU->VMONIO0CTRL);
mbed_official 50:a417edff4437 1757 bit = _EMU_VMONIO0CTRL_EN_SHIFT;
mbed_official 50:a417edff4437 1758 break;
mbed_official 50:a417edff4437 1759 default:
mbed_official 50:a417edff4437 1760 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1761 return;
mbed_official 50:a417edff4437 1762 }
mbed_official 50:a417edff4437 1763
mbed_official 50:a417edff4437 1764 BUS_RegBitWrite(reg, bit, enable);
mbed_official 50:a417edff4437 1765 }
mbed_official 50:a417edff4437 1766
mbed_official 50:a417edff4437 1767 /***************************************************************************//**
mbed_official 50:a417edff4437 1768 * @brief
mbed_official 50:a417edff4437 1769 * Get the status of a voltage monitor channel.
mbed_official 50:a417edff4437 1770 *
mbed_official 50:a417edff4437 1771 * @param[in] channel
mbed_official 50:a417edff4437 1772 * VMON channel to get status for
mbed_official 50:a417edff4437 1773 *
mbed_official 50:a417edff4437 1774 * @return
mbed_official 50:a417edff4437 1775 * Status of the selected VMON channel. True if channel is triggered.
mbed_official 50:a417edff4437 1776 ******************************************************************************/
mbed_official 50:a417edff4437 1777 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)
mbed_official 50:a417edff4437 1778 {
mbed_official 50:a417edff4437 1779 uint32_t bit;
mbed_official 50:a417edff4437 1780 switch(channel)
mbed_official 50:a417edff4437 1781 {
mbed_official 50:a417edff4437 1782 case emuVmonChannel_AVDD:
mbed_official 50:a417edff4437 1783 bit = _EMU_STATUS_VMONAVDD_SHIFT;
mbed_official 50:a417edff4437 1784 break;
mbed_official 50:a417edff4437 1785 case emuVmonChannel_ALTAVDD:
mbed_official 50:a417edff4437 1786 bit = _EMU_STATUS_VMONALTAVDD_SHIFT;
mbed_official 50:a417edff4437 1787 break;
mbed_official 50:a417edff4437 1788 case emuVmonChannel_DVDD:
mbed_official 50:a417edff4437 1789 bit = _EMU_STATUS_VMONDVDD_SHIFT;
mbed_official 50:a417edff4437 1790 break;
mbed_official 50:a417edff4437 1791 case emuVmonChannel_IOVDD0:
mbed_official 50:a417edff4437 1792 bit = _EMU_STATUS_VMONIO0_SHIFT;
mbed_official 50:a417edff4437 1793 break;
mbed_official 50:a417edff4437 1794 default:
mbed_official 50:a417edff4437 1795 EFM_ASSERT(false);
mbed_official 50:a417edff4437 1796 bit = 0;
mbed_official 50:a417edff4437 1797 }
mbed_official 50:a417edff4437 1798
mbed_official 50:a417edff4437 1799 return BUS_RegBitRead(&EMU->STATUS, bit);
mbed_official 50:a417edff4437 1800 }
mbed_official 50:a417edff4437 1801 #endif /* EMU_STATUS_VMONRDY */
mbed_official 50:a417edff4437 1802
bogdanm 0:9b334a45a8ff 1803 /** @} (end addtogroup EMU) */
bogdanm 0:9b334a45a8ff 1804 /** @} (end addtogroup EM_Library) */
bogdanm 0:9b334a45a8ff 1805 #endif /* __EM_EMU_H */