Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c@50:a417edff4437, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 07:45:16 2016 +0000
Revision:
50:a417edff4437
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9



Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/



Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file em_burtc.c
bogdanm 0:9b334a45a8ff 3 * @brief Backup Real Time Counter (BURTC) Peripheral API
mbed_official 50:a417edff4437 4 * @version 4.2.1
bogdanm 0:9b334a45a8ff 5 *******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
mbed_official 50:a417edff4437 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 *******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 21 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 22 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 23 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 24 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 25 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 28 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 29 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 ******************************************************************************/
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33
mbed_official 50:a417edff4437 34 #include "em_burtc.h"
bogdanm 0:9b334a45a8ff 35 #if defined(BURTC_PRESENT)
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 38 * @addtogroup EM_Library
bogdanm 0:9b334a45a8ff 39 * @{
bogdanm 0:9b334a45a8ff 40 ******************************************************************************/
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 43 * @addtogroup BURTC
bogdanm 0:9b334a45a8ff 44 * @brief Backup Real Time Counter (BURTC) Peripheral API
bogdanm 0:9b334a45a8ff 45 * @{
bogdanm 0:9b334a45a8ff 46 ******************************************************************************/
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 /*******************************************************************************
bogdanm 0:9b334a45a8ff 49 ******************************* DEFINES ***********************************
bogdanm 0:9b334a45a8ff 50 ******************************************************************************/
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /*******************************************************************************
bogdanm 0:9b334a45a8ff 53 ************************** LOCAL FUNCTIONS ********************************
bogdanm 0:9b334a45a8ff 54 ******************************************************************************/
bogdanm 0:9b334a45a8ff 55
mbed_official 50:a417edff4437 56 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 57 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 58 * @brief Convert dividend to prescaler logarithmic value. Only works for even
bogdanm 0:9b334a45a8ff 59 * numbers equal to 2^n
bogdanm 0:9b334a45a8ff 60 * @param[in] div Unscaled dividend,
bogdanm 0:9b334a45a8ff 61 * @return Base 2 logarithm of input, as used by fixed prescalers
bogdanm 0:9b334a45a8ff 62 ******************************************************************************/
mbed_official 50:a417edff4437 63 __STATIC_INLINE uint32_t divToLog2(uint32_t div)
bogdanm 0:9b334a45a8ff 64 {
bogdanm 0:9b334a45a8ff 65 uint32_t log2;
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 /* Prescaler accepts an argument of 128 or less, valid values being 2^n */
bogdanm 0:9b334a45a8ff 68 EFM_ASSERT((div > 0) && (div <= 32768));
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic */
bogdanm 0:9b334a45a8ff 71 log2 = (31 - __CLZ(div));
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 return log2;
bogdanm 0:9b334a45a8ff 74 }
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 78 * @brief
bogdanm 0:9b334a45a8ff 79 * Wait for ongoing sync of register(s) to low frequency domain to complete.
bogdanm 0:9b334a45a8ff 80 *
bogdanm 0:9b334a45a8ff 81 * @param[in] mask
bogdanm 0:9b334a45a8ff 82 * Bitmask corresponding to SYNCBUSY register defined bits, indicating
bogdanm 0:9b334a45a8ff 83 * registers that must complete any ongoing synchronization.
bogdanm 0:9b334a45a8ff 84 ******************************************************************************/
mbed_official 50:a417edff4437 85 __STATIC_INLINE void regSync(uint32_t mask)
bogdanm 0:9b334a45a8ff 86 {
bogdanm 0:9b334a45a8ff 87 /* Avoid deadlock if modifying the same register twice when freeze mode is
bogdanm 0:9b334a45a8ff 88 activated, or when no clock is selected for the BURTC. If no clock is
bogdanm 0:9b334a45a8ff 89 selected, then the sync is done once the clock source is set. */
bogdanm 0:9b334a45a8ff 90 if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE)
bogdanm 0:9b334a45a8ff 91 || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) != _BURTC_CTRL_CLKSEL_NONE))
bogdanm 0:9b334a45a8ff 92 {
bogdanm 0:9b334a45a8ff 93 return;
bogdanm 0:9b334a45a8ff 94 }
bogdanm 0:9b334a45a8ff 95 /* Wait for any pending previous write operation to have been completed */
bogdanm 0:9b334a45a8ff 96 /* in low frequency domain. This is only required for the Gecko Family */
bogdanm 0:9b334a45a8ff 97 while (BURTC->SYNCBUSY & mask)
bogdanm 0:9b334a45a8ff 98 ;
bogdanm 0:9b334a45a8ff 99 }
mbed_official 50:a417edff4437 100 /** @endcond */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /*******************************************************************************
bogdanm 0:9b334a45a8ff 104 ************************** GLOBAL FUNCTIONS *******************************
bogdanm 0:9b334a45a8ff 105 ******************************************************************************/
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 108 * @brief Initialize BURTC
bogdanm 0:9b334a45a8ff 109 *
bogdanm 0:9b334a45a8ff 110 * @details
bogdanm 0:9b334a45a8ff 111 * Configures the BURTC peripheral.
bogdanm 0:9b334a45a8ff 112 *
bogdanm 0:9b334a45a8ff 113 * @note
bogdanm 0:9b334a45a8ff 114 * Before initialization, BURTC module must first be enabled by clearing the
bogdanm 0:9b334a45a8ff 115 * reset bit in the RMU, i.e.
bogdanm 0:9b334a45a8ff 116 * @verbatim
mbed_official 50:a417edff4437 117 * RMU_ResetControl(rmuResetBU, rmuResetModeClear);
bogdanm 0:9b334a45a8ff 118 * @endverbatim
bogdanm 0:9b334a45a8ff 119 * Compare channel 0 must be configured outside this function, before
bogdanm 0:9b334a45a8ff 120 * initialization if enable is set to true. The counter will always be reset.
bogdanm 0:9b334a45a8ff 121 *
bogdanm 0:9b334a45a8ff 122 * @param[in] burtcInit
bogdanm 0:9b334a45a8ff 123 * Pointer to BURTC initialization structure
bogdanm 0:9b334a45a8ff 124 ******************************************************************************/
bogdanm 0:9b334a45a8ff 125 void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
bogdanm 0:9b334a45a8ff 126 {
bogdanm 0:9b334a45a8ff 127 uint32_t ctrl;
bogdanm 0:9b334a45a8ff 128 uint32_t presc;
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Check initializer structure integrity */
bogdanm 0:9b334a45a8ff 131 EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0);
bogdanm 0:9b334a45a8ff 132 /* Clock divider must be between 1 and 128, really on the form 2^n */
bogdanm 0:9b334a45a8ff 133 EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128));
bogdanm 0:9b334a45a8ff 134 /* Ignored compare bits during low power operation must be less than 7 */
bogdanm 0:9b334a45a8ff 135 /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7 */
bogdanm 0:9b334a45a8ff 136 EFM_ASSERT(burtcInit->lowPowerComp <= 6);
bogdanm 0:9b334a45a8ff 137 /* You cannot enable the BURTC if mode is set to disabled */
bogdanm 0:9b334a45a8ff 138 EFM_ASSERT((burtcInit->enable == false) ||
mbed_official 50:a417edff4437 139 ((burtcInit->enable == true)
mbed_official 50:a417edff4437 140 && (burtcInit->mode != burtcModeDisable)));
bogdanm 0:9b334a45a8ff 141 /* Low power mode is only available with LFRCO or LFXO as clock source */
mbed_official 50:a417edff4437 142 EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO)
mbed_official 50:a417edff4437 143 || ((burtcInit->clkSel == burtcClkSelULFRCO)
mbed_official 50:a417edff4437 144 && (burtcInit->lowPowerMode == burtcLPDisable)));
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /* Calculate prescaler value from clock divider input */
bogdanm 0:9b334a45a8ff 147 /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of
bogdanm 0:9b334a45a8ff 148 value 1 will select a 2kHz ULFRCO clock, while any other value will
bogdanm 0:9b334a45a8ff 149 select a 1kHz ULFRCO clock source. */
mbed_official 50:a417edff4437 150 presc = divToLog2(burtcInit->clkDiv);
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /* Make sure all registers are updated simultaneously */
bogdanm 0:9b334a45a8ff 153 if (burtcInit->enable)
bogdanm 0:9b334a45a8ff 154 {
bogdanm 0:9b334a45a8ff 155 BURTC_FreezeEnable(true);
bogdanm 0:9b334a45a8ff 156 }
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /* Modification of LPMODE register requires sync with potential ongoing
bogdanm 0:9b334a45a8ff 159 * register updates in LF domain. */
mbed_official 50:a417edff4437 160 regSync(BURTC_SYNCBUSY_LPMODE);
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /* Configure low power mode */
bogdanm 0:9b334a45a8ff 163 BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode);
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* New configuration */
mbed_official 50:a417edff4437 166 ctrl = (BURTC_CTRL_RSTEN
mbed_official 50:a417edff4437 167 | (burtcInit->mode)
mbed_official 50:a417edff4437 168 | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT)
mbed_official 50:a417edff4437 169 | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT)
mbed_official 50:a417edff4437 170 | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT)
mbed_official 50:a417edff4437 171 | (presc << _BURTC_CTRL_PRESC_SHIFT)
mbed_official 50:a417edff4437 172 | (burtcInit->clkSel)
mbed_official 50:a417edff4437 173 | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /* Clear interrupts */
bogdanm 0:9b334a45a8ff 176 BURTC_IntClear(0xFFFFFFFF);
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 /* Set new configuration */
bogdanm 0:9b334a45a8ff 179 BURTC->CTRL = ctrl;
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /* Enable BURTC and counter */
bogdanm 0:9b334a45a8ff 182 if (burtcInit->enable)
bogdanm 0:9b334a45a8ff 183 {
bogdanm 0:9b334a45a8ff 184 /* To enable BURTC counter, we need to disable reset */
bogdanm 0:9b334a45a8ff 185 BURTC_Enable(true);
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /* Clear freeze */
bogdanm 0:9b334a45a8ff 188 BURTC_FreezeEnable(false);
bogdanm 0:9b334a45a8ff 189 }
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 194 * @brief Set BURTC compare channel
bogdanm 0:9b334a45a8ff 195 *
bogdanm 0:9b334a45a8ff 196 * @param[in] comp Compare channel index, must be 0 for Giant / Leopard Gecko
bogdanm 0:9b334a45a8ff 197 *
bogdanm 0:9b334a45a8ff 198 * @param[in] value New compare value
bogdanm 0:9b334a45a8ff 199 ******************************************************************************/
bogdanm 0:9b334a45a8ff 200 void BURTC_CompareSet(unsigned int comp, uint32_t value)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 EFM_ASSERT(comp == 0);
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Modification of COMP0 register requires sync with potential ongoing
bogdanm 0:9b334a45a8ff 207 * register updates in LF domain. */
mbed_official 50:a417edff4437 208 regSync(BURTC_SYNCBUSY_COMP0);
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Configure compare channel 0 */
bogdanm 0:9b334a45a8ff 211 BURTC->COMP0 = value;
bogdanm 0:9b334a45a8ff 212 }
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 216 * @brief Get BURTC compare value
bogdanm 0:9b334a45a8ff 217 *
bogdanm 0:9b334a45a8ff 218 * @param[in] comp Compare channel index value, must be 0 for Giant/Leopard.
bogdanm 0:9b334a45a8ff 219 *
bogdanm 0:9b334a45a8ff 220 * @return Currently configured value for this compare channel
bogdanm 0:9b334a45a8ff 221 ******************************************************************************/
bogdanm 0:9b334a45a8ff 222 uint32_t BURTC_CompareGet(unsigned int comp)
bogdanm 0:9b334a45a8ff 223 {
bogdanm 0:9b334a45a8ff 224 (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 EFM_ASSERT(comp == 0);
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 return BURTC->COMP0;
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 233 * @brief Reset counter
bogdanm 0:9b334a45a8ff 234 ******************************************************************************/
bogdanm 0:9b334a45a8ff 235 void BURTC_CounterReset(void)
bogdanm 0:9b334a45a8ff 236 {
bogdanm 0:9b334a45a8ff 237 /* Set and clear reset bit */
mbed_official 50:a417edff4437 238 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
mbed_official 50:a417edff4437 239 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
bogdanm 0:9b334a45a8ff 240 }
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 244 * @brief
bogdanm 0:9b334a45a8ff 245 * Restore BURTC to reset state
bogdanm 0:9b334a45a8ff 246 * @note
bogdanm 0:9b334a45a8ff 247 * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared.
bogdanm 0:9b334a45a8ff 248 * LOCK will not be reset to default value, as this will disable access
bogdanm 0:9b334a45a8ff 249 * to core BURTC registers.
bogdanm 0:9b334a45a8ff 250 ******************************************************************************/
bogdanm 0:9b334a45a8ff 251 void BURTC_Reset(void)
bogdanm 0:9b334a45a8ff 252 {
bogdanm 0:9b334a45a8ff 253 bool buResetState;
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /* Read reset state, set reset and restore state */
mbed_official 50:a417edff4437 256 buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);
mbed_official 50:a417edff4437 257 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);
mbed_official 50:a417edff4437 258 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 263 * @brief
bogdanm 0:9b334a45a8ff 264 * Get clock frequency of the BURTC.
bogdanm 0:9b334a45a8ff 265 *
bogdanm 0:9b334a45a8ff 266 * @return
bogdanm 0:9b334a45a8ff 267 * The current frequency in Hz.
bogdanm 0:9b334a45a8ff 268 ******************************************************************************/
bogdanm 0:9b334a45a8ff 269 uint32_t BURTC_ClockFreqGet(void)
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 uint32_t clkSel;
bogdanm 0:9b334a45a8ff 272 uint32_t clkDiv;
bogdanm 0:9b334a45a8ff 273 uint32_t frequency;
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK;
bogdanm 0:9b334a45a8ff 276 clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT;
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 switch (clkSel)
bogdanm 0:9b334a45a8ff 279 {
mbed_official 50:a417edff4437 280 /** Ultra low frequency (1 kHz) clock */
mbed_official 50:a417edff4437 281 case BURTC_CTRL_CLKSEL_ULFRCO:
mbed_official 50:a417edff4437 282 if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)
mbed_official 50:a417edff4437 283 {
mbed_official 50:a417edff4437 284 frequency = 2000; /* 2KHz when clock divisor is 1. */
mbed_official 50:a417edff4437 285 }
mbed_official 50:a417edff4437 286 else
mbed_official 50:a417edff4437 287 {
mbed_official 50:a417edff4437 288 frequency = SystemULFRCOClockGet(); /* 1KHz when divisor is different
mbed_official 50:a417edff4437 289 from 1. */
mbed_official 50:a417edff4437 290 }
mbed_official 50:a417edff4437 291 break;
bogdanm 0:9b334a45a8ff 292
mbed_official 50:a417edff4437 293 /** Low frequency RC oscillator */
mbed_official 50:a417edff4437 294 case BURTC_CTRL_CLKSEL_LFRCO:
mbed_official 50:a417edff4437 295 frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */
mbed_official 50:a417edff4437 296 break;
bogdanm 0:9b334a45a8ff 297
mbed_official 50:a417edff4437 298 /** Low frequency crystal osciallator */
mbed_official 50:a417edff4437 299 case BURTC_CTRL_CLKSEL_LFXO:
mbed_official 50:a417edff4437 300 frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */
mbed_official 50:a417edff4437 301 break;
bogdanm 0:9b334a45a8ff 302
mbed_official 50:a417edff4437 303 default:
mbed_official 50:a417edff4437 304 /* No clock selected for BURTC. */
mbed_official 50:a417edff4437 305 frequency = 0;
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 return frequency;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /** @} (end addtogroup BURTC) */
bogdanm 0:9b334a45a8ff 312 /** @} (end addtogroup EM_Library) */
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 #endif /* BURTC_PRESENT */