Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c@83:a036322b8637, 2016-03-07 (annotated)

Committer:
mbed_official
Date:
Mon Mar 07 10:00:14 2016 +0000
Revision:
83:a036322b8637
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b



Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/



[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_rcc.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief RCC HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 ##### RCC specific features #####
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 [..]
bogdanm 0:9b334a45a8ff 18 After reset the device is running from Internal High Speed oscillator
bogdanm 0:9b334a45a8ff 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
bogdanm 0:9b334a45a8ff 20 and I-Cache are disabled, and all peripherals are off except internal
bogdanm 0:9b334a45a8ff 21 SRAM, Flash and JTAG.
bogdanm 0:9b334a45a8ff 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
bogdanm 0:9b334a45a8ff 23 all peripherals mapped on these busses are running at HSI speed.
bogdanm 0:9b334a45a8ff 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
bogdanm 0:9b334a45a8ff 25 (+) All GPIOs are in input floating state, except the JTAG pins which
bogdanm 0:9b334a45a8ff 26 are assigned to be used for debug purpose.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 [..]
bogdanm 0:9b334a45a8ff 29 Once the device started from reset, the user application has to:
bogdanm 0:9b334a45a8ff 30 (+) Configure the clock source to be used to drive the System clock
bogdanm 0:9b334a45a8ff 31 (if the application needs higher frequency/performance)
bogdanm 0:9b334a45a8ff 32 (+) Configure the System clock frequency and Flash settings
bogdanm 0:9b334a45a8ff 33 (+) Configure the AHB and APB busses prescalers
bogdanm 0:9b334a45a8ff 34 (+) Enable the clock for the peripheral(s) to be used
bogdanm 0:9b334a45a8ff 35 (+) Configure the clock source(s) for peripherals which clocks are not
bogdanm 0:9b334a45a8ff 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 ##### RCC Limitations #####
bogdanm 0:9b334a45a8ff 39 ==============================================================================
bogdanm 0:9b334a45a8ff 40 [..]
bogdanm 0:9b334a45a8ff 41 A delay between an RCC peripheral clock enable and the effective peripheral
bogdanm 0:9b334a45a8ff 42 enabling should be taken into account in order to manage the peripheral read/write
bogdanm 0:9b334a45a8ff 43 from/to registers.
bogdanm 0:9b334a45a8ff 44 (+) This delay depends on the peripheral mapping.
bogdanm 0:9b334a45a8ff 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
bogdanm 0:9b334a45a8ff 46 after the clock enable bit is set on the hardware register
bogdanm 0:9b334a45a8ff 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
bogdanm 0:9b334a45a8ff 48 after the clock enable bit is set on the hardware register
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 [..]
bogdanm 0:9b334a45a8ff 51 Implemented Workaround:
bogdanm 0:9b334a45a8ff 52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
bogdanm 0:9b334a45a8ff 53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 @endverbatim
bogdanm 0:9b334a45a8ff 56 ******************************************************************************
bogdanm 0:9b334a45a8ff 57 * @attention
bogdanm 0:9b334a45a8ff 58 *
bogdanm 0:9b334a45a8ff 59 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 60 *
bogdanm 0:9b334a45a8ff 61 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 62 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 63 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 64 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 65 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 66 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 67 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 69 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 70 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 71 *
bogdanm 0:9b334a45a8ff 72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 82 *
bogdanm 0:9b334a45a8ff 83 ******************************************************************************
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 87 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 90 * @{
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /** @defgroup RCC RCC
bogdanm 0:9b334a45a8ff 94 * @brief RCC HAL module driver
bogdanm 0:9b334a45a8ff 95 * @{
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103 /** @defgroup RCC_Private_Macros RCC Private Macros
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
bogdanm 0:9b334a45a8ff 108 #define MCO1_GPIO_PORT GPIOA
bogdanm 0:9b334a45a8ff 109 #define MCO1_PIN GPIO_PIN_8
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
bogdanm 0:9b334a45a8ff 112 #define MCO2_GPIO_PORT GPIOC
bogdanm 0:9b334a45a8ff 113 #define MCO2_PIN GPIO_PIN_9
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /**
bogdanm 0:9b334a45a8ff 116 * @}
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /** @defgroup RCC_Private_Variables RCC Private Variables
bogdanm 0:9b334a45a8ff 120 * @{
bogdanm 0:9b334a45a8ff 121 */
bogdanm 0:9b334a45a8ff 122 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /**
bogdanm 0:9b334a45a8ff 125 * @}
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 129 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @defgroup RCC_Exported_Functions RCC Exported Functions
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 136 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 137 *
bogdanm 0:9b334a45a8ff 138 @verbatim
bogdanm 0:9b334a45a8ff 139 ===============================================================================
bogdanm 0:9b334a45a8ff 140 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 141 ===============================================================================
bogdanm 0:9b334a45a8ff 142 [..]
bogdanm 0:9b334a45a8ff 143 This section provides functions allowing to configure the internal/external oscillators
bogdanm 0:9b334a45a8ff 144 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
bogdanm 0:9b334a45a8ff 145 and APB2).
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 [..] Internal/external clock and PLL configuration
bogdanm 0:9b334a45a8ff 148 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
bogdanm 0:9b334a45a8ff 149 the PLL as System clock source.
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
bogdanm 0:9b334a45a8ff 152 clock source.
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
bogdanm 0:9b334a45a8ff 155 through the PLL as System clock source. Can be used also as RTC clock source.
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
bogdanm 0:9b334a45a8ff 160 (++) The first output is used to generate the high speed system clock (up to 216 MHz)
bogdanm 0:9b334a45a8ff 161 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
bogdanm 0:9b334a45a8ff 162 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
bogdanm 0:9b334a45a8ff 165 and if a HSE clock failure occurs(HSE used directly or through PLL as System
bogdanm 0:9b334a45a8ff 166 clock source), the System clock is automatically switched to HSI and an interrupt
bogdanm 0:9b334a45a8ff 167 is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
bogdanm 0:9b334a45a8ff 168 (Non-Maskable Interrupt) exception vector.
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
bogdanm 0:9b334a45a8ff 171 clock (through a configurable prescaler) on PA8 pin.
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
bogdanm 0:9b334a45a8ff 174 clock (through a configurable prescaler) on PC9 pin.
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 [..] System, AHB and APB busses clocks configuration
bogdanm 0:9b334a45a8ff 177 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
bogdanm 0:9b334a45a8ff 178 HSE and PLL.
bogdanm 0:9b334a45a8ff 179 The AHB clock (HCLK) is derived from System clock through configurable
bogdanm 0:9b334a45a8ff 180 prescaler and used to clock the CPU, memory and peripherals mapped
bogdanm 0:9b334a45a8ff 181 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
bogdanm 0:9b334a45a8ff 182 from AHB clock through configurable prescalers and used to clock
bogdanm 0:9b334a45a8ff 183 the peripherals mapped on these busses. You can use
bogdanm 0:9b334a45a8ff 184 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
bogdanm 0:9b334a45a8ff 187 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
bogdanm 0:9b334a45a8ff 188 from an external clock mapped on the I2S_CKIN pin.
bogdanm 0:9b334a45a8ff 189 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
bogdanm 0:9b334a45a8ff 190 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
bogdanm 0:9b334a45a8ff 191 from an external clock mapped on the I2S_CKIN pin.
bogdanm 0:9b334a45a8ff 192 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
bogdanm 0:9b334a45a8ff 193 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
bogdanm 0:9b334a45a8ff 194 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
bogdanm 0:9b334a45a8ff 195 macros to configure this clock.
bogdanm 0:9b334a45a8ff 196 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
bogdanm 0:9b334a45a8ff 197 to work correctly, while the SDIO require a frequency equal or lower than
bogdanm 0:9b334a45a8ff 198 to 48. This clock is derived of the main PLL through PLLQ divider.
bogdanm 0:9b334a45a8ff 199 (+@) IWDG clock which is always the LSI clock.
bogdanm 0:9b334a45a8ff 200 @endverbatim
bogdanm 0:9b334a45a8ff 201 * @{
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /**
bogdanm 0:9b334a45a8ff 205 * @brief Resets the RCC clock configuration to the default reset state.
bogdanm 0:9b334a45a8ff 206 * @note The default reset state of the clock configuration is given below:
bogdanm 0:9b334a45a8ff 207 * - HSI ON and used as system clock source
bogdanm 0:9b334a45a8ff 208 * - HSE, PLL and PLLI2S OFF
bogdanm 0:9b334a45a8ff 209 * - AHB, APB1 and APB2 prescaler set to 1.
bogdanm 0:9b334a45a8ff 210 * - CSS, MCO1 and MCO2 OFF
bogdanm 0:9b334a45a8ff 211 * - All interrupts disabled
bogdanm 0:9b334a45a8ff 212 * @note This function doesn't modify the configuration of the
bogdanm 0:9b334a45a8ff 213 * - Peripheral clocks
bogdanm 0:9b334a45a8ff 214 * - LSI, LSE and RTC clocks
bogdanm 0:9b334a45a8ff 215 * @retval None
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217 void HAL_RCC_DeInit(void)
bogdanm 0:9b334a45a8ff 218 {
bogdanm 0:9b334a45a8ff 219 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 220 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 223 CLEAR_REG(RCC->CFGR);
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /* Reset HSEON, CSSON, PLLON, PLLI2S */
bogdanm 0:9b334a45a8ff 226 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Reset PLLCFGR register */
bogdanm 0:9b334a45a8ff 229 CLEAR_REG(RCC->PLLCFGR);
bogdanm 0:9b334a45a8ff 230 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Reset PLLI2SCFGR register */
bogdanm 0:9b334a45a8ff 233 CLEAR_REG(RCC->PLLI2SCFGR);
bogdanm 0:9b334a45a8ff 234 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 237 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 240 CLEAR_REG(RCC->CIR);
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm 0:9b334a45a8ff 245 * RCC_OscInitTypeDef.
bogdanm 0:9b334a45a8ff 246 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 247 * contains the configuration information for the RCC Oscillators.
bogdanm 0:9b334a45a8ff 248 * @note The PLL is not disabled when used as system clock.
bogdanm 0:9b334a45a8ff 249 * @retval HAL status
bogdanm 0:9b334a45a8ff 250 */
bogdanm 0:9b334a45a8ff 251 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 252 {
bogdanm 0:9b334a45a8ff 253 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /* Check the parameters */
bogdanm 0:9b334a45a8ff 256 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /*------------------------------- HSE Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 259 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm 0:9b334a45a8ff 260 {
bogdanm 0:9b334a45a8ff 261 /* Check the parameters */
bogdanm 0:9b334a45a8ff 262 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm 0:9b334a45a8ff 263 /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
bogdanm 0:9b334a45a8ff 264 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 265 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
bogdanm 0:9b334a45a8ff 266 {
bogdanm 0:9b334a45a8ff 267 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271 }
bogdanm 0:9b334a45a8ff 272 else
bogdanm 0:9b334a45a8ff 273 {
bogdanm 0:9b334a45a8ff 274 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm 0:9b334a45a8ff 275 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 278 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /* Wait till HSE is disabled */
bogdanm 0:9b334a45a8ff 281 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /* Set the new HSE configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 290 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /* Check the HSE State */
bogdanm 0:9b334a45a8ff 293 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
bogdanm 0:9b334a45a8ff 294 {
bogdanm 0:9b334a45a8ff 295 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 296 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /* Wait till HSE is ready */
bogdanm 0:9b334a45a8ff 299 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 300 {
bogdanm 0:9b334a45a8ff 301 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 302 {
bogdanm 0:9b334a45a8ff 303 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 else
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 310 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /* Wait till HSE is bypassed or disabled */
bogdanm 0:9b334a45a8ff 313 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 314 {
bogdanm 0:9b334a45a8ff 315 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 318 }
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320 }
bogdanm 0:9b334a45a8ff 321 }
bogdanm 0:9b334a45a8ff 322 }
bogdanm 0:9b334a45a8ff 323 /*----------------------------- HSI Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 324 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 /* Check the parameters */
bogdanm 0:9b334a45a8ff 327 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm 0:9b334a45a8ff 328 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm 0:9b334a45a8ff 331 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 332 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
bogdanm 0:9b334a45a8ff 333 {
bogdanm 0:9b334a45a8ff 334 /* When HSI is used as system clock it will not disabled */
bogdanm 0:9b334a45a8ff 335 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 336 {
bogdanm 0:9b334a45a8ff 337 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 338 }
bogdanm 0:9b334a45a8ff 339 /* Otherwise, just the calibration is allowed */
bogdanm 0:9b334a45a8ff 340 else
bogdanm 0:9b334a45a8ff 341 {
bogdanm 0:9b334a45a8ff 342 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 343 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 344 }
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346 else
bogdanm 0:9b334a45a8ff 347 {
bogdanm 0:9b334a45a8ff 348 /* Check the HSI State */
bogdanm 0:9b334a45a8ff 349 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
bogdanm 0:9b334a45a8ff 350 {
bogdanm 0:9b334a45a8ff 351 /* Enable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 352 __HAL_RCC_HSI_ENABLE();
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 355 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 358 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 361 {
bogdanm 0:9b334a45a8ff 362 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 367 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369 else
bogdanm 0:9b334a45a8ff 370 {
bogdanm 0:9b334a45a8ff 371 /* Disable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 372 __HAL_RCC_HSI_DISABLE();
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 375 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 378 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 379 {
bogdanm 0:9b334a45a8ff 380 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 383 }
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387 }
bogdanm 0:9b334a45a8ff 388 /*------------------------------ LSI Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 389 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm 0:9b334a45a8ff 390 {
bogdanm 0:9b334a45a8ff 391 /* Check the parameters */
bogdanm 0:9b334a45a8ff 392 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /* Check the LSI State */
bogdanm 0:9b334a45a8ff 395 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
bogdanm 0:9b334a45a8ff 396 {
bogdanm 0:9b334a45a8ff 397 /* Enable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 398 __HAL_RCC_LSI_ENABLE();
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 401 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 404 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 405 {
bogdanm 0:9b334a45a8ff 406 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410 }
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412 else
bogdanm 0:9b334a45a8ff 413 {
bogdanm 0:9b334a45a8ff 414 /* Disable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 415 __HAL_RCC_LSI_DISABLE();
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 418 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 421 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 422 {
bogdanm 0:9b334a45a8ff 423 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 424 {
bogdanm 0:9b334a45a8ff 425 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427 }
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430 /*------------------------------ LSE Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 431 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 /* Check the parameters */
bogdanm 0:9b334a45a8ff 434 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 437 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 440 PWR->CR1 |= PWR_CR1_DBP;
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 443 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 448 {
bogdanm 0:9b334a45a8ff 449 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 450 }
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm 0:9b334a45a8ff 454 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 457 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 460 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 465 }
bogdanm 0:9b334a45a8ff 466 }
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /* Set the new LSE configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 469 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm 0:9b334a45a8ff 470 /* Check the LSE State */
bogdanm 0:9b334a45a8ff 471 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 474 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 477 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 478 {
bogdanm 0:9b334a45a8ff 479 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 480 {
bogdanm 0:9b334a45a8ff 481 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485 else
bogdanm 0:9b334a45a8ff 486 {
bogdanm 0:9b334a45a8ff 487 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 488 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 491 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 494 {
bogdanm 0:9b334a45a8ff 495 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 496 }
bogdanm 0:9b334a45a8ff 497 }
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500 /*-------------------------------- PLL Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 501 /* Check the parameters */
bogdanm 0:9b334a45a8ff 502 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm 0:9b334a45a8ff 503 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 /* Check if the PLL is used as system clock or not */
bogdanm 0:9b334a45a8ff 506 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm 0:9b334a45a8ff 509 {
bogdanm 0:9b334a45a8ff 510 /* Check the parameters */
bogdanm 0:9b334a45a8ff 511 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm 0:9b334a45a8ff 512 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
bogdanm 0:9b334a45a8ff 513 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
bogdanm 0:9b334a45a8ff 514 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
bogdanm 0:9b334a45a8ff 515 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 518 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 521 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 524 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 525 {
bogdanm 0:9b334a45a8ff 526 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 527 {
bogdanm 0:9b334a45a8ff 528 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 529 }
bogdanm 0:9b334a45a8ff 530 }
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /* Configure the main PLL clock source, multiplication and division factors. */
bogdanm 0:9b334a45a8ff 533 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm 0:9b334a45a8ff 534 RCC_OscInitStruct->PLL.PLLM,
bogdanm 0:9b334a45a8ff 535 RCC_OscInitStruct->PLL.PLLN,
bogdanm 0:9b334a45a8ff 536 RCC_OscInitStruct->PLL.PLLP,
bogdanm 0:9b334a45a8ff 537 RCC_OscInitStruct->PLL.PLLQ);
bogdanm 0:9b334a45a8ff 538 /* Enable the main PLL. */
bogdanm 0:9b334a45a8ff 539 __HAL_RCC_PLL_ENABLE();
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 542 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 545 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 548 {
bogdanm 0:9b334a45a8ff 549 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 550 }
bogdanm 0:9b334a45a8ff 551 }
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553 else
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 556 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 559 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 562 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 563 {
bogdanm 0:9b334a45a8ff 564 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 567 }
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571 else
bogdanm 0:9b334a45a8ff 572 {
bogdanm 0:9b334a45a8ff 573 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576 return HAL_OK;
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /**
bogdanm 0:9b334a45a8ff 580 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
bogdanm 0:9b334a45a8ff 581 * parameters in the RCC_ClkInitStruct.
bogdanm 0:9b334a45a8ff 582 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 583 * contains the configuration information for the RCC peripheral.
bogdanm 0:9b334a45a8ff 584 * @param FLatency: FLASH Latency, this parameter depend on device selected
bogdanm 0:9b334a45a8ff 585 *
bogdanm 0:9b334a45a8ff 586 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 587 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
bogdanm 0:9b334a45a8ff 588 *
bogdanm 0:9b334a45a8ff 589 * @note The HSI is used (enabled by hardware) as system clock source after
bogdanm 0:9b334a45a8ff 590 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
bogdanm 0:9b334a45a8ff 591 * of failure of the HSE used directly or indirectly as system clock
bogdanm 0:9b334a45a8ff 592 * (if the Clock Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 593 *
bogdanm 0:9b334a45a8ff 594 * @note A switch from one clock source to another occurs only if the target
bogdanm 0:9b334a45a8ff 595 * clock source is ready (clock stable after startup delay or PLL locked).
bogdanm 0:9b334a45a8ff 596 * If a clock source which is not yet ready is selected, the switch will
bogdanm 0:9b334a45a8ff 597 * occur when the clock source will be ready.
bogdanm 0:9b334a45a8ff 598 * You can use HAL_RCC_GetClockConfig() function to know which clock is
bogdanm 0:9b334a45a8ff 599 * currently used as system clock source.
bogdanm 0:9b334a45a8ff 600 * @note Depending on the device voltage range, the software has to set correctly
bogdanm 0:9b334a45a8ff 601 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
bogdanm 0:9b334a45a8ff 602 * (for more details refer to section above "Initialization/de-initialization functions")
bogdanm 0:9b334a45a8ff 603 * @retval None
bogdanm 0:9b334a45a8ff 604 */
bogdanm 0:9b334a45a8ff 605 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
bogdanm 0:9b334a45a8ff 606 {
bogdanm 0:9b334a45a8ff 607 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 /* Check the parameters */
bogdanm 0:9b334a45a8ff 610 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
bogdanm 0:9b334a45a8ff 611 assert_param(IS_FLASH_LATENCY(FLatency));
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
bogdanm 0:9b334a45a8ff 614 must be correctly programmed according to the frequency of the CPU clock
bogdanm 0:9b334a45a8ff 615 (HCLK) and the supply voltage of the device. */
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /* Increasing the CPU frequency */
bogdanm 0:9b334a45a8ff 618 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
bogdanm 0:9b334a45a8ff 619 {
bogdanm 0:9b334a45a8ff 620 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 621 __HAL_FLASH_SET_LATENCY(FLatency);
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* Check that the new number of wait states is taken into account to access the Flash
bogdanm 0:9b334a45a8ff 624 memory by reading the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 625 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm 0:9b334a45a8ff 626 {
bogdanm 0:9b334a45a8ff 627 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 628 }
bogdanm 0:9b334a45a8ff 629
bogdanm 0:9b334a45a8ff 630 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 631 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 632 {
bogdanm 0:9b334a45a8ff 633 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 634 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 635 }
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /*------------------------- SYSCLK Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 638 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 643 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 644 {
bogdanm 0:9b334a45a8ff 645 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 646 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 647 {
bogdanm 0:9b334a45a8ff 648 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 649 }
bogdanm 0:9b334a45a8ff 650 }
bogdanm 0:9b334a45a8ff 651 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 652 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 653 {
bogdanm 0:9b334a45a8ff 654 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 655 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 656 {
bogdanm 0:9b334a45a8ff 657 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659 }
bogdanm 0:9b334a45a8ff 660 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 661 else
bogdanm 0:9b334a45a8ff 662 {
bogdanm 0:9b334a45a8ff 663 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 664 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 665 {
bogdanm 0:9b334a45a8ff 666 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 667 }
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 671 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 672 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 675 {
bogdanm 0:9b334a45a8ff 676 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 679 {
bogdanm 0:9b334a45a8ff 680 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682 }
bogdanm 0:9b334a45a8ff 683 }
bogdanm 0:9b334a45a8ff 684 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 685 {
bogdanm 0:9b334a45a8ff 686 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 687 {
bogdanm 0:9b334a45a8ff 688 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 689 {
bogdanm 0:9b334a45a8ff 690 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692 }
bogdanm 0:9b334a45a8ff 693 }
bogdanm 0:9b334a45a8ff 694 else
bogdanm 0:9b334a45a8ff 695 {
bogdanm 0:9b334a45a8ff 696 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 697 {
bogdanm 0:9b334a45a8ff 698 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 699 {
bogdanm 0:9b334a45a8ff 700 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 701 }
bogdanm 0:9b334a45a8ff 702 }
bogdanm 0:9b334a45a8ff 703 }
bogdanm 0:9b334a45a8ff 704 }
bogdanm 0:9b334a45a8ff 705 }
bogdanm 0:9b334a45a8ff 706 /* Decreasing the CPU frequency */
bogdanm 0:9b334a45a8ff 707 else
bogdanm 0:9b334a45a8ff 708 {
bogdanm 0:9b334a45a8ff 709 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 710 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 711 {
bogdanm 0:9b334a45a8ff 712 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 713 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /*------------------------- SYSCLK Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 717 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 718 {
bogdanm 0:9b334a45a8ff 719 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 722 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 723 {
bogdanm 0:9b334a45a8ff 724 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 725 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 726 {
bogdanm 0:9b334a45a8ff 727 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 728 }
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 731 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 732 {
bogdanm 0:9b334a45a8ff 733 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 734 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 735 {
bogdanm 0:9b334a45a8ff 736 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 737 }
bogdanm 0:9b334a45a8ff 738 }
bogdanm 0:9b334a45a8ff 739 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 740 else
bogdanm 0:9b334a45a8ff 741 {
bogdanm 0:9b334a45a8ff 742 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 743 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 744 {
bogdanm 0:9b334a45a8ff 745 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 746 }
bogdanm 0:9b334a45a8ff 747 }
bogdanm 0:9b334a45a8ff 748 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 749 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 750 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 753 {
bogdanm 0:9b334a45a8ff 754 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 755 {
bogdanm 0:9b334a45a8ff 756 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 757 {
bogdanm 0:9b334a45a8ff 758 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761 }
bogdanm 0:9b334a45a8ff 762 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 763 {
bogdanm 0:9b334a45a8ff 764 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 765 {
bogdanm 0:9b334a45a8ff 766 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 767 {
bogdanm 0:9b334a45a8ff 768 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 769 }
bogdanm 0:9b334a45a8ff 770 }
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772 else
bogdanm 0:9b334a45a8ff 773 {
bogdanm 0:9b334a45a8ff 774 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 775 {
bogdanm 0:9b334a45a8ff 776 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 777 {
bogdanm 0:9b334a45a8ff 778 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 779 }
bogdanm 0:9b334a45a8ff 780 }
bogdanm 0:9b334a45a8ff 781 }
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 785 __HAL_FLASH_SET_LATENCY(FLatency);
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 /* Check that the new number of wait states is taken into account to access the Flash
bogdanm 0:9b334a45a8ff 788 memory by reading the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 789 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm 0:9b334a45a8ff 790 {
bogdanm 0:9b334a45a8ff 791 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 792 }
bogdanm 0:9b334a45a8ff 793 }
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /*-------------------------- PCLK1 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 796 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
bogdanm 0:9b334a45a8ff 797 {
bogdanm 0:9b334a45a8ff 798 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
bogdanm 0:9b334a45a8ff 799 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
bogdanm 0:9b334a45a8ff 800 }
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /*-------------------------- PCLK2 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 803 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
bogdanm 0:9b334a45a8ff 804 {
bogdanm 0:9b334a45a8ff 805 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
bogdanm 0:9b334a45a8ff 806 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 /* Configure the source of time base considering new system clocks settings*/
bogdanm 0:9b334a45a8ff 810 HAL_InitTick (TICK_INT_PRIORITY);
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 return HAL_OK;
bogdanm 0:9b334a45a8ff 813 }
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 /**
bogdanm 0:9b334a45a8ff 816 * @}
bogdanm 0:9b334a45a8ff 817 */
bogdanm 0:9b334a45a8ff 818
bogdanm 0:9b334a45a8ff 819 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 820 * @brief RCC clocks control functions
bogdanm 0:9b334a45a8ff 821 *
bogdanm 0:9b334a45a8ff 822 @verbatim
bogdanm 0:9b334a45a8ff 823 ===============================================================================
bogdanm 0:9b334a45a8ff 824 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 825 ===============================================================================
bogdanm 0:9b334a45a8ff 826 [..]
bogdanm 0:9b334a45a8ff 827 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 828 frequencies.
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 @endverbatim
bogdanm 0:9b334a45a8ff 831 * @{
bogdanm 0:9b334a45a8ff 832 */
bogdanm 0:9b334a45a8ff 833
bogdanm 0:9b334a45a8ff 834 /**
bogdanm 0:9b334a45a8ff 835 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
bogdanm 0:9b334a45a8ff 836 * @note PA8/PC9 should be configured in alternate function mode.
bogdanm 0:9b334a45a8ff 837 * @param RCC_MCOx: specifies the output direction for the clock source.
bogdanm 0:9b334a45a8ff 838 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 839 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
bogdanm 0:9b334a45a8ff 840 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
bogdanm 0:9b334a45a8ff 841 * @param RCC_MCOSource: specifies the clock source to output.
bogdanm 0:9b334a45a8ff 842 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 843 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
bogdanm 0:9b334a45a8ff 844 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
bogdanm 0:9b334a45a8ff 845 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
bogdanm 0:9b334a45a8ff 846 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
bogdanm 0:9b334a45a8ff 847 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
bogdanm 0:9b334a45a8ff 848 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
bogdanm 0:9b334a45a8ff 849 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
bogdanm 0:9b334a45a8ff 850 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
bogdanm 0:9b334a45a8ff 851 * @param RCC_MCODiv: specifies the MCOx prescaler.
bogdanm 0:9b334a45a8ff 852 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 853 * @arg RCC_MCODIV_1: no division applied to MCOx clock
bogdanm 0:9b334a45a8ff 854 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
bogdanm 0:9b334a45a8ff 855 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
bogdanm 0:9b334a45a8ff 856 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
bogdanm 0:9b334a45a8ff 857 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
bogdanm 0:9b334a45a8ff 858 * @retval None
bogdanm 0:9b334a45a8ff 859 */
bogdanm 0:9b334a45a8ff 860 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
bogdanm 0:9b334a45a8ff 861 {
bogdanm 0:9b334a45a8ff 862 GPIO_InitTypeDef GPIO_InitStruct;
bogdanm 0:9b334a45a8ff 863 /* Check the parameters */
bogdanm 0:9b334a45a8ff 864 assert_param(IS_RCC_MCO(RCC_MCOx));
bogdanm 0:9b334a45a8ff 865 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
bogdanm 0:9b334a45a8ff 866 /* RCC_MCO1 */
bogdanm 0:9b334a45a8ff 867 if(RCC_MCOx == RCC_MCO1)
bogdanm 0:9b334a45a8ff 868 {
bogdanm 0:9b334a45a8ff 869 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /* MCO1 Clock Enable */
bogdanm 0:9b334a45a8ff 872 MCO1_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 /* Configure the MCO1 pin in alternate function mode */
bogdanm 0:9b334a45a8ff 875 GPIO_InitStruct.Pin = MCO1_PIN;
bogdanm 0:9b334a45a8ff 876 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
bogdanm 0:9b334a45a8ff 877 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
bogdanm 0:9b334a45a8ff 878 GPIO_InitStruct.Pull = GPIO_NOPULL;
bogdanm 0:9b334a45a8ff 879 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
bogdanm 0:9b334a45a8ff 880 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
bogdanm 0:9b334a45a8ff 881
bogdanm 0:9b334a45a8ff 882 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
bogdanm 0:9b334a45a8ff 883 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
bogdanm 0:9b334a45a8ff 884 }
bogdanm 0:9b334a45a8ff 885 else
bogdanm 0:9b334a45a8ff 886 {
bogdanm 0:9b334a45a8ff 887 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
bogdanm 0:9b334a45a8ff 888
bogdanm 0:9b334a45a8ff 889 /* MCO2 Clock Enable */
bogdanm 0:9b334a45a8ff 890 MCO2_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 /* Configure the MCO2 pin in alternate function mode */
bogdanm 0:9b334a45a8ff 893 GPIO_InitStruct.Pin = MCO2_PIN;
bogdanm 0:9b334a45a8ff 894 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
bogdanm 0:9b334a45a8ff 895 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
bogdanm 0:9b334a45a8ff 896 GPIO_InitStruct.Pull = GPIO_NOPULL;
bogdanm 0:9b334a45a8ff 897 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
bogdanm 0:9b334a45a8ff 898 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
bogdanm 0:9b334a45a8ff 899
bogdanm 0:9b334a45a8ff 900 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
bogdanm 0:9b334a45a8ff 901 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
bogdanm 0:9b334a45a8ff 902 }
bogdanm 0:9b334a45a8ff 903 }
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /**
bogdanm 0:9b334a45a8ff 906 * @brief Enables the Clock Security System.
bogdanm 0:9b334a45a8ff 907 * @note If a failure is detected on the HSE oscillator clock, this oscillator
bogdanm 0:9b334a45a8ff 908 * is automatically disabled and an interrupt is generated to inform the
bogdanm 0:9b334a45a8ff 909 * software about the failure (Clock Security System Interrupt, CSSI),
bogdanm 0:9b334a45a8ff 910 * allowing the MCU to perform rescue operations. The CSSI is linked to
bogdanm 0:9b334a45a8ff 911 * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
bogdanm 0:9b334a45a8ff 912 * @retval None
bogdanm 0:9b334a45a8ff 913 */
bogdanm 0:9b334a45a8ff 914 void HAL_RCC_EnableCSS(void)
bogdanm 0:9b334a45a8ff 915 {
bogdanm 0:9b334a45a8ff 916 SET_BIT(RCC->CR, RCC_CR_CSSON);
bogdanm 0:9b334a45a8ff 917 }
bogdanm 0:9b334a45a8ff 918
bogdanm 0:9b334a45a8ff 919 /**
bogdanm 0:9b334a45a8ff 920 * @brief Disables the Clock Security System.
bogdanm 0:9b334a45a8ff 921 * @retval None
bogdanm 0:9b334a45a8ff 922 */
bogdanm 0:9b334a45a8ff 923 void HAL_RCC_DisableCSS(void)
bogdanm 0:9b334a45a8ff 924 {
bogdanm 0:9b334a45a8ff 925 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
bogdanm 0:9b334a45a8ff 926 }
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /**
bogdanm 0:9b334a45a8ff 929 * @brief Returns the SYSCLK frequency
bogdanm 0:9b334a45a8ff 930 *
bogdanm 0:9b334a45a8ff 931 * @note The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 932 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 933 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 934 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 935 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 936 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 937 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 938 * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 939 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 940 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 941 * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 942 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 943 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 944 * have wrong result.
bogdanm 0:9b334a45a8ff 945 *
bogdanm 0:9b334a45a8ff 946 * @note The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 947 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 948 *
bogdanm 0:9b334a45a8ff 949 * @note This function can be used by the user application to compute the
bogdanm 0:9b334a45a8ff 950 * baudrate for the communication peripherals or configure other parameters.
bogdanm 0:9b334a45a8ff 951 *
bogdanm 0:9b334a45a8ff 952 * @note Each time SYSCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 953 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 954 *
bogdanm 0:9b334a45a8ff 955 *
bogdanm 0:9b334a45a8ff 956 * @retval SYSCLK frequency
bogdanm 0:9b334a45a8ff 957 */
bogdanm 0:9b334a45a8ff 958 uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm 0:9b334a45a8ff 959 {
bogdanm 0:9b334a45a8ff 960 uint32_t pllm = 0, pllvco = 0, pllp = 0;
bogdanm 0:9b334a45a8ff 961 uint32_t sysclockfreq = 0;
bogdanm 0:9b334a45a8ff 962
bogdanm 0:9b334a45a8ff 963 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 964 switch (RCC->CFGR & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 965 {
bogdanm 0:9b334a45a8ff 966 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 967 {
bogdanm 0:9b334a45a8ff 968 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 969 break;
bogdanm 0:9b334a45a8ff 970 }
bogdanm 0:9b334a45a8ff 971 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 972 {
bogdanm 0:9b334a45a8ff 973 sysclockfreq = HSE_VALUE;
bogdanm 0:9b334a45a8ff 974 break;
bogdanm 0:9b334a45a8ff 975 }
bogdanm 0:9b334a45a8ff 976 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 977 {
bogdanm 0:9b334a45a8ff 978 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
bogdanm 0:9b334a45a8ff 979 SYSCLK = PLL_VCO / PLLP */
bogdanm 0:9b334a45a8ff 980 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm 0:9b334a45a8ff 981 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
bogdanm 0:9b334a45a8ff 982 {
bogdanm 0:9b334a45a8ff 983 /* HSE used as PLL clock source */
bogdanm 0:9b334a45a8ff 984 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm 0:9b334a45a8ff 985 }
bogdanm 0:9b334a45a8ff 986 else
bogdanm 0:9b334a45a8ff 987 {
bogdanm 0:9b334a45a8ff 988 /* HSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 989 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm 0:9b334a45a8ff 990 }
bogdanm 0:9b334a45a8ff 991 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 sysclockfreq = pllvco/pllp;
bogdanm 0:9b334a45a8ff 994 break;
bogdanm 0:9b334a45a8ff 995 }
bogdanm 0:9b334a45a8ff 996 default:
bogdanm 0:9b334a45a8ff 997 {
bogdanm 0:9b334a45a8ff 998 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 999 break;
bogdanm 0:9b334a45a8ff 1000 }
bogdanm 0:9b334a45a8ff 1001 }
bogdanm 0:9b334a45a8ff 1002 return sysclockfreq;
bogdanm 0:9b334a45a8ff 1003 }
bogdanm 0:9b334a45a8ff 1004
bogdanm 0:9b334a45a8ff 1005 /**
bogdanm 0:9b334a45a8ff 1006 * @brief Returns the HCLK frequency
bogdanm 0:9b334a45a8ff 1007 * @note Each time HCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1008 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1009 *
bogdanm 0:9b334a45a8ff 1010 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 1011 * and updated within this function
bogdanm 0:9b334a45a8ff 1012 * @retval HCLK frequency
bogdanm 0:9b334a45a8ff 1013 */
bogdanm 0:9b334a45a8ff 1014 uint32_t HAL_RCC_GetHCLKFreq(void)
bogdanm 0:9b334a45a8ff 1015 {
bogdanm 0:9b334a45a8ff 1016 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
bogdanm 0:9b334a45a8ff 1017 return SystemCoreClock;
bogdanm 0:9b334a45a8ff 1018 }
bogdanm 0:9b334a45a8ff 1019
bogdanm 0:9b334a45a8ff 1020 /**
bogdanm 0:9b334a45a8ff 1021 * @brief Returns the PCLK1 frequency
bogdanm 0:9b334a45a8ff 1022 * @note Each time PCLK1 changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1023 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1024 * @retval PCLK1 frequency
bogdanm 0:9b334a45a8ff 1025 */
bogdanm 0:9b334a45a8ff 1026 uint32_t HAL_RCC_GetPCLK1Freq(void)
bogdanm 0:9b334a45a8ff 1027 {
bogdanm 0:9b334a45a8ff 1028 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
bogdanm 0:9b334a45a8ff 1029 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
bogdanm 0:9b334a45a8ff 1030 }
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 /**
bogdanm 0:9b334a45a8ff 1033 * @brief Returns the PCLK2 frequency
bogdanm 0:9b334a45a8ff 1034 * @note Each time PCLK2 changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1035 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1036 * @retval PCLK2 frequency
bogdanm 0:9b334a45a8ff 1037 */
bogdanm 0:9b334a45a8ff 1038 uint32_t HAL_RCC_GetPCLK2Freq(void)
bogdanm 0:9b334a45a8ff 1039 {
bogdanm 0:9b334a45a8ff 1040 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
bogdanm 0:9b334a45a8ff 1041 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
bogdanm 0:9b334a45a8ff 1042 }
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /**
bogdanm 0:9b334a45a8ff 1045 * @brief Configures the RCC_OscInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1046 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1047 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1048 * will be configured.
bogdanm 0:9b334a45a8ff 1049 * @retval None
bogdanm 0:9b334a45a8ff 1050 */
bogdanm 0:9b334a45a8ff 1051 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 1052 {
bogdanm 0:9b334a45a8ff 1053 /* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm 0:9b334a45a8ff 1054 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 /* Get the HSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1057 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm 0:9b334a45a8ff 1058 {
bogdanm 0:9b334a45a8ff 1059 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm 0:9b334a45a8ff 1060 }
bogdanm 0:9b334a45a8ff 1061 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 1064 }
bogdanm 0:9b334a45a8ff 1065 else
bogdanm 0:9b334a45a8ff 1066 {
bogdanm 0:9b334a45a8ff 1067 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 1068 }
bogdanm 0:9b334a45a8ff 1069
bogdanm 0:9b334a45a8ff 1070 /* Get the HSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1071 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm 0:9b334a45a8ff 1072 {
bogdanm 0:9b334a45a8ff 1073 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 1074 }
bogdanm 0:9b334a45a8ff 1075 else
bogdanm 0:9b334a45a8ff 1076 {
bogdanm 0:9b334a45a8ff 1077 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 1078 }
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 /* Get the LSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1083 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm 0:9b334a45a8ff 1084 {
bogdanm 0:9b334a45a8ff 1085 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm 0:9b334a45a8ff 1086 }
bogdanm 0:9b334a45a8ff 1087 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm 0:9b334a45a8ff 1088 {
bogdanm 0:9b334a45a8ff 1089 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm 0:9b334a45a8ff 1090 }
bogdanm 0:9b334a45a8ff 1091 else
bogdanm 0:9b334a45a8ff 1092 {
bogdanm 0:9b334a45a8ff 1093 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm 0:9b334a45a8ff 1094 }
bogdanm 0:9b334a45a8ff 1095
bogdanm 0:9b334a45a8ff 1096 /* Get the LSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1097 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm 0:9b334a45a8ff 1098 {
bogdanm 0:9b334a45a8ff 1099 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm 0:9b334a45a8ff 1100 }
bogdanm 0:9b334a45a8ff 1101 else
bogdanm 0:9b334a45a8ff 1102 {
bogdanm 0:9b334a45a8ff 1103 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm 0:9b334a45a8ff 1104 }
bogdanm 0:9b334a45a8ff 1105
bogdanm 0:9b334a45a8ff 1106 /* Get the PLL configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1107 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 1108 {
bogdanm 0:9b334a45a8ff 1109 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 1110 }
bogdanm 0:9b334a45a8ff 1111 else
bogdanm 0:9b334a45a8ff 1112 {
bogdanm 0:9b334a45a8ff 1113 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm 0:9b334a45a8ff 1114 }
bogdanm 0:9b334a45a8ff 1115 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
bogdanm 0:9b334a45a8ff 1116 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
bogdanm 0:9b334a45a8ff 1117 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
bogdanm 0:9b334a45a8ff 1118 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
bogdanm 0:9b334a45a8ff 1119 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
bogdanm 0:9b334a45a8ff 1120 }
bogdanm 0:9b334a45a8ff 1121
bogdanm 0:9b334a45a8ff 1122 /**
bogdanm 0:9b334a45a8ff 1123 * @brief Configures the RCC_ClkInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1124 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1125 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1126 * will be configured.
bogdanm 0:9b334a45a8ff 1127 * @param pFLatency: Pointer on the Flash Latency.
bogdanm 0:9b334a45a8ff 1128 * @retval None
bogdanm 0:9b334a45a8ff 1129 */
bogdanm 0:9b334a45a8ff 1130 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
bogdanm 0:9b334a45a8ff 1131 {
bogdanm 0:9b334a45a8ff 1132 /* Set all possible values for the Clock type parameter --------------------*/
bogdanm 0:9b334a45a8ff 1133 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /* Get the SYSCLK configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 1136 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 /* Get the HCLK configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1139 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
bogdanm 0:9b334a45a8ff 1140
bogdanm 0:9b334a45a8ff 1141 /* Get the APB1 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1142 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 /* Get the APB2 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1145 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
bogdanm 0:9b334a45a8ff 1146
bogdanm 0:9b334a45a8ff 1147 /* Get the Flash Wait State (Latency) configuration ------------------------*/
bogdanm 0:9b334a45a8ff 1148 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
bogdanm 0:9b334a45a8ff 1149 }
bogdanm 0:9b334a45a8ff 1150
bogdanm 0:9b334a45a8ff 1151 /**
bogdanm 0:9b334a45a8ff 1152 * @brief This function handles the RCC CSS interrupt request.
bogdanm 0:9b334a45a8ff 1153 * @note This API should be called under the NMI_Handler().
bogdanm 0:9b334a45a8ff 1154 * @retval None
bogdanm 0:9b334a45a8ff 1155 */
bogdanm 0:9b334a45a8ff 1156 void HAL_RCC_NMI_IRQHandler(void)
bogdanm 0:9b334a45a8ff 1157 {
bogdanm 0:9b334a45a8ff 1158 /* Check RCC CSSF flag */
bogdanm 0:9b334a45a8ff 1159 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
bogdanm 0:9b334a45a8ff 1160 {
bogdanm 0:9b334a45a8ff 1161 /* RCC Clock Security System interrupt user callback */
bogdanm 0:9b334a45a8ff 1162 HAL_RCC_CSSCallback();
bogdanm 0:9b334a45a8ff 1163
bogdanm 0:9b334a45a8ff 1164 /* Clear RCC CSS pending bit */
bogdanm 0:9b334a45a8ff 1165 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
bogdanm 0:9b334a45a8ff 1166 }
bogdanm 0:9b334a45a8ff 1167 }
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /**
bogdanm 0:9b334a45a8ff 1170 * @brief RCC Clock Security System interrupt callback
bogdanm 0:9b334a45a8ff 1171 * @retval None
bogdanm 0:9b334a45a8ff 1172 */
bogdanm 0:9b334a45a8ff 1173 __weak void HAL_RCC_CSSCallback(void)
bogdanm 0:9b334a45a8ff 1174 {
bogdanm 0:9b334a45a8ff 1175 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1176 the HAL_RCC_CSSCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1177 */
bogdanm 0:9b334a45a8ff 1178 }
bogdanm 0:9b334a45a8ff 1179
bogdanm 0:9b334a45a8ff 1180 /**
bogdanm 0:9b334a45a8ff 1181 * @}
bogdanm 0:9b334a45a8ff 1182 */
bogdanm 0:9b334a45a8ff 1183
bogdanm 0:9b334a45a8ff 1184 /**
bogdanm 0:9b334a45a8ff 1185 * @}
bogdanm 0:9b334a45a8ff 1186 */
bogdanm 0:9b334a45a8ff 1187
bogdanm 0:9b334a45a8ff 1188 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1189 /**
bogdanm 0:9b334a45a8ff 1190 * @}
bogdanm 0:9b334a45a8ff 1191 */
bogdanm 0:9b334a45a8ff 1192
bogdanm 0:9b334a45a8ff 1193 /**
bogdanm 0:9b334a45a8ff 1194 * @}
bogdanm 0:9b334a45a8ff 1195 */
bogdanm 0:9b334a45a8ff 1196
bogdanm 0:9b334a45a8ff 1197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/