Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_irq_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2015 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <stddef.h>
bogdanm 0:9b334a45a8ff 17 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 #include "gpio_irq_api.h"
bogdanm 0:9b334a45a8ff 20 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 #define CHANNEL_NUM 160
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 0:9b334a45a8ff 25 static gpio_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 #define IRQ_DISABLED (0)
bogdanm 0:9b334a45a8ff 28 #define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
bogdanm 0:9b334a45a8ff 29 #define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
bogdanm 0:9b334a45a8ff 30 #define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 static void handle_interrupt_in(PORT_Type *port, int ch_base) {
bogdanm 0:9b334a45a8ff 33 uint32_t isfr;
bogdanm 0:9b334a45a8ff 34 uint32_t pin;
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 while ((isfr = port->ISFR) != 0) {
bogdanm 0:9b334a45a8ff 37 pin = 31 - __CLZ(isfr);
bogdanm 0:9b334a45a8ff 38 uint32_t id = channel_ids[ch_base + pin];
bogdanm 0:9b334a45a8ff 39 if (id == 0) {
bogdanm 0:9b334a45a8ff 40 continue;
bogdanm 0:9b334a45a8ff 41 }
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 GPIO_Type *gpio = PTA;
bogdanm 0:9b334a45a8ff 44 gpio_irq_event event = IRQ_NONE;
bogdanm 0:9b334a45a8ff 45 uint32_t port_num = (port - PORTA) >> 12;
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 switch (port->PCR[pin] & PORT_PCR_IRQC_MASK) {
bogdanm 0:9b334a45a8ff 48 case IRQ_RAISING_EDGE:
bogdanm 0:9b334a45a8ff 49 event = IRQ_RISE;
bogdanm 0:9b334a45a8ff 50 break;
bogdanm 0:9b334a45a8ff 51 case IRQ_FALLING_EDGE:
bogdanm 0:9b334a45a8ff 52 event = IRQ_FALL;
bogdanm 0:9b334a45a8ff 53 break;
bogdanm 0:9b334a45a8ff 54 case IRQ_EITHER_EDGE:
bogdanm 0:9b334a45a8ff 55 gpio += (port_num * 0x40);
bogdanm 0:9b334a45a8ff 56 event = (gpio->PDIR & (1 << pin)) ? (IRQ_RISE) : (IRQ_FALL);
bogdanm 0:9b334a45a8ff 57 break;
bogdanm 0:9b334a45a8ff 58 }
bogdanm 0:9b334a45a8ff 59 if (event != IRQ_NONE) {
bogdanm 0:9b334a45a8ff 60 irq_handler(id, event);
bogdanm 0:9b334a45a8ff 61 }
bogdanm 0:9b334a45a8ff 62 port->ISFR = 1 << pin;
bogdanm 0:9b334a45a8ff 63 }
bogdanm 0:9b334a45a8ff 64 }
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 void gpio_irqA(void) {
bogdanm 0:9b334a45a8ff 67 handle_interrupt_in(PORTA, 0);
bogdanm 0:9b334a45a8ff 68 }
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 void gpio_irqB(void)
bogdanm 0:9b334a45a8ff 71 {
bogdanm 0:9b334a45a8ff 72 handle_interrupt_in(PORTB, 32);
bogdanm 0:9b334a45a8ff 73 }
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 void gpio_irqC(void)
bogdanm 0:9b334a45a8ff 76 {
bogdanm 0:9b334a45a8ff 77 handle_interrupt_in(PORTC, 64);
bogdanm 0:9b334a45a8ff 78 }
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 void gpio_irqD(void)
bogdanm 0:9b334a45a8ff 81 {
bogdanm 0:9b334a45a8ff 82 handle_interrupt_in(PORTD, 96);
bogdanm 0:9b334a45a8ff 83 }
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 void gpio_irqE(void)
bogdanm 0:9b334a45a8ff 86 {
bogdanm 0:9b334a45a8ff 87 handle_interrupt_in(PORTE, 128);
bogdanm 0:9b334a45a8ff 88 }
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 0:9b334a45a8ff 92 if (pin == NC)
bogdanm 0:9b334a45a8ff 93 return -1;
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 irq_handler = handler;
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 obj->port = pin >> PORT_SHIFT;
bogdanm 0:9b334a45a8ff 98 obj->pin = (pin & 0x7F) >> 2;
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 uint32_t ch_base, vector;
bogdanm 0:9b334a45a8ff 101 IRQn_Type irq_n;
bogdanm 0:9b334a45a8ff 102 switch (obj->port) {
bogdanm 0:9b334a45a8ff 103 case PortA:
bogdanm 0:9b334a45a8ff 104 ch_base = 0;
bogdanm 0:9b334a45a8ff 105 irq_n = PORTA_IRQn;
bogdanm 0:9b334a45a8ff 106 vector = (uint32_t)gpio_irqA;
bogdanm 0:9b334a45a8ff 107 break;
bogdanm 0:9b334a45a8ff 108 case PortB:
bogdanm 0:9b334a45a8ff 109 ch_base = 32;
bogdanm 0:9b334a45a8ff 110 irq_n = PORTB_IRQn;
bogdanm 0:9b334a45a8ff 111 vector = (uint32_t)gpio_irqB;
bogdanm 0:9b334a45a8ff 112 break;
bogdanm 0:9b334a45a8ff 113 case PortC:
bogdanm 0:9b334a45a8ff 114 ch_base = 64;
bogdanm 0:9b334a45a8ff 115 irq_n = PORTC_IRQn;
bogdanm 0:9b334a45a8ff 116 vector = (uint32_t)gpio_irqC;
bogdanm 0:9b334a45a8ff 117 break;
bogdanm 0:9b334a45a8ff 118 case PortD:
bogdanm 0:9b334a45a8ff 119 ch_base = 96;
bogdanm 0:9b334a45a8ff 120 irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD;
bogdanm 0:9b334a45a8ff 121 break;
bogdanm 0:9b334a45a8ff 122 case PortE:
bogdanm 0:9b334a45a8ff 123 ch_base = 128;
bogdanm 0:9b334a45a8ff 124 irq_n = PORTE_IRQn;
bogdanm 0:9b334a45a8ff 125 vector = (uint32_t)gpio_irqE;
bogdanm 0:9b334a45a8ff 126 break;
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 default:
bogdanm 0:9b334a45a8ff 129 error("gpio_irq only supported on port A-E.");
bogdanm 0:9b334a45a8ff 130 break;
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132 NVIC_SetVector(irq_n, vector);
bogdanm 0:9b334a45a8ff 133 NVIC_EnableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 obj->ch = ch_base + obj->pin;
bogdanm 0:9b334a45a8ff 136 channel_ids[obj->ch] = id;
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 return 0;
bogdanm 0:9b334a45a8ff 139 }
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 142 channel_ids[obj->ch] = 0;
bogdanm 0:9b334a45a8ff 143 }
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 0:9b334a45a8ff 146 PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 uint32_t irq_settings = IRQ_DISABLED;
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
bogdanm 0:9b334a45a8ff 151 case IRQ_DISABLED:
bogdanm 0:9b334a45a8ff 152 if (enable)
bogdanm 0:9b334a45a8ff 153 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
bogdanm 0:9b334a45a8ff 154 break;
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 case IRQ_RAISING_EDGE:
bogdanm 0:9b334a45a8ff 157 if (enable) {
bogdanm 0:9b334a45a8ff 158 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
bogdanm 0:9b334a45a8ff 159 } else {
bogdanm 0:9b334a45a8ff 160 if (event == IRQ_FALL)
bogdanm 0:9b334a45a8ff 161 irq_settings = IRQ_RAISING_EDGE;
bogdanm 0:9b334a45a8ff 162 }
bogdanm 0:9b334a45a8ff 163 break;
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 case IRQ_FALLING_EDGE:
bogdanm 0:9b334a45a8ff 166 if (enable) {
bogdanm 0:9b334a45a8ff 167 irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
bogdanm 0:9b334a45a8ff 168 } else {
bogdanm 0:9b334a45a8ff 169 if (event == IRQ_RISE)
bogdanm 0:9b334a45a8ff 170 irq_settings = IRQ_FALLING_EDGE;
bogdanm 0:9b334a45a8ff 171 }
bogdanm 0:9b334a45a8ff 172 break;
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 case IRQ_EITHER_EDGE:
bogdanm 0:9b334a45a8ff 175 if (enable) {
bogdanm 0:9b334a45a8ff 176 irq_settings = IRQ_EITHER_EDGE;
bogdanm 0:9b334a45a8ff 177 } else {
bogdanm 0:9b334a45a8ff 178 irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180 break;
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 // Interrupt configuration and clear interrupt
bogdanm 0:9b334a45a8ff 184 port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
bogdanm 0:9b334a45a8ff 185 }
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 void gpio_irq_enable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 188 switch (obj->port) {
bogdanm 0:9b334a45a8ff 189 case PortA:
bogdanm 0:9b334a45a8ff 190 NVIC_EnableIRQ(PORTA_IRQn);
bogdanm 0:9b334a45a8ff 191 break;
bogdanm 0:9b334a45a8ff 192 case PortB:
bogdanm 0:9b334a45a8ff 193 NVIC_EnableIRQ(PORTB_IRQn);
bogdanm 0:9b334a45a8ff 194 break;
bogdanm 0:9b334a45a8ff 195 case PortC:
bogdanm 0:9b334a45a8ff 196 NVIC_EnableIRQ(PORTC_IRQn);
bogdanm 0:9b334a45a8ff 197 break;
bogdanm 0:9b334a45a8ff 198 case PortD:
bogdanm 0:9b334a45a8ff 199 NVIC_EnableIRQ(PORTD_IRQn);
bogdanm 0:9b334a45a8ff 200 break;
bogdanm 0:9b334a45a8ff 201 case PortE:
bogdanm 0:9b334a45a8ff 202 NVIC_EnableIRQ(PORTE_IRQn);
bogdanm 0:9b334a45a8ff 203 break;
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205 }
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 void gpio_irq_disable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 208 switch (obj->port) {
bogdanm 0:9b334a45a8ff 209 case PortA:
bogdanm 0:9b334a45a8ff 210 NVIC_DisableIRQ(PORTA_IRQn);
bogdanm 0:9b334a45a8ff 211 break;
bogdanm 0:9b334a45a8ff 212 case PortB:
bogdanm 0:9b334a45a8ff 213 NVIC_DisableIRQ(PORTB_IRQn);
bogdanm 0:9b334a45a8ff 214 break;
bogdanm 0:9b334a45a8ff 215 case PortC:
bogdanm 0:9b334a45a8ff 216 NVIC_DisableIRQ(PORTC_IRQn);
bogdanm 0:9b334a45a8ff 217 break;
bogdanm 0:9b334a45a8ff 218 case PortD:
bogdanm 0:9b334a45a8ff 219 NVIC_DisableIRQ(PORTD_IRQn);
bogdanm 0:9b334a45a8ff 220 break;
bogdanm 0:9b334a45a8ff 221 case PortE:
bogdanm 0:9b334a45a8ff 222 NVIC_DisableIRQ(PORTE_IRQn);
bogdanm 0:9b334a45a8ff 223 break;
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225 }