Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /******************************************************************************
bogdanm 0:9b334a45a8ff 2 * @file: system_LPC8xx.c
bogdanm 0:9b334a45a8ff 3 * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
bogdanm 0:9b334a45a8ff 4 * for the NXP LPC8xx Device Series
bogdanm 0:9b334a45a8ff 5 * @version: V1.0
bogdanm 0:9b334a45a8ff 6 * @date: 16. Aug. 2012
bogdanm 0:9b334a45a8ff 7 *----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2012 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
bogdanm 0:9b334a45a8ff 12 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 13 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 ******************************************************************************/
bogdanm 0:9b334a45a8ff 22 #include <stdint.h>
bogdanm 0:9b334a45a8ff 23 #include "LPC82x.h"
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 /*
bogdanm 0:9b334a45a8ff 26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 27 */
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 /*--------------------- Clock Configuration ----------------------------------*/
bogdanm 0:9b334a45a8ff 30 //
bogdanm 0:9b334a45a8ff 31 // <e> Clock Configuration
bogdanm 0:9b334a45a8ff 32 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 33 // <h> System Oscillator Control Register (SYSOSCCTRL)
bogdanm 0:9b334a45a8ff 34 // <o.0> BYPASS: System Oscillator Bypass Enable
bogdanm 0:9b334a45a8ff 35 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 0:9b334a45a8ff 36 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 0:9b334a45a8ff 37 // <o.1> FREQRANGE: System Oscillator Frequency Range
bogdanm 0:9b334a45a8ff 38 // <i> Determines frequency range for Low-power oscillator.
bogdanm 0:9b334a45a8ff 39 // <0=> 1 - 20 MHz
bogdanm 0:9b334a45a8ff 40 // <1=> 15 - 25 MHz
bogdanm 0:9b334a45a8ff 41 // </h>
bogdanm 0:9b334a45a8ff 42 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 43 //
bogdanm 0:9b334a45a8ff 44 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
bogdanm 0:9b334a45a8ff 45 // <o.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 0:9b334a45a8ff 46 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
bogdanm 0:9b334a45a8ff 47 // <0-31>
bogdanm 0:9b334a45a8ff 48 // <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
bogdanm 0:9b334a45a8ff 49 // <0=> Undefined
bogdanm 0:9b334a45a8ff 50 // <1=> 0.6 MHz
bogdanm 0:9b334a45a8ff 51 // <2=> 1.05 MHz
bogdanm 0:9b334a45a8ff 52 // <3=> 1.4 MHz
bogdanm 0:9b334a45a8ff 53 // <4=> 1.75 MHz
bogdanm 0:9b334a45a8ff 54 // <5=> 2.1 MHz
bogdanm 0:9b334a45a8ff 55 // <6=> 2.4 MHz
bogdanm 0:9b334a45a8ff 56 // <7=> 2.7 MHz
bogdanm 0:9b334a45a8ff 57 // <8=> 3.0 MHz
bogdanm 0:9b334a45a8ff 58 // <9=> 3.25 MHz
bogdanm 0:9b334a45a8ff 59 // <10=> 3.5 MHz
bogdanm 0:9b334a45a8ff 60 // <11=> 3.75 MHz
bogdanm 0:9b334a45a8ff 61 // <12=> 4.0 MHz
bogdanm 0:9b334a45a8ff 62 // <13=> 4.2 MHz
bogdanm 0:9b334a45a8ff 63 // <14=> 4.4 MHz
bogdanm 0:9b334a45a8ff 64 // <15=> 4.6 MHz
bogdanm 0:9b334a45a8ff 65 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 66 // </h>
bogdanm 0:9b334a45a8ff 67 // <h> System PLL Control Register (SYSPLLCTRL)
bogdanm 0:9b334a45a8ff 68 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 69 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 70 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 71 // <o.0..4> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 72 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 73 // <0-31>
bogdanm 0:9b334a45a8ff 74 // <o.5..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 75 // <0=> P = 1
bogdanm 0:9b334a45a8ff 76 // <1=> P = 2
bogdanm 0:9b334a45a8ff 77 // <2=> P = 4
bogdanm 0:9b334a45a8ff 78 // <3=> P = 8
bogdanm 0:9b334a45a8ff 79 // </h>
bogdanm 0:9b334a45a8ff 80 #define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
bogdanm 0:9b334a45a8ff 81 //
bogdanm 0:9b334a45a8ff 82 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
bogdanm 0:9b334a45a8ff 83 // <o.0..1> SEL: System PLL Clock Source
bogdanm 0:9b334a45a8ff 84 // <0=> IRC
bogdanm 0:9b334a45a8ff 85 // <1=> Crystal Oscillator
bogdanm 0:9b334a45a8ff 86 // <2=> Reserved
bogdanm 0:9b334a45a8ff 87 // <3=> CLKIN. External clock input.
bogdanm 0:9b334a45a8ff 88 // </h>
bogdanm 0:9b334a45a8ff 89 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 0:9b334a45a8ff 90 //
bogdanm 0:9b334a45a8ff 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
bogdanm 0:9b334a45a8ff 92 // <o.0..1> SEL: Clock Source for Main Clock
bogdanm 0:9b334a45a8ff 93 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 94 // <1=> PLL input
bogdanm 0:9b334a45a8ff 95 // <2=> Watchdog Oscillator
bogdanm 0:9b334a45a8ff 96 // <3=> PLL output
bogdanm 0:9b334a45a8ff 97 // </h>
bogdanm 0:9b334a45a8ff 98 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
bogdanm 0:9b334a45a8ff 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
bogdanm 0:9b334a45a8ff 100 // <o.0..7> DIV: System AHB Clock Divider
bogdanm 0:9b334a45a8ff 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 0:9b334a45a8ff 102 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 103 // <0-255>
bogdanm 0:9b334a45a8ff 104 // </h>
bogdanm 0:9b334a45a8ff 105 #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
bogdanm 0:9b334a45a8ff 106 // </e>
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 //#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /*
bogdanm 0:9b334a45a8ff 111 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 112 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 113 #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
bogdanm 0:9b334a45a8ff 114 #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
bogdanm 0:9b334a45a8ff 115 #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
bogdanm 0:9b334a45a8ff 116 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 117 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 0:9b334a45a8ff 118 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 119 // #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 120 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 121 #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
bogdanm 0:9b334a45a8ff 122 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 0:9b334a45a8ff 123 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
bogdanm 0:9b334a45a8ff 124 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 0:9b334a45a8ff 125 #endif
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /*
bogdanm 0:9b334a45a8ff 129 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 133 Check the register settings
bogdanm 0:9b334a45a8ff 134 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 135 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 136 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Clock Configuration -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 139 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 140 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 141 #endif
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 144 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 145 #endif
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
bogdanm 0:9b334a45a8ff 148 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 149 #endif
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 152 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 153 #endif
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 156 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 157 #endif
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 160 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 161 #endif
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 165 DEFINES
bogdanm 0:9b334a45a8ff 166 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 169 Define clocks
bogdanm 0:9b334a45a8ff 170 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 171 #define __XTAL (12000000UL) /* Oscillator frequency */
bogdanm 0:9b334a45a8ff 172 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
bogdanm 0:9b334a45a8ff 173 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
bogdanm 0:9b334a45a8ff 174 #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 0:9b334a45a8ff 178 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 181 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 182 #define __WDT_OSC_CLK ( 0) /* undefined */
bogdanm 0:9b334a45a8ff 183 #elif (__FREQSEL == 1)
bogdanm 0:9b334a45a8ff 184 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 185 #elif (__FREQSEL == 2)
bogdanm 0:9b334a45a8ff 186 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 187 #elif (__FREQSEL == 3)
bogdanm 0:9b334a45a8ff 188 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 189 #elif (__FREQSEL == 4)
bogdanm 0:9b334a45a8ff 190 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 191 #elif (__FREQSEL == 5)
bogdanm 0:9b334a45a8ff 192 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 193 #elif (__FREQSEL == 6)
bogdanm 0:9b334a45a8ff 194 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 195 #elif (__FREQSEL == 7)
bogdanm 0:9b334a45a8ff 196 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 197 #elif (__FREQSEL == 8)
bogdanm 0:9b334a45a8ff 198 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 199 #elif (__FREQSEL == 9)
bogdanm 0:9b334a45a8ff 200 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 201 #elif (__FREQSEL == 10)
bogdanm 0:9b334a45a8ff 202 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 203 #elif (__FREQSEL == 11)
bogdanm 0:9b334a45a8ff 204 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 205 #elif (__FREQSEL == 12)
bogdanm 0:9b334a45a8ff 206 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 207 #elif (__FREQSEL == 13)
bogdanm 0:9b334a45a8ff 208 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 209 #elif (__FREQSEL == 14)
bogdanm 0:9b334a45a8ff 210 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 211 #else
bogdanm 0:9b334a45a8ff 212 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 213 #endif
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* sys_pllclkin calculation */
bogdanm 0:9b334a45a8ff 216 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 217 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 218 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 219 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 0:9b334a45a8ff 220 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 221 #define __SYS_PLLCLKIN (__CLKIN_CLK)
bogdanm 0:9b334a45a8ff 222 #else
bogdanm 0:9b334a45a8ff 223 #define __SYS_PLLCLKIN (0)
bogdanm 0:9b334a45a8ff 224 #endif
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* main clock calculation */
bogdanm 0:9b334a45a8ff 229 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 230 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 231 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 232 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 0:9b334a45a8ff 233 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 234 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 235 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
bogdanm 0:9b334a45a8ff 236 #else
bogdanm 0:9b334a45a8ff 237 #define __MAIN_CLOCK (__WDT_OSC_CLK)
bogdanm 0:9b334a45a8ff 238 #endif
bogdanm 0:9b334a45a8ff 239 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 240 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 0:9b334a45a8ff 241 #else
bogdanm 0:9b334a45a8ff 242 #define __MAIN_CLOCK (0)
bogdanm 0:9b334a45a8ff 243 #endif
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 #else
bogdanm 0:9b334a45a8ff 248 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 249 #endif // CLOCK_SETUP
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 253 Clock Variable definitions
bogdanm 0:9b334a45a8ff 254 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 255 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
bogdanm 0:9b334a45a8ff 256 uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 259 Clock functions
bogdanm 0:9b334a45a8ff 260 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 261 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 uint32_t wdt_osc = 0;
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 266 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 0:9b334a45a8ff 267 case 0: wdt_osc = 0; break;
bogdanm 0:9b334a45a8ff 268 case 1: wdt_osc = 500000; break;
bogdanm 0:9b334a45a8ff 269 case 2: wdt_osc = 800000; break;
bogdanm 0:9b334a45a8ff 270 case 3: wdt_osc = 1100000; break;
bogdanm 0:9b334a45a8ff 271 case 4: wdt_osc = 1400000; break;
bogdanm 0:9b334a45a8ff 272 case 5: wdt_osc = 1600000; break;
bogdanm 0:9b334a45a8ff 273 case 6: wdt_osc = 1800000; break;
bogdanm 0:9b334a45a8ff 274 case 7: wdt_osc = 2000000; break;
bogdanm 0:9b334a45a8ff 275 case 8: wdt_osc = 2200000; break;
bogdanm 0:9b334a45a8ff 276 case 9: wdt_osc = 2400000; break;
bogdanm 0:9b334a45a8ff 277 case 10: wdt_osc = 2600000; break;
bogdanm 0:9b334a45a8ff 278 case 11: wdt_osc = 2700000; break;
bogdanm 0:9b334a45a8ff 279 case 12: wdt_osc = 2900000; break;
bogdanm 0:9b334a45a8ff 280 case 13: wdt_osc = 3100000; break;
bogdanm 0:9b334a45a8ff 281 case 14: wdt_osc = 3200000; break;
bogdanm 0:9b334a45a8ff 282 case 15: wdt_osc = 3400000; break;
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 287 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 288 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 289 break;
bogdanm 0:9b334a45a8ff 290 case 1: /* Input Clock to System PLL */
bogdanm 0:9b334a45a8ff 291 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 292 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 293 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 294 break;
bogdanm 0:9b334a45a8ff 295 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 296 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 297 break;
bogdanm 0:9b334a45a8ff 298 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 299 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 300 break;
bogdanm 0:9b334a45a8ff 301 case 3: /* CLKIN pin */
bogdanm 0:9b334a45a8ff 302 SystemCoreClock = __CLKIN_CLK;
bogdanm 0:9b334a45a8ff 303 break;
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305 break;
bogdanm 0:9b334a45a8ff 306 case 2: /* WDT Oscillator */
bogdanm 0:9b334a45a8ff 307 SystemCoreClock = wdt_osc;
bogdanm 0:9b334a45a8ff 308 break;
bogdanm 0:9b334a45a8ff 309 case 3: /* System PLL Clock Out */
bogdanm 0:9b334a45a8ff 310 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 311 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 312 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 313 break;
bogdanm 0:9b334a45a8ff 314 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 315 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 316 break;
bogdanm 0:9b334a45a8ff 317 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 318 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 319 break;
bogdanm 0:9b334a45a8ff 320 case 3: /* CLKIN pin */
bogdanm 0:9b334a45a8ff 321 SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 322 break;
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324 break;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /**
bogdanm 0:9b334a45a8ff 332 * Initialize the system
bogdanm 0:9b334a45a8ff 333 *
bogdanm 0:9b334a45a8ff 334 * @param none
bogdanm 0:9b334a45a8ff 335 * @return none
bogdanm 0:9b334a45a8ff 336 *
bogdanm 0:9b334a45a8ff 337 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 338 * Initialize the System.
bogdanm 0:9b334a45a8ff 339 */
bogdanm 0:9b334a45a8ff 340 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 341 volatile uint32_t i;
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* System clock to the IOCON & the SWM need to be enabled or
bogdanm 0:9b334a45a8ff 344 most of the I/O related peripherals won't work. */
bogdanm 0:9b334a45a8ff 345 LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 350 LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
bogdanm 0:9b334a45a8ff 351 LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
bogdanm 0:9b334a45a8ff 352 LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
bogdanm 0:9b334a45a8ff 353 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
bogdanm 0:9b334a45a8ff 354 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 355 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 356 #endif
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 359 LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
bogdanm 0:9b334a45a8ff 360 LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
bogdanm 0:9b334a45a8ff 361 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 362 #endif
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
bogdanm 0:9b334a45a8ff 365 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 366 LPC_SYSCON->SYSPLLCLKUEN = 0;
bogdanm 0:9b334a45a8ff 367 LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
bogdanm 0:9b334a45a8ff 368 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 0:9b334a45a8ff 371 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 372 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
bogdanm 0:9b334a45a8ff 373 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 374 #endif
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 0:9b334a45a8ff 377 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 378 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
bogdanm 0:9b334a45a8ff 379 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 380 #endif
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
bogdanm 0:9b334a45a8ff 383 LPC_SYSCON->MAINCLKUEN = 0;
bogdanm 0:9b334a45a8ff 384 LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
bogdanm 0:9b334a45a8ff 385 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 0:9b334a45a8ff 388 #endif
bogdanm 0:9b334a45a8ff 389 }