Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.S@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* File: startup_ARMCM3.s
bogdanm 0:9b334a45a8ff 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
bogdanm 0:9b334a45a8ff 3 * GNU Tools for ARM Embedded Processors
bogdanm 0:9b334a45a8ff 4 * Version: V1.1
bogdanm 0:9b334a45a8ff 5 * Date: 17 June 2011
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
bogdanm 0:9b334a45a8ff 9 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 10 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 17 */
bogdanm 0:9b334a45a8ff 18 .syntax unified
bogdanm 0:9b334a45a8ff 19 .arch armv7-m
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 /* Memory Model
bogdanm 0:9b334a45a8ff 22 The HEAP starts at the end of the DATA section and grows upward.
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 The STACK starts at the end of the RAM and grows downward.
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 The HEAP and stack STACK are only checked at compile time:
bogdanm 0:9b334a45a8ff 27 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 This is just a check for the bare minimum for the Heap+Stack area before
bogdanm 0:9b334a45a8ff 30 aborting compilation, it is not the run time limit:
bogdanm 0:9b334a45a8ff 31 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33 .section .stack
bogdanm 0:9b334a45a8ff 34 .align 3
bogdanm 0:9b334a45a8ff 35 #ifdef __STACK_SIZE
bogdanm 0:9b334a45a8ff 36 .equ Stack_Size, __STACK_SIZE
bogdanm 0:9b334a45a8ff 37 #else
bogdanm 0:9b334a45a8ff 38 .equ Stack_Size, 0xc00
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40 .globl __StackTop
bogdanm 0:9b334a45a8ff 41 .globl __StackLimit
bogdanm 0:9b334a45a8ff 42 __StackLimit:
bogdanm 0:9b334a45a8ff 43 .space Stack_Size
bogdanm 0:9b334a45a8ff 44 .size __StackLimit, . - __StackLimit
bogdanm 0:9b334a45a8ff 45 __StackTop:
bogdanm 0:9b334a45a8ff 46 .size __StackTop, . - __StackTop
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 .section .heap
bogdanm 0:9b334a45a8ff 49 .align 3
bogdanm 0:9b334a45a8ff 50 #ifdef __HEAP_SIZE
bogdanm 0:9b334a45a8ff 51 .equ Heap_Size, __HEAP_SIZE
bogdanm 0:9b334a45a8ff 52 #else
bogdanm 0:9b334a45a8ff 53 .equ Heap_Size, 0x800
bogdanm 0:9b334a45a8ff 54 #endif
bogdanm 0:9b334a45a8ff 55 .globl __HeapBase
bogdanm 0:9b334a45a8ff 56 .globl __HeapLimit
bogdanm 0:9b334a45a8ff 57 __HeapBase:
bogdanm 0:9b334a45a8ff 58 .space Heap_Size
bogdanm 0:9b334a45a8ff 59 .size __HeapBase, . - __HeapBase
bogdanm 0:9b334a45a8ff 60 __HeapLimit:
bogdanm 0:9b334a45a8ff 61 .size __HeapLimit, . - __HeapLimit
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 .section .isr_vector
bogdanm 0:9b334a45a8ff 64 .align 2
bogdanm 0:9b334a45a8ff 65 .globl __isr_vector
bogdanm 0:9b334a45a8ff 66 __isr_vector:
bogdanm 0:9b334a45a8ff 67 .long __StackTop /* Top of Stack */
bogdanm 0:9b334a45a8ff 68 .long Reset_Handler /* Reset Handler */
bogdanm 0:9b334a45a8ff 69 .long NMI_Handler /* NMI Handler */
bogdanm 0:9b334a45a8ff 70 .long HardFault_Handler /* Hard Fault Handler */
bogdanm 0:9b334a45a8ff 71 .long MemManage_Handler /* MPU Fault Handler */
bogdanm 0:9b334a45a8ff 72 .long BusFault_Handler /* Bus Fault Handler */
bogdanm 0:9b334a45a8ff 73 .long UsageFault_Handler /* Usage Fault Handler */
bogdanm 0:9b334a45a8ff 74 .long 0 /* Reserved */
bogdanm 0:9b334a45a8ff 75 .long 0 /* Reserved */
bogdanm 0:9b334a45a8ff 76 .long 0 /* Reserved */
bogdanm 0:9b334a45a8ff 77 .long 0 /* Reserved */
bogdanm 0:9b334a45a8ff 78 .long SVC_Handler /* SVCall Handler */
bogdanm 0:9b334a45a8ff 79 .long DebugMon_Handler /* Debug Monitor Handler */
bogdanm 0:9b334a45a8ff 80 .long 0 /* Reserved */
bogdanm 0:9b334a45a8ff 81 .long PendSV_Handler /* PendSV Handler */
bogdanm 0:9b334a45a8ff 82 .long SysTick_Handler /* SysTick Handler */
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /* External interrupts */
bogdanm 0:9b334a45a8ff 85 .long WDT_IRQHandler /* 16: Watchdog Timer */
bogdanm 0:9b334a45a8ff 86 .long TIMER0_IRQHandler /* 17: Timer0 */
bogdanm 0:9b334a45a8ff 87 .long TIMER1_IRQHandler /* 18: Timer1 */
bogdanm 0:9b334a45a8ff 88 .long TIMER2_IRQHandler /* 19: Timer2 */
bogdanm 0:9b334a45a8ff 89 .long TIMER3_IRQHandler /* 20: Timer3 */
bogdanm 0:9b334a45a8ff 90 .long UART0_IRQHandler /* 21: UART0 */
bogdanm 0:9b334a45a8ff 91 .long UART1_IRQHandler /* 22: UART1 */
bogdanm 0:9b334a45a8ff 92 .long UART2_IRQHandler /* 23: UART2 */
bogdanm 0:9b334a45a8ff 93 .long UART3_IRQHandler /* 24: UART3 */
bogdanm 0:9b334a45a8ff 94 .long PWM1_IRQHandler /* 25: PWM1 */
bogdanm 0:9b334a45a8ff 95 .long I2C0_IRQHandler /* 26: I2C0 */
bogdanm 0:9b334a45a8ff 96 .long I2C1_IRQHandler /* 27: I2C1 */
bogdanm 0:9b334a45a8ff 97 .long I2C2_IRQHandler /* 28: I2C2 */
bogdanm 0:9b334a45a8ff 98 .long SPI_IRQHandler /* 29: SPI */
bogdanm 0:9b334a45a8ff 99 .long SSP0_IRQHandler /* 30: SSP0 */
bogdanm 0:9b334a45a8ff 100 .long SSP1_IRQHandler /* 31: SSP1 */
bogdanm 0:9b334a45a8ff 101 .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
bogdanm 0:9b334a45a8ff 102 .long RTC_IRQHandler /* 33: Real Time Clock */
bogdanm 0:9b334a45a8ff 103 .long EINT0_IRQHandler /* 34: External Interrupt 0 */
bogdanm 0:9b334a45a8ff 104 .long EINT1_IRQHandler /* 35: External Interrupt 1 */
bogdanm 0:9b334a45a8ff 105 .long EINT2_IRQHandler /* 36: External Interrupt 2 */
bogdanm 0:9b334a45a8ff 106 .long EINT3_IRQHandler /* 37: External Interrupt 3 */
bogdanm 0:9b334a45a8ff 107 .long ADC_IRQHandler /* 38: A/D Converter */
bogdanm 0:9b334a45a8ff 108 .long BOD_IRQHandler /* 39: Brown-Out Detect */
bogdanm 0:9b334a45a8ff 109 .long USB_IRQHandler /* 40: USB */
bogdanm 0:9b334a45a8ff 110 .long CAN_IRQHandler /* 41: CAN */
bogdanm 0:9b334a45a8ff 111 .long DMA_IRQHandler /* 42: General Purpose DMA */
bogdanm 0:9b334a45a8ff 112 .long I2S_IRQHandler /* 43: I2S */
bogdanm 0:9b334a45a8ff 113 .long ENET_IRQHandler /* 44: Ethernet */
bogdanm 0:9b334a45a8ff 114 .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */
bogdanm 0:9b334a45a8ff 115 .long MCPWM_IRQHandler /* 46: Motor Control PWM */
bogdanm 0:9b334a45a8ff 116 .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
bogdanm 0:9b334a45a8ff 117 .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
bogdanm 0:9b334a45a8ff 118 .long USBActivity_IRQHandler /* 49: USB Activity */
bogdanm 0:9b334a45a8ff 119 .long CANActivity_IRQHandler /* 50: CAN Activity */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 .size __isr_vector, . - __isr_vector
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 .text
bogdanm 0:9b334a45a8ff 124 .thumb
bogdanm 0:9b334a45a8ff 125 .thumb_func
bogdanm 0:9b334a45a8ff 126 .align 2
bogdanm 0:9b334a45a8ff 127 .globl Reset_Handler
bogdanm 0:9b334a45a8ff 128 .type Reset_Handler, %function
bogdanm 0:9b334a45a8ff 129 Reset_Handler:
bogdanm 0:9b334a45a8ff 130 /* Loop to copy data from read only memory to RAM. The ranges
bogdanm 0:9b334a45a8ff 131 * of copy from/to are specified by following symbols evaluated in
bogdanm 0:9b334a45a8ff 132 * linker script.
bogdanm 0:9b334a45a8ff 133 * _etext: End of code section, i.e., begin of data sections to copy from.
bogdanm 0:9b334a45a8ff 134 * __data_start__/__data_end__: RAM address range that data should be
bogdanm 0:9b334a45a8ff 135 * copied to. Both must be aligned to 4 bytes boundary. */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 ldr r1, =__etext
bogdanm 0:9b334a45a8ff 138 ldr r2, =__data_start__
bogdanm 0:9b334a45a8ff 139 ldr r3, =__data_end__
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 .Lflash_to_ram_loop:
bogdanm 0:9b334a45a8ff 142 cmp r2, r3
bogdanm 0:9b334a45a8ff 143 ittt lt
bogdanm 0:9b334a45a8ff 144 ldrlt r0, [r1], #4
bogdanm 0:9b334a45a8ff 145 strlt r0, [r2], #4
bogdanm 0:9b334a45a8ff 146 blt .Lflash_to_ram_loop
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 ldr r0, =SystemInit
bogdanm 0:9b334a45a8ff 149 blx r0
bogdanm 0:9b334a45a8ff 150 ldr r0, =_start
bogdanm 0:9b334a45a8ff 151 bx r0
bogdanm 0:9b334a45a8ff 152 .pool
bogdanm 0:9b334a45a8ff 153 .size Reset_Handler, . - Reset_Handler
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 .text
bogdanm 0:9b334a45a8ff 156 /* Macro to define default handlers. Default handler
bogdanm 0:9b334a45a8ff 157 * will be weak symbol and just dead loops. They can be
bogdanm 0:9b334a45a8ff 158 * overwritten by other handlers */
bogdanm 0:9b334a45a8ff 159 .macro def_default_handler handler_name
bogdanm 0:9b334a45a8ff 160 .align 1
bogdanm 0:9b334a45a8ff 161 .thumb_func
bogdanm 0:9b334a45a8ff 162 .weak \handler_name
bogdanm 0:9b334a45a8ff 163 .type \handler_name, %function
bogdanm 0:9b334a45a8ff 164 \handler_name :
bogdanm 0:9b334a45a8ff 165 b .
bogdanm 0:9b334a45a8ff 166 .size \handler_name, . - \handler_name
bogdanm 0:9b334a45a8ff 167 .endm
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 def_default_handler NMI_Handler
bogdanm 0:9b334a45a8ff 170 def_default_handler HardFault_Handler
bogdanm 0:9b334a45a8ff 171 def_default_handler MemManage_Handler
bogdanm 0:9b334a45a8ff 172 def_default_handler BusFault_Handler
bogdanm 0:9b334a45a8ff 173 def_default_handler UsageFault_Handler
bogdanm 0:9b334a45a8ff 174 def_default_handler SVC_Handler
bogdanm 0:9b334a45a8ff 175 def_default_handler DebugMon_Handler
bogdanm 0:9b334a45a8ff 176 def_default_handler PendSV_Handler
bogdanm 0:9b334a45a8ff 177 def_default_handler SysTick_Handler
bogdanm 0:9b334a45a8ff 178 def_default_handler Default_Handler
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 .macro def_irq_default_handler handler_name
bogdanm 0:9b334a45a8ff 181 .weak \handler_name
bogdanm 0:9b334a45a8ff 182 .set \handler_name, Default_Handler
bogdanm 0:9b334a45a8ff 183 .endm
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 def_irq_default_handler WDT_IRQHandler
bogdanm 0:9b334a45a8ff 186 def_irq_default_handler TIMER0_IRQHandler
bogdanm 0:9b334a45a8ff 187 def_irq_default_handler TIMER1_IRQHandler
bogdanm 0:9b334a45a8ff 188 def_irq_default_handler TIMER2_IRQHandler
bogdanm 0:9b334a45a8ff 189 def_irq_default_handler TIMER3_IRQHandler
bogdanm 0:9b334a45a8ff 190 def_irq_default_handler UART0_IRQHandler
bogdanm 0:9b334a45a8ff 191 def_irq_default_handler UART1_IRQHandler
bogdanm 0:9b334a45a8ff 192 def_irq_default_handler UART2_IRQHandler
bogdanm 0:9b334a45a8ff 193 def_irq_default_handler UART3_IRQHandler
bogdanm 0:9b334a45a8ff 194 def_irq_default_handler PWM1_IRQHandler
bogdanm 0:9b334a45a8ff 195 def_irq_default_handler I2C0_IRQHandler
bogdanm 0:9b334a45a8ff 196 def_irq_default_handler I2C1_IRQHandler
bogdanm 0:9b334a45a8ff 197 def_irq_default_handler I2C2_IRQHandler
bogdanm 0:9b334a45a8ff 198 def_irq_default_handler SPI_IRQHandler
bogdanm 0:9b334a45a8ff 199 def_irq_default_handler SSP0_IRQHandler
bogdanm 0:9b334a45a8ff 200 def_irq_default_handler SSP1_IRQHandler
bogdanm 0:9b334a45a8ff 201 def_irq_default_handler PLL0_IRQHandler
bogdanm 0:9b334a45a8ff 202 def_irq_default_handler RTC_IRQHandler
bogdanm 0:9b334a45a8ff 203 def_irq_default_handler EINT0_IRQHandler
bogdanm 0:9b334a45a8ff 204 def_irq_default_handler EINT1_IRQHandler
bogdanm 0:9b334a45a8ff 205 def_irq_default_handler EINT2_IRQHandler
bogdanm 0:9b334a45a8ff 206 def_irq_default_handler EINT3_IRQHandler
bogdanm 0:9b334a45a8ff 207 def_irq_default_handler ADC_IRQHandler
bogdanm 0:9b334a45a8ff 208 def_irq_default_handler BOD_IRQHandler
bogdanm 0:9b334a45a8ff 209 def_irq_default_handler USB_IRQHandler
bogdanm 0:9b334a45a8ff 210 def_irq_default_handler CAN_IRQHandler
bogdanm 0:9b334a45a8ff 211 def_irq_default_handler DMA_IRQHandler
bogdanm 0:9b334a45a8ff 212 def_irq_default_handler I2S_IRQHandler
bogdanm 0:9b334a45a8ff 213 def_irq_default_handler ENET_IRQHandler
bogdanm 0:9b334a45a8ff 214 def_irq_default_handler RIT_IRQHandler
bogdanm 0:9b334a45a8ff 215 def_irq_default_handler MCPWM_IRQHandler
bogdanm 0:9b334a45a8ff 216 def_irq_default_handler QEI_IRQHandler
bogdanm 0:9b334a45a8ff 217 def_irq_default_handler PLL1_IRQHandler
bogdanm 0:9b334a45a8ff 218 def_irq_default_handler USBActivity_IRQHandler
bogdanm 0:9b334a45a8ff 219 def_irq_default_handler CANActivity_IRQHandler
bogdanm 0:9b334a45a8ff 220 def_irq_default_handler DEF_IRQHandler
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 .end
bogdanm 0:9b334a45a8ff 223