Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processor: MK64FN1M0VMD12
bogdanm 0:9b334a45a8ff 4 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 5 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 6 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 7 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 0:9b334a45a8ff 8 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 9 **
bogdanm 0:9b334a45a8ff 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
bogdanm 0:9b334a45a8ff 11 ** Version: rev. 2.5, 2014-02-10
bogdanm 0:9b334a45a8ff 12 ** Build: b140611
bogdanm 0:9b334a45a8ff 13 **
bogdanm 0:9b334a45a8ff 14 ** Abstract:
bogdanm 0:9b334a45a8ff 15 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 16 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 17 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 18 **
bogdanm 0:9b334a45a8ff 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 20 ** All rights reserved.
bogdanm 0:9b334a45a8ff 21 **
bogdanm 0:9b334a45a8ff 22 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 23 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 24 **
bogdanm 0:9b334a45a8ff 25 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 26 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 27 **
bogdanm 0:9b334a45a8ff 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 29 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 30 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 31 **
bogdanm 0:9b334a45a8ff 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 33 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 34 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 35 **
bogdanm 0:9b334a45a8ff 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 46 **
bogdanm 0:9b334a45a8ff 47 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 48 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 49 **
bogdanm 0:9b334a45a8ff 50 ** Revisions:
bogdanm 0:9b334a45a8ff 51 ** - rev. 1.0 (2013-08-12)
bogdanm 0:9b334a45a8ff 52 ** Initial version.
bogdanm 0:9b334a45a8ff 53 ** - rev. 2.0 (2013-10-29)
bogdanm 0:9b334a45a8ff 54 ** Register accessor macros added to the memory map.
bogdanm 0:9b334a45a8ff 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
bogdanm 0:9b334a45a8ff 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
bogdanm 0:9b334a45a8ff 57 ** System initialization updated.
bogdanm 0:9b334a45a8ff 58 ** MCG - registers updated.
bogdanm 0:9b334a45a8ff 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
bogdanm 0:9b334a45a8ff 60 ** - rev. 2.1 (2013-10-30)
bogdanm 0:9b334a45a8ff 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
bogdanm 0:9b334a45a8ff 62 ** - rev. 2.2 (2013-12-09)
bogdanm 0:9b334a45a8ff 63 ** DMA - EARS register removed.
bogdanm 0:9b334a45a8ff 64 ** AIPS0, AIPS1 - MPRA register updated.
bogdanm 0:9b334a45a8ff 65 ** - rev. 2.3 (2014-01-24)
bogdanm 0:9b334a45a8ff 66 ** Update according to reference manual rev. 2
bogdanm 0:9b334a45a8ff 67 ** ENET, MCG, MCM, SIM, USB - registers updated
bogdanm 0:9b334a45a8ff 68 ** - rev. 2.4 (2014-02-10)
bogdanm 0:9b334a45a8ff 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
bogdanm 0:9b334a45a8ff 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
bogdanm 0:9b334a45a8ff 71 ** - rev. 2.5 (2014-02-10)
bogdanm 0:9b334a45a8ff 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
bogdanm 0:9b334a45a8ff 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
bogdanm 0:9b334a45a8ff 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
bogdanm 0:9b334a45a8ff 75 **
bogdanm 0:9b334a45a8ff 76 ** ###################################################################
bogdanm 0:9b334a45a8ff 77 */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /*!
bogdanm 0:9b334a45a8ff 80 * @file MK64F12
bogdanm 0:9b334a45a8ff 81 * @version 2.5
bogdanm 0:9b334a45a8ff 82 * @date 2014-02-10
bogdanm 0:9b334a45a8ff 83 * @brief Device specific configuration file for MK64F12 (header file)
bogdanm 0:9b334a45a8ff 84 *
bogdanm 0:9b334a45a8ff 85 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 86 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 87 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #ifndef SYSTEM_MK64F12_H_
bogdanm 0:9b334a45a8ff 91 #define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 94 extern "C" {
bogdanm 0:9b334a45a8ff 95 #endif
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 #include <stdint.h>
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 #define DISABLE_WDOG 1
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 #ifndef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 103 #define CLOCK_SETUP 4
bogdanm 0:9b334a45a8ff 104 #endif
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* MCG mode constants */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 #define MCG_MODE_FEI 0U
bogdanm 0:9b334a45a8ff 109 #define MCG_MODE_FBI 1U
bogdanm 0:9b334a45a8ff 110 #define MCG_MODE_BLPI 2U
bogdanm 0:9b334a45a8ff 111 #define MCG_MODE_FEE 3U
bogdanm 0:9b334a45a8ff 112 #define MCG_MODE_FBE 4U
bogdanm 0:9b334a45a8ff 113 #define MCG_MODE_BLPE 5U
bogdanm 0:9b334a45a8ff 114 #define MCG_MODE_PBE 6U
bogdanm 0:9b334a45a8ff 115 #define MCG_MODE_PEE 7U
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Predefined clock setups
bogdanm 0:9b334a45a8ff 118 0 ... Default part configuration
bogdanm 0:9b334a45a8ff 119 Multipurpose Clock Generator (MCG) in FEI mode.
bogdanm 0:9b334a45a8ff 120 Reference clock source for MCG module: Slow internal reference clock
bogdanm 0:9b334a45a8ff 121 Core clock = 20.97152MHz
bogdanm 0:9b334a45a8ff 122 Bus clock = 20.97152MHz
bogdanm 0:9b334a45a8ff 123 1 ... Maximum achievable clock frequency configuration
bogdanm 0:9b334a45a8ff 124 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 125 Reference clock source for MCG module: System oscillator 0 reference clock
bogdanm 0:9b334a45a8ff 126 Core clock = 120MHz
bogdanm 0:9b334a45a8ff 127 Bus clock = 60MHz
bogdanm 0:9b334a45a8ff 128 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
bogdanm 0:9b334a45a8ff 129 Multipurpose Clock Generator (MCG) in BLPI mode.
bogdanm 0:9b334a45a8ff 130 Reference clock source for MCG module: Fast internal reference clock
bogdanm 0:9b334a45a8ff 131 Core clock = 4MHz
bogdanm 0:9b334a45a8ff 132 Bus clock = 4MHz
bogdanm 0:9b334a45a8ff 133 3 ... Chip externally clocked, ready for Very Low Power Run mode.
bogdanm 0:9b334a45a8ff 134 Multipurpose Clock Generator (MCG) in BLPE mode.
bogdanm 0:9b334a45a8ff 135 Reference clock source for MCG module: RTC oscillator reference clock
bogdanm 0:9b334a45a8ff 136 Core clock = 0.032768MHz
bogdanm 0:9b334a45a8ff 137 Bus clock = 0.032768MHz
bogdanm 0:9b334a45a8ff 138 4 ... USB clock setup
bogdanm 0:9b334a45a8ff 139 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 140 Reference clock source for MCG module: System oscillator 0 reference clock
bogdanm 0:9b334a45a8ff 141 Core clock = 120MHz
bogdanm 0:9b334a45a8ff 142 Bus clock = 60MHz
bogdanm 0:9b334a45a8ff 143 */
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /* Define clock source values */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 148 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 149 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 150 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 151 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* RTC oscillator setting */
bogdanm 0:9b334a45a8ff 154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
bogdanm 0:9b334a45a8ff 155 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 /* Low power mode enable */
bogdanm 0:9b334a45a8ff 158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
bogdanm 0:9b334a45a8ff 159 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* Internal reference clock trim */
bogdanm 0:9b334a45a8ff 162 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 163 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 164 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 165 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 168 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
bogdanm 0:9b334a45a8ff 169 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
bogdanm 0:9b334a45a8ff 170 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 171 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 172 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 173 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 174 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 175 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 176 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 177 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 179 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 181 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 182 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 183 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 185 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
bogdanm 0:9b334a45a8ff 186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 187 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
bogdanm 0:9b334a45a8ff 189 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 191 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 193 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 194 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 195 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 196 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 197 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 198 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 199 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 200 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 201 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 202 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 203 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 204 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
bogdanm 0:9b334a45a8ff 206 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
bogdanm 0:9b334a45a8ff 208 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 209 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 210 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 212 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 214 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 216 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 218 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 220 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 221 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 222 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 223 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
bogdanm 0:9b334a45a8ff 224 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 225 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 226 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
bogdanm 0:9b334a45a8ff 227 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 228 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 229 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 230 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 231 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 233 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 235 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 236 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 237 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 239 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 241 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 243 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 245 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 247 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 248 #elif (CLOCK_SETUP == 3)
bogdanm 0:9b334a45a8ff 249 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
bogdanm 0:9b334a45a8ff 250 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 251 /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 252 #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 253 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
bogdanm 0:9b334a45a8ff 254 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 255 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 256 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 257 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
bogdanm 0:9b334a45a8ff 258 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
bogdanm 0:9b334a45a8ff 259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 260 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 262 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 263 /* MCG_C7: OSCSEL=1 */
bogdanm 0:9b334a45a8ff 264 #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 266 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
bogdanm 0:9b334a45a8ff 267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 268 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
bogdanm 0:9b334a45a8ff 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 274 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 275 #elif (CLOCK_SETUP == 4)
bogdanm 0:9b334a45a8ff 276 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 277 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 278 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 279 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 280 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 281 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 282 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 283 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 284 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 285 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
bogdanm 0:9b334a45a8ff 287 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
bogdanm 0:9b334a45a8ff 289 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 290 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 291 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 293 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 295 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 297 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
bogdanm 0:9b334a45a8ff 299 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
bogdanm 0:9b334a45a8ff 300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 301 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 303 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 304 #endif
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 /**
bogdanm 0:9b334a45a8ff 307 * @brief System clock frequency (core clock)
bogdanm 0:9b334a45a8ff 308 *
bogdanm 0:9b334a45a8ff 309 * The system clock frequency supplied to the SysTick timer and the processor
bogdanm 0:9b334a45a8ff 310 * core clock. This variable can be used by the user application to setup the
bogdanm 0:9b334a45a8ff 311 * SysTick timer or configure other parameters. It may also be used by debugger to
bogdanm 0:9b334a45a8ff 312 * query the frequency of the debug timer or configure the trace clock speed
bogdanm 0:9b334a45a8ff 313 * SystemCoreClock is initialized with a correct predefined value.
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315 extern uint32_t SystemCoreClock;
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /**
bogdanm 0:9b334a45a8ff 318 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 319 *
bogdanm 0:9b334a45a8ff 320 * Typically this function configures the oscillator (PLL) that is part of the
bogdanm 0:9b334a45a8ff 321 * microcontroller device. For systems with variable clock speed it also updates
bogdanm 0:9b334a45a8ff 322 * the variable SystemCoreClock. SystemInit is called from startup_device file.
bogdanm 0:9b334a45a8ff 323 */
bogdanm 0:9b334a45a8ff 324 void SystemInit (void);
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /**
bogdanm 0:9b334a45a8ff 327 * @brief Updates the SystemCoreClock variable.
bogdanm 0:9b334a45a8ff 328 *
bogdanm 0:9b334a45a8ff 329 * It must be called whenever the core clock is changed during program
bogdanm 0:9b334a45a8ff 330 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
bogdanm 0:9b334a45a8ff 331 * the current core clock.
bogdanm 0:9b334a45a8ff 332 */
bogdanm 0:9b334a45a8ff 333 void SystemCoreClockUpdate (void);
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 336 }
bogdanm 0:9b334a45a8ff 337 #endif
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 #endif /* #if !defined(SYSTEM_MK64F12_H_) */