Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processor: MK64FN1M0VMD12
bogdanm 0:9b334a45a8ff 4 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 5 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 6 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 7 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 0:9b334a45a8ff 8 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 9 **
bogdanm 0:9b334a45a8ff 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
bogdanm 0:9b334a45a8ff 11 ** Version: rev. 2.5, 2014-02-10
bogdanm 0:9b334a45a8ff 12 ** Build: b140611
bogdanm 0:9b334a45a8ff 13 **
bogdanm 0:9b334a45a8ff 14 ** Abstract:
bogdanm 0:9b334a45a8ff 15 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 16 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 17 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 18 **
bogdanm 0:9b334a45a8ff 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 20 ** All rights reserved.
bogdanm 0:9b334a45a8ff 21 **
bogdanm 0:9b334a45a8ff 22 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 23 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 24 **
bogdanm 0:9b334a45a8ff 25 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 26 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 27 **
bogdanm 0:9b334a45a8ff 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 29 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 30 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 31 **
bogdanm 0:9b334a45a8ff 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 33 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 34 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 35 **
bogdanm 0:9b334a45a8ff 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 46 **
bogdanm 0:9b334a45a8ff 47 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 48 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 49 **
bogdanm 0:9b334a45a8ff 50 ** Revisions:
bogdanm 0:9b334a45a8ff 51 ** - rev. 1.0 (2013-08-12)
bogdanm 0:9b334a45a8ff 52 ** Initial version.
bogdanm 0:9b334a45a8ff 53 ** - rev. 2.0 (2013-10-29)
bogdanm 0:9b334a45a8ff 54 ** Register accessor macros added to the memory map.
bogdanm 0:9b334a45a8ff 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
bogdanm 0:9b334a45a8ff 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
bogdanm 0:9b334a45a8ff 57 ** System initialization updated.
bogdanm 0:9b334a45a8ff 58 ** MCG - registers updated.
bogdanm 0:9b334a45a8ff 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
bogdanm 0:9b334a45a8ff 60 ** - rev. 2.1 (2013-10-30)
bogdanm 0:9b334a45a8ff 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
bogdanm 0:9b334a45a8ff 62 ** - rev. 2.2 (2013-12-09)
bogdanm 0:9b334a45a8ff 63 ** DMA - EARS register removed.
bogdanm 0:9b334a45a8ff 64 ** AIPS0, AIPS1 - MPRA register updated.
bogdanm 0:9b334a45a8ff 65 ** - rev. 2.3 (2014-01-24)
bogdanm 0:9b334a45a8ff 66 ** Update according to reference manual rev. 2
bogdanm 0:9b334a45a8ff 67 ** ENET, MCG, MCM, SIM, USB - registers updated
bogdanm 0:9b334a45a8ff 68 ** - rev. 2.4 (2014-02-10)
bogdanm 0:9b334a45a8ff 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
bogdanm 0:9b334a45a8ff 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
bogdanm 0:9b334a45a8ff 71 ** - rev. 2.5 (2014-02-10)
bogdanm 0:9b334a45a8ff 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
bogdanm 0:9b334a45a8ff 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
bogdanm 0:9b334a45a8ff 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
bogdanm 0:9b334a45a8ff 75 **
bogdanm 0:9b334a45a8ff 76 ** ###################################################################
bogdanm 0:9b334a45a8ff 77 */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /*!
bogdanm 0:9b334a45a8ff 80 * @file MK64F12
bogdanm 0:9b334a45a8ff 81 * @version 2.5
bogdanm 0:9b334a45a8ff 82 * @date 2014-02-10
bogdanm 0:9b334a45a8ff 83 * @brief Device specific configuration file for MK64F12 (implementation file)
bogdanm 0:9b334a45a8ff 84 *
bogdanm 0:9b334a45a8ff 85 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 86 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 87 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #include <stdint.h>
bogdanm 0:9b334a45a8ff 91 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 96 -- Core clock
bogdanm 0:9b334a45a8ff 97 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 102 -- SystemInit()
bogdanm 0:9b334a45a8ff 103 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 106 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
bogdanm 0:9b334a45a8ff 107 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
bogdanm 0:9b334a45a8ff 108 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
bogdanm 0:9b334a45a8ff 109 #if (DISABLE_WDOG)
bogdanm 0:9b334a45a8ff 110 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
bogdanm 0:9b334a45a8ff 111 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
bogdanm 0:9b334a45a8ff 112 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
bogdanm 0:9b334a45a8ff 113 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
bogdanm 0:9b334a45a8ff 114 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
bogdanm 0:9b334a45a8ff 115 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
bogdanm 0:9b334a45a8ff 116 WDOG_STCTRLH_WAITEN_MASK |
bogdanm 0:9b334a45a8ff 117 WDOG_STCTRLH_STOPEN_MASK |
bogdanm 0:9b334a45a8ff 118 WDOG_STCTRLH_ALLOWUPDATE_MASK |
bogdanm 0:9b334a45a8ff 119 WDOG_STCTRLH_CLKSRC_MASK |
bogdanm 0:9b334a45a8ff 120 0x0100U;
bogdanm 0:9b334a45a8ff 121 #endif /* (DISABLE_WDOG) */
bogdanm 0:9b334a45a8ff 122 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
bogdanm 0:9b334a45a8ff 123 {
bogdanm 0:9b334a45a8ff 124 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
bogdanm 0:9b334a45a8ff 125 {
bogdanm 0:9b334a45a8ff 126 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
bogdanm 0:9b334a45a8ff 127 }
bogdanm 0:9b334a45a8ff 128 } else {
bogdanm 0:9b334a45a8ff 129 #ifdef SYSTEM_RTC_CR_VALUE
bogdanm 0:9b334a45a8ff 130 SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
bogdanm 0:9b334a45a8ff 131 if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
bogdanm 0:9b334a45a8ff 132 RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
bogdanm 0:9b334a45a8ff 133 RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
bogdanm 0:9b334a45a8ff 134 RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136 #endif
bogdanm 0:9b334a45a8ff 137 }
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /* Power mode protection initialization */
bogdanm 0:9b334a45a8ff 140 #ifdef SYSTEM_SMC_PMPROT_VALUE
bogdanm 0:9b334a45a8ff 141 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
bogdanm 0:9b334a45a8ff 142 #endif
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /* System clock initialization */
bogdanm 0:9b334a45a8ff 145 /* Internal reference clock trim initialization */
bogdanm 0:9b334a45a8ff 146 #if defined(SLOW_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 147 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
bogdanm 0:9b334a45a8ff 148 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
bogdanm 0:9b334a45a8ff 149 #endif /* defined(SLOW_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 150 #if defined(SLOW_FINE_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 151 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
bogdanm 0:9b334a45a8ff 152 #endif
bogdanm 0:9b334a45a8ff 153 #if defined(FAST_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 154 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
bogdanm 0:9b334a45a8ff 155 #endif
bogdanm 0:9b334a45a8ff 156 #if defined(FAST_FINE_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 157 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
bogdanm 0:9b334a45a8ff 158 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 159 #if defined(SLOW_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 160 }
bogdanm 0:9b334a45a8ff 161 #endif /* defined(SLOW_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* Set system prescalers and clock sources */
bogdanm 0:9b334a45a8ff 164 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
bogdanm 0:9b334a45a8ff 165 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
bogdanm 0:9b334a45a8ff 166 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
bogdanm 0:9b334a45a8ff 167 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
bogdanm 0:9b334a45a8ff 168 /* Set MCG and OSC */
bogdanm 0:9b334a45a8ff 169 #if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
bogdanm 0:9b334a45a8ff 170 /* SIM_SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 171 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 0:9b334a45a8ff 172 /* PORTA_PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 173 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 174 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 175 /* PORTA_PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 176 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 177 }
bogdanm 0:9b334a45a8ff 178 #endif
bogdanm 0:9b334a45a8ff 179 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
bogdanm 0:9b334a45a8ff 180 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
bogdanm 0:9b334a45a8ff 181 /* Check that the source of the FLL reference clock is the requested one. */
bogdanm 0:9b334a45a8ff 182 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 183 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 184 }
bogdanm 0:9b334a45a8ff 185 } else {
bogdanm 0:9b334a45a8ff 186 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 187 }
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
bogdanm 0:9b334a45a8ff 190 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
bogdanm 0:9b334a45a8ff 191 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
bogdanm 0:9b334a45a8ff 192 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
bogdanm 0:9b334a45a8ff 193 #if (MCG_MODE == MCG_MODE_BLPI)
bogdanm 0:9b334a45a8ff 194 /* BLPI specific */
bogdanm 0:9b334a45a8ff 195 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
bogdanm 0:9b334a45a8ff 196 #endif
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 #else /* MCG_MODE */
bogdanm 0:9b334a45a8ff 199 /* Set MCG and OSC */
bogdanm 0:9b334a45a8ff 200 #if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
bogdanm 0:9b334a45a8ff 201 /* SIM_SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 202 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 0:9b334a45a8ff 203 /* PORTA_PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 204 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 205 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 206 /* PORTA_PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 207 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 208 }
bogdanm 0:9b334a45a8ff 209 #endif
bogdanm 0:9b334a45a8ff 210 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
bogdanm 0:9b334a45a8ff 211 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
bogdanm 0:9b334a45a8ff 212 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
bogdanm 0:9b334a45a8ff 213 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
bogdanm 0:9b334a45a8ff 214 #if (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 215 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
bogdanm 0:9b334a45a8ff 216 #else
bogdanm 0:9b334a45a8ff 217 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
bogdanm 0:9b334a45a8ff 218 #endif
bogdanm 0:9b334a45a8ff 219 if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
bogdanm 0:9b334a45a8ff 220 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223 /* Check that the source of the FLL reference clock is the requested one. */
bogdanm 0:9b334a45a8ff 224 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 225 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227 } else {
bogdanm 0:9b334a45a8ff 228 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230 }
bogdanm 0:9b334a45a8ff 231 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
bogdanm 0:9b334a45a8ff 232 #endif /* MCG_MODE */
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /* Common for all MCG modes */
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
bogdanm 0:9b334a45a8ff 237 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
bogdanm 0:9b334a45a8ff 238 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
bogdanm 0:9b334a45a8ff 239 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
bogdanm 0:9b334a45a8ff 240 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242 /* BLPE, PEE and PBE MCG mode specific */
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 #if (MCG_MODE == MCG_MODE_BLPE)
bogdanm 0:9b334a45a8ff 245 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
bogdanm 0:9b334a45a8ff 246 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
bogdanm 0:9b334a45a8ff 247 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
bogdanm 0:9b334a45a8ff 248 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
bogdanm 0:9b334a45a8ff 249 }
bogdanm 0:9b334a45a8ff 250 #if (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 251 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
bogdanm 0:9b334a45a8ff 252 #endif
bogdanm 0:9b334a45a8ff 253 #endif
bogdanm 0:9b334a45a8ff 254 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
bogdanm 0:9b334a45a8ff 255 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
bogdanm 0:9b334a45a8ff 256 }
bogdanm 0:9b334a45a8ff 257 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
bogdanm 0:9b334a45a8ff 258 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
bogdanm 0:9b334a45a8ff 261 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263 #elif (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 264 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266 #endif
bogdanm 0:9b334a45a8ff 267 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
bogdanm 0:9b334a45a8ff 268 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
bogdanm 0:9b334a45a8ff 269 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271 #endif
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
bogdanm 0:9b334a45a8ff 274 SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
bogdanm 0:9b334a45a8ff 275 #endif
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /* PLL loss of lock interrupt request initialization */
bogdanm 0:9b334a45a8ff 278 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
bogdanm 0:9b334a45a8ff 279 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 284 -- SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 285 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 void SystemCoreClockUpdate (void) {
bogdanm 0:9b334a45a8ff 288 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
bogdanm 0:9b334a45a8ff 289 uint16_t Divider;
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 292 /* Output of FLL or PLL is selected */
bogdanm 0:9b334a45a8ff 293 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 294 /* FLL is selected */
bogdanm 0:9b334a45a8ff 295 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 296 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 297 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
bogdanm 0:9b334a45a8ff 298 case 0x00U:
bogdanm 0:9b334a45a8ff 299 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 300 break;
bogdanm 0:9b334a45a8ff 301 case 0x01U:
bogdanm 0:9b334a45a8ff 302 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 303 break;
bogdanm 0:9b334a45a8ff 304 case 0x02U:
bogdanm 0:9b334a45a8ff 305 default:
bogdanm 0:9b334a45a8ff 306 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 307 break;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
bogdanm 0:9b334a45a8ff 310 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
bogdanm 0:9b334a45a8ff 311 case 0x38U:
bogdanm 0:9b334a45a8ff 312 Divider = 1536U;
bogdanm 0:9b334a45a8ff 313 break;
bogdanm 0:9b334a45a8ff 314 case 0x30U:
bogdanm 0:9b334a45a8ff 315 Divider = 1280U;
bogdanm 0:9b334a45a8ff 316 break;
bogdanm 0:9b334a45a8ff 317 default:
bogdanm 0:9b334a45a8ff 318 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 319 break;
bogdanm 0:9b334a45a8ff 320 }
bogdanm 0:9b334a45a8ff 321 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
bogdanm 0:9b334a45a8ff 322 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 0:9b334a45a8ff 325 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 326 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 0:9b334a45a8ff 327 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 328 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 329 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 330 case 0x00U:
bogdanm 0:9b334a45a8ff 331 MCGOUTClock *= 640U;
bogdanm 0:9b334a45a8ff 332 break;
bogdanm 0:9b334a45a8ff 333 case 0x20U:
bogdanm 0:9b334a45a8ff 334 MCGOUTClock *= 1280U;
bogdanm 0:9b334a45a8ff 335 break;
bogdanm 0:9b334a45a8ff 336 case 0x40U:
bogdanm 0:9b334a45a8ff 337 MCGOUTClock *= 1920U;
bogdanm 0:9b334a45a8ff 338 break;
bogdanm 0:9b334a45a8ff 339 case 0x60U:
bogdanm 0:9b334a45a8ff 340 MCGOUTClock *= 2560U;
bogdanm 0:9b334a45a8ff 341 break;
bogdanm 0:9b334a45a8ff 342 case 0x80U:
bogdanm 0:9b334a45a8ff 343 MCGOUTClock *= 732U;
bogdanm 0:9b334a45a8ff 344 break;
bogdanm 0:9b334a45a8ff 345 case 0xA0U:
bogdanm 0:9b334a45a8ff 346 MCGOUTClock *= 1464U;
bogdanm 0:9b334a45a8ff 347 break;
bogdanm 0:9b334a45a8ff 348 case 0xC0U:
bogdanm 0:9b334a45a8ff 349 MCGOUTClock *= 2197U;
bogdanm 0:9b334a45a8ff 350 break;
bogdanm 0:9b334a45a8ff 351 case 0xE0U:
bogdanm 0:9b334a45a8ff 352 MCGOUTClock *= 2929U;
bogdanm 0:9b334a45a8ff 353 break;
bogdanm 0:9b334a45a8ff 354 default:
bogdanm 0:9b334a45a8ff 355 break;
bogdanm 0:9b334a45a8ff 356 }
bogdanm 0:9b334a45a8ff 357 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 358 /* PLL is selected */
bogdanm 0:9b334a45a8ff 359 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
bogdanm 0:9b334a45a8ff 360 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
bogdanm 0:9b334a45a8ff 361 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
bogdanm 0:9b334a45a8ff 362 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 363 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 364 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
bogdanm 0:9b334a45a8ff 365 /* Internal reference clock is selected */
bogdanm 0:9b334a45a8ff 366 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 367 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 0:9b334a45a8ff 368 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 369 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 370 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
bogdanm 0:9b334a45a8ff 371 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 372 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
bogdanm 0:9b334a45a8ff 373 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 374 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
bogdanm 0:9b334a45a8ff 375 case 0x00U:
bogdanm 0:9b334a45a8ff 376 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 377 break;
bogdanm 0:9b334a45a8ff 378 case 0x01U:
bogdanm 0:9b334a45a8ff 379 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 380 break;
bogdanm 0:9b334a45a8ff 381 case 0x02U:
bogdanm 0:9b334a45a8ff 382 default:
bogdanm 0:9b334a45a8ff 383 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 384 break;
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 387 /* Reserved value */
bogdanm 0:9b334a45a8ff 388 return;
bogdanm 0:9b334a45a8ff 389 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 390 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 391 }