Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processors: MKL26Z128CAL4
bogdanm 0:9b334a45a8ff 4 ** MKL26Z128VFM4
bogdanm 0:9b334a45a8ff 5 ** MKL26Z64VFM4
bogdanm 0:9b334a45a8ff 6 ** MKL26Z32VM4
bogdanm 0:9b334a45a8ff 7 ** MKL26Z128VFT4
bogdanm 0:9b334a45a8ff 8 ** MKL26Z64VFT4
bogdanm 0:9b334a45a8ff 9 ** MKL26Z32VFT4
bogdanm 0:9b334a45a8ff 10 ** MKL26Z128VLH4
bogdanm 0:9b334a45a8ff 11 ** MKL26Z64VLH4
bogdanm 0:9b334a45a8ff 12 ** MKL26Z32VLH4
bogdanm 0:9b334a45a8ff 13 ** MKL26Z256VLH4
bogdanm 0:9b334a45a8ff 14 ** MKL26Z256VLL4
bogdanm 0:9b334a45a8ff 15 ** MKL26Z128VLL4
bogdanm 0:9b334a45a8ff 16 ** MKL26Z256VMC4
bogdanm 0:9b334a45a8ff 17 ** MKL26Z128VMC4
bogdanm 0:9b334a45a8ff 18 ** MKL26Z256VMP4
bogdanm 0:9b334a45a8ff 19 **
bogdanm 0:9b334a45a8ff 20 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 21 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 22 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 23 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 0:9b334a45a8ff 24 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 25 **
bogdanm 0:9b334a45a8ff 26 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
bogdanm 0:9b334a45a8ff 27 ** KL26P121M48SF4RM, Rev.2, Dec 2012
bogdanm 0:9b334a45a8ff 28 **
bogdanm 0:9b334a45a8ff 29 ** Version: rev. 1.7, 2015-01-13
bogdanm 0:9b334a45a8ff 30 ** Build: b150129
bogdanm 0:9b334a45a8ff 31 **
bogdanm 0:9b334a45a8ff 32 ** Abstract:
bogdanm 0:9b334a45a8ff 33 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 34 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 35 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 36 **
bogdanm 0:9b334a45a8ff 37 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 38 ** All rights reserved.
bogdanm 0:9b334a45a8ff 39 **
bogdanm 0:9b334a45a8ff 40 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 41 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 42 **
bogdanm 0:9b334a45a8ff 43 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 44 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 45 **
bogdanm 0:9b334a45a8ff 46 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 47 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 48 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 49 **
bogdanm 0:9b334a45a8ff 50 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 51 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 52 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 53 **
bogdanm 0:9b334a45a8ff 54 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 55 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 56 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 57 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 58 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 59 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 60 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 61 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 62 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 63 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 64 **
bogdanm 0:9b334a45a8ff 65 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 66 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 67 **
bogdanm 0:9b334a45a8ff 68 ** Revisions:
bogdanm 0:9b334a45a8ff 69 ** - rev. 1.0 (2012-12-12)
bogdanm 0:9b334a45a8ff 70 ** Initial version.
bogdanm 0:9b334a45a8ff 71 ** - rev. 1.1 (2013-04-05)
bogdanm 0:9b334a45a8ff 72 ** Changed start of doxygen comment.
bogdanm 0:9b334a45a8ff 73 ** - rev. 1.2 (2013-04-12)
bogdanm 0:9b334a45a8ff 74 ** SystemInit function fixed for clock configuration 1.
bogdanm 0:9b334a45a8ff 75 ** Name of the interrupt num. 31 updated to reflect proper function.
bogdanm 0:9b334a45a8ff 76 ** - rev. 1.3 (2014-05-27)
bogdanm 0:9b334a45a8ff 77 ** Updated to Kinetis SDK support standard.
bogdanm 0:9b334a45a8ff 78 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
bogdanm 0:9b334a45a8ff 79 ** - rev. 1.4 (2014-07-25)
bogdanm 0:9b334a45a8ff 80 ** System initialization updated:
bogdanm 0:9b334a45a8ff 81 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
bogdanm 0:9b334a45a8ff 82 ** - VLLSx wake-up recovery added.
bogdanm 0:9b334a45a8ff 83 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
bogdanm 0:9b334a45a8ff 84 ** - rev. 1.5 (2014-08-28)
bogdanm 0:9b334a45a8ff 85 ** Update of system files - default clock configuration changed, fix of OSC initialization.
bogdanm 0:9b334a45a8ff 86 ** Update of startup files - possibility to override DefaultISR added.
bogdanm 0:9b334a45a8ff 87 ** - rev. 1.6 (2014-10-14)
bogdanm 0:9b334a45a8ff 88 ** Renamed interrupt vector LPTimer to LPTMR0
bogdanm 0:9b334a45a8ff 89 ** - rev. 1.7 (2015-01-13)
bogdanm 0:9b334a45a8ff 90 ** Update of the copyright.
bogdanm 0:9b334a45a8ff 91 **
bogdanm 0:9b334a45a8ff 92 ** ###################################################################
bogdanm 0:9b334a45a8ff 93 */
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /*!
bogdanm 0:9b334a45a8ff 96 * @file MKL26Z4
bogdanm 0:9b334a45a8ff 97 * @version 1.7
bogdanm 0:9b334a45a8ff 98 * @date 2015-01-13
bogdanm 0:9b334a45a8ff 99 * @brief Device specific configuration file for MKL26Z4 (header file)
bogdanm 0:9b334a45a8ff 100 *
bogdanm 0:9b334a45a8ff 101 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 102 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 103 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 #ifndef SYSTEM_MKL26Z4_H_
bogdanm 0:9b334a45a8ff 107 #define SYSTEM_MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 110 extern "C" {
bogdanm 0:9b334a45a8ff 111 #endif
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 #include <stdint.h>
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 #ifndef DISABLE_WDOG
bogdanm 0:9b334a45a8ff 117 #define DISABLE_WDOG 1
bogdanm 0:9b334a45a8ff 118 #endif
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 #define ACK_ISOLATION 1
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 #ifndef RTC_CLKIN_USED
bogdanm 0:9b334a45a8ff 123 #define RTC_CLKIN_USED 1
bogdanm 0:9b334a45a8ff 124 #endif
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /* MCG mode constants */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 #define MCG_MODE_FEI 0U
bogdanm 0:9b334a45a8ff 130 #define MCG_MODE_FBI 1U
bogdanm 0:9b334a45a8ff 131 #define MCG_MODE_BLPI 2U
bogdanm 0:9b334a45a8ff 132 #define MCG_MODE_FEE 3U
bogdanm 0:9b334a45a8ff 133 #define MCG_MODE_FBE 4U
bogdanm 0:9b334a45a8ff 134 #define MCG_MODE_BLPE 5U
bogdanm 0:9b334a45a8ff 135 #define MCG_MODE_PBE 6U
bogdanm 0:9b334a45a8ff 136 #define MCG_MODE_PEE 7U
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Predefined clock setups
bogdanm 0:9b334a45a8ff 139 0 ... Default part configuration
bogdanm 0:9b334a45a8ff 140 Multipurpose Clock Generator (MCG) in FEI mode.
bogdanm 0:9b334a45a8ff 141 Reference clock source for MCG module: Slow internal reference clock
bogdanm 0:9b334a45a8ff 142 Core clock = 20.97152MHz
bogdanm 0:9b334a45a8ff 143 Bus clock = 20.97152MHz
bogdanm 0:9b334a45a8ff 144 1 ... Maximum achievable clock frequency configuration
bogdanm 0:9b334a45a8ff 145 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 146 Reference clock source for MCG module: System oscillator reference clock
bogdanm 0:9b334a45a8ff 147 Core clock = 48MHz
bogdanm 0:9b334a45a8ff 148 Bus clock = 24MHz
bogdanm 0:9b334a45a8ff 149 2 ... Chip internally clocked, ready for Very Low Power Run mode
bogdanm 0:9b334a45a8ff 150 Multipurpose Clock Generator (MCG) in BLPI mode.
bogdanm 0:9b334a45a8ff 151 Reference clock source for MCG module: Fast internal reference clock
bogdanm 0:9b334a45a8ff 152 Core clock = 4MHz
bogdanm 0:9b334a45a8ff 153 Bus clock = 0.8MHz
bogdanm 0:9b334a45a8ff 154 3 ... Chip externally clocked, ready for Very Low Power Run mode
bogdanm 0:9b334a45a8ff 155 Multipurpose Clock Generator (MCG) in BLPE mode.
bogdanm 0:9b334a45a8ff 156 Reference clock source for MCG module: System oscillator reference clock
bogdanm 0:9b334a45a8ff 157 Core clock = 4MHz
bogdanm 0:9b334a45a8ff 158 Bus clock = 1MHz
bogdanm 0:9b334a45a8ff 159 4 ... USB clock setup
bogdanm 0:9b334a45a8ff 160 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 161 Reference clock source for MCG module: System oscillator reference clock
bogdanm 0:9b334a45a8ff 162 Core clock = 48MHz
bogdanm 0:9b334a45a8ff 163 Bus clock = 24MHz
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /* Define clock source values */
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 #define CPU_XTAL_CLK_HZ 8000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
bogdanm 0:9b334a45a8ff 169 #define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 170 #define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /* RTC oscillator setting */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Low power mode enable */
bogdanm 0:9b334a45a8ff 175 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
bogdanm 0:9b334a45a8ff 176 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 /* Internal reference clock trim */
bogdanm 0:9b334a45a8ff 179 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 180 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 181 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 182 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 #ifdef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 185 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 186 #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
bogdanm 0:9b334a45a8ff 187 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
bogdanm 0:9b334a45a8ff 188 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 189 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 190 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 191 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 192 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 193 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 194 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 195 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 196 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 197 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 198 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 199 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 200 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 201 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
bogdanm 0:9b334a45a8ff 202 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 203 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 204 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
bogdanm 0:9b334a45a8ff 205 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 206 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
bogdanm 0:9b334a45a8ff 207 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 208 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 209 #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 210 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 211 #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */
bogdanm 0:9b334a45a8ff 212 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 213 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 214 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 215 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 216 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 217 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 218 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 219 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 220 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 221 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
bogdanm 0:9b334a45a8ff 222 #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 223 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 224 #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 225 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 226 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
bogdanm 0:9b334a45a8ff 227 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 228 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 229 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
bogdanm 0:9b334a45a8ff 230 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 231 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
bogdanm 0:9b334a45a8ff 232 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 233 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 234 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 235 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 236 #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
bogdanm 0:9b334a45a8ff 237 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
bogdanm 0:9b334a45a8ff 238 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 239 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 240 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
bogdanm 0:9b334a45a8ff 241 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 242 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 243 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 244 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 245 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 246 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 247 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 248 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 249 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 250 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 251 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
bogdanm 0:9b334a45a8ff 252 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 253 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 254 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 255 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 256 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
bogdanm 0:9b334a45a8ff 257 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 258 /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 259 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 260 #elif (CLOCK_SETUP == 3)
bogdanm 0:9b334a45a8ff 261 #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
bogdanm 0:9b334a45a8ff 262 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 263 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 264 #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 265 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
bogdanm 0:9b334a45a8ff 266 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 267 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 268 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 269 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 270 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 271 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 272 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 273 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 274 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 275 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 276 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
bogdanm 0:9b334a45a8ff 277 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 278 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 279 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */
bogdanm 0:9b334a45a8ff 280 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 281 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
bogdanm 0:9b334a45a8ff 282 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 283 /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 284 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 285 #elif (CLOCK_SETUP == 4)
bogdanm 0:9b334a45a8ff 286 #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */
bogdanm 0:9b334a45a8ff 287 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 288 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 289 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 290 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 291 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 292 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 293 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 294 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 295 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 296 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
bogdanm 0:9b334a45a8ff 297 #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 298 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=24 */
bogdanm 0:9b334a45a8ff 299 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 300 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 301 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
bogdanm 0:9b334a45a8ff 302 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 303 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 304 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
bogdanm 0:9b334a45a8ff 305 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 306 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
bogdanm 0:9b334a45a8ff 307 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 308 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 309 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 310 #else
bogdanm 0:9b334a45a8ff 311 #error The selected clock setup is not supported.
bogdanm 0:9b334a45a8ff 312 #endif
bogdanm 0:9b334a45a8ff 313 #else //#ifdef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 314 #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
bogdanm 0:9b334a45a8ff 315 #endif //#ifdef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @brief System clock frequency (core clock)
bogdanm 0:9b334a45a8ff 320 *
bogdanm 0:9b334a45a8ff 321 * The system clock frequency supplied to the SysTick timer and the processor
bogdanm 0:9b334a45a8ff 322 * core clock. This variable can be used by the user application to setup the
bogdanm 0:9b334a45a8ff 323 * SysTick timer or configure other parameters. It may also be used by debugger to
bogdanm 0:9b334a45a8ff 324 * query the frequency of the debug timer or configure the trace clock speed
bogdanm 0:9b334a45a8ff 325 * SystemCoreClock is initialized with a correct predefined value.
bogdanm 0:9b334a45a8ff 326 */
bogdanm 0:9b334a45a8ff 327 extern uint32_t SystemCoreClock;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /**
bogdanm 0:9b334a45a8ff 330 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 331 *
bogdanm 0:9b334a45a8ff 332 * Typically this function configures the oscillator (PLL) that is part of the
bogdanm 0:9b334a45a8ff 333 * microcontroller device. For systems with variable clock speed it also updates
bogdanm 0:9b334a45a8ff 334 * the variable SystemCoreClock. SystemInit is called from startup_device file.
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336 void SystemInit (void);
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /**
bogdanm 0:9b334a45a8ff 339 * @brief Updates the SystemCoreClock variable.
bogdanm 0:9b334a45a8ff 340 *
bogdanm 0:9b334a45a8ff 341 * It must be called whenever the core clock is changed during program
bogdanm 0:9b334a45a8ff 342 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
bogdanm 0:9b334a45a8ff 343 * the current core clock.
bogdanm 0:9b334a45a8ff 344 */
bogdanm 0:9b334a45a8ff 345 void SystemCoreClockUpdate (void);
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 348 }
bogdanm 0:9b334a45a8ff 349 #endif
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 #endif /* #if !defined(SYSTEM_MKL26Z4_H_) */