added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_Freescale/TARGET_KL27Z/MKL27Z644_features.h@121:7f86b4238bec, 2016-05-03 (annotated)
- Committer:
- mbed_official
- Date:
- Tue May 03 00:15:16 2016 +0100
- Revision:
- 121:7f86b4238bec
Synchronized with git revision 9cef243de23875778f461bbe9a8c1bc47e65212b
Full URL: https://github.com/mbedmicro/mbed/commit/9cef243de23875778f461bbe9a8c1bc47e65212b/
Switch to KSDK 2.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 121:7f86b4238bec | 1 | /* |
mbed_official | 121:7f86b4238bec | 2 | ** ################################################################### |
mbed_official | 121:7f86b4238bec | 3 | ** Version: rev. 1.8, 2015-05-27 |
mbed_official | 121:7f86b4238bec | 4 | ** Build: b151216 |
mbed_official | 121:7f86b4238bec | 5 | ** |
mbed_official | 121:7f86b4238bec | 6 | ** Abstract: |
mbed_official | 121:7f86b4238bec | 7 | ** Chip specific module features. |
mbed_official | 121:7f86b4238bec | 8 | ** |
mbed_official | 121:7f86b4238bec | 9 | ** Copyright (c) 2015 Freescale Semiconductor, Inc. |
mbed_official | 121:7f86b4238bec | 10 | ** All rights reserved. |
mbed_official | 121:7f86b4238bec | 11 | ** |
mbed_official | 121:7f86b4238bec | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 121:7f86b4238bec | 13 | ** are permitted provided that the following conditions are met: |
mbed_official | 121:7f86b4238bec | 14 | ** |
mbed_official | 121:7f86b4238bec | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
mbed_official | 121:7f86b4238bec | 16 | ** of conditions and the following disclaimer. |
mbed_official | 121:7f86b4238bec | 17 | ** |
mbed_official | 121:7f86b4238bec | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
mbed_official | 121:7f86b4238bec | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
mbed_official | 121:7f86b4238bec | 20 | ** other materials provided with the distribution. |
mbed_official | 121:7f86b4238bec | 21 | ** |
mbed_official | 121:7f86b4238bec | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
mbed_official | 121:7f86b4238bec | 23 | ** contributors may be used to endorse or promote products derived from this |
mbed_official | 121:7f86b4238bec | 24 | ** software without specific prior written permission. |
mbed_official | 121:7f86b4238bec | 25 | ** |
mbed_official | 121:7f86b4238bec | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
mbed_official | 121:7f86b4238bec | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
mbed_official | 121:7f86b4238bec | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 121:7f86b4238bec | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
mbed_official | 121:7f86b4238bec | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
mbed_official | 121:7f86b4238bec | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
mbed_official | 121:7f86b4238bec | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
mbed_official | 121:7f86b4238bec | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
mbed_official | 121:7f86b4238bec | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
mbed_official | 121:7f86b4238bec | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 121:7f86b4238bec | 36 | ** |
mbed_official | 121:7f86b4238bec | 37 | ** http: www.freescale.com |
mbed_official | 121:7f86b4238bec | 38 | ** mail: support@freescale.com |
mbed_official | 121:7f86b4238bec | 39 | ** |
mbed_official | 121:7f86b4238bec | 40 | ** Revisions: |
mbed_official | 121:7f86b4238bec | 41 | ** - rev. 1.0 (2014-05-12) |
mbed_official | 121:7f86b4238bec | 42 | ** Initial version. |
mbed_official | 121:7f86b4238bec | 43 | ** - rev. 1.1 (2014-07-10) |
mbed_official | 121:7f86b4238bec | 44 | ** UART0 - UART0 module renamed to UART2. |
mbed_official | 121:7f86b4238bec | 45 | ** - rev. 1.2 (2014-08-12) |
mbed_official | 121:7f86b4238bec | 46 | ** CRC - CRC register renamed to DATA. |
mbed_official | 121:7f86b4238bec | 47 | ** - rev. 1.3 (2014-09-02) |
mbed_official | 121:7f86b4238bec | 48 | ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. |
mbed_official | 121:7f86b4238bec | 49 | ** USB - USB0_CTL1 was renamed to USB0_CTL register. |
mbed_official | 121:7f86b4238bec | 50 | ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. |
mbed_official | 121:7f86b4238bec | 51 | ** - rev. 1.4 (2014-09-22) |
mbed_official | 121:7f86b4238bec | 52 | ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. |
mbed_official | 121:7f86b4238bec | 53 | ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. |
mbed_official | 121:7f86b4238bec | 54 | ** SIM - Removed bitfield DIEID in SDID register. |
mbed_official | 121:7f86b4238bec | 55 | ** UART2 - Removed ED register. |
mbed_official | 121:7f86b4238bec | 56 | ** UART2 - Removed MODEM register. |
mbed_official | 121:7f86b4238bec | 57 | ** UART2 - Removed IR register. |
mbed_official | 121:7f86b4238bec | 58 | ** UART2 - Removed PFIFO register. |
mbed_official | 121:7f86b4238bec | 59 | ** UART2 - Removed CFIFO register. |
mbed_official | 121:7f86b4238bec | 60 | ** UART2 - Removed SFIFO register. |
mbed_official | 121:7f86b4238bec | 61 | ** UART2 - Removed TWFIFO register. |
mbed_official | 121:7f86b4238bec | 62 | ** UART2 - Removed TCFIFO register. |
mbed_official | 121:7f86b4238bec | 63 | ** UART2 - Removed RWFIFO register. |
mbed_official | 121:7f86b4238bec | 64 | ** UART2 - Removed RCFIFO register. |
mbed_official | 121:7f86b4238bec | 65 | ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. |
mbed_official | 121:7f86b4238bec | 66 | ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. |
mbed_official | 121:7f86b4238bec | 67 | ** - rev. 1.5 (2015-01-21) |
mbed_official | 121:7f86b4238bec | 68 | ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances |
mbed_official | 121:7f86b4238bec | 69 | ** - rev. 1.6 (2015-05-19) |
mbed_official | 121:7f86b4238bec | 70 | ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. |
mbed_official | 121:7f86b4238bec | 71 | ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. |
mbed_official | 121:7f86b4238bec | 72 | ** Added features for PORT. |
mbed_official | 121:7f86b4238bec | 73 | ** - rev. 1.7 (2015-05-25) |
mbed_official | 121:7f86b4238bec | 74 | ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS |
mbed_official | 121:7f86b4238bec | 75 | ** - rev. 1.8 (2015-05-27) |
mbed_official | 121:7f86b4238bec | 76 | ** Several USB features added. |
mbed_official | 121:7f86b4238bec | 77 | ** |
mbed_official | 121:7f86b4238bec | 78 | ** ################################################################### |
mbed_official | 121:7f86b4238bec | 79 | */ |
mbed_official | 121:7f86b4238bec | 80 | |
mbed_official | 121:7f86b4238bec | 81 | #ifndef _MKL27Z644_FEATURES_H_ |
mbed_official | 121:7f86b4238bec | 82 | #define _MKL27Z644_FEATURES_H_ |
mbed_official | 121:7f86b4238bec | 83 | |
mbed_official | 121:7f86b4238bec | 84 | /* SOC module features */ |
mbed_official | 121:7f86b4238bec | 85 | |
mbed_official | 121:7f86b4238bec | 86 | /* @brief ACMP availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 87 | #define FSL_FEATURE_SOC_ACMP_COUNT (0) |
mbed_official | 121:7f86b4238bec | 88 | /* @brief ADC16 availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 89 | #define FSL_FEATURE_SOC_ADC16_COUNT (1) |
mbed_official | 121:7f86b4238bec | 90 | /* @brief ADC12 availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 91 | #define FSL_FEATURE_SOC_ADC12_COUNT (0) |
mbed_official | 121:7f86b4238bec | 92 | /* @brief AFE availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 93 | #define FSL_FEATURE_SOC_AFE_COUNT (0) |
mbed_official | 121:7f86b4238bec | 94 | /* @brief AIPS availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 95 | #define FSL_FEATURE_SOC_AIPS_COUNT (0) |
mbed_official | 121:7f86b4238bec | 96 | /* @brief AOI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 97 | #define FSL_FEATURE_SOC_AOI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 98 | /* @brief AXBS availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 99 | #define FSL_FEATURE_SOC_AXBS_COUNT (0) |
mbed_official | 121:7f86b4238bec | 100 | /* @brief ASMC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 101 | #define FSL_FEATURE_SOC_ASMC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 102 | /* @brief CADC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 103 | #define FSL_FEATURE_SOC_CADC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 104 | /* @brief FLEXCAN availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 105 | #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) |
mbed_official | 121:7f86b4238bec | 106 | /* @brief MMCAU availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 107 | #define FSL_FEATURE_SOC_MMCAU_COUNT (0) |
mbed_official | 121:7f86b4238bec | 108 | /* @brief CMP availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 109 | #define FSL_FEATURE_SOC_CMP_COUNT (1) |
mbed_official | 121:7f86b4238bec | 110 | /* @brief CMT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 111 | #define FSL_FEATURE_SOC_CMT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 112 | /* @brief CNC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 113 | #define FSL_FEATURE_SOC_CNC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 114 | /* @brief CRC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 115 | #define FSL_FEATURE_SOC_CRC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 116 | /* @brief DAC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 117 | #define FSL_FEATURE_SOC_DAC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 118 | /* @brief DAC32 availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 119 | #define FSL_FEATURE_SOC_DAC32_COUNT (0) |
mbed_official | 121:7f86b4238bec | 120 | /* @brief DCDC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 121 | #define FSL_FEATURE_SOC_DCDC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 122 | /* @brief DDR availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 123 | #define FSL_FEATURE_SOC_DDR_COUNT (0) |
mbed_official | 121:7f86b4238bec | 124 | /* @brief DMA availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 125 | #define FSL_FEATURE_SOC_DMA_COUNT (1) |
mbed_official | 121:7f86b4238bec | 126 | /* @brief EDMA availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 127 | #define FSL_FEATURE_SOC_EDMA_COUNT (0) |
mbed_official | 121:7f86b4238bec | 128 | /* @brief DMAMUX availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 129 | #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) |
mbed_official | 121:7f86b4238bec | 130 | /* @brief DRY availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 131 | #define FSL_FEATURE_SOC_DRY_COUNT (0) |
mbed_official | 121:7f86b4238bec | 132 | /* @brief DSPI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 133 | #define FSL_FEATURE_SOC_DSPI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 134 | /* @brief EMVSIM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 135 | #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 136 | /* @brief ENC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 137 | #define FSL_FEATURE_SOC_ENC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 138 | /* @brief ENET availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 139 | #define FSL_FEATURE_SOC_ENET_COUNT (0) |
mbed_official | 121:7f86b4238bec | 140 | /* @brief EWM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 141 | #define FSL_FEATURE_SOC_EWM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 142 | /* @brief FB availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 143 | #define FSL_FEATURE_SOC_FB_COUNT (0) |
mbed_official | 121:7f86b4238bec | 144 | /* @brief FGPIO availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 145 | #define FSL_FEATURE_SOC_FGPIO_COUNT (0) |
mbed_official | 121:7f86b4238bec | 146 | /* @brief FLEXIO availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 147 | #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) |
mbed_official | 121:7f86b4238bec | 148 | /* @brief FMC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 149 | #define FSL_FEATURE_SOC_FMC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 150 | /* @brief FSKDT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 151 | #define FSL_FEATURE_SOC_FSKDT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 152 | /* @brief FTFA availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 153 | #define FSL_FEATURE_SOC_FTFA_COUNT (1) |
mbed_official | 121:7f86b4238bec | 154 | /* @brief FTFE availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 155 | #define FSL_FEATURE_SOC_FTFE_COUNT (0) |
mbed_official | 121:7f86b4238bec | 156 | /* @brief FTFL availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 157 | #define FSL_FEATURE_SOC_FTFL_COUNT (0) |
mbed_official | 121:7f86b4238bec | 158 | /* @brief FTM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 159 | #define FSL_FEATURE_SOC_FTM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 160 | /* @brief FTMRA availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 161 | #define FSL_FEATURE_SOC_FTMRA_COUNT (0) |
mbed_official | 121:7f86b4238bec | 162 | /* @brief FTMRE availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 163 | #define FSL_FEATURE_SOC_FTMRE_COUNT (0) |
mbed_official | 121:7f86b4238bec | 164 | /* @brief FTMRH availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 165 | #define FSL_FEATURE_SOC_FTMRH_COUNT (0) |
mbed_official | 121:7f86b4238bec | 166 | /* @brief GPIO availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 167 | #define FSL_FEATURE_SOC_GPIO_COUNT (5) |
mbed_official | 121:7f86b4238bec | 168 | /* @brief HSADC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 169 | #define FSL_FEATURE_SOC_HSADC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 170 | /* @brief I2C availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 171 | #define FSL_FEATURE_SOC_I2C_COUNT (2) |
mbed_official | 121:7f86b4238bec | 172 | /* @brief I2S availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 173 | #define FSL_FEATURE_SOC_I2S_COUNT (0) |
mbed_official | 121:7f86b4238bec | 174 | /* @brief ICS availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 175 | #define FSL_FEATURE_SOC_ICS_COUNT (0) |
mbed_official | 121:7f86b4238bec | 176 | /* @brief INTMUX availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 177 | #define FSL_FEATURE_SOC_INTMUX_COUNT (0) |
mbed_official | 121:7f86b4238bec | 178 | /* @brief IRQ availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 179 | #define FSL_FEATURE_SOC_IRQ_COUNT (0) |
mbed_official | 121:7f86b4238bec | 180 | /* @brief KBI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 181 | #define FSL_FEATURE_SOC_KBI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 182 | /* @brief SLCD availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 183 | #define FSL_FEATURE_SOC_SLCD_COUNT (0) |
mbed_official | 121:7f86b4238bec | 184 | /* @brief LCDC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 185 | #define FSL_FEATURE_SOC_LCDC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 186 | /* @brief LDO availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 187 | #define FSL_FEATURE_SOC_LDO_COUNT (0) |
mbed_official | 121:7f86b4238bec | 188 | /* @brief LLWU availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 189 | #define FSL_FEATURE_SOC_LLWU_COUNT (1) |
mbed_official | 121:7f86b4238bec | 190 | /* @brief LMEM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 191 | #define FSL_FEATURE_SOC_LMEM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 192 | /* @brief LPI2C availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 193 | #define FSL_FEATURE_SOC_LPI2C_COUNT (0) |
mbed_official | 121:7f86b4238bec | 194 | /* @brief LPIT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 195 | #define FSL_FEATURE_SOC_LPIT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 196 | /* @brief LPSCI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 197 | #define FSL_FEATURE_SOC_LPSCI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 198 | /* @brief LPSPI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 199 | #define FSL_FEATURE_SOC_LPSPI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 200 | /* @brief LPTMR availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 201 | #define FSL_FEATURE_SOC_LPTMR_COUNT (1) |
mbed_official | 121:7f86b4238bec | 202 | /* @brief LPTPM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 203 | #define FSL_FEATURE_SOC_LPTPM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 204 | /* @brief LPUART availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 205 | #define FSL_FEATURE_SOC_LPUART_COUNT (2) |
mbed_official | 121:7f86b4238bec | 206 | /* @brief LTC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 207 | #define FSL_FEATURE_SOC_LTC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 208 | /* @brief MC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 209 | #define FSL_FEATURE_SOC_MC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 210 | /* @brief MCG availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 211 | #define FSL_FEATURE_SOC_MCG_COUNT (0) |
mbed_official | 121:7f86b4238bec | 212 | /* @brief MCGLITE availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 213 | #define FSL_FEATURE_SOC_MCGLITE_COUNT (1) |
mbed_official | 121:7f86b4238bec | 214 | /* @brief MCM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 215 | #define FSL_FEATURE_SOC_MCM_COUNT (1) |
mbed_official | 121:7f86b4238bec | 216 | /* @brief MMAU availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 217 | #define FSL_FEATURE_SOC_MMAU_COUNT (0) |
mbed_official | 121:7f86b4238bec | 218 | /* @brief MMDVSQ availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 219 | #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) |
mbed_official | 121:7f86b4238bec | 220 | /* @brief MPU availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 221 | #define FSL_FEATURE_SOC_MPU_COUNT (0) |
mbed_official | 121:7f86b4238bec | 222 | /* @brief MSCAN availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 223 | #define FSL_FEATURE_SOC_MSCAN_COUNT (0) |
mbed_official | 121:7f86b4238bec | 224 | /* @brief MSCM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 225 | #define FSL_FEATURE_SOC_MSCM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 226 | /* @brief MTB availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 227 | #define FSL_FEATURE_SOC_MTB_COUNT (1) |
mbed_official | 121:7f86b4238bec | 228 | /* @brief MTBDWT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 229 | #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) |
mbed_official | 121:7f86b4238bec | 230 | /* @brief MU availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 231 | #define FSL_FEATURE_SOC_MU_COUNT (0) |
mbed_official | 121:7f86b4238bec | 232 | /* @brief NFC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 233 | #define FSL_FEATURE_SOC_NFC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 234 | /* @brief OPAMP availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 235 | #define FSL_FEATURE_SOC_OPAMP_COUNT (0) |
mbed_official | 121:7f86b4238bec | 236 | /* @brief OSC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 237 | #define FSL_FEATURE_SOC_OSC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 238 | /* @brief OSC32 availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 239 | #define FSL_FEATURE_SOC_OSC32_COUNT (0) |
mbed_official | 121:7f86b4238bec | 240 | /* @brief OTFAD availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 241 | #define FSL_FEATURE_SOC_OTFAD_COUNT (0) |
mbed_official | 121:7f86b4238bec | 242 | /* @brief PDB availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 243 | #define FSL_FEATURE_SOC_PDB_COUNT (0) |
mbed_official | 121:7f86b4238bec | 244 | /* @brief PCC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 245 | #define FSL_FEATURE_SOC_PCC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 246 | /* @brief PGA availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 247 | #define FSL_FEATURE_SOC_PGA_COUNT (0) |
mbed_official | 121:7f86b4238bec | 248 | /* @brief PIT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 249 | #define FSL_FEATURE_SOC_PIT_COUNT (1) |
mbed_official | 121:7f86b4238bec | 250 | /* @brief PMC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 251 | #define FSL_FEATURE_SOC_PMC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 252 | /* @brief PORT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 253 | #define FSL_FEATURE_SOC_PORT_COUNT (5) |
mbed_official | 121:7f86b4238bec | 254 | /* @brief PWM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 255 | #define FSL_FEATURE_SOC_PWM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 256 | /* @brief PWT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 257 | #define FSL_FEATURE_SOC_PWT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 258 | /* @brief QuadSPI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 259 | #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 260 | /* @brief RCM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 261 | #define FSL_FEATURE_SOC_RCM_COUNT (1) |
mbed_official | 121:7f86b4238bec | 262 | /* @brief RFSYS availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 263 | #define FSL_FEATURE_SOC_RFSYS_COUNT (0) |
mbed_official | 121:7f86b4238bec | 264 | /* @brief RFVBAT availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 265 | #define FSL_FEATURE_SOC_RFVBAT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 266 | /* @brief RNG availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 267 | #define FSL_FEATURE_SOC_RNG_COUNT (0) |
mbed_official | 121:7f86b4238bec | 268 | /* @brief RNGB availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 269 | #define FSL_FEATURE_SOC_RNGB_COUNT (0) |
mbed_official | 121:7f86b4238bec | 270 | /* @brief ROM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 271 | #define FSL_FEATURE_SOC_ROM_COUNT (1) |
mbed_official | 121:7f86b4238bec | 272 | /* @brief RSIM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 273 | #define FSL_FEATURE_SOC_RSIM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 274 | /* @brief RTC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 275 | #define FSL_FEATURE_SOC_RTC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 276 | /* @brief SCG availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 277 | #define FSL_FEATURE_SOC_SCG_COUNT (0) |
mbed_official | 121:7f86b4238bec | 278 | /* @brief SCI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 279 | #define FSL_FEATURE_SOC_SCI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 280 | /* @brief SDHC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 281 | #define FSL_FEATURE_SOC_SDHC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 282 | /* @brief SDRAM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 283 | #define FSL_FEATURE_SOC_SDRAM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 284 | /* @brief SEMA42 availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 285 | #define FSL_FEATURE_SOC_SEMA42_COUNT (0) |
mbed_official | 121:7f86b4238bec | 286 | /* @brief SIM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 287 | #define FSL_FEATURE_SOC_SIM_COUNT (1) |
mbed_official | 121:7f86b4238bec | 288 | /* @brief SMC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 289 | #define FSL_FEATURE_SOC_SMC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 290 | /* @brief SPI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 291 | #define FSL_FEATURE_SOC_SPI_COUNT (2) |
mbed_official | 121:7f86b4238bec | 292 | /* @brief TMR availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 293 | #define FSL_FEATURE_SOC_TMR_COUNT (0) |
mbed_official | 121:7f86b4238bec | 294 | /* @brief TPM availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 295 | #define FSL_FEATURE_SOC_TPM_COUNT (3) |
mbed_official | 121:7f86b4238bec | 296 | /* @brief TRGMUX availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 297 | #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) |
mbed_official | 121:7f86b4238bec | 298 | /* @brief TRIAMP availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 299 | #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) |
mbed_official | 121:7f86b4238bec | 300 | /* @brief TRNG availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 301 | #define FSL_FEATURE_SOC_TRNG_COUNT (0) |
mbed_official | 121:7f86b4238bec | 302 | /* @brief TSI availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 303 | #define FSL_FEATURE_SOC_TSI_COUNT (0) |
mbed_official | 121:7f86b4238bec | 304 | /* @brief TSTMR availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 305 | #define FSL_FEATURE_SOC_TSTMR_COUNT (0) |
mbed_official | 121:7f86b4238bec | 306 | /* @brief UART availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 307 | #define FSL_FEATURE_SOC_UART_COUNT (1) |
mbed_official | 121:7f86b4238bec | 308 | /* @brief USB availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 309 | #define FSL_FEATURE_SOC_USB_COUNT (1) |
mbed_official | 121:7f86b4238bec | 310 | /* @brief USBDCD availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 311 | #define FSL_FEATURE_SOC_USBDCD_COUNT (0) |
mbed_official | 121:7f86b4238bec | 312 | /* @brief USBHSDCD availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 313 | #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) |
mbed_official | 121:7f86b4238bec | 314 | /* @brief USBPHY availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 315 | #define FSL_FEATURE_SOC_USBPHY_COUNT (0) |
mbed_official | 121:7f86b4238bec | 316 | /* @brief VREF availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 317 | #define FSL_FEATURE_SOC_VREF_COUNT (1) |
mbed_official | 121:7f86b4238bec | 318 | /* @brief WDOG availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 319 | #define FSL_FEATURE_SOC_WDOG_COUNT (0) |
mbed_official | 121:7f86b4238bec | 320 | /* @brief XBAR availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 321 | #define FSL_FEATURE_SOC_XBAR_COUNT (0) |
mbed_official | 121:7f86b4238bec | 322 | /* @brief XBARA availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 323 | #define FSL_FEATURE_SOC_XBARA_COUNT (0) |
mbed_official | 121:7f86b4238bec | 324 | /* @brief XBARB availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 325 | #define FSL_FEATURE_SOC_XBARB_COUNT (0) |
mbed_official | 121:7f86b4238bec | 326 | /* @brief XCVR availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 327 | #define FSL_FEATURE_SOC_XCVR_COUNT (0) |
mbed_official | 121:7f86b4238bec | 328 | /* @brief XRDC availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 329 | #define FSL_FEATURE_SOC_XRDC_COUNT (0) |
mbed_official | 121:7f86b4238bec | 330 | /* @brief ZLL availability on the SoC. */ |
mbed_official | 121:7f86b4238bec | 331 | #define FSL_FEATURE_SOC_ZLL_COUNT (0) |
mbed_official | 121:7f86b4238bec | 332 | |
mbed_official | 121:7f86b4238bec | 333 | /* ADC16 module features */ |
mbed_official | 121:7f86b4238bec | 334 | |
mbed_official | 121:7f86b4238bec | 335 | /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ |
mbed_official | 121:7f86b4238bec | 336 | #define FSL_FEATURE_ADC16_HAS_PGA (0) |
mbed_official | 121:7f86b4238bec | 337 | /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ |
mbed_official | 121:7f86b4238bec | 338 | #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) |
mbed_official | 121:7f86b4238bec | 339 | /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ |
mbed_official | 121:7f86b4238bec | 340 | #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) |
mbed_official | 121:7f86b4238bec | 341 | /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ |
mbed_official | 121:7f86b4238bec | 342 | #define FSL_FEATURE_ADC16_HAS_DMA (1) |
mbed_official | 121:7f86b4238bec | 343 | /* @brief Has differential mode (bitfield SC1x[DIFF]). */ |
mbed_official | 121:7f86b4238bec | 344 | #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) |
mbed_official | 121:7f86b4238bec | 345 | /* @brief Has FIFO (bit SC4[AFDEP]). */ |
mbed_official | 121:7f86b4238bec | 346 | #define FSL_FEATURE_ADC16_HAS_FIFO (0) |
mbed_official | 121:7f86b4238bec | 347 | /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ |
mbed_official | 121:7f86b4238bec | 348 | #define FSL_FEATURE_ADC16_FIFO_SIZE (0) |
mbed_official | 121:7f86b4238bec | 349 | /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ |
mbed_official | 121:7f86b4238bec | 350 | #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) |
mbed_official | 121:7f86b4238bec | 351 | /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ |
mbed_official | 121:7f86b4238bec | 352 | #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) |
mbed_official | 121:7f86b4238bec | 353 | /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ |
mbed_official | 121:7f86b4238bec | 354 | #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) |
mbed_official | 121:7f86b4238bec | 355 | /* @brief Has HW averaging (bit SC3[AVGE]). */ |
mbed_official | 121:7f86b4238bec | 356 | #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) |
mbed_official | 121:7f86b4238bec | 357 | /* @brief Has offset correction (register OFS). */ |
mbed_official | 121:7f86b4238bec | 358 | #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) |
mbed_official | 121:7f86b4238bec | 359 | /* @brief Maximum ADC resolution. */ |
mbed_official | 121:7f86b4238bec | 360 | #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) |
mbed_official | 121:7f86b4238bec | 361 | /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ |
mbed_official | 121:7f86b4238bec | 362 | #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) |
mbed_official | 121:7f86b4238bec | 363 | |
mbed_official | 121:7f86b4238bec | 364 | /* CMP module features */ |
mbed_official | 121:7f86b4238bec | 365 | |
mbed_official | 121:7f86b4238bec | 366 | /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ |
mbed_official | 121:7f86b4238bec | 367 | #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) |
mbed_official | 121:7f86b4238bec | 368 | /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ |
mbed_official | 121:7f86b4238bec | 369 | #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) |
mbed_official | 121:7f86b4238bec | 370 | /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ |
mbed_official | 121:7f86b4238bec | 371 | #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 372 | /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ |
mbed_official | 121:7f86b4238bec | 373 | #define FSL_FEATURE_CMP_HAS_DMA (1) |
mbed_official | 121:7f86b4238bec | 374 | /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ |
mbed_official | 121:7f86b4238bec | 375 | #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) |
mbed_official | 121:7f86b4238bec | 376 | /* @brief Has DAC Test function in CMP (register DACTEST). */ |
mbed_official | 121:7f86b4238bec | 377 | #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) |
mbed_official | 121:7f86b4238bec | 378 | |
mbed_official | 121:7f86b4238bec | 379 | /* COP module features */ |
mbed_official | 121:7f86b4238bec | 380 | |
mbed_official | 121:7f86b4238bec | 381 | /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ |
mbed_official | 121:7f86b4238bec | 382 | #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) |
mbed_official | 121:7f86b4238bec | 383 | /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ |
mbed_official | 121:7f86b4238bec | 384 | #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) |
mbed_official | 121:7f86b4238bec | 385 | /* @brief Has more clock sources like MCGIRC */ |
mbed_official | 121:7f86b4238bec | 386 | #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) |
mbed_official | 121:7f86b4238bec | 387 | /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ |
mbed_official | 121:7f86b4238bec | 388 | #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) |
mbed_official | 121:7f86b4238bec | 389 | |
mbed_official | 121:7f86b4238bec | 390 | /* CRC module features */ |
mbed_official | 121:7f86b4238bec | 391 | |
mbed_official | 121:7f86b4238bec | 392 | /* @brief Has data register with name CRC */ |
mbed_official | 121:7f86b4238bec | 393 | #define FSL_FEATURE_CRC_HAS_CRC_REG (0) |
mbed_official | 121:7f86b4238bec | 394 | |
mbed_official | 121:7f86b4238bec | 395 | /* DMA module features */ |
mbed_official | 121:7f86b4238bec | 396 | |
mbed_official | 121:7f86b4238bec | 397 | /* @brief Total number of DMA channels on all modules. */ |
mbed_official | 121:7f86b4238bec | 398 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4) |
mbed_official | 121:7f86b4238bec | 399 | |
mbed_official | 121:7f86b4238bec | 400 | /* DMAMUX module features */ |
mbed_official | 121:7f86b4238bec | 401 | |
mbed_official | 121:7f86b4238bec | 402 | /* @brief Number of DMA channels (related to number of register CHCFGn). */ |
mbed_official | 121:7f86b4238bec | 403 | #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) |
mbed_official | 121:7f86b4238bec | 404 | /* @brief Total number of DMA channels on all modules. */ |
mbed_official | 121:7f86b4238bec | 405 | #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) |
mbed_official | 121:7f86b4238bec | 406 | /* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */ |
mbed_official | 121:7f86b4238bec | 407 | #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) |
mbed_official | 121:7f86b4238bec | 408 | |
mbed_official | 121:7f86b4238bec | 409 | /* FLEXIO module features */ |
mbed_official | 121:7f86b4238bec | 410 | |
mbed_official | 121:7f86b4238bec | 411 | /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ |
mbed_official | 121:7f86b4238bec | 412 | #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) |
mbed_official | 121:7f86b4238bec | 413 | /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ |
mbed_official | 121:7f86b4238bec | 414 | #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0) |
mbed_official | 121:7f86b4238bec | 415 | /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ |
mbed_official | 121:7f86b4238bec | 416 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0) |
mbed_official | 121:7f86b4238bec | 417 | /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ |
mbed_official | 121:7f86b4238bec | 418 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0) |
mbed_official | 121:7f86b4238bec | 419 | /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ |
mbed_official | 121:7f86b4238bec | 420 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0) |
mbed_official | 121:7f86b4238bec | 421 | /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ |
mbed_official | 121:7f86b4238bec | 422 | #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) |
mbed_official | 121:7f86b4238bec | 423 | /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ |
mbed_official | 121:7f86b4238bec | 424 | #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) |
mbed_official | 121:7f86b4238bec | 425 | /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ |
mbed_official | 121:7f86b4238bec | 426 | #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 427 | /* @brief Reset value of the FLEXIO_VERID register */ |
mbed_official | 121:7f86b4238bec | 428 | #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000) |
mbed_official | 121:7f86b4238bec | 429 | /* @brief Reset value of the FLEXIO_PARAM register */ |
mbed_official | 121:7f86b4238bec | 430 | #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404) |
mbed_official | 121:7f86b4238bec | 431 | |
mbed_official | 121:7f86b4238bec | 432 | /* FLASH module features */ |
mbed_official | 121:7f86b4238bec | 433 | |
mbed_official | 121:7f86b4238bec | 434 | #if defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z32VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z32VLH4) || \ |
mbed_official | 121:7f86b4238bec | 435 | defined(CPU_MKL27Z32VMP4) |
mbed_official | 121:7f86b4238bec | 436 | /* @brief Is of type FTFA. */ |
mbed_official | 121:7f86b4238bec | 437 | #define FSL_FEATURE_FLASH_IS_FTFA (1) |
mbed_official | 121:7f86b4238bec | 438 | /* @brief Is of type FTFE. */ |
mbed_official | 121:7f86b4238bec | 439 | #define FSL_FEATURE_FLASH_IS_FTFE (0) |
mbed_official | 121:7f86b4238bec | 440 | /* @brief Is of type FTFL. */ |
mbed_official | 121:7f86b4238bec | 441 | #define FSL_FEATURE_FLASH_IS_FTFL (0) |
mbed_official | 121:7f86b4238bec | 442 | /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ |
mbed_official | 121:7f86b4238bec | 443 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) |
mbed_official | 121:7f86b4238bec | 444 | /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ |
mbed_official | 121:7f86b4238bec | 445 | #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) |
mbed_official | 121:7f86b4238bec | 446 | /* @brief Has EEPROM region protection (register FEPROT). */ |
mbed_official | 121:7f86b4238bec | 447 | #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) |
mbed_official | 121:7f86b4238bec | 448 | /* @brief Has data flash region protection (register FDPROT). */ |
mbed_official | 121:7f86b4238bec | 449 | #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) |
mbed_official | 121:7f86b4238bec | 450 | /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ |
mbed_official | 121:7f86b4238bec | 451 | #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) |
mbed_official | 121:7f86b4238bec | 452 | /* @brief Has flash cache control in FMC module. */ |
mbed_official | 121:7f86b4238bec | 453 | #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) |
mbed_official | 121:7f86b4238bec | 454 | /* @brief Has flash cache control in MCM module. */ |
mbed_official | 121:7f86b4238bec | 455 | #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) |
mbed_official | 121:7f86b4238bec | 456 | /* @brief P-Flash start address. */ |
mbed_official | 121:7f86b4238bec | 457 | #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) |
mbed_official | 121:7f86b4238bec | 458 | /* @brief P-Flash block count. */ |
mbed_official | 121:7f86b4238bec | 459 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) |
mbed_official | 121:7f86b4238bec | 460 | /* @brief P-Flash block size. */ |
mbed_official | 121:7f86b4238bec | 461 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) |
mbed_official | 121:7f86b4238bec | 462 | /* @brief P-Flash sector size. */ |
mbed_official | 121:7f86b4238bec | 463 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) |
mbed_official | 121:7f86b4238bec | 464 | /* @brief P-Flash write unit size. */ |
mbed_official | 121:7f86b4238bec | 465 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) |
mbed_official | 121:7f86b4238bec | 466 | /* @brief P-Flash data path width. */ |
mbed_official | 121:7f86b4238bec | 467 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) |
mbed_official | 121:7f86b4238bec | 468 | /* @brief P-Flash block swap feature. */ |
mbed_official | 121:7f86b4238bec | 469 | #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) |
mbed_official | 121:7f86b4238bec | 470 | /* @brief Has FlexNVM memory. */ |
mbed_official | 121:7f86b4238bec | 471 | #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) |
mbed_official | 121:7f86b4238bec | 472 | /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ |
mbed_official | 121:7f86b4238bec | 473 | #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) |
mbed_official | 121:7f86b4238bec | 474 | /* @brief FlexNVM block count. */ |
mbed_official | 121:7f86b4238bec | 475 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) |
mbed_official | 121:7f86b4238bec | 476 | /* @brief FlexNVM block size. */ |
mbed_official | 121:7f86b4238bec | 477 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) |
mbed_official | 121:7f86b4238bec | 478 | /* @brief FlexNVM sector size. */ |
mbed_official | 121:7f86b4238bec | 479 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) |
mbed_official | 121:7f86b4238bec | 480 | /* @brief FlexNVM write unit size. */ |
mbed_official | 121:7f86b4238bec | 481 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) |
mbed_official | 121:7f86b4238bec | 482 | /* @brief FlexNVM data path width. */ |
mbed_official | 121:7f86b4238bec | 483 | #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 484 | /* @brief Has FlexRAM memory. */ |
mbed_official | 121:7f86b4238bec | 485 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) |
mbed_official | 121:7f86b4238bec | 486 | /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ |
mbed_official | 121:7f86b4238bec | 487 | #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) |
mbed_official | 121:7f86b4238bec | 488 | /* @brief FlexRAM size. */ |
mbed_official | 121:7f86b4238bec | 489 | #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) |
mbed_official | 121:7f86b4238bec | 490 | /* @brief Has 0x00 Read 1s Block command. */ |
mbed_official | 121:7f86b4238bec | 491 | #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) |
mbed_official | 121:7f86b4238bec | 492 | /* @brief Has 0x01 Read 1s Section command. */ |
mbed_official | 121:7f86b4238bec | 493 | #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) |
mbed_official | 121:7f86b4238bec | 494 | /* @brief Has 0x02 Program Check command. */ |
mbed_official | 121:7f86b4238bec | 495 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) |
mbed_official | 121:7f86b4238bec | 496 | /* @brief Has 0x03 Read Resource command. */ |
mbed_official | 121:7f86b4238bec | 497 | #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) |
mbed_official | 121:7f86b4238bec | 498 | /* @brief Has 0x06 Program Longword command. */ |
mbed_official | 121:7f86b4238bec | 499 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) |
mbed_official | 121:7f86b4238bec | 500 | /* @brief Has 0x07 Program Phrase command. */ |
mbed_official | 121:7f86b4238bec | 501 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) |
mbed_official | 121:7f86b4238bec | 502 | /* @brief Has 0x08 Erase Flash Block command. */ |
mbed_official | 121:7f86b4238bec | 503 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) |
mbed_official | 121:7f86b4238bec | 504 | /* @brief Has 0x09 Erase Flash Sector command. */ |
mbed_official | 121:7f86b4238bec | 505 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) |
mbed_official | 121:7f86b4238bec | 506 | /* @brief Has 0x0B Program Section command. */ |
mbed_official | 121:7f86b4238bec | 507 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) |
mbed_official | 121:7f86b4238bec | 508 | /* @brief Has 0x40 Read 1s All Blocks command. */ |
mbed_official | 121:7f86b4238bec | 509 | #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) |
mbed_official | 121:7f86b4238bec | 510 | /* @brief Has 0x41 Read Once command. */ |
mbed_official | 121:7f86b4238bec | 511 | #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) |
mbed_official | 121:7f86b4238bec | 512 | /* @brief Has 0x43 Program Once command. */ |
mbed_official | 121:7f86b4238bec | 513 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) |
mbed_official | 121:7f86b4238bec | 514 | /* @brief Has 0x44 Erase All Blocks command. */ |
mbed_official | 121:7f86b4238bec | 515 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) |
mbed_official | 121:7f86b4238bec | 516 | /* @brief Has 0x45 Verify Backdoor Access Key command. */ |
mbed_official | 121:7f86b4238bec | 517 | #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) |
mbed_official | 121:7f86b4238bec | 518 | /* @brief Has 0x46 Swap Control command. */ |
mbed_official | 121:7f86b4238bec | 519 | #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) |
mbed_official | 121:7f86b4238bec | 520 | /* @brief Has 0x49 Erase All Blocks Unsecure command. */ |
mbed_official | 121:7f86b4238bec | 521 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) |
mbed_official | 121:7f86b4238bec | 522 | /* @brief Has 0x80 Program Partition command. */ |
mbed_official | 121:7f86b4238bec | 523 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) |
mbed_official | 121:7f86b4238bec | 524 | /* @brief Has 0x81 Set FlexRAM Function command. */ |
mbed_official | 121:7f86b4238bec | 525 | #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) |
mbed_official | 121:7f86b4238bec | 526 | /* @brief P-Flash Erase/Read 1st all block command address alignment. */ |
mbed_official | 121:7f86b4238bec | 527 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 528 | /* @brief P-Flash Erase sector command address alignment. */ |
mbed_official | 121:7f86b4238bec | 529 | #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 530 | /* @brief P-Flash Rrogram/Verify section command address alignment. */ |
mbed_official | 121:7f86b4238bec | 531 | #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 532 | /* @brief P-Flash Read resource command address alignment. */ |
mbed_official | 121:7f86b4238bec | 533 | #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 534 | /* @brief P-Flash Program check command address alignment. */ |
mbed_official | 121:7f86b4238bec | 535 | #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 536 | /* @brief P-Flash Program check command address alignment. */ |
mbed_official | 121:7f86b4238bec | 537 | #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 538 | /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ |
mbed_official | 121:7f86b4238bec | 539 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 540 | /* @brief FlexNVM Erase sector command address alignment. */ |
mbed_official | 121:7f86b4238bec | 541 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 542 | /* @brief FlexNVM Rrogram/Verify section command address alignment. */ |
mbed_official | 121:7f86b4238bec | 543 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 544 | /* @brief FlexNVM Read resource command address alignment. */ |
mbed_official | 121:7f86b4238bec | 545 | #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 546 | /* @brief FlexNVM Program check command address alignment. */ |
mbed_official | 121:7f86b4238bec | 547 | #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 548 | /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 549 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 550 | /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 551 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 552 | /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 553 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 554 | /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 555 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 556 | /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 557 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 558 | /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 559 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 560 | /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 561 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 562 | /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 563 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 564 | /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 565 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 566 | /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 567 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 568 | /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 569 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 570 | /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 571 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 572 | /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 573 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 574 | /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 575 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 576 | /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 577 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 578 | /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 579 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 580 | /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 581 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 582 | /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 583 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 584 | /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 585 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 586 | /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 587 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 588 | /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 589 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 590 | /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 591 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 592 | /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 593 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 594 | /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 595 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 596 | /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 597 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 598 | /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 599 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 600 | /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 601 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 602 | /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 603 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 604 | /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 605 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 606 | /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 607 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 608 | /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 609 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 610 | /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 611 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 612 | #elif defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z64VFT4) || defined(CPU_MKL27Z64VLH4) || \ |
mbed_official | 121:7f86b4238bec | 613 | defined(CPU_MKL27Z64VMP4) |
mbed_official | 121:7f86b4238bec | 614 | /* @brief Is of type FTFA. */ |
mbed_official | 121:7f86b4238bec | 615 | #define FSL_FEATURE_FLASH_IS_FTFA (1) |
mbed_official | 121:7f86b4238bec | 616 | /* @brief Is of type FTFE. */ |
mbed_official | 121:7f86b4238bec | 617 | #define FSL_FEATURE_FLASH_IS_FTFE (0) |
mbed_official | 121:7f86b4238bec | 618 | /* @brief Is of type FTFL. */ |
mbed_official | 121:7f86b4238bec | 619 | #define FSL_FEATURE_FLASH_IS_FTFL (0) |
mbed_official | 121:7f86b4238bec | 620 | /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ |
mbed_official | 121:7f86b4238bec | 621 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) |
mbed_official | 121:7f86b4238bec | 622 | /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ |
mbed_official | 121:7f86b4238bec | 623 | #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) |
mbed_official | 121:7f86b4238bec | 624 | /* @brief Has EEPROM region protection (register FEPROT). */ |
mbed_official | 121:7f86b4238bec | 625 | #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) |
mbed_official | 121:7f86b4238bec | 626 | /* @brief Has data flash region protection (register FDPROT). */ |
mbed_official | 121:7f86b4238bec | 627 | #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) |
mbed_official | 121:7f86b4238bec | 628 | /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ |
mbed_official | 121:7f86b4238bec | 629 | #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) |
mbed_official | 121:7f86b4238bec | 630 | /* @brief Has flash cache control in FMC module. */ |
mbed_official | 121:7f86b4238bec | 631 | #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) |
mbed_official | 121:7f86b4238bec | 632 | /* @brief Has flash cache control in MCM module. */ |
mbed_official | 121:7f86b4238bec | 633 | #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) |
mbed_official | 121:7f86b4238bec | 634 | /* @brief P-Flash start address. */ |
mbed_official | 121:7f86b4238bec | 635 | #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) |
mbed_official | 121:7f86b4238bec | 636 | /* @brief P-Flash block count. */ |
mbed_official | 121:7f86b4238bec | 637 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) |
mbed_official | 121:7f86b4238bec | 638 | /* @brief P-Flash block size. */ |
mbed_official | 121:7f86b4238bec | 639 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) |
mbed_official | 121:7f86b4238bec | 640 | /* @brief P-Flash sector size. */ |
mbed_official | 121:7f86b4238bec | 641 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) |
mbed_official | 121:7f86b4238bec | 642 | /* @brief P-Flash write unit size. */ |
mbed_official | 121:7f86b4238bec | 643 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) |
mbed_official | 121:7f86b4238bec | 644 | /* @brief P-Flash data path width. */ |
mbed_official | 121:7f86b4238bec | 645 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) |
mbed_official | 121:7f86b4238bec | 646 | /* @brief P-Flash block swap feature. */ |
mbed_official | 121:7f86b4238bec | 647 | #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) |
mbed_official | 121:7f86b4238bec | 648 | /* @brief Has FlexNVM memory. */ |
mbed_official | 121:7f86b4238bec | 649 | #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) |
mbed_official | 121:7f86b4238bec | 650 | /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ |
mbed_official | 121:7f86b4238bec | 651 | #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) |
mbed_official | 121:7f86b4238bec | 652 | /* @brief FlexNVM block count. */ |
mbed_official | 121:7f86b4238bec | 653 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) |
mbed_official | 121:7f86b4238bec | 654 | /* @brief FlexNVM block size. */ |
mbed_official | 121:7f86b4238bec | 655 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) |
mbed_official | 121:7f86b4238bec | 656 | /* @brief FlexNVM sector size. */ |
mbed_official | 121:7f86b4238bec | 657 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) |
mbed_official | 121:7f86b4238bec | 658 | /* @brief FlexNVM write unit size. */ |
mbed_official | 121:7f86b4238bec | 659 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) |
mbed_official | 121:7f86b4238bec | 660 | /* @brief FlexNVM data path width. */ |
mbed_official | 121:7f86b4238bec | 661 | #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 662 | /* @brief Has FlexRAM memory. */ |
mbed_official | 121:7f86b4238bec | 663 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) |
mbed_official | 121:7f86b4238bec | 664 | /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ |
mbed_official | 121:7f86b4238bec | 665 | #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) |
mbed_official | 121:7f86b4238bec | 666 | /* @brief FlexRAM size. */ |
mbed_official | 121:7f86b4238bec | 667 | #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) |
mbed_official | 121:7f86b4238bec | 668 | /* @brief Has 0x00 Read 1s Block command. */ |
mbed_official | 121:7f86b4238bec | 669 | #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) |
mbed_official | 121:7f86b4238bec | 670 | /* @brief Has 0x01 Read 1s Section command. */ |
mbed_official | 121:7f86b4238bec | 671 | #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) |
mbed_official | 121:7f86b4238bec | 672 | /* @brief Has 0x02 Program Check command. */ |
mbed_official | 121:7f86b4238bec | 673 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) |
mbed_official | 121:7f86b4238bec | 674 | /* @brief Has 0x03 Read Resource command. */ |
mbed_official | 121:7f86b4238bec | 675 | #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) |
mbed_official | 121:7f86b4238bec | 676 | /* @brief Has 0x06 Program Longword command. */ |
mbed_official | 121:7f86b4238bec | 677 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) |
mbed_official | 121:7f86b4238bec | 678 | /* @brief Has 0x07 Program Phrase command. */ |
mbed_official | 121:7f86b4238bec | 679 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) |
mbed_official | 121:7f86b4238bec | 680 | /* @brief Has 0x08 Erase Flash Block command. */ |
mbed_official | 121:7f86b4238bec | 681 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) |
mbed_official | 121:7f86b4238bec | 682 | /* @brief Has 0x09 Erase Flash Sector command. */ |
mbed_official | 121:7f86b4238bec | 683 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) |
mbed_official | 121:7f86b4238bec | 684 | /* @brief Has 0x0B Program Section command. */ |
mbed_official | 121:7f86b4238bec | 685 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) |
mbed_official | 121:7f86b4238bec | 686 | /* @brief Has 0x40 Read 1s All Blocks command. */ |
mbed_official | 121:7f86b4238bec | 687 | #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) |
mbed_official | 121:7f86b4238bec | 688 | /* @brief Has 0x41 Read Once command. */ |
mbed_official | 121:7f86b4238bec | 689 | #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) |
mbed_official | 121:7f86b4238bec | 690 | /* @brief Has 0x43 Program Once command. */ |
mbed_official | 121:7f86b4238bec | 691 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) |
mbed_official | 121:7f86b4238bec | 692 | /* @brief Has 0x44 Erase All Blocks command. */ |
mbed_official | 121:7f86b4238bec | 693 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) |
mbed_official | 121:7f86b4238bec | 694 | /* @brief Has 0x45 Verify Backdoor Access Key command. */ |
mbed_official | 121:7f86b4238bec | 695 | #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) |
mbed_official | 121:7f86b4238bec | 696 | /* @brief Has 0x46 Swap Control command. */ |
mbed_official | 121:7f86b4238bec | 697 | #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) |
mbed_official | 121:7f86b4238bec | 698 | /* @brief Has 0x49 Erase All Blocks Unsecure command. */ |
mbed_official | 121:7f86b4238bec | 699 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) |
mbed_official | 121:7f86b4238bec | 700 | /* @brief Has 0x80 Program Partition command. */ |
mbed_official | 121:7f86b4238bec | 701 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) |
mbed_official | 121:7f86b4238bec | 702 | /* @brief Has 0x81 Set FlexRAM Function command. */ |
mbed_official | 121:7f86b4238bec | 703 | #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) |
mbed_official | 121:7f86b4238bec | 704 | /* @brief P-Flash Erase/Read 1st all block command address alignment. */ |
mbed_official | 121:7f86b4238bec | 705 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 706 | /* @brief P-Flash Erase sector command address alignment. */ |
mbed_official | 121:7f86b4238bec | 707 | #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 708 | /* @brief P-Flash Rrogram/Verify section command address alignment. */ |
mbed_official | 121:7f86b4238bec | 709 | #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 710 | /* @brief P-Flash Read resource command address alignment. */ |
mbed_official | 121:7f86b4238bec | 711 | #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 712 | /* @brief P-Flash Program check command address alignment. */ |
mbed_official | 121:7f86b4238bec | 713 | #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) |
mbed_official | 121:7f86b4238bec | 714 | /* @brief P-Flash Program check command address alignment. */ |
mbed_official | 121:7f86b4238bec | 715 | #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 716 | /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ |
mbed_official | 121:7f86b4238bec | 717 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 718 | /* @brief FlexNVM Erase sector command address alignment. */ |
mbed_official | 121:7f86b4238bec | 719 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 720 | /* @brief FlexNVM Rrogram/Verify section command address alignment. */ |
mbed_official | 121:7f86b4238bec | 721 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 722 | /* @brief FlexNVM Read resource command address alignment. */ |
mbed_official | 121:7f86b4238bec | 723 | #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 724 | /* @brief FlexNVM Program check command address alignment. */ |
mbed_official | 121:7f86b4238bec | 725 | #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) |
mbed_official | 121:7f86b4238bec | 726 | /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 727 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 728 | /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 729 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 730 | /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 731 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 732 | /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 733 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 734 | /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 735 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 736 | /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 737 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 738 | /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 739 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 740 | /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 741 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 742 | /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 743 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 744 | /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 745 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 746 | /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 747 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 748 | /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 749 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 750 | /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 751 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 752 | /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 753 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 754 | /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 755 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 756 | /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 757 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) |
mbed_official | 121:7f86b4238bec | 758 | /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 759 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 760 | /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 761 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 762 | /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 763 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 764 | /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 765 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 766 | /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 767 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 768 | /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 769 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 770 | /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 771 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 772 | /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 773 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 774 | /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 775 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 776 | /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 777 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 778 | /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 779 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 780 | /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 781 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 782 | /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 783 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 784 | /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 785 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 786 | /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 787 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 788 | /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
mbed_official | 121:7f86b4238bec | 789 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) |
mbed_official | 121:7f86b4238bec | 790 | #endif /* defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z32VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z32VLH4) || \ |
mbed_official | 121:7f86b4238bec | 791 | defined(CPU_MKL27Z32VMP4) */ |
mbed_official | 121:7f86b4238bec | 792 | |
mbed_official | 121:7f86b4238bec | 793 | /* GPIO module features */ |
mbed_official | 121:7f86b4238bec | 794 | |
mbed_official | 121:7f86b4238bec | 795 | /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ |
mbed_official | 121:7f86b4238bec | 796 | #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) |
mbed_official | 121:7f86b4238bec | 797 | /* @brief Has port input disable register (PIDR). */ |
mbed_official | 121:7f86b4238bec | 798 | #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) |
mbed_official | 121:7f86b4238bec | 799 | /* @brief Has dedicated interrupt vector. */ |
mbed_official | 121:7f86b4238bec | 800 | #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) |
mbed_official | 121:7f86b4238bec | 801 | |
mbed_official | 121:7f86b4238bec | 802 | /* I2C module features */ |
mbed_official | 121:7f86b4238bec | 803 | |
mbed_official | 121:7f86b4238bec | 804 | /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ |
mbed_official | 121:7f86b4238bec | 805 | #define FSL_FEATURE_I2C_HAS_SMBUS (1) |
mbed_official | 121:7f86b4238bec | 806 | /* @brief Maximum supported baud rate in kilobit per second. */ |
mbed_official | 121:7f86b4238bec | 807 | #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) |
mbed_official | 121:7f86b4238bec | 808 | /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ |
mbed_official | 121:7f86b4238bec | 809 | #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) |
mbed_official | 121:7f86b4238bec | 810 | /* @brief Has DMA support (register bit C1[DMAEN]). */ |
mbed_official | 121:7f86b4238bec | 811 | #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 812 | /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ |
mbed_official | 121:7f86b4238bec | 813 | #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) |
mbed_official | 121:7f86b4238bec | 814 | /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ |
mbed_official | 121:7f86b4238bec | 815 | #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) |
mbed_official | 121:7f86b4238bec | 816 | /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ |
mbed_official | 121:7f86b4238bec | 817 | #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) |
mbed_official | 121:7f86b4238bec | 818 | /* @brief Maximum width of the glitch filter in number of bus clocks. */ |
mbed_official | 121:7f86b4238bec | 819 | #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) |
mbed_official | 121:7f86b4238bec | 820 | /* @brief Has control of the drive capability of the I2C pins. */ |
mbed_official | 121:7f86b4238bec | 821 | #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 822 | /* @brief Has double buffering support (register S2). */ |
mbed_official | 121:7f86b4238bec | 823 | #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) |
mbed_official | 121:7f86b4238bec | 824 | |
mbed_official | 121:7f86b4238bec | 825 | /* LLWU module features */ |
mbed_official | 121:7f86b4238bec | 826 | |
mbed_official | 121:7f86b4238bec | 827 | /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 828 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) |
mbed_official | 121:7f86b4238bec | 829 | /* @brief Has pins 8-15 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 830 | #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) |
mbed_official | 121:7f86b4238bec | 831 | /* @brief Maximum number of internal modules connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 832 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) |
mbed_official | 121:7f86b4238bec | 833 | /* @brief Number of digital filters. */ |
mbed_official | 121:7f86b4238bec | 834 | #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) |
mbed_official | 121:7f86b4238bec | 835 | /* @brief Has MF5 register. */ |
mbed_official | 121:7f86b4238bec | 836 | #define FSL_FEATURE_LLWU_HAS_MF (0) |
mbed_official | 121:7f86b4238bec | 837 | /* @brief Has PF register. */ |
mbed_official | 121:7f86b4238bec | 838 | #define FSL_FEATURE_LLWU_HAS_PF (0) |
mbed_official | 121:7f86b4238bec | 839 | /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ |
mbed_official | 121:7f86b4238bec | 840 | #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) |
mbed_official | 121:7f86b4238bec | 841 | /* @brief Has external pin 0 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 842 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) |
mbed_official | 121:7f86b4238bec | 843 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 844 | #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 845 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 846 | #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 847 | /* @brief Has external pin 1 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 848 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) |
mbed_official | 121:7f86b4238bec | 849 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 850 | #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 851 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 852 | #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 853 | /* @brief Has external pin 2 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 854 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) |
mbed_official | 121:7f86b4238bec | 855 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 856 | #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 857 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 858 | #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 859 | /* @brief Has external pin 3 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 860 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) |
mbed_official | 121:7f86b4238bec | 861 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 862 | #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 863 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 864 | #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 865 | /* @brief Has external pin 4 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 866 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) |
mbed_official | 121:7f86b4238bec | 867 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 868 | #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 869 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 870 | #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 871 | /* @brief Has external pin 5 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 872 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) |
mbed_official | 121:7f86b4238bec | 873 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 874 | #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) |
mbed_official | 121:7f86b4238bec | 875 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 876 | #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 877 | /* @brief Has external pin 6 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 878 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) |
mbed_official | 121:7f86b4238bec | 879 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 880 | #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) |
mbed_official | 121:7f86b4238bec | 881 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 882 | #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) |
mbed_official | 121:7f86b4238bec | 883 | /* @brief Has external pin 7 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 884 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) |
mbed_official | 121:7f86b4238bec | 885 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 886 | #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) |
mbed_official | 121:7f86b4238bec | 887 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 888 | #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) |
mbed_official | 121:7f86b4238bec | 889 | /* @brief Has external pin 8 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 890 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) |
mbed_official | 121:7f86b4238bec | 891 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 892 | #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) |
mbed_official | 121:7f86b4238bec | 893 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 894 | #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) |
mbed_official | 121:7f86b4238bec | 895 | /* @brief Has external pin 9 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 896 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) |
mbed_official | 121:7f86b4238bec | 897 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 898 | #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) |
mbed_official | 121:7f86b4238bec | 899 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 900 | #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) |
mbed_official | 121:7f86b4238bec | 901 | /* @brief Has external pin 10 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 902 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) |
mbed_official | 121:7f86b4238bec | 903 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 904 | #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) |
mbed_official | 121:7f86b4238bec | 905 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 906 | #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) |
mbed_official | 121:7f86b4238bec | 907 | /* @brief Has external pin 11 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 908 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) |
mbed_official | 121:7f86b4238bec | 909 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 910 | #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 911 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 912 | #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 913 | /* @brief Has external pin 12 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 914 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) |
mbed_official | 121:7f86b4238bec | 915 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 916 | #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 917 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 918 | #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 919 | /* @brief Has external pin 13 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 920 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) |
mbed_official | 121:7f86b4238bec | 921 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 922 | #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 923 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 924 | #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 925 | /* @brief Has external pin 14 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 926 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) |
mbed_official | 121:7f86b4238bec | 927 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 928 | #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) |
mbed_official | 121:7f86b4238bec | 929 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 930 | #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) |
mbed_official | 121:7f86b4238bec | 931 | /* @brief Has external pin 15 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 932 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) |
mbed_official | 121:7f86b4238bec | 933 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 934 | #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) |
mbed_official | 121:7f86b4238bec | 935 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 936 | #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) |
mbed_official | 121:7f86b4238bec | 937 | /* @brief Has external pin 16 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 938 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) |
mbed_official | 121:7f86b4238bec | 939 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 940 | #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 941 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 942 | #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 943 | /* @brief Has external pin 17 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 944 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) |
mbed_official | 121:7f86b4238bec | 945 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 946 | #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 947 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 948 | #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 949 | /* @brief Has external pin 18 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 950 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) |
mbed_official | 121:7f86b4238bec | 951 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 952 | #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 953 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 954 | #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 955 | /* @brief Has external pin 19 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 956 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) |
mbed_official | 121:7f86b4238bec | 957 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 958 | #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 959 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 960 | #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 961 | /* @brief Has external pin 20 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 962 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) |
mbed_official | 121:7f86b4238bec | 963 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 964 | #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 965 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 966 | #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 967 | /* @brief Has external pin 21 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 968 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) |
mbed_official | 121:7f86b4238bec | 969 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 970 | #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 971 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 972 | #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 973 | /* @brief Has external pin 22 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 974 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) |
mbed_official | 121:7f86b4238bec | 975 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 976 | #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 977 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 978 | #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 979 | /* @brief Has external pin 23 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 980 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) |
mbed_official | 121:7f86b4238bec | 981 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 982 | #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 983 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 984 | #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 985 | /* @brief Has external pin 24 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 986 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) |
mbed_official | 121:7f86b4238bec | 987 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 988 | #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 989 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 990 | #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 991 | /* @brief Has external pin 25 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 992 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) |
mbed_official | 121:7f86b4238bec | 993 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 994 | #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 995 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 996 | #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 997 | /* @brief Has external pin 26 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 998 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) |
mbed_official | 121:7f86b4238bec | 999 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 1000 | #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 1001 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 1002 | #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 1003 | /* @brief Has external pin 27 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1004 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) |
mbed_official | 121:7f86b4238bec | 1005 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 1006 | #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 1007 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 1008 | #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 1009 | /* @brief Has external pin 28 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1010 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) |
mbed_official | 121:7f86b4238bec | 1011 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 1012 | #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 1013 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 1014 | #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 1015 | /* @brief Has external pin 29 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1016 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) |
mbed_official | 121:7f86b4238bec | 1017 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 1018 | #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 1019 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 1020 | #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 1021 | /* @brief Has external pin 30 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1022 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) |
mbed_official | 121:7f86b4238bec | 1023 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 1024 | #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 1025 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 1026 | #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 1027 | /* @brief Has external pin 31 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1028 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) |
mbed_official | 121:7f86b4238bec | 1029 | /* @brief Index of port of external pin. */ |
mbed_official | 121:7f86b4238bec | 1030 | #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) |
mbed_official | 121:7f86b4238bec | 1031 | /* @brief Number of external pin port on specified port. */ |
mbed_official | 121:7f86b4238bec | 1032 | #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) |
mbed_official | 121:7f86b4238bec | 1033 | /* @brief Has internal module 0 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1034 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) |
mbed_official | 121:7f86b4238bec | 1035 | /* @brief Has internal module 1 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1036 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) |
mbed_official | 121:7f86b4238bec | 1037 | /* @brief Has internal module 2 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1038 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) |
mbed_official | 121:7f86b4238bec | 1039 | /* @brief Has internal module 3 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1040 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) |
mbed_official | 121:7f86b4238bec | 1041 | /* @brief Has internal module 4 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1042 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) |
mbed_official | 121:7f86b4238bec | 1043 | /* @brief Has internal module 5 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1044 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) |
mbed_official | 121:7f86b4238bec | 1045 | /* @brief Has internal module 6 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1046 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) |
mbed_official | 121:7f86b4238bec | 1047 | /* @brief Has internal module 7 connected to LLWU device. */ |
mbed_official | 121:7f86b4238bec | 1048 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) |
mbed_official | 121:7f86b4238bec | 1049 | /* @brief Has Version ID Register (LLWU_VERID). */ |
mbed_official | 121:7f86b4238bec | 1050 | #define FSL_FEATURE_LLWU_HAS_VERID (0) |
mbed_official | 121:7f86b4238bec | 1051 | /* @brief Has Parameter Register (LLWU_PARAM). */ |
mbed_official | 121:7f86b4238bec | 1052 | #define FSL_FEATURE_LLWU_HAS_PARAM (0) |
mbed_official | 121:7f86b4238bec | 1053 | /* @brief Width of registers of the LLWU. */ |
mbed_official | 121:7f86b4238bec | 1054 | #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) |
mbed_official | 121:7f86b4238bec | 1055 | /* @brief Has DMA Enable register (LLWU_DE). */ |
mbed_official | 121:7f86b4238bec | 1056 | #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) |
mbed_official | 121:7f86b4238bec | 1057 | |
mbed_official | 121:7f86b4238bec | 1058 | /* LPTMR module features */ |
mbed_official | 121:7f86b4238bec | 1059 | |
mbed_official | 121:7f86b4238bec | 1060 | /* @brief Has shared interrupt handler with another LPTMR module. */ |
mbed_official | 121:7f86b4238bec | 1061 | #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) |
mbed_official | 121:7f86b4238bec | 1062 | |
mbed_official | 121:7f86b4238bec | 1063 | /* LPUART module features */ |
mbed_official | 121:7f86b4238bec | 1064 | |
mbed_official | 121:7f86b4238bec | 1065 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ |
mbed_official | 121:7f86b4238bec | 1066 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) |
mbed_official | 121:7f86b4238bec | 1067 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1068 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1069 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1070 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
mbed_official | 121:7f86b4238bec | 1071 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
mbed_official | 121:7f86b4238bec | 1072 | #define FSL_FEATURE_LPUART_HAS_FIFO (0) |
mbed_official | 121:7f86b4238bec | 1073 | /* @brief Has 32-bit register MODIR */ |
mbed_official | 121:7f86b4238bec | 1074 | #define FSL_FEATURE_LPUART_HAS_MODIR (0) |
mbed_official | 121:7f86b4238bec | 1075 | /* @brief Hardware flow control (RTS, CTS) is supported. */ |
mbed_official | 121:7f86b4238bec | 1076 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1077 | /* @brief Infrared (modulation) is supported. */ |
mbed_official | 121:7f86b4238bec | 1078 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1079 | /* @brief 2 bits long stop bit is available. */ |
mbed_official | 121:7f86b4238bec | 1080 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1081 | /* @brief Maximal data width without parity bit. */ |
mbed_official | 121:7f86b4238bec | 1082 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1083 | /* @brief Baud rate fine adjustment is available. */ |
mbed_official | 121:7f86b4238bec | 1084 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1085 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1086 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1087 | /* @brief Baud rate oversampling is available. */ |
mbed_official | 121:7f86b4238bec | 1088 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1089 | /* @brief Baud rate oversampling is available. */ |
mbed_official | 121:7f86b4238bec | 1090 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1091 | /* @brief Peripheral type. */ |
mbed_official | 121:7f86b4238bec | 1092 | #define FSL_FEATURE_LPUART_IS_SCI (1) |
mbed_official | 121:7f86b4238bec | 1093 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
mbed_official | 121:7f86b4238bec | 1094 | #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) |
mbed_official | 121:7f86b4238bec | 1095 | /* @brief Maximal data width without parity bit. */ |
mbed_official | 121:7f86b4238bec | 1096 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) |
mbed_official | 121:7f86b4238bec | 1097 | /* @brief Maximal data width with parity bit. */ |
mbed_official | 121:7f86b4238bec | 1098 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) |
mbed_official | 121:7f86b4238bec | 1099 | /* @brief Supports two match addresses to filter incoming frames. */ |
mbed_official | 121:7f86b4238bec | 1100 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) |
mbed_official | 121:7f86b4238bec | 1101 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1102 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) |
mbed_official | 121:7f86b4238bec | 1103 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ |
mbed_official | 121:7f86b4238bec | 1104 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) |
mbed_official | 121:7f86b4238bec | 1105 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1106 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) |
mbed_official | 121:7f86b4238bec | 1107 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ |
mbed_official | 121:7f86b4238bec | 1108 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1109 | /* @brief Has improved smart card (ISO7816 protocol) support. */ |
mbed_official | 121:7f86b4238bec | 1110 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1111 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ |
mbed_official | 121:7f86b4238bec | 1112 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1113 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ |
mbed_official | 121:7f86b4238bec | 1114 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) |
mbed_official | 121:7f86b4238bec | 1115 | /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ |
mbed_official | 121:7f86b4238bec | 1116 | #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0) |
mbed_official | 121:7f86b4238bec | 1117 | /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ |
mbed_official | 121:7f86b4238bec | 1118 | #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) |
mbed_official | 121:7f86b4238bec | 1119 | /* @brief Has separate DMA RX and TX requests. */ |
mbed_official | 121:7f86b4238bec | 1120 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) |
mbed_official | 121:7f86b4238bec | 1121 | /* @brief Has LPAURT_PARAM. */ |
mbed_official | 121:7f86b4238bec | 1122 | #define FSL_FEATURE_LPUART_HAS_PARAM (0) |
mbed_official | 121:7f86b4238bec | 1123 | /* @brief Has LPUART_VERID. */ |
mbed_official | 121:7f86b4238bec | 1124 | #define FSL_FEATURE_LPUART_HAS_VERID (0) |
mbed_official | 121:7f86b4238bec | 1125 | /* @brief Has LPUART_GLOBAL. */ |
mbed_official | 121:7f86b4238bec | 1126 | #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) |
mbed_official | 121:7f86b4238bec | 1127 | /* @brief Has LPUART_PINCFG. */ |
mbed_official | 121:7f86b4238bec | 1128 | #define FSL_FEATURE_LPUART_HAS_PINCFG (0) |
mbed_official | 121:7f86b4238bec | 1129 | |
mbed_official | 121:7f86b4238bec | 1130 | /* MCGLITE module features */ |
mbed_official | 121:7f86b4238bec | 1131 | |
mbed_official | 121:7f86b4238bec | 1132 | /* @brief Defines that clock generator is MCG Lite. */ |
mbed_official | 121:7f86b4238bec | 1133 | #define FSL_FEATURE_MCGLITE_MCGLITE (1) |
mbed_official | 121:7f86b4238bec | 1134 | /* @brief Has Crystal Oscillator Operation Mode Selection. */ |
mbed_official | 121:7f86b4238bec | 1135 | #define FSL_FEATURE_MCGLITE_HAS_HGO0 (1) |
mbed_official | 121:7f86b4238bec | 1136 | /* @brief Has HCTRIM register available. */ |
mbed_official | 121:7f86b4238bec | 1137 | #define FSL_FEATURE_MCGLITE_HAS_HCTRIM (0) |
mbed_official | 121:7f86b4238bec | 1138 | /* @brief Has HTTRIM register available. */ |
mbed_official | 121:7f86b4238bec | 1139 | #define FSL_FEATURE_MCGLITE_HAS_HTTRIM (0) |
mbed_official | 121:7f86b4238bec | 1140 | /* @brief Has HFTRIM register available. */ |
mbed_official | 121:7f86b4238bec | 1141 | #define FSL_FEATURE_MCGLITE_HAS_HFTRIM (0) |
mbed_official | 121:7f86b4238bec | 1142 | /* @brief Has LTRIMRNG register available. */ |
mbed_official | 121:7f86b4238bec | 1143 | #define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (0) |
mbed_official | 121:7f86b4238bec | 1144 | /* @brief Has LFTRIM register available. */ |
mbed_official | 121:7f86b4238bec | 1145 | #define FSL_FEATURE_MCGLITE_HAS_LFTRIM (0) |
mbed_official | 121:7f86b4238bec | 1146 | /* @brief Has LSTRIM register available. */ |
mbed_official | 121:7f86b4238bec | 1147 | #define FSL_FEATURE_MCGLITE_HAS_LSTRIM (0) |
mbed_official | 121:7f86b4238bec | 1148 | /* @brief Has External Clock Source Frequency Range Selection. */ |
mbed_official | 121:7f86b4238bec | 1149 | #define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1) |
mbed_official | 121:7f86b4238bec | 1150 | |
mbed_official | 121:7f86b4238bec | 1151 | /* interrupt module features */ |
mbed_official | 121:7f86b4238bec | 1152 | |
mbed_official | 121:7f86b4238bec | 1153 | /* @brief Lowest interrupt request number. */ |
mbed_official | 121:7f86b4238bec | 1154 | #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) |
mbed_official | 121:7f86b4238bec | 1155 | /* @brief Highest interrupt request number. */ |
mbed_official | 121:7f86b4238bec | 1156 | #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) |
mbed_official | 121:7f86b4238bec | 1157 | |
mbed_official | 121:7f86b4238bec | 1158 | /* OSC module features */ |
mbed_official | 121:7f86b4238bec | 1159 | |
mbed_official | 121:7f86b4238bec | 1160 | /* @brief Has OSC1 external oscillator. */ |
mbed_official | 121:7f86b4238bec | 1161 | #define FSL_FEATURE_OSC_HAS_OSC1 (0) |
mbed_official | 121:7f86b4238bec | 1162 | /* @brief Has OSC0 external oscillator. */ |
mbed_official | 121:7f86b4238bec | 1163 | #define FSL_FEATURE_OSC_HAS_OSC0 (1) |
mbed_official | 121:7f86b4238bec | 1164 | /* @brief Has OSC external oscillator (without index). */ |
mbed_official | 121:7f86b4238bec | 1165 | #define FSL_FEATURE_OSC_HAS_OSC (0) |
mbed_official | 121:7f86b4238bec | 1166 | /* @brief Number of OSC external oscillators. */ |
mbed_official | 121:7f86b4238bec | 1167 | #define FSL_FEATURE_OSC_OSC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 1168 | /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ |
mbed_official | 121:7f86b4238bec | 1169 | #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) |
mbed_official | 121:7f86b4238bec | 1170 | |
mbed_official | 121:7f86b4238bec | 1171 | /* PIT module features */ |
mbed_official | 121:7f86b4238bec | 1172 | |
mbed_official | 121:7f86b4238bec | 1173 | /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ |
mbed_official | 121:7f86b4238bec | 1174 | #define FSL_FEATURE_PIT_TIMER_COUNT (2) |
mbed_official | 121:7f86b4238bec | 1175 | /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ |
mbed_official | 121:7f86b4238bec | 1176 | #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) |
mbed_official | 121:7f86b4238bec | 1177 | /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ |
mbed_official | 121:7f86b4238bec | 1178 | #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) |
mbed_official | 121:7f86b4238bec | 1179 | /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ |
mbed_official | 121:7f86b4238bec | 1180 | #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) |
mbed_official | 121:7f86b4238bec | 1181 | |
mbed_official | 121:7f86b4238bec | 1182 | /* PMC module features */ |
mbed_official | 121:7f86b4238bec | 1183 | |
mbed_official | 121:7f86b4238bec | 1184 | /* @brief Has Bandgap Enable In VLPx Operation support. */ |
mbed_official | 121:7f86b4238bec | 1185 | #define FSL_FEATURE_PMC_HAS_BGEN (1) |
mbed_official | 121:7f86b4238bec | 1186 | /* @brief Has Bandgap Buffer Enable. */ |
mbed_official | 121:7f86b4238bec | 1187 | #define FSL_FEATURE_PMC_HAS_BGBE (1) |
mbed_official | 121:7f86b4238bec | 1188 | /* @brief Has Bandgap Buffer Drive Select. */ |
mbed_official | 121:7f86b4238bec | 1189 | #define FSL_FEATURE_PMC_HAS_BGBDS (0) |
mbed_official | 121:7f86b4238bec | 1190 | /* @brief Has Low-Voltage Detect Voltage Select support. */ |
mbed_official | 121:7f86b4238bec | 1191 | #define FSL_FEATURE_PMC_HAS_LVDV (1) |
mbed_official | 121:7f86b4238bec | 1192 | /* @brief Has Low-Voltage Warning Voltage Select support. */ |
mbed_official | 121:7f86b4238bec | 1193 | #define FSL_FEATURE_PMC_HAS_LVWV (1) |
mbed_official | 121:7f86b4238bec | 1194 | /* @brief Has LPO. */ |
mbed_official | 121:7f86b4238bec | 1195 | #define FSL_FEATURE_PMC_HAS_LPO (0) |
mbed_official | 121:7f86b4238bec | 1196 | /* @brief Has VLPx option PMC_REGSC[VLPO]. */ |
mbed_official | 121:7f86b4238bec | 1197 | #define FSL_FEATURE_PMC_HAS_VLPO (1) |
mbed_official | 121:7f86b4238bec | 1198 | /* @brief Has acknowledge isolation support. */ |
mbed_official | 121:7f86b4238bec | 1199 | #define FSL_FEATURE_PMC_HAS_ACKISO (1) |
mbed_official | 121:7f86b4238bec | 1200 | /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ |
mbed_official | 121:7f86b4238bec | 1201 | #define FSL_FEATURE_PMC_HAS_REGFPM (0) |
mbed_official | 121:7f86b4238bec | 1202 | /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ |
mbed_official | 121:7f86b4238bec | 1203 | #define FSL_FEATURE_PMC_HAS_REGONS (1) |
mbed_official | 121:7f86b4238bec | 1204 | /* @brief Has PMC_HVDSC1. */ |
mbed_official | 121:7f86b4238bec | 1205 | #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) |
mbed_official | 121:7f86b4238bec | 1206 | /* @brief Has PMC_PARAM. */ |
mbed_official | 121:7f86b4238bec | 1207 | #define FSL_FEATURE_PMC_HAS_PARAM (0) |
mbed_official | 121:7f86b4238bec | 1208 | /* @brief Has PMC_VERID. */ |
mbed_official | 121:7f86b4238bec | 1209 | #define FSL_FEATURE_PMC_HAS_VERID (0) |
mbed_official | 121:7f86b4238bec | 1210 | |
mbed_official | 121:7f86b4238bec | 1211 | /* PORT module features */ |
mbed_official | 121:7f86b4238bec | 1212 | |
mbed_official | 121:7f86b4238bec | 1213 | /* @brief Has control lock (register bit PCR[LK]). */ |
mbed_official | 121:7f86b4238bec | 1214 | #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) |
mbed_official | 121:7f86b4238bec | 1215 | /* @brief Has open drain control (register bit PCR[ODE]). */ |
mbed_official | 121:7f86b4238bec | 1216 | #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) |
mbed_official | 121:7f86b4238bec | 1217 | /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ |
mbed_official | 121:7f86b4238bec | 1218 | #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) |
mbed_official | 121:7f86b4238bec | 1219 | /* @brief Has DMA request (register bit field PCR[IRQC] values). */ |
mbed_official | 121:7f86b4238bec | 1220 | #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) |
mbed_official | 121:7f86b4238bec | 1221 | /* @brief Has pull resistor selection available. */ |
mbed_official | 121:7f86b4238bec | 1222 | #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1223 | /* @brief Has pull resistor enable (register bit PCR[PE]). */ |
mbed_official | 121:7f86b4238bec | 1224 | #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) |
mbed_official | 121:7f86b4238bec | 1225 | /* @brief Has slew rate control (register bit PCR[SRE]). */ |
mbed_official | 121:7f86b4238bec | 1226 | #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) |
mbed_official | 121:7f86b4238bec | 1227 | /* @brief Has passive filter (register bit field PCR[PFE]). */ |
mbed_official | 121:7f86b4238bec | 1228 | #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) |
mbed_official | 121:7f86b4238bec | 1229 | /* @brief Has drive strength control (register bit PCR[DSE]). */ |
mbed_official | 121:7f86b4238bec | 1230 | #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) |
mbed_official | 121:7f86b4238bec | 1231 | /* @brief Has separate drive strength register (HDRVE). */ |
mbed_official | 121:7f86b4238bec | 1232 | #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) |
mbed_official | 121:7f86b4238bec | 1233 | /* @brief Has glitch filter (register IOFLT). */ |
mbed_official | 121:7f86b4238bec | 1234 | #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) |
mbed_official | 121:7f86b4238bec | 1235 | /* @brief Defines width of PCR[MUX] field. */ |
mbed_official | 121:7f86b4238bec | 1236 | #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) |
mbed_official | 121:7f86b4238bec | 1237 | /* @brief Has dedicated interrupt vector. */ |
mbed_official | 121:7f86b4238bec | 1238 | #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) |
mbed_official | 121:7f86b4238bec | 1239 | /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ |
mbed_official | 121:7f86b4238bec | 1240 | #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) |
mbed_official | 121:7f86b4238bec | 1241 | /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ |
mbed_official | 121:7f86b4238bec | 1242 | #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) |
mbed_official | 121:7f86b4238bec | 1243 | |
mbed_official | 121:7f86b4238bec | 1244 | /* RCM module features */ |
mbed_official | 121:7f86b4238bec | 1245 | |
mbed_official | 121:7f86b4238bec | 1246 | /* @brief Has Loss-of-Lock Reset support. */ |
mbed_official | 121:7f86b4238bec | 1247 | #define FSL_FEATURE_RCM_HAS_LOL (0) |
mbed_official | 121:7f86b4238bec | 1248 | /* @brief Has Loss-of-Clock Reset support. */ |
mbed_official | 121:7f86b4238bec | 1249 | #define FSL_FEATURE_RCM_HAS_LOC (0) |
mbed_official | 121:7f86b4238bec | 1250 | /* @brief Has JTAG generated Reset support. */ |
mbed_official | 121:7f86b4238bec | 1251 | #define FSL_FEATURE_RCM_HAS_JTAG (0) |
mbed_official | 121:7f86b4238bec | 1252 | /* @brief Has EzPort generated Reset support. */ |
mbed_official | 121:7f86b4238bec | 1253 | #define FSL_FEATURE_RCM_HAS_EZPORT (0) |
mbed_official | 121:7f86b4238bec | 1254 | /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ |
mbed_official | 121:7f86b4238bec | 1255 | #define FSL_FEATURE_RCM_HAS_EZPMS (0) |
mbed_official | 121:7f86b4238bec | 1256 | /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ |
mbed_official | 121:7f86b4238bec | 1257 | #define FSL_FEATURE_RCM_HAS_BOOTROM (1) |
mbed_official | 121:7f86b4238bec | 1258 | /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ |
mbed_official | 121:7f86b4238bec | 1259 | #define FSL_FEATURE_RCM_HAS_SSRS (1) |
mbed_official | 121:7f86b4238bec | 1260 | /* @brief Has Version ID Register (RCM_VERID). */ |
mbed_official | 121:7f86b4238bec | 1261 | #define FSL_FEATURE_RCM_HAS_VERID (0) |
mbed_official | 121:7f86b4238bec | 1262 | /* @brief Has Parameter Register (RCM_PARAM). */ |
mbed_official | 121:7f86b4238bec | 1263 | #define FSL_FEATURE_RCM_HAS_PARAM (0) |
mbed_official | 121:7f86b4238bec | 1264 | /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ |
mbed_official | 121:7f86b4238bec | 1265 | #define FSL_FEATURE_RCM_HAS_SRIE (0) |
mbed_official | 121:7f86b4238bec | 1266 | /* @brief Width of registers of the RCM. */ |
mbed_official | 121:7f86b4238bec | 1267 | #define FSL_FEATURE_RCM_REG_WIDTH (8) |
mbed_official | 121:7f86b4238bec | 1268 | /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ |
mbed_official | 121:7f86b4238bec | 1269 | #define FSL_FEATURE_RCM_HAS_CORE1 (0) |
mbed_official | 121:7f86b4238bec | 1270 | /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ |
mbed_official | 121:7f86b4238bec | 1271 | #define FSL_FEATURE_RCM_HAS_MDM_AP (1) |
mbed_official | 121:7f86b4238bec | 1272 | /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ |
mbed_official | 121:7f86b4238bec | 1273 | #define FSL_FEATURE_RCM_HAS_WAKEUP (1) |
mbed_official | 121:7f86b4238bec | 1274 | |
mbed_official | 121:7f86b4238bec | 1275 | /* RTC module features */ |
mbed_official | 121:7f86b4238bec | 1276 | |
mbed_official | 121:7f86b4238bec | 1277 | /* @brief Has wakeup pin. */ |
mbed_official | 121:7f86b4238bec | 1278 | #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) |
mbed_official | 121:7f86b4238bec | 1279 | /* @brief Has wakeup pin selection (bit field CR[WPS]). */ |
mbed_official | 121:7f86b4238bec | 1280 | #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1281 | /* @brief Has low power features (registers MER, MCLR and MCHR). */ |
mbed_official | 121:7f86b4238bec | 1282 | #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) |
mbed_official | 121:7f86b4238bec | 1283 | /* @brief Has read/write access control (registers WAR and RAR). */ |
mbed_official | 121:7f86b4238bec | 1284 | #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) |
mbed_official | 121:7f86b4238bec | 1285 | /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ |
mbed_official | 121:7f86b4238bec | 1286 | #define FSL_FEATURE_RTC_HAS_SECURITY (0) |
mbed_official | 121:7f86b4238bec | 1287 | /* @brief Has RTC_CLKIN available. */ |
mbed_official | 121:7f86b4238bec | 1288 | #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) |
mbed_official | 121:7f86b4238bec | 1289 | /* @brief Has prescaler adjust for LPO. */ |
mbed_official | 121:7f86b4238bec | 1290 | #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) |
mbed_official | 121:7f86b4238bec | 1291 | /* @brief Has Clock Pin Enable field. */ |
mbed_official | 121:7f86b4238bec | 1292 | #define FSL_FEATURE_RTC_HAS_CPE (0) |
mbed_official | 121:7f86b4238bec | 1293 | /* @brief Has Timer Seconds Interrupt Configuration field. */ |
mbed_official | 121:7f86b4238bec | 1294 | #define FSL_FEATURE_RTC_HAS_TSIC (0) |
mbed_official | 121:7f86b4238bec | 1295 | /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ |
mbed_official | 121:7f86b4238bec | 1296 | #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) |
mbed_official | 121:7f86b4238bec | 1297 | |
mbed_official | 121:7f86b4238bec | 1298 | /* SIM module features */ |
mbed_official | 121:7f86b4238bec | 1299 | |
mbed_official | 121:7f86b4238bec | 1300 | /* @brief Has USB FS divider. */ |
mbed_official | 121:7f86b4238bec | 1301 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
mbed_official | 121:7f86b4238bec | 1302 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
mbed_official | 121:7f86b4238bec | 1303 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
mbed_official | 121:7f86b4238bec | 1304 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
mbed_official | 121:7f86b4238bec | 1305 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
mbed_official | 121:7f86b4238bec | 1306 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
mbed_official | 121:7f86b4238bec | 1307 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
mbed_official | 121:7f86b4238bec | 1308 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
mbed_official | 121:7f86b4238bec | 1309 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1310 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
mbed_official | 121:7f86b4238bec | 1311 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
mbed_official | 121:7f86b4238bec | 1312 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
mbed_official | 121:7f86b4238bec | 1313 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1314 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
mbed_official | 121:7f86b4238bec | 1315 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
mbed_official | 121:7f86b4238bec | 1316 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
mbed_official | 121:7f86b4238bec | 1317 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
mbed_official | 121:7f86b4238bec | 1318 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
mbed_official | 121:7f86b4238bec | 1319 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
mbed_official | 121:7f86b4238bec | 1320 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
mbed_official | 121:7f86b4238bec | 1321 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
mbed_official | 121:7f86b4238bec | 1322 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
mbed_official | 121:7f86b4238bec | 1323 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
mbed_official | 121:7f86b4238bec | 1324 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
mbed_official | 121:7f86b4238bec | 1325 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
mbed_official | 121:7f86b4238bec | 1326 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
mbed_official | 121:7f86b4238bec | 1327 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) |
mbed_official | 121:7f86b4238bec | 1328 | /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ |
mbed_official | 121:7f86b4238bec | 1329 | #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2) |
mbed_official | 121:7f86b4238bec | 1330 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
mbed_official | 121:7f86b4238bec | 1331 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) |
mbed_official | 121:7f86b4238bec | 1332 | /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ |
mbed_official | 121:7f86b4238bec | 1333 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) |
mbed_official | 121:7f86b4238bec | 1334 | /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ |
mbed_official | 121:7f86b4238bec | 1335 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) |
mbed_official | 121:7f86b4238bec | 1336 | /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ |
mbed_official | 121:7f86b4238bec | 1337 | #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) |
mbed_official | 121:7f86b4238bec | 1338 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
mbed_official | 121:7f86b4238bec | 1339 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) |
mbed_official | 121:7f86b4238bec | 1340 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
mbed_official | 121:7f86b4238bec | 1341 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) |
mbed_official | 121:7f86b4238bec | 1342 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
mbed_official | 121:7f86b4238bec | 1343 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
mbed_official | 121:7f86b4238bec | 1344 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1345 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) |
mbed_official | 121:7f86b4238bec | 1346 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1347 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
mbed_official | 121:7f86b4238bec | 1348 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1349 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) |
mbed_official | 121:7f86b4238bec | 1350 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1351 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) |
mbed_official | 121:7f86b4238bec | 1352 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1353 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) |
mbed_official | 121:7f86b4238bec | 1354 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1355 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 1356 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1357 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) |
mbed_official | 121:7f86b4238bec | 1358 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1359 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 1360 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1361 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) |
mbed_official | 121:7f86b4238bec | 1362 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1363 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) |
mbed_official | 121:7f86b4238bec | 1364 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
mbed_official | 121:7f86b4238bec | 1365 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 1366 | /* @brief Has FTM module(s) configuration. */ |
mbed_official | 121:7f86b4238bec | 1367 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
mbed_official | 121:7f86b4238bec | 1368 | /* @brief Number of FTM modules. */ |
mbed_official | 121:7f86b4238bec | 1369 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
mbed_official | 121:7f86b4238bec | 1370 | /* @brief Number of FTM triggers with selectable source. */ |
mbed_official | 121:7f86b4238bec | 1371 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
mbed_official | 121:7f86b4238bec | 1372 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
mbed_official | 121:7f86b4238bec | 1373 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
mbed_official | 121:7f86b4238bec | 1374 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
mbed_official | 121:7f86b4238bec | 1375 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
mbed_official | 121:7f86b4238bec | 1376 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1377 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
mbed_official | 121:7f86b4238bec | 1378 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1379 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
mbed_official | 121:7f86b4238bec | 1380 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1381 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
mbed_official | 121:7f86b4238bec | 1382 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
mbed_official | 121:7f86b4238bec | 1383 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
mbed_official | 121:7f86b4238bec | 1384 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
mbed_official | 121:7f86b4238bec | 1385 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 1386 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
mbed_official | 121:7f86b4238bec | 1387 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 1388 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
mbed_official | 121:7f86b4238bec | 1389 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 1390 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
mbed_official | 121:7f86b4238bec | 1391 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
mbed_official | 121:7f86b4238bec | 1392 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
mbed_official | 121:7f86b4238bec | 1393 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
mbed_official | 121:7f86b4238bec | 1394 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
mbed_official | 121:7f86b4238bec | 1395 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
mbed_official | 121:7f86b4238bec | 1396 | /* @brief Has TPM module(s) configuration. */ |
mbed_official | 121:7f86b4238bec | 1397 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
mbed_official | 121:7f86b4238bec | 1398 | /* @brief The highest TPM module index. */ |
mbed_official | 121:7f86b4238bec | 1399 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) |
mbed_official | 121:7f86b4238bec | 1400 | /* @brief Has TPM module with index 0. */ |
mbed_official | 121:7f86b4238bec | 1401 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
mbed_official | 121:7f86b4238bec | 1402 | /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ |
mbed_official | 121:7f86b4238bec | 1403 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) |
mbed_official | 121:7f86b4238bec | 1404 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
mbed_official | 121:7f86b4238bec | 1405 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) |
mbed_official | 121:7f86b4238bec | 1406 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1407 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1408 | /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ |
mbed_official | 121:7f86b4238bec | 1409 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) |
mbed_official | 121:7f86b4238bec | 1410 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1411 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) |
mbed_official | 121:7f86b4238bec | 1412 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1413 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1414 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
mbed_official | 121:7f86b4238bec | 1415 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) |
mbed_official | 121:7f86b4238bec | 1416 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
mbed_official | 121:7f86b4238bec | 1417 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
mbed_official | 121:7f86b4238bec | 1418 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
mbed_official | 121:7f86b4238bec | 1419 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
mbed_official | 121:7f86b4238bec | 1420 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
mbed_official | 121:7f86b4238bec | 1421 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
mbed_official | 121:7f86b4238bec | 1422 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
mbed_official | 121:7f86b4238bec | 1423 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
mbed_official | 121:7f86b4238bec | 1424 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
mbed_official | 121:7f86b4238bec | 1425 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
mbed_official | 121:7f86b4238bec | 1426 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
mbed_official | 121:7f86b4238bec | 1427 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
mbed_official | 121:7f86b4238bec | 1428 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
mbed_official | 121:7f86b4238bec | 1429 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
mbed_official | 121:7f86b4238bec | 1430 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
mbed_official | 121:7f86b4238bec | 1431 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
mbed_official | 121:7f86b4238bec | 1432 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
mbed_official | 121:7f86b4238bec | 1433 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
mbed_official | 121:7f86b4238bec | 1434 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
mbed_official | 121:7f86b4238bec | 1435 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
mbed_official | 121:7f86b4238bec | 1436 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
mbed_official | 121:7f86b4238bec | 1437 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
mbed_official | 121:7f86b4238bec | 1438 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
mbed_official | 121:7f86b4238bec | 1439 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
mbed_official | 121:7f86b4238bec | 1440 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1441 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) |
mbed_official | 121:7f86b4238bec | 1442 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
mbed_official | 121:7f86b4238bec | 1443 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) |
mbed_official | 121:7f86b4238bec | 1444 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
mbed_official | 121:7f86b4238bec | 1445 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) |
mbed_official | 121:7f86b4238bec | 1446 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
mbed_official | 121:7f86b4238bec | 1447 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
mbed_official | 121:7f86b4238bec | 1448 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
mbed_official | 121:7f86b4238bec | 1449 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
mbed_official | 121:7f86b4238bec | 1450 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
mbed_official | 121:7f86b4238bec | 1451 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
mbed_official | 121:7f86b4238bec | 1452 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
mbed_official | 121:7f86b4238bec | 1453 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
mbed_official | 121:7f86b4238bec | 1454 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
mbed_official | 121:7f86b4238bec | 1455 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
mbed_official | 121:7f86b4238bec | 1456 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
mbed_official | 121:7f86b4238bec | 1457 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
mbed_official | 121:7f86b4238bec | 1458 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
mbed_official | 121:7f86b4238bec | 1459 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
mbed_official | 121:7f86b4238bec | 1460 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
mbed_official | 121:7f86b4238bec | 1461 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
mbed_official | 121:7f86b4238bec | 1462 | /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ |
mbed_official | 121:7f86b4238bec | 1463 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) |
mbed_official | 121:7f86b4238bec | 1464 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1465 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
mbed_official | 121:7f86b4238bec | 1466 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1467 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
mbed_official | 121:7f86b4238bec | 1468 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1469 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
mbed_official | 121:7f86b4238bec | 1470 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1471 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
mbed_official | 121:7f86b4238bec | 1472 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1473 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
mbed_official | 121:7f86b4238bec | 1474 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1475 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
mbed_official | 121:7f86b4238bec | 1476 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
mbed_official | 121:7f86b4238bec | 1477 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
mbed_official | 121:7f86b4238bec | 1478 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
mbed_official | 121:7f86b4238bec | 1479 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
mbed_official | 121:7f86b4238bec | 1480 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
mbed_official | 121:7f86b4238bec | 1481 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
mbed_official | 121:7f86b4238bec | 1482 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
mbed_official | 121:7f86b4238bec | 1483 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
mbed_official | 121:7f86b4238bec | 1484 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
mbed_official | 121:7f86b4238bec | 1485 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
mbed_official | 121:7f86b4238bec | 1486 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
mbed_official | 121:7f86b4238bec | 1487 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) |
mbed_official | 121:7f86b4238bec | 1488 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
mbed_official | 121:7f86b4238bec | 1489 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
mbed_official | 121:7f86b4238bec | 1490 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
mbed_official | 121:7f86b4238bec | 1491 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
mbed_official | 121:7f86b4238bec | 1492 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
mbed_official | 121:7f86b4238bec | 1493 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
mbed_official | 121:7f86b4238bec | 1494 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
mbed_official | 121:7f86b4238bec | 1495 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
mbed_official | 121:7f86b4238bec | 1496 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
mbed_official | 121:7f86b4238bec | 1497 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
mbed_official | 121:7f86b4238bec | 1498 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
mbed_official | 121:7f86b4238bec | 1499 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
mbed_official | 121:7f86b4238bec | 1500 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
mbed_official | 121:7f86b4238bec | 1501 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
mbed_official | 121:7f86b4238bec | 1502 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
mbed_official | 121:7f86b4238bec | 1503 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
mbed_official | 121:7f86b4238bec | 1504 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
mbed_official | 121:7f86b4238bec | 1505 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
mbed_official | 121:7f86b4238bec | 1506 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
mbed_official | 121:7f86b4238bec | 1507 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
mbed_official | 121:7f86b4238bec | 1508 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
mbed_official | 121:7f86b4238bec | 1509 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
mbed_official | 121:7f86b4238bec | 1510 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
mbed_official | 121:7f86b4238bec | 1511 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
mbed_official | 121:7f86b4238bec | 1512 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
mbed_official | 121:7f86b4238bec | 1513 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
mbed_official | 121:7f86b4238bec | 1514 | /* @brief Has miscellanious control register (register MCR). */ |
mbed_official | 121:7f86b4238bec | 1515 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
mbed_official | 121:7f86b4238bec | 1516 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
mbed_official | 121:7f86b4238bec | 1517 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
mbed_official | 121:7f86b4238bec | 1518 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
mbed_official | 121:7f86b4238bec | 1519 | #define FSL_FEATURE_SIM_HAS_COP_STOP (1) |
mbed_official | 121:7f86b4238bec | 1520 | /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ |
mbed_official | 121:7f86b4238bec | 1521 | #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) |
mbed_official | 121:7f86b4238bec | 1522 | |
mbed_official | 121:7f86b4238bec | 1523 | /* SMC module features */ |
mbed_official | 121:7f86b4238bec | 1524 | |
mbed_official | 121:7f86b4238bec | 1525 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
mbed_official | 121:7f86b4238bec | 1526 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
mbed_official | 121:7f86b4238bec | 1527 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
mbed_official | 121:7f86b4238bec | 1528 | #define FSL_FEATURE_SMC_HAS_LPOPO (1) |
mbed_official | 121:7f86b4238bec | 1529 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
mbed_official | 121:7f86b4238bec | 1530 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
mbed_official | 121:7f86b4238bec | 1531 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
mbed_official | 121:7f86b4238bec | 1532 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
mbed_official | 121:7f86b4238bec | 1533 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
mbed_official | 121:7f86b4238bec | 1534 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) |
mbed_official | 121:7f86b4238bec | 1535 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
mbed_official | 121:7f86b4238bec | 1536 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
mbed_official | 121:7f86b4238bec | 1537 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
mbed_official | 121:7f86b4238bec | 1538 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) |
mbed_official | 121:7f86b4238bec | 1539 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
mbed_official | 121:7f86b4238bec | 1540 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
mbed_official | 121:7f86b4238bec | 1541 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
mbed_official | 121:7f86b4238bec | 1542 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) |
mbed_official | 121:7f86b4238bec | 1543 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
mbed_official | 121:7f86b4238bec | 1544 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
mbed_official | 121:7f86b4238bec | 1545 | /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ |
mbed_official | 121:7f86b4238bec | 1546 | #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) |
mbed_official | 121:7f86b4238bec | 1547 | /* @brief Has stop submode. */ |
mbed_official | 121:7f86b4238bec | 1548 | #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) |
mbed_official | 121:7f86b4238bec | 1549 | /* @brief Has stop submode 0(VLLS0). */ |
mbed_official | 121:7f86b4238bec | 1550 | #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) |
mbed_official | 121:7f86b4238bec | 1551 | /* @brief Has stop submode 2(VLLS2). */ |
mbed_official | 121:7f86b4238bec | 1552 | #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) |
mbed_official | 121:7f86b4238bec | 1553 | /* @brief Has SMC_PARAM. */ |
mbed_official | 121:7f86b4238bec | 1554 | #define FSL_FEATURE_SMC_HAS_PARAM (0) |
mbed_official | 121:7f86b4238bec | 1555 | /* @brief Has SMC_VERID. */ |
mbed_official | 121:7f86b4238bec | 1556 | #define FSL_FEATURE_SMC_HAS_VERID (0) |
mbed_official | 121:7f86b4238bec | 1557 | |
mbed_official | 121:7f86b4238bec | 1558 | /* SPI module features */ |
mbed_official | 121:7f86b4238bec | 1559 | |
mbed_official | 121:7f86b4238bec | 1560 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
mbed_official | 121:7f86b4238bec | 1561 | #define FSL_FEATURE_SPI_HAS_FIFO (1) |
mbed_official | 121:7f86b4238bec | 1562 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ |
mbed_official | 121:7f86b4238bec | 1563 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1564 | /* @brief Has separate DMA RX and TX requests. */ |
mbed_official | 121:7f86b4238bec | 1565 | #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) |
mbed_official | 121:7f86b4238bec | 1566 | /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ |
mbed_official | 121:7f86b4238bec | 1567 | #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ |
mbed_official | 121:7f86b4238bec | 1568 | ((x) == SPI0 ? (0) : \ |
mbed_official | 121:7f86b4238bec | 1569 | ((x) == SPI1 ? (4) : (-1))) |
mbed_official | 121:7f86b4238bec | 1570 | /* @brief Maximum transfer data width in bits. */ |
mbed_official | 121:7f86b4238bec | 1571 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
mbed_official | 121:7f86b4238bec | 1572 | /* @brief The data register name has postfix (L as low and H as high). */ |
mbed_official | 121:7f86b4238bec | 1573 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) |
mbed_official | 121:7f86b4238bec | 1574 | /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ |
mbed_official | 121:7f86b4238bec | 1575 | #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) |
mbed_official | 121:7f86b4238bec | 1576 | /* @brief Has 16-bit data transfer support. */ |
mbed_official | 121:7f86b4238bec | 1577 | #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) |
mbed_official | 121:7f86b4238bec | 1578 | |
mbed_official | 121:7f86b4238bec | 1579 | /* SysTick module features */ |
mbed_official | 121:7f86b4238bec | 1580 | |
mbed_official | 121:7f86b4238bec | 1581 | /* @brief Systick has external reference clock. */ |
mbed_official | 121:7f86b4238bec | 1582 | #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) |
mbed_official | 121:7f86b4238bec | 1583 | /* @brief Systick external reference clock is core clock divided by this value. */ |
mbed_official | 121:7f86b4238bec | 1584 | #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) |
mbed_official | 121:7f86b4238bec | 1585 | |
mbed_official | 121:7f86b4238bec | 1586 | /* TPM module features */ |
mbed_official | 121:7f86b4238bec | 1587 | |
mbed_official | 121:7f86b4238bec | 1588 | /* @brief Bus clock is the source clock for the module. */ |
mbed_official | 121:7f86b4238bec | 1589 | #define FSL_FEATURE_TPM_BUS_CLOCK (0) |
mbed_official | 121:7f86b4238bec | 1590 | /* @brief Number of channels. */ |
mbed_official | 121:7f86b4238bec | 1591 | #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ |
mbed_official | 121:7f86b4238bec | 1592 | ((x) == TPM0 ? (6) : \ |
mbed_official | 121:7f86b4238bec | 1593 | ((x) == TPM1 ? (2) : \ |
mbed_official | 121:7f86b4238bec | 1594 | ((x) == TPM2 ? (2) : (-1)))) |
mbed_official | 121:7f86b4238bec | 1595 | /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ |
mbed_official | 121:7f86b4238bec | 1596 | #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) |
mbed_official | 121:7f86b4238bec | 1597 | /* @brief Has TPM_PARAM. */ |
mbed_official | 121:7f86b4238bec | 1598 | #define FSL_FEATURE_TPM_HAS_PARAM (0) |
mbed_official | 121:7f86b4238bec | 1599 | /* @brief Has TPM_VERID. */ |
mbed_official | 121:7f86b4238bec | 1600 | #define FSL_FEATURE_TPM_HAS_VERID (0) |
mbed_official | 121:7f86b4238bec | 1601 | /* @brief Has TPM_GLOBAL. */ |
mbed_official | 121:7f86b4238bec | 1602 | #define FSL_FEATURE_TPM_HAS_GLOBAL (0) |
mbed_official | 121:7f86b4238bec | 1603 | /* @brief Has TPM_TRIG. */ |
mbed_official | 121:7f86b4238bec | 1604 | #define FSL_FEATURE_TPM_HAS_TRIG (0) |
mbed_official | 121:7f86b4238bec | 1605 | /* @brief Has counter pause on trigger. */ |
mbed_official | 121:7f86b4238bec | 1606 | #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) |
mbed_official | 121:7f86b4238bec | 1607 | /* @brief Has external trigger selection. */ |
mbed_official | 121:7f86b4238bec | 1608 | #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) |
mbed_official | 121:7f86b4238bec | 1609 | /* @brief Has TPM_COMBINE. */ |
mbed_official | 121:7f86b4238bec | 1610 | #define FSL_FEATURE_TPM_HAS_COMBINE (0) |
mbed_official | 121:7f86b4238bec | 1611 | /* @brief Has TPM_FILTER. */ |
mbed_official | 121:7f86b4238bec | 1612 | #define FSL_FEATURE_TPM_HAS_FILTER (0) |
mbed_official | 121:7f86b4238bec | 1613 | /* @brief Has TPM_QDCTRL. */ |
mbed_official | 121:7f86b4238bec | 1614 | #define FSL_FEATURE_TPM_HAS_QDCTRL (0) |
mbed_official | 121:7f86b4238bec | 1615 | |
mbed_official | 121:7f86b4238bec | 1616 | /* UART module features */ |
mbed_official | 121:7f86b4238bec | 1617 | |
mbed_official | 121:7f86b4238bec | 1618 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ |
mbed_official | 121:7f86b4238bec | 1619 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) |
mbed_official | 121:7f86b4238bec | 1620 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1621 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1622 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1623 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) |
mbed_official | 121:7f86b4238bec | 1624 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
mbed_official | 121:7f86b4238bec | 1625 | #define FSL_FEATURE_UART_HAS_FIFO (0) |
mbed_official | 121:7f86b4238bec | 1626 | /* @brief Hardware flow control (RTS, CTS) is supported. */ |
mbed_official | 121:7f86b4238bec | 1627 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1628 | /* @brief Infrared (modulation) is supported. */ |
mbed_official | 121:7f86b4238bec | 1629 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1630 | /* @brief 2 bits long stop bit is available. */ |
mbed_official | 121:7f86b4238bec | 1631 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1632 | /* @brief Maximal data width without parity bit. */ |
mbed_official | 121:7f86b4238bec | 1633 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1634 | /* @brief Baud rate fine adjustment is available. */ |
mbed_official | 121:7f86b4238bec | 1635 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1636 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1637 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1638 | /* @brief Baud rate oversampling is available. */ |
mbed_official | 121:7f86b4238bec | 1639 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1640 | /* @brief Baud rate oversampling is available. */ |
mbed_official | 121:7f86b4238bec | 1641 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1642 | /* @brief Peripheral type. */ |
mbed_official | 121:7f86b4238bec | 1643 | #define FSL_FEATURE_UART_IS_SCI (0) |
mbed_official | 121:7f86b4238bec | 1644 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
mbed_official | 121:7f86b4238bec | 1645 | #define FSL_FEATURE_UART_FIFO_SIZEn(x) (0) |
mbed_official | 121:7f86b4238bec | 1646 | /* @brief Maximal data width without parity bit. */ |
mbed_official | 121:7f86b4238bec | 1647 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
mbed_official | 121:7f86b4238bec | 1648 | /* @brief Maximal data width with parity bit. */ |
mbed_official | 121:7f86b4238bec | 1649 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) |
mbed_official | 121:7f86b4238bec | 1650 | /* @brief Supports two match addresses to filter incoming frames. */ |
mbed_official | 121:7f86b4238bec | 1651 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) |
mbed_official | 121:7f86b4238bec | 1652 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1653 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
mbed_official | 121:7f86b4238bec | 1654 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ |
mbed_official | 121:7f86b4238bec | 1655 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
mbed_official | 121:7f86b4238bec | 1656 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ |
mbed_official | 121:7f86b4238bec | 1657 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) |
mbed_official | 121:7f86b4238bec | 1658 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ |
mbed_official | 121:7f86b4238bec | 1659 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1660 | /* @brief Has improved smart card (ISO7816 protocol) support. */ |
mbed_official | 121:7f86b4238bec | 1661 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) |
mbed_official | 121:7f86b4238bec | 1662 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ |
mbed_official | 121:7f86b4238bec | 1663 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
mbed_official | 121:7f86b4238bec | 1664 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ |
mbed_official | 121:7f86b4238bec | 1665 | #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) |
mbed_official | 121:7f86b4238bec | 1666 | /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ |
mbed_official | 121:7f86b4238bec | 1667 | #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0) |
mbed_official | 121:7f86b4238bec | 1668 | /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ |
mbed_official | 121:7f86b4238bec | 1669 | #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0) |
mbed_official | 121:7f86b4238bec | 1670 | /* @brief Has separate DMA RX and TX requests. */ |
mbed_official | 121:7f86b4238bec | 1671 | #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) |
mbed_official | 121:7f86b4238bec | 1672 | |
mbed_official | 121:7f86b4238bec | 1673 | /* USB module features */ |
mbed_official | 121:7f86b4238bec | 1674 | |
mbed_official | 121:7f86b4238bec | 1675 | /* @brief HOST mode enabled */ |
mbed_official | 121:7f86b4238bec | 1676 | #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0) |
mbed_official | 121:7f86b4238bec | 1677 | /* @brief OTG mode enabled */ |
mbed_official | 121:7f86b4238bec | 1678 | #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0) |
mbed_official | 121:7f86b4238bec | 1679 | /* @brief Size of the USB dedicated RAM */ |
mbed_official | 121:7f86b4238bec | 1680 | #define FSL_FEATURE_USB_KHCI_USB_RAM (512) |
mbed_official | 121:7f86b4238bec | 1681 | /* @brief Base address of the USB dedicated RAM */ |
mbed_official | 121:7f86b4238bec | 1682 | #define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074782208) |
mbed_official | 121:7f86b4238bec | 1683 | /* @brief Has KEEP_ALIVE_CTRL register */ |
mbed_official | 121:7f86b4238bec | 1684 | #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) |
mbed_official | 121:7f86b4238bec | 1685 | /* @brief Has the Dynamic SOF threshold compare support */ |
mbed_official | 121:7f86b4238bec | 1686 | #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) |
mbed_official | 121:7f86b4238bec | 1687 | /* @brief Has the VBUS detect support */ |
mbed_official | 121:7f86b4238bec | 1688 | #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) |
mbed_official | 121:7f86b4238bec | 1689 | /* @brief Has the IRC48M module clock support */ |
mbed_official | 121:7f86b4238bec | 1690 | #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) |
mbed_official | 121:7f86b4238bec | 1691 | /* @brief Number of endpoints supported */ |
mbed_official | 121:7f86b4238bec | 1692 | #define FSL_FEATURE_USB_ENDPT_COUNT (16) |
mbed_official | 121:7f86b4238bec | 1693 | |
mbed_official | 121:7f86b4238bec | 1694 | /* VREF module features */ |
mbed_official | 121:7f86b4238bec | 1695 | |
mbed_official | 121:7f86b4238bec | 1696 | /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ |
mbed_official | 121:7f86b4238bec | 1697 | #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) |
mbed_official | 121:7f86b4238bec | 1698 | /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ |
mbed_official | 121:7f86b4238bec | 1699 | #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) |
mbed_official | 121:7f86b4238bec | 1700 | /* @brief Describes the set of SC[MODE_LV] bitfield values */ |
mbed_official | 121:7f86b4238bec | 1701 | #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) |
mbed_official | 121:7f86b4238bec | 1702 | /* @brief Module has also low reference (registers VREFL/VREFH) */ |
mbed_official | 121:7f86b4238bec | 1703 | #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) |
mbed_official | 121:7f86b4238bec | 1704 | /* @brief Has VREF_TRM4. */ |
mbed_official | 121:7f86b4238bec | 1705 | #define FSL_FEATURE_VREF_HAS_TRM4 (0) |
mbed_official | 121:7f86b4238bec | 1706 | |
mbed_official | 121:7f86b4238bec | 1707 | #endif /* _MKL27Z644_FEATURES_H_ */ |
mbed_official | 121:7f86b4238bec | 1708 |