Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c@52:4ce9155acc4d, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 13:15:11 2016 +0000
Revision:
52:4ce9155acc4d
Parent:
50:a417edff4437
Child:
144:ef7eb2e8f9f7
Synchronized with git revision fa45092ecb5b8bb969a1a14c37bb03a80c0e1ba9



Full URL: https://github.com/mbedmicro/mbed/commit/fa45092ecb5b8bb969a1a14c37bb03a80c0e1ba9/



[Silicon Labs] Allow faster I2C baudrates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file i2c_api.c
bogdanm 0:9b334a45a8ff 3 *******************************************************************************
bogdanm 0:9b334a45a8ff 4 * @section License
bogdanm 0:9b334a45a8ff 5 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 6 *******************************************************************************
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 9 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 10 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 13 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 14 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 15 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 16 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 19 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 20 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 21 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 22 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 23 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 24 *
bogdanm 0:9b334a45a8ff 25 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 26 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 27 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 ******************************************************************************/
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 #include "device.h"
bogdanm 0:9b334a45a8ff 32 #include "clocking.h"
bogdanm 0:9b334a45a8ff 33 #include <stdio.h>
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 #if DEVICE_I2C
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 38 #include "i2c_api.h"
bogdanm 0:9b334a45a8ff 39 #include "PeripheralPins.h"
bogdanm 0:9b334a45a8ff 40 #include "pinmap_function.h"
bogdanm 0:9b334a45a8ff 41 #include "sleepmodes.h"
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 #include "em_i2c.h"
bogdanm 0:9b334a45a8ff 44 #include "em_cmu.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** Error flags indicating I2C transfer has failed somehow. */
bogdanm 0:9b334a45a8ff 47 /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
bogdanm 0:9b334a45a8ff 48 /* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
bogdanm 0:9b334a45a8ff 49 /* RXUF is only likely to occur with this SW if using a debugger peeking into */
bogdanm 0:9b334a45a8ff 50 /* RXDATA register. Thus, we ignore those types of fault. */
bogdanm 0:9b334a45a8ff 51 #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
bogdanm 0:9b334a45a8ff 52 #define I2C_TIMEOUT 100000
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 /* Prototypes */
bogdanm 0:9b334a45a8ff 55 int block_and_wait_for_ack(I2C_TypeDef *i2c);
bogdanm 0:9b334a45a8ff 56 void i2c_enable(i2c_t *obj, uint8_t enable);
bogdanm 0:9b334a45a8ff 57 void i2c_enable_pins(i2c_t *obj, uint8_t enable);
bogdanm 0:9b334a45a8ff 58 void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable);
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 static uint8_t i2c_get_index(i2c_t *obj)
bogdanm 0:9b334a45a8ff 61 {
bogdanm 0:9b334a45a8ff 62 uint8_t index = 0;
bogdanm 0:9b334a45a8ff 63 switch ((int)obj->i2c.i2c) {
bogdanm 0:9b334a45a8ff 64 #ifdef I2C0
bogdanm 0:9b334a45a8ff 65 case I2C_0:
bogdanm 0:9b334a45a8ff 66 index = 0;
bogdanm 0:9b334a45a8ff 67 break;
bogdanm 0:9b334a45a8ff 68 #endif
bogdanm 0:9b334a45a8ff 69 #ifdef I2C1
bogdanm 0:9b334a45a8ff 70 case I2C_1:
bogdanm 0:9b334a45a8ff 71 index = 1;
bogdanm 0:9b334a45a8ff 72 break;
bogdanm 0:9b334a45a8ff 73 #endif
bogdanm 0:9b334a45a8ff 74 default:
bogdanm 0:9b334a45a8ff 75 printf("I2C module not available.. Out of bound access.");
bogdanm 0:9b334a45a8ff 76 break;
bogdanm 0:9b334a45a8ff 77 }
bogdanm 0:9b334a45a8ff 78 return index;
bogdanm 0:9b334a45a8ff 79 }
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 static CMU_Clock_TypeDef i2c_get_clock(i2c_t *obj)
bogdanm 0:9b334a45a8ff 82 {
bogdanm 0:9b334a45a8ff 83 CMU_Clock_TypeDef clock;
bogdanm 0:9b334a45a8ff 84 switch ((int)obj->i2c.i2c) {
bogdanm 0:9b334a45a8ff 85 #ifdef I2C0
bogdanm 0:9b334a45a8ff 86 case I2C_0:
bogdanm 0:9b334a45a8ff 87 clock = cmuClock_I2C0;
bogdanm 0:9b334a45a8ff 88 break;
bogdanm 0:9b334a45a8ff 89 #endif
bogdanm 0:9b334a45a8ff 90 #ifdef I2C1
bogdanm 0:9b334a45a8ff 91 case I2C_1:
bogdanm 0:9b334a45a8ff 92 clock = cmuClock_I2C1;
bogdanm 0:9b334a45a8ff 93 break;
bogdanm 0:9b334a45a8ff 94 #endif
bogdanm 0:9b334a45a8ff 95 default:
bogdanm 0:9b334a45a8ff 96 printf("I2C module not available.. Out of bound access. (clock)");
bogdanm 0:9b334a45a8ff 97 clock = cmuClock_HFPER;
bogdanm 0:9b334a45a8ff 98 break;
bogdanm 0:9b334a45a8ff 99 }
bogdanm 0:9b334a45a8ff 100 return clock;
bogdanm 0:9b334a45a8ff 101 }
bogdanm 0:9b334a45a8ff 102
mbed_official 50:a417edff4437 103 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
bogdanm 0:9b334a45a8ff 104 {
mbed_official 50:a417edff4437 105 /* Find out which I2C peripheral we're asked to use */
bogdanm 0:9b334a45a8ff 106 I2CName i2c_sda = (I2CName) pinmap_peripheral(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 107 I2CName i2c_scl = (I2CName) pinmap_peripheral(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 108 obj->i2c.i2c = (I2C_TypeDef*) pinmap_merge(i2c_sda, i2c_scl);
bogdanm 0:9b334a45a8ff 109 MBED_ASSERT(((int) obj->i2c.i2c) != NC);
mbed_official 52:4ce9155acc4d 110
mbed_official 52:4ce9155acc4d 111 /* You need both SDA and SCL for I2C, so configuring one of them to NC is illegal */
mbed_official 52:4ce9155acc4d 112 MBED_ASSERT((uint32_t)sda != (uint32_t)NC);
mbed_official 52:4ce9155acc4d 113 MBED_ASSERT((uint32_t)scl != (uint32_t)NC);
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /* Enable clock for the peripheral */
bogdanm 0:9b334a45a8ff 116 CMU_ClockEnable(i2c_get_clock(obj), true);
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /* Initializing the I2C */
bogdanm 0:9b334a45a8ff 119 /* Using default settings */
bogdanm 0:9b334a45a8ff 120 I2C_Init_TypeDef i2cInit = I2C_INIT_DEFAULT;
bogdanm 0:9b334a45a8ff 121 I2C_Init(obj->i2c.i2c, &i2cInit);
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /* Enable pins at correct location */
mbed_official 50:a417edff4437 124 #ifdef I2C_ROUTE_SDAPEN
mbed_official 50:a417edff4437 125 /* Find common location in pinmap */
mbed_official 50:a417edff4437 126 int loc_sda = pin_location(sda, PinMap_I2C_SDA);
mbed_official 50:a417edff4437 127 int loc_scl = pin_location(scl, PinMap_I2C_SCL);
mbed_official 50:a417edff4437 128 int loc = pinmap_merge(loc_sda, loc_scl);
mbed_official 50:a417edff4437 129 MBED_ASSERT(loc != NC);
mbed_official 50:a417edff4437 130 /* Set location */
mbed_official 50:a417edff4437 131 obj->i2c.i2c->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
mbed_official 50:a417edff4437 132 #else
mbed_official 50:a417edff4437 133 obj->i2c.i2c->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN;
mbed_official 50:a417edff4437 134 obj->i2c.i2c->ROUTELOC0 = (pin_location(sda, PinMap_I2C_SDA) << _I2C_ROUTELOC0_SDALOC_SHIFT) |
mbed_official 50:a417edff4437 135 (pin_location(scl, PinMap_I2C_SCL) << _I2C_ROUTELOC0_SCLLOC_SHIFT);
mbed_official 50:a417edff4437 136 #endif
mbed_official 50:a417edff4437 137
mbed_official 50:a417edff4437 138 /* Set up the pins for I2C use */
mbed_official 52:4ce9155acc4d 139 /* Note: Set up pins in higher drive strength to reduce slew rate */
mbed_official 52:4ce9155acc4d 140 /* Though this requires user knowledge, since drive strength is controlled per port, not pin */
mbed_official 50:a417edff4437 141 pin_mode(scl, WiredAndPullUp);
mbed_official 50:a417edff4437 142 pin_mode(sda, WiredAndPullUp);
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /* Enable General Call Address Mode. That is; we respond to the general address (0x0) */
bogdanm 0:9b334a45a8ff 145 obj->i2c.i2c->CTRL |= _I2C_CTRL_GCAMEN_MASK;
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* We are assuming that there is only one master. So disable automatic arbitration */
bogdanm 0:9b334a45a8ff 148 obj->i2c.i2c->CTRL |= _I2C_CTRL_ARBDIS_MASK;
bogdanm 0:9b334a45a8ff 149
mbed_official 50:a417edff4437 150 /* Set to master (needed if this I2C block was used previously as slave) */
mbed_official 50:a417edff4437 151 i2c_slave_mode(obj, false);
mbed_official 50:a417edff4437 152
bogdanm 0:9b334a45a8ff 153 /* Enable i2c */
bogdanm 0:9b334a45a8ff 154 i2c_enable(obj, true);
bogdanm 0:9b334a45a8ff 155 }
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 void i2c_enable(i2c_t *obj, uint8_t enable)
bogdanm 0:9b334a45a8ff 158 {
bogdanm 0:9b334a45a8ff 159 I2C_Enable(obj->i2c.i2c, enable);
bogdanm 0:9b334a45a8ff 160 if (!enable) {
bogdanm 0:9b334a45a8ff 161 /* After a reset BUSY is usually set. We assume that we are the only master and call abort,
bogdanm 0:9b334a45a8ff 162 * which sends nothing on the bus, it just allows us to assume that the bus is idle */
bogdanm 0:9b334a45a8ff 163 if (obj->i2c.i2c->STATE & I2C_STATE_BUSY) {
bogdanm 0:9b334a45a8ff 164 obj->i2c.i2c->CMD = I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166 }
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable)
bogdanm 0:9b334a45a8ff 170 {
bogdanm 0:9b334a45a8ff 171 IRQn_Type irq_number;
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 switch (i2c_get_index(obj)) {
bogdanm 0:9b334a45a8ff 174 #ifdef I2C0
bogdanm 0:9b334a45a8ff 175 case 0:
bogdanm 0:9b334a45a8ff 176 irq_number = I2C0_IRQn;
bogdanm 0:9b334a45a8ff 177 break;
bogdanm 0:9b334a45a8ff 178 #endif
bogdanm 0:9b334a45a8ff 179 #ifdef I2C1
bogdanm 0:9b334a45a8ff 180 case 1:
bogdanm 0:9b334a45a8ff 181 irq_number = I2C1_IRQn;
bogdanm 0:9b334a45a8ff 182 break;
bogdanm 0:9b334a45a8ff 183 #endif
bogdanm 0:9b334a45a8ff 184 }
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 NVIC_SetVector(irq_number, address);
bogdanm 0:9b334a45a8ff 187 /* Lower IRQ priority to avoid messing with asynch RX on UART */
bogdanm 0:9b334a45a8ff 188 NVIC_SetPriority(irq_number, 1);
bogdanm 0:9b334a45a8ff 189 if (enable) {
bogdanm 0:9b334a45a8ff 190 NVIC_EnableIRQ(irq_number);
bogdanm 0:9b334a45a8ff 191 } else {
bogdanm 0:9b334a45a8ff 192 NVIC_DisableIRQ(irq_number);
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /* Set the frequency of the I2C interface */
bogdanm 0:9b334a45a8ff 197 void i2c_frequency(i2c_t *obj, int hz)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 /* Set frequency. As the second argument is 0,
bogdanm 0:9b334a45a8ff 200 * HFPER clock frequency is used as reference freq */
mbed_official 52:4ce9155acc4d 201 if (hz <= 0) return;
mbed_official 52:4ce9155acc4d 202 /* In I2C Normal mode (50% duty), we can go up to 100kHz */
mbed_official 52:4ce9155acc4d 203 if (hz <= 100000) {
mbed_official 52:4ce9155acc4d 204 I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRStandard);
mbed_official 52:4ce9155acc4d 205 }
mbed_official 52:4ce9155acc4d 206 /* In I2C Fast mode (6:3 ratio), we can go up to 400kHz */
mbed_official 52:4ce9155acc4d 207 else if (hz <= 400000) {
mbed_official 52:4ce9155acc4d 208 I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRAsymetric);
mbed_official 52:4ce9155acc4d 209 }
mbed_official 52:4ce9155acc4d 210 /* In I2C Fast+ mode (11:6 ratio), we can go up to 1 MHz */
mbed_official 52:4ce9155acc4d 211 else if (hz <= 1000000) {
mbed_official 52:4ce9155acc4d 212 I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRFast);
mbed_official 52:4ce9155acc4d 213 }
mbed_official 52:4ce9155acc4d 214 /* Cap requested frequency at 1MHz */
mbed_official 52:4ce9155acc4d 215 else {
mbed_official 52:4ce9155acc4d 216 I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, 1000000, i2cClockHLRFast);
mbed_official 52:4ce9155acc4d 217 }
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 /* Creates a start condition on the I2C bus */
bogdanm 0:9b334a45a8ff 221 int i2c_start(i2c_t *obj)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 I2C_TypeDef *i2c = obj->i2c.i2c;
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /* Ensure buffers are empty */
bogdanm 0:9b334a45a8ff 226 i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
bogdanm 0:9b334a45a8ff 227 if (i2c->IF & I2C_IF_RXDATAV) {
bogdanm 0:9b334a45a8ff 228 (void) i2c->RXDATA;
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /* Clear all pending interrupts prior to starting transfer. */
bogdanm 0:9b334a45a8ff 232 i2c->IFC = _I2C_IFC_MASK;
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /* Send start */
bogdanm 0:9b334a45a8ff 235 obj->i2c.i2c->CMD = I2C_CMD_START;
bogdanm 0:9b334a45a8ff 236 return 0;
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /* Creates a stop condition on the I2C bus */
bogdanm 0:9b334a45a8ff 240 int i2c_stop(i2c_t *obj)
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 obj->i2c.i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /* Wait for the stop to be sent */
bogdanm 0:9b334a45a8ff 245 int timeout = I2C_TIMEOUT;
bogdanm 0:9b334a45a8ff 246 while (!(obj->i2c.i2c->IF & I2C_IF_MSTOP) && !timeout--);
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 return 0;
bogdanm 0:9b334a45a8ff 249 }
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Returns number of bytes read */
bogdanm 0:9b334a45a8ff 252 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
bogdanm 0:9b334a45a8ff 253 {
bogdanm 0:9b334a45a8ff 254 int retval;
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 i2c_start(obj);
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 retval = i2c_byte_write(obj, (address | 1));
bogdanm 0:9b334a45a8ff 259 if ((!retval) || (length == 0)) { //Write address with W flag (last bit 1)
bogdanm 0:9b334a45a8ff 260 obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 261 while(obj->i2c.i2c->STATE & I2C_STATE_BUSY); // Wait until the bus is done
bogdanm 0:9b334a45a8ff 262 return (retval == 0 ? I2C_ERROR_NO_SLAVE : 0); //NACK or error when writing adress. Return 0 as 0 bytes were read
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264 int i = 0;
bogdanm 0:9b334a45a8ff 265 while (i < length) {
bogdanm 0:9b334a45a8ff 266 uint8_t last = (i == length - 1);
bogdanm 0:9b334a45a8ff 267 data[i++] = i2c_byte_read(obj, last);
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 if (stop) {
bogdanm 0:9b334a45a8ff 271 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 272 }
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 return length;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 i2c_start(obj);
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 if (!i2c_byte_write(obj, (address & 0xFE))) {
bogdanm 0:9b334a45a8ff 282 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 283 return I2C_ERROR_NO_SLAVE; //NACK or error when writing adress. Return 0 as 0 bytes were written
bogdanm 0:9b334a45a8ff 284 }
bogdanm 0:9b334a45a8ff 285 int i;
bogdanm 0:9b334a45a8ff 286 for (i = 0; i < length; i++) {
bogdanm 0:9b334a45a8ff 287 if (!i2c_byte_write(obj, data[i])) {
bogdanm 0:9b334a45a8ff 288 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 289 return i;
bogdanm 0:9b334a45a8ff 290 }
bogdanm 0:9b334a45a8ff 291 }
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 if (stop) {
bogdanm 0:9b334a45a8ff 294 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 return length;
bogdanm 0:9b334a45a8ff 298 }
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 void i2c_reset(i2c_t *obj)
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 /* EMLib function */
bogdanm 0:9b334a45a8ff 303 I2C_Reset(obj->i2c.i2c);
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 int i2c_byte_read(i2c_t *obj, int last)
bogdanm 0:9b334a45a8ff 307 {
bogdanm 0:9b334a45a8ff 308 int timeout = I2C_TIMEOUT;
bogdanm 0:9b334a45a8ff 309 /* Wait for data */
bogdanm 0:9b334a45a8ff 310 while (!(obj->i2c.i2c->STATUS & I2C_STATUS_RXDATAV) && timeout--);
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 if (timeout <= 0) {
bogdanm 0:9b334a45a8ff 313 return 0; //TODO Is this the correct way to handle this?
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315 char data = obj->i2c.i2c->RXDATA;
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 if (last) {
bogdanm 0:9b334a45a8ff 318 obj->i2c.i2c->CMD = I2C_CMD_NACK;
bogdanm 0:9b334a45a8ff 319 } else {
bogdanm 0:9b334a45a8ff 320 obj->i2c.i2c->CMD = I2C_CMD_ACK;
bogdanm 0:9b334a45a8ff 321 }
bogdanm 0:9b334a45a8ff 322 return data;
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 int i2c_byte_write(i2c_t *obj, int data)
bogdanm 0:9b334a45a8ff 326 {
bogdanm 0:9b334a45a8ff 327 obj->i2c.i2c->TXDATA = data;
bogdanm 0:9b334a45a8ff 328 return block_and_wait_for_ack(obj->i2c.i2c);
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /*
bogdanm 0:9b334a45a8ff 332 * Returns 1 for ACK. 0 for NACK, timeout or error.
bogdanm 0:9b334a45a8ff 333 */
bogdanm 0:9b334a45a8ff 334 int block_and_wait_for_ack(I2C_TypeDef *i2c)
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 uint32_t pending;
bogdanm 0:9b334a45a8ff 337 uint32_t timeout = I2C_TIMEOUT;
bogdanm 0:9b334a45a8ff 338 while (timeout > 0) {
bogdanm 0:9b334a45a8ff 339 timeout -= 1;
bogdanm 0:9b334a45a8ff 340 pending = i2c->IF;
bogdanm 0:9b334a45a8ff 341 /* If some sort of fault, abort transfer. */
bogdanm 0:9b334a45a8ff 342 if (pending & I2C_IF_ERRORS) {
bogdanm 0:9b334a45a8ff 343 if (pending & I2C_IF_ARBLOST) {
bogdanm 0:9b334a45a8ff 344 /* If arbitration fault, it indicates either a slave device */
bogdanm 0:9b334a45a8ff 345 /* not responding as expected, or other master which is not */
bogdanm 0:9b334a45a8ff 346 /* supported by this SW. */
bogdanm 0:9b334a45a8ff 347 return 0;
bogdanm 0:9b334a45a8ff 348 } else if (pending & I2C_IF_BUSERR) {
bogdanm 0:9b334a45a8ff 349 /* A bus error indicates a misplaced start or stop, which should */
bogdanm 0:9b334a45a8ff 350 /* not occur in master mode controlled by this SW. */
bogdanm 0:9b334a45a8ff 351 return 0;
bogdanm 0:9b334a45a8ff 352 }
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 if (pending & I2C_IF_NACK) {
bogdanm 0:9b334a45a8ff 356 i2c->IFC = I2C_IFC_NACK;
bogdanm 0:9b334a45a8ff 357 return 0; //Received NACK
bogdanm 0:9b334a45a8ff 358 } else if (pending & I2C_IF_ACK) {
bogdanm 0:9b334a45a8ff 359 i2c->IFC = I2C_IFC_ACK;
bogdanm 0:9b334a45a8ff 360 return 1; //Got ACK
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362 }
bogdanm 0:9b334a45a8ff 363 return 0; //Timeout
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 #if DEVICE_I2CSLAVE
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 #define NoData 0
bogdanm 0:9b334a45a8ff 369 #define ReadAddressed 1
bogdanm 0:9b334a45a8ff 370 #define WriteGeneral 2
bogdanm 0:9b334a45a8ff 371 #define WriteAddressed 3
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 void i2c_slave_mode(i2c_t *obj, int enable_slave)
bogdanm 0:9b334a45a8ff 375 {
bogdanm 0:9b334a45a8ff 376 if(enable_slave) {
mbed_official 52:4ce9155acc4d 377 /* Reference manual note: DIV must be set to 1 during slave operation */
mbed_official 52:4ce9155acc4d 378 obj->i2c.i2c->CLKDIV = 1;
bogdanm 0:9b334a45a8ff 379 obj->i2c.i2c->CTRL |= _I2C_CTRL_SLAVE_MASK;
bogdanm 0:9b334a45a8ff 380 obj->i2c.i2c->CTRL |= _I2C_CTRL_AUTOACK_MASK; //Slave implementation assumes auto acking
bogdanm 0:9b334a45a8ff 381 } else {
bogdanm 0:9b334a45a8ff 382 obj->i2c.i2c->CTRL &= ~_I2C_CTRL_SLAVE_MASK;
bogdanm 0:9b334a45a8ff 383 obj->i2c.i2c->CTRL &= ~_I2C_CTRL_AUTOACK_MASK; //Master implementation ACKs manually
mbed_official 52:4ce9155acc4d 384 /* function is only called with enable_slave = false through i2c_init(..), so frequency is
mbed_official 52:4ce9155acc4d 385 already guaranteed to be set */
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387 }
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 int i2c_slave_receive(i2c_t *obj)
bogdanm 0:9b334a45a8ff 390 {
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 if(obj->i2c.i2c->IF & I2C_IF_ADDR) {
bogdanm 0:9b334a45a8ff 393 obj->i2c.i2c->IFC = I2C_IF_ADDR; //Clear interrupt
bogdanm 0:9b334a45a8ff 394 /*0x00 is the address for general write.
bogdanm 0:9b334a45a8ff 395 The address the master wrote is in RXDATA now
bogdanm 0:9b334a45a8ff 396 and reading it also frees the buffer for the next
bogdanm 0:9b334a45a8ff 397 write which can then be acked. */
bogdanm 0:9b334a45a8ff 398 if(obj->i2c.i2c->RXDATA == 0x00) {
bogdanm 0:9b334a45a8ff 399 return WriteGeneral; //Read the address;
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER) {
bogdanm 0:9b334a45a8ff 403 return ReadAddressed;
bogdanm 0:9b334a45a8ff 404 } else {
bogdanm 0:9b334a45a8ff 405 return WriteAddressed;
bogdanm 0:9b334a45a8ff 406 }
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 return NoData;
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 int i2c_slave_read(i2c_t *obj, char *data, int length)
bogdanm 0:9b334a45a8ff 414 {
bogdanm 0:9b334a45a8ff 415 int count;
bogdanm 0:9b334a45a8ff 416 for (count = 0; count < length; count++) {
bogdanm 0:9b334a45a8ff 417 data[count] = i2c_byte_read(obj, 0);
bogdanm 0:9b334a45a8ff 418 }
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 return count;
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 }
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 int i2c_slave_write(i2c_t *obj, const char *data, int length)
bogdanm 0:9b334a45a8ff 426 {
bogdanm 0:9b334a45a8ff 427 int count;
bogdanm 0:9b334a45a8ff 428 for (count = 0; count < length; count++) {
bogdanm 0:9b334a45a8ff 429 i2c_byte_write(obj, data[count]);
bogdanm 0:9b334a45a8ff 430 }
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 return count;
bogdanm 0:9b334a45a8ff 433 }
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
bogdanm 0:9b334a45a8ff 436 {
bogdanm 0:9b334a45a8ff 437 obj->i2c.i2c->SADDR = address;
bogdanm 0:9b334a45a8ff 438 obj->i2c.i2c->SADDRMASK = 0xFE;//mask;
bogdanm 0:9b334a45a8ff 439 }
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 #endif //DEVICE_I2CSLAVE
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 #ifdef DEVICE_I2C_ASYNCH
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 #include "em_dma.h"
bogdanm 0:9b334a45a8ff 446 #include "dma_api_HAL.h"
bogdanm 0:9b334a45a8ff 447 #include "dma_api.h"
bogdanm 0:9b334a45a8ff 448 #include "sleep_api.h"
bogdanm 0:9b334a45a8ff 449 #include "buffer.h"
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /** Start i2c asynchronous transfer.
bogdanm 0:9b334a45a8ff 452 * @param obj The I2C object
bogdanm 0:9b334a45a8ff 453 * @param tx The buffer to send
bogdanm 0:9b334a45a8ff 454 * @param tx_length The number of words to transmit
bogdanm 0:9b334a45a8ff 455 * @param rx The buffer to receive
bogdanm 0:9b334a45a8ff 456 * @param rx_length The number of words to receive
bogdanm 0:9b334a45a8ff 457 * @param address The address to be set - 7bit or 9 bit
bogdanm 0:9b334a45a8ff 458 * @param stop If true, stop will be generated after the transfer is done
bogdanm 0:9b334a45a8ff 459 * @param handler The I2C IRQ handler to be set
bogdanm 0:9b334a45a8ff 460 * @param hint DMA hint usage
bogdanm 0:9b334a45a8ff 461 */
bogdanm 0:9b334a45a8ff 462 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464 I2C_TransferReturn_TypeDef retval;
bogdanm 0:9b334a45a8ff 465 if(i2c_active(obj)) return;
bogdanm 0:9b334a45a8ff 466 if((tx_length == 0) && (rx_length == 0)) return;
bogdanm 0:9b334a45a8ff 467 // For now, we are assuming a solely interrupt-driven implementation.
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 // Store transfer config
bogdanm 0:9b334a45a8ff 470 obj->i2c.xfer.addr = address;
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 // Some combination of tx_length and rx_length will tell us what to do
bogdanm 0:9b334a45a8ff 473 if((tx_length > 0) && (rx_length == 0)) {
bogdanm 0:9b334a45a8ff 474 obj->i2c.xfer.flags = I2C_FLAG_WRITE;
bogdanm 0:9b334a45a8ff 475 //Store buffer info
bogdanm 0:9b334a45a8ff 476 obj->i2c.xfer.buf[0].data = (void *)tx;
bogdanm 0:9b334a45a8ff 477 obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
bogdanm 0:9b334a45a8ff 478 } else if ((tx_length == 0) && (rx_length > 0)) {
bogdanm 0:9b334a45a8ff 479 obj->i2c.xfer.flags = I2C_FLAG_READ;
bogdanm 0:9b334a45a8ff 480 //Store buffer info
bogdanm 0:9b334a45a8ff 481 obj->i2c.xfer.buf[0].data = rx;
bogdanm 0:9b334a45a8ff 482 obj->i2c.xfer.buf[0].len = (uint16_t) rx_length;
bogdanm 0:9b334a45a8ff 483 } else if ((tx_length > 0) && (rx_length > 0)) {
bogdanm 0:9b334a45a8ff 484 obj->i2c.xfer.flags = I2C_FLAG_WRITE_READ;
bogdanm 0:9b334a45a8ff 485 //Store buffer info
bogdanm 0:9b334a45a8ff 486 obj->i2c.xfer.buf[0].data = (void *)tx;
bogdanm 0:9b334a45a8ff 487 obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
bogdanm 0:9b334a45a8ff 488 obj->i2c.xfer.buf[1].data = rx;
bogdanm 0:9b334a45a8ff 489 obj->i2c.xfer.buf[1].len = (uint16_t) rx_length;
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 if(address > 255) obj->i2c.xfer.flags |= I2C_FLAG_10BIT_ADDR;
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 // Store event flags
bogdanm 0:9b334a45a8ff 495 obj->i2c.events = event;
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 // Enable interrupt
bogdanm 0:9b334a45a8ff 498 i2c_enable_interrupt(obj, handler, true);
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 // Kick off the transfer
bogdanm 0:9b334a45a8ff 501 retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer));
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 if(retval == i2cTransferInProgress) {
bogdanm 0:9b334a45a8ff 504 blockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 505 } else {
bogdanm 0:9b334a45a8ff 506 // something happened, and the transfer did not go through
bogdanm 0:9b334a45a8ff 507 // So, we need to clean up
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 // Disable interrupt
bogdanm 0:9b334a45a8ff 510 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 // Block until free
bogdanm 0:9b334a45a8ff 513 while(i2c_active(obj));
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515 }
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /** The asynchronous IRQ handler
bogdanm 0:9b334a45a8ff 518 * @param obj The I2C object which holds the transfer information
bogdanm 0:9b334a45a8ff 519 * @return Returns event flags if a transfer termination condition was met or 0 otherwise.
bogdanm 0:9b334a45a8ff 520 */
bogdanm 0:9b334a45a8ff 521 uint32_t i2c_irq_handler_asynch(i2c_t *obj)
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 // For now, we are assuming a solely interrupt-driven implementation.
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 I2C_TransferReturn_TypeDef status = I2C_Transfer(obj->i2c.i2c);
bogdanm 0:9b334a45a8ff 527 switch(status) {
bogdanm 0:9b334a45a8ff 528 case i2cTransferInProgress:
bogdanm 0:9b334a45a8ff 529 // Still busy transferring, so let it.
bogdanm 0:9b334a45a8ff 530 return 0;
bogdanm 0:9b334a45a8ff 531 case i2cTransferDone:
bogdanm 0:9b334a45a8ff 532 // Transfer has completed
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 // Disable interrupt
bogdanm 0:9b334a45a8ff 535 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events;
bogdanm 0:9b334a45a8ff 540 case i2cTransferNack:
bogdanm 0:9b334a45a8ff 541 // A NACK has been received while an ACK was expected. This is usually because the slave did not respond to the address.
bogdanm 0:9b334a45a8ff 542 // Disable interrupt
bogdanm 0:9b334a45a8ff 543 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events;
bogdanm 0:9b334a45a8ff 548 default:
bogdanm 0:9b334a45a8ff 549 // An error situation has arisen.
bogdanm 0:9b334a45a8ff 550 // Disable interrupt
bogdanm 0:9b334a45a8ff 551 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 // return error
bogdanm 0:9b334a45a8ff 556 return I2C_EVENT_ERROR & obj->i2c.events;
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /** Attempts to determine if I2C peripheral is already in use.
bogdanm 0:9b334a45a8ff 561 * @param obj The I2C object
bogdanm 0:9b334a45a8ff 562 * @return non-zero if the I2C module is active or zero if it is not
bogdanm 0:9b334a45a8ff 563 */
bogdanm 0:9b334a45a8ff 564 uint8_t i2c_active(i2c_t *obj)
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 return (obj->i2c.i2c->STATE & I2C_STATE_BUSY);
bogdanm 0:9b334a45a8ff 567 }
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 /** Abort ongoing asynchronous transaction.
bogdanm 0:9b334a45a8ff 570 * @param obj The I2C object
bogdanm 0:9b334a45a8ff 571 */
bogdanm 0:9b334a45a8ff 572 void i2c_abort_asynch(i2c_t *obj)
bogdanm 0:9b334a45a8ff 573 {
bogdanm 0:9b334a45a8ff 574 // Do not deactivate I2C twice
bogdanm 0:9b334a45a8ff 575 if (!i2c_active(obj)) return;
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 // Disable interrupt
bogdanm 0:9b334a45a8ff 578 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 // Abort
bogdanm 0:9b334a45a8ff 581 obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 // Block until free
bogdanm 0:9b334a45a8ff 584 while(i2c_active(obj));
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 #endif //DEVICE_I2C ASYNCH
bogdanm 0:9b334a45a8ff 590 #endif //DEVICE_I2C